So as my last couple posts alluded to, I’ve been having problems with my DRAM-based design. My controller isn’t dual-port. And I’ve been trying to wrap my head around a time-slot method for arbitration...
Archive - December 2011
on memory controller optimization
So I’ve been trying to optimize a freeware memory controller for my particular memory chip. I’m running into this situation where the DRAM to ALTRAM copy takes upwards of 24us per line. But I only have a...
maybe a big problem, memory arbitration on FPGAs
So far, I’ve been using a user-selectable mux, with a physical switch, to control which process is connected to the single-port memory controller. If the switch is in one position, you can upload via USB a...
my level converter board with lcx245’s
I put this together last night. It takes the amiga 5v video signals in on the right hand side and then outputs 3.3v to IDC40-pin connector that connects to the FPGA board. Once I build my header cables, they will plug...
more ordering of parts, soldered pins for lcx245 parts
So I was looking everywhere for a female-female header cable that has the right number of pins, to basically interface the Denise IC DIP Clip to my level converting solderless breadboard. I couldn’t seem to find...