|BeMicro_MAX10_top
SYS_CLK => SYS_CLK.IN1
USER_CLK => ~NO_FANOUT~
PB[1] => ~NO_FANOUT~
PB[2] => ~NO_FANOUT~
PB[3] => ~NO_FANOUT~
PB[4] => ~NO_FANOUT~
USER_LED[1] <= dac_clocks:dac_clocks_inst.locked
USER_LED[2] <= <GND>
USER_LED[3] <= <GND>
USER_LED[4] <= <GND>
USER_LED[5] <= <GND>
USER_LED[6] <= <GND>
USER_LED[7] <= <GND>
USER_LED[8] <= <GND>
GPIO_01 <> <UNC>
GPIO_02 <> <UNC>
GPIO_03 <> <UNC>
GPIO_04 <> <UNC>
GPIO_05 <> <UNC>
GPIO_06 <> <UNC>
GPIO_07 <> <UNC>
GPIO_08 <> <UNC>
GPIO_09 <> <UNC>
GPIO_10 <> <UNC>
GPIO_11 <> <UNC>
GPIO_12 <> <UNC>
GPIO_A <> <UNC>
GPIO_B <> <UNC>
I2C_SCL <> <UNC>
I2C_SDA <> <UNC>
PMOD_A[0] <> <UNC>
PMOD_A[1] <> <UNC>
PMOD_A[2] <> <UNC>
PMOD_A[3] <> <UNC>
PMOD_B[0] <> PMOD_B[0]
PMOD_B[1] <> PMOD_B[1]
PMOD_B[2] <> PMOD_B[2]
PMOD_B[3] <> PMOD_B[3]
PMOD_C[0] <> <UNC>
PMOD_C[1] <> <UNC>
PMOD_C[2] <> <UNC>
PMOD_C[3] <> <UNC>
PMOD_D[0] <> <UNC>
PMOD_D[1] <> <UNC>
PMOD_D[2] <> <UNC>
PMOD_D[3] <> <UNC>


|BeMicro_MAX10_top|dac_clocks:dac_clocks_inst
areset => areset.IN1
inclk0 => sub_wire1[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk
c2 <= altpll:altpll_component.clk
locked <= altpll:altpll_component.locked


|BeMicro_MAX10_top|dac_clocks:dac_clocks_inst|altpll:altpll_component
inclk[0] => dac_clocks_altpll:auto_generated.inclk[0]
inclk[1] => dac_clocks_altpll:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => dac_clocks_altpll:auto_generated.areset
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= dac_clocks_altpll:auto_generated.locked
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>


|BeMicro_MAX10_top|dac_clocks:dac_clocks_inst|altpll:altpll_component|dac_clocks_altpll:auto_generated
areset => pll_lock_sync.ACLR
areset => pll1.ARESET
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1
locked <= locked.DB_MAX_OUTPUT_PORT_TYPE


|BeMicro_MAX10_top|dacrom:dacrom_inst
address[0] => address[0].IN1
address[1] => address[1].IN1
address[2] => address[2].IN1
address[3] => address[3].IN1
address[4] => address[4].IN1
address[5] => address[5].IN1
address[6] => address[6].IN1
address[7] => address[7].IN1
address[8] => address[8].IN1
address[9] => address[9].IN1
address[10] => address[10].IN1
address[11] => address[11].IN1
address[12] => address[12].IN1
address[13] => address[13].IN1
clock => clock.IN1
q[0] <= altsyncram:altsyncram_component.q_a
q[1] <= altsyncram:altsyncram_component.q_a
q[2] <= altsyncram:altsyncram_component.q_a
q[3] <= altsyncram:altsyncram_component.q_a
q[4] <= altsyncram:altsyncram_component.q_a
q[5] <= altsyncram:altsyncram_component.q_a
q[6] <= altsyncram:altsyncram_component.q_a
q[7] <= altsyncram:altsyncram_component.q_a
q[8] <= altsyncram:altsyncram_component.q_a
q[9] <= altsyncram:altsyncram_component.q_a
q[10] <= altsyncram:altsyncram_component.q_a
q[11] <= altsyncram:altsyncram_component.q_a
q[12] <= altsyncram:altsyncram_component.q_a
q[13] <= altsyncram:altsyncram_component.q_a
q[14] <= altsyncram:altsyncram_component.q_a
q[15] <= altsyncram:altsyncram_component.q_a


|BeMicro_MAX10_top|dacrom:dacrom_inst|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_e4a1:auto_generated.address_a[0]
address_a[1] => altsyncram_e4a1:auto_generated.address_a[1]
address_a[2] => altsyncram_e4a1:auto_generated.address_a[2]
address_a[3] => altsyncram_e4a1:auto_generated.address_a[3]
address_a[4] => altsyncram_e4a1:auto_generated.address_a[4]
address_a[5] => altsyncram_e4a1:auto_generated.address_a[5]
address_a[6] => altsyncram_e4a1:auto_generated.address_a[6]
address_a[7] => altsyncram_e4a1:auto_generated.address_a[7]
address_a[8] => altsyncram_e4a1:auto_generated.address_a[8]
address_a[9] => altsyncram_e4a1:auto_generated.address_a[9]
address_a[10] => altsyncram_e4a1:auto_generated.address_a[10]
address_a[11] => altsyncram_e4a1:auto_generated.address_a[11]
address_a[12] => altsyncram_e4a1:auto_generated.address_a[12]
address_a[13] => altsyncram_e4a1:auto_generated.address_a[13]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_e4a1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_e4a1:auto_generated.q_a[0]
q_a[1] <= altsyncram_e4a1:auto_generated.q_a[1]
q_a[2] <= altsyncram_e4a1:auto_generated.q_a[2]
q_a[3] <= altsyncram_e4a1:auto_generated.q_a[3]
q_a[4] <= altsyncram_e4a1:auto_generated.q_a[4]
q_a[5] <= altsyncram_e4a1:auto_generated.q_a[5]
q_a[6] <= altsyncram_e4a1:auto_generated.q_a[6]
q_a[7] <= altsyncram_e4a1:auto_generated.q_a[7]
q_a[8] <= altsyncram_e4a1:auto_generated.q_a[8]
q_a[9] <= altsyncram_e4a1:auto_generated.q_a[9]
q_a[10] <= altsyncram_e4a1:auto_generated.q_a[10]
q_a[11] <= altsyncram_e4a1:auto_generated.q_a[11]
q_a[12] <= altsyncram_e4a1:auto_generated.q_a[12]
q_a[13] <= altsyncram_e4a1:auto_generated.q_a[13]
q_a[14] <= altsyncram_e4a1:auto_generated.q_a[14]
q_a[15] <= altsyncram_e4a1:auto_generated.q_a[15]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|BeMicro_MAX10_top|dacrom:dacrom_inst|altsyncram:altsyncram_component|altsyncram_e4a1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1
address_a[1] => ram_block1a26.PORTAADDR1
address_a[1] => ram_block1a27.PORTAADDR1
address_a[1] => ram_block1a28.PORTAADDR1
address_a[1] => ram_block1a29.PORTAADDR1
address_a[1] => ram_block1a30.PORTAADDR1
address_a[1] => ram_block1a31.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[2] => ram_block1a16.PORTAADDR2
address_a[2] => ram_block1a17.PORTAADDR2
address_a[2] => ram_block1a18.PORTAADDR2
address_a[2] => ram_block1a19.PORTAADDR2
address_a[2] => ram_block1a20.PORTAADDR2
address_a[2] => ram_block1a21.PORTAADDR2
address_a[2] => ram_block1a22.PORTAADDR2
address_a[2] => ram_block1a23.PORTAADDR2
address_a[2] => ram_block1a24.PORTAADDR2
address_a[2] => ram_block1a25.PORTAADDR2
address_a[2] => ram_block1a26.PORTAADDR2
address_a[2] => ram_block1a27.PORTAADDR2
address_a[2] => ram_block1a28.PORTAADDR2
address_a[2] => ram_block1a29.PORTAADDR2
address_a[2] => ram_block1a30.PORTAADDR2
address_a[2] => ram_block1a31.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[3] => ram_block1a16.PORTAADDR3
address_a[3] => ram_block1a17.PORTAADDR3
address_a[3] => ram_block1a18.PORTAADDR3
address_a[3] => ram_block1a19.PORTAADDR3
address_a[3] => ram_block1a20.PORTAADDR3
address_a[3] => ram_block1a21.PORTAADDR3
address_a[3] => ram_block1a22.PORTAADDR3
address_a[3] => ram_block1a23.PORTAADDR3
address_a[3] => ram_block1a24.PORTAADDR3
address_a[3] => ram_block1a25.PORTAADDR3
address_a[3] => ram_block1a26.PORTAADDR3
address_a[3] => ram_block1a27.PORTAADDR3
address_a[3] => ram_block1a28.PORTAADDR3
address_a[3] => ram_block1a29.PORTAADDR3
address_a[3] => ram_block1a30.PORTAADDR3
address_a[3] => ram_block1a31.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[4] => ram_block1a16.PORTAADDR4
address_a[4] => ram_block1a17.PORTAADDR4
address_a[4] => ram_block1a18.PORTAADDR4
address_a[4] => ram_block1a19.PORTAADDR4
address_a[4] => ram_block1a20.PORTAADDR4
address_a[4] => ram_block1a21.PORTAADDR4
address_a[4] => ram_block1a22.PORTAADDR4
address_a[4] => ram_block1a23.PORTAADDR4
address_a[4] => ram_block1a24.PORTAADDR4
address_a[4] => ram_block1a25.PORTAADDR4
address_a[4] => ram_block1a26.PORTAADDR4
address_a[4] => ram_block1a27.PORTAADDR4
address_a[4] => ram_block1a28.PORTAADDR4
address_a[4] => ram_block1a29.PORTAADDR4
address_a[4] => ram_block1a30.PORTAADDR4
address_a[4] => ram_block1a31.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[5] => ram_block1a16.PORTAADDR5
address_a[5] => ram_block1a17.PORTAADDR5
address_a[5] => ram_block1a18.PORTAADDR5
address_a[5] => ram_block1a19.PORTAADDR5
address_a[5] => ram_block1a20.PORTAADDR5
address_a[5] => ram_block1a21.PORTAADDR5
address_a[5] => ram_block1a22.PORTAADDR5
address_a[5] => ram_block1a23.PORTAADDR5
address_a[5] => ram_block1a24.PORTAADDR5
address_a[5] => ram_block1a25.PORTAADDR5
address_a[5] => ram_block1a26.PORTAADDR5
address_a[5] => ram_block1a27.PORTAADDR5
address_a[5] => ram_block1a28.PORTAADDR5
address_a[5] => ram_block1a29.PORTAADDR5
address_a[5] => ram_block1a30.PORTAADDR5
address_a[5] => ram_block1a31.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[6] => ram_block1a16.PORTAADDR6
address_a[6] => ram_block1a17.PORTAADDR6
address_a[6] => ram_block1a18.PORTAADDR6
address_a[6] => ram_block1a19.PORTAADDR6
address_a[6] => ram_block1a20.PORTAADDR6
address_a[6] => ram_block1a21.PORTAADDR6
address_a[6] => ram_block1a22.PORTAADDR6
address_a[6] => ram_block1a23.PORTAADDR6
address_a[6] => ram_block1a24.PORTAADDR6
address_a[6] => ram_block1a25.PORTAADDR6
address_a[6] => ram_block1a26.PORTAADDR6
address_a[6] => ram_block1a27.PORTAADDR6
address_a[6] => ram_block1a28.PORTAADDR6
address_a[6] => ram_block1a29.PORTAADDR6
address_a[6] => ram_block1a30.PORTAADDR6
address_a[6] => ram_block1a31.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
address_a[7] => ram_block1a16.PORTAADDR7
address_a[7] => ram_block1a17.PORTAADDR7
address_a[7] => ram_block1a18.PORTAADDR7
address_a[7] => ram_block1a19.PORTAADDR7
address_a[7] => ram_block1a20.PORTAADDR7
address_a[7] => ram_block1a21.PORTAADDR7
address_a[7] => ram_block1a22.PORTAADDR7
address_a[7] => ram_block1a23.PORTAADDR7
address_a[7] => ram_block1a24.PORTAADDR7
address_a[7] => ram_block1a25.PORTAADDR7
address_a[7] => ram_block1a26.PORTAADDR7
address_a[7] => ram_block1a27.PORTAADDR7
address_a[7] => ram_block1a28.PORTAADDR7
address_a[7] => ram_block1a29.PORTAADDR7
address_a[7] => ram_block1a30.PORTAADDR7
address_a[7] => ram_block1a31.PORTAADDR7
address_a[8] => ram_block1a0.PORTAADDR8
address_a[8] => ram_block1a1.PORTAADDR8
address_a[8] => ram_block1a2.PORTAADDR8
address_a[8] => ram_block1a3.PORTAADDR8
address_a[8] => ram_block1a4.PORTAADDR8
address_a[8] => ram_block1a5.PORTAADDR8
address_a[8] => ram_block1a6.PORTAADDR8
address_a[8] => ram_block1a7.PORTAADDR8
address_a[8] => ram_block1a8.PORTAADDR8
address_a[8] => ram_block1a9.PORTAADDR8
address_a[8] => ram_block1a10.PORTAADDR8
address_a[8] => ram_block1a11.PORTAADDR8
address_a[8] => ram_block1a12.PORTAADDR8
address_a[8] => ram_block1a13.PORTAADDR8
address_a[8] => ram_block1a14.PORTAADDR8
address_a[8] => ram_block1a15.PORTAADDR8
address_a[8] => ram_block1a16.PORTAADDR8
address_a[8] => ram_block1a17.PORTAADDR8
address_a[8] => ram_block1a18.PORTAADDR8
address_a[8] => ram_block1a19.PORTAADDR8
address_a[8] => ram_block1a20.PORTAADDR8
address_a[8] => ram_block1a21.PORTAADDR8
address_a[8] => ram_block1a22.PORTAADDR8
address_a[8] => ram_block1a23.PORTAADDR8
address_a[8] => ram_block1a24.PORTAADDR8
address_a[8] => ram_block1a25.PORTAADDR8
address_a[8] => ram_block1a26.PORTAADDR8
address_a[8] => ram_block1a27.PORTAADDR8
address_a[8] => ram_block1a28.PORTAADDR8
address_a[8] => ram_block1a29.PORTAADDR8
address_a[8] => ram_block1a30.PORTAADDR8
address_a[8] => ram_block1a31.PORTAADDR8
address_a[9] => ram_block1a0.PORTAADDR9
address_a[9] => ram_block1a1.PORTAADDR9
address_a[9] => ram_block1a2.PORTAADDR9
address_a[9] => ram_block1a3.PORTAADDR9
address_a[9] => ram_block1a4.PORTAADDR9
address_a[9] => ram_block1a5.PORTAADDR9
address_a[9] => ram_block1a6.PORTAADDR9
address_a[9] => ram_block1a7.PORTAADDR9
address_a[9] => ram_block1a8.PORTAADDR9
address_a[9] => ram_block1a9.PORTAADDR9
address_a[9] => ram_block1a10.PORTAADDR9
address_a[9] => ram_block1a11.PORTAADDR9
address_a[9] => ram_block1a12.PORTAADDR9
address_a[9] => ram_block1a13.PORTAADDR9
address_a[9] => ram_block1a14.PORTAADDR9
address_a[9] => ram_block1a15.PORTAADDR9
address_a[9] => ram_block1a16.PORTAADDR9
address_a[9] => ram_block1a17.PORTAADDR9
address_a[9] => ram_block1a18.PORTAADDR9
address_a[9] => ram_block1a19.PORTAADDR9
address_a[9] => ram_block1a20.PORTAADDR9
address_a[9] => ram_block1a21.PORTAADDR9
address_a[9] => ram_block1a22.PORTAADDR9
address_a[9] => ram_block1a23.PORTAADDR9
address_a[9] => ram_block1a24.PORTAADDR9
address_a[9] => ram_block1a25.PORTAADDR9
address_a[9] => ram_block1a26.PORTAADDR9
address_a[9] => ram_block1a27.PORTAADDR9
address_a[9] => ram_block1a28.PORTAADDR9
address_a[9] => ram_block1a29.PORTAADDR9
address_a[9] => ram_block1a30.PORTAADDR9
address_a[9] => ram_block1a31.PORTAADDR9
address_a[10] => ram_block1a0.PORTAADDR10
address_a[10] => ram_block1a1.PORTAADDR10
address_a[10] => ram_block1a2.PORTAADDR10
address_a[10] => ram_block1a3.PORTAADDR10
address_a[10] => ram_block1a4.PORTAADDR10
address_a[10] => ram_block1a5.PORTAADDR10
address_a[10] => ram_block1a6.PORTAADDR10
address_a[10] => ram_block1a7.PORTAADDR10
address_a[10] => ram_block1a8.PORTAADDR10
address_a[10] => ram_block1a9.PORTAADDR10
address_a[10] => ram_block1a10.PORTAADDR10
address_a[10] => ram_block1a11.PORTAADDR10
address_a[10] => ram_block1a12.PORTAADDR10
address_a[10] => ram_block1a13.PORTAADDR10
address_a[10] => ram_block1a14.PORTAADDR10
address_a[10] => ram_block1a15.PORTAADDR10
address_a[10] => ram_block1a16.PORTAADDR10
address_a[10] => ram_block1a17.PORTAADDR10
address_a[10] => ram_block1a18.PORTAADDR10
address_a[10] => ram_block1a19.PORTAADDR10
address_a[10] => ram_block1a20.PORTAADDR10
address_a[10] => ram_block1a21.PORTAADDR10
address_a[10] => ram_block1a22.PORTAADDR10
address_a[10] => ram_block1a23.PORTAADDR10
address_a[10] => ram_block1a24.PORTAADDR10
address_a[10] => ram_block1a25.PORTAADDR10
address_a[10] => ram_block1a26.PORTAADDR10
address_a[10] => ram_block1a27.PORTAADDR10
address_a[10] => ram_block1a28.PORTAADDR10
address_a[10] => ram_block1a29.PORTAADDR10
address_a[10] => ram_block1a30.PORTAADDR10
address_a[10] => ram_block1a31.PORTAADDR10
address_a[11] => ram_block1a0.PORTAADDR11
address_a[11] => ram_block1a1.PORTAADDR11
address_a[11] => ram_block1a2.PORTAADDR11
address_a[11] => ram_block1a3.PORTAADDR11
address_a[11] => ram_block1a4.PORTAADDR11
address_a[11] => ram_block1a5.PORTAADDR11
address_a[11] => ram_block1a6.PORTAADDR11
address_a[11] => ram_block1a7.PORTAADDR11
address_a[11] => ram_block1a8.PORTAADDR11
address_a[11] => ram_block1a9.PORTAADDR11
address_a[11] => ram_block1a10.PORTAADDR11
address_a[11] => ram_block1a11.PORTAADDR11
address_a[11] => ram_block1a12.PORTAADDR11
address_a[11] => ram_block1a13.PORTAADDR11
address_a[11] => ram_block1a14.PORTAADDR11
address_a[11] => ram_block1a15.PORTAADDR11
address_a[11] => ram_block1a16.PORTAADDR11
address_a[11] => ram_block1a17.PORTAADDR11
address_a[11] => ram_block1a18.PORTAADDR11
address_a[11] => ram_block1a19.PORTAADDR11
address_a[11] => ram_block1a20.PORTAADDR11
address_a[11] => ram_block1a21.PORTAADDR11
address_a[11] => ram_block1a22.PORTAADDR11
address_a[11] => ram_block1a23.PORTAADDR11
address_a[11] => ram_block1a24.PORTAADDR11
address_a[11] => ram_block1a25.PORTAADDR11
address_a[11] => ram_block1a26.PORTAADDR11
address_a[11] => ram_block1a27.PORTAADDR11
address_a[11] => ram_block1a28.PORTAADDR11
address_a[11] => ram_block1a29.PORTAADDR11
address_a[11] => ram_block1a30.PORTAADDR11
address_a[11] => ram_block1a31.PORTAADDR11
address_a[12] => ram_block1a0.PORTAADDR12
address_a[12] => ram_block1a1.PORTAADDR12
address_a[12] => ram_block1a2.PORTAADDR12
address_a[12] => ram_block1a3.PORTAADDR12
address_a[12] => ram_block1a4.PORTAADDR12
address_a[12] => ram_block1a5.PORTAADDR12
address_a[12] => ram_block1a6.PORTAADDR12
address_a[12] => ram_block1a7.PORTAADDR12
address_a[12] => ram_block1a8.PORTAADDR12
address_a[12] => ram_block1a9.PORTAADDR12
address_a[12] => ram_block1a10.PORTAADDR12
address_a[12] => ram_block1a11.PORTAADDR12
address_a[12] => ram_block1a12.PORTAADDR12
address_a[12] => ram_block1a13.PORTAADDR12
address_a[12] => ram_block1a14.PORTAADDR12
address_a[12] => ram_block1a15.PORTAADDR12
address_a[12] => ram_block1a16.PORTAADDR12
address_a[12] => ram_block1a17.PORTAADDR12
address_a[12] => ram_block1a18.PORTAADDR12
address_a[12] => ram_block1a19.PORTAADDR12
address_a[12] => ram_block1a20.PORTAADDR12
address_a[12] => ram_block1a21.PORTAADDR12
address_a[12] => ram_block1a22.PORTAADDR12
address_a[12] => ram_block1a23.PORTAADDR12
address_a[12] => ram_block1a24.PORTAADDR12
address_a[12] => ram_block1a25.PORTAADDR12
address_a[12] => ram_block1a26.PORTAADDR12
address_a[12] => ram_block1a27.PORTAADDR12
address_a[12] => ram_block1a28.PORTAADDR12
address_a[12] => ram_block1a29.PORTAADDR12
address_a[12] => ram_block1a30.PORTAADDR12
address_a[12] => ram_block1a31.PORTAADDR12
address_a[13] => address_reg_a[0].DATAIN
address_a[13] => decode_2j9:rden_decode.data[0]
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
clock0 => ram_block1a16.CLK0
clock0 => ram_block1a17.CLK0
clock0 => ram_block1a18.CLK0
clock0 => ram_block1a19.CLK0
clock0 => ram_block1a20.CLK0
clock0 => ram_block1a21.CLK0
clock0 => ram_block1a22.CLK0
clock0 => ram_block1a23.CLK0
clock0 => ram_block1a24.CLK0
clock0 => ram_block1a25.CLK0
clock0 => ram_block1a26.CLK0
clock0 => ram_block1a27.CLK0
clock0 => ram_block1a28.CLK0
clock0 => ram_block1a29.CLK0
clock0 => ram_block1a30.CLK0
clock0 => ram_block1a31.CLK0
clock0 => address_reg_a[0].CLK
q_a[0] <= mux_83b:mux2.result[0]
q_a[1] <= mux_83b:mux2.result[1]
q_a[2] <= mux_83b:mux2.result[2]
q_a[3] <= mux_83b:mux2.result[3]
q_a[4] <= mux_83b:mux2.result[4]
q_a[5] <= mux_83b:mux2.result[5]
q_a[6] <= mux_83b:mux2.result[6]
q_a[7] <= mux_83b:mux2.result[7]
q_a[8] <= mux_83b:mux2.result[8]
q_a[9] <= mux_83b:mux2.result[9]
q_a[10] <= mux_83b:mux2.result[10]
q_a[11] <= mux_83b:mux2.result[11]
q_a[12] <= mux_83b:mux2.result[12]
q_a[13] <= mux_83b:mux2.result[13]
q_a[14] <= mux_83b:mux2.result[14]
q_a[15] <= mux_83b:mux2.result[15]


|BeMicro_MAX10_top|dacrom:dacrom_inst|altsyncram:altsyncram_component|altsyncram_e4a1:auto_generated|decode_2j9:rden_decode
data[0] => eq_node[1].IN0
data[0] => eq_node[0].IN0
eq[0] <= eq_node[0].DB_MAX_OUTPUT_PORT_TYPE
eq[1] <= eq_node[1].DB_MAX_OUTPUT_PORT_TYPE


|BeMicro_MAX10_top|dacrom:dacrom_inst|altsyncram:altsyncram_component|altsyncram_e4a1:auto_generated|mux_83b:mux2
data[0] => result_node[0].IN1
data[1] => result_node[1].IN1
data[2] => result_node[2].IN1
data[3] => result_node[3].IN1
data[4] => result_node[4].IN1
data[5] => result_node[5].IN1
data[6] => result_node[6].IN1
data[7] => result_node[7].IN1
data[8] => result_node[8].IN1
data[9] => result_node[9].IN1
data[10] => result_node[10].IN1
data[11] => result_node[11].IN1
data[12] => result_node[12].IN1
data[13] => result_node[13].IN1
data[14] => result_node[14].IN1
data[15] => result_node[15].IN1
data[16] => result_node[0].IN1
data[17] => result_node[1].IN1
data[18] => result_node[2].IN1
data[19] => result_node[3].IN1
data[20] => result_node[4].IN1
data[21] => result_node[5].IN1
data[22] => result_node[6].IN1
data[23] => result_node[7].IN1
data[24] => result_node[8].IN1
data[25] => result_node[9].IN1
data[26] => result_node[10].IN1
data[27] => result_node[11].IN1
data[28] => result_node[12].IN1
data[29] => result_node[13].IN1
data[30] => result_node[14].IN1
data[31] => result_node[15].IN1
result[0] <= result_node[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= result_node[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= result_node[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= result_node[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= result_node[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= result_node[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= result_node[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= result_node[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= result_node[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= result_node[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= result_node[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= result_node[11].DB_MAX_OUTPUT_PORT_TYPE
result[12] <= result_node[12].DB_MAX_OUTPUT_PORT_TYPE
result[13] <= result_node[13].DB_MAX_OUTPUT_PORT_TYPE
result[14] <= result_node[14].DB_MAX_OUTPUT_PORT_TYPE
result[15] <= result_node[15].DB_MAX_OUTPUT_PORT_TYPE
sel[0] => result_node[15].IN0
sel[0] => _.IN0
sel[0] => result_node[14].IN0
sel[0] => _.IN0
sel[0] => result_node[13].IN0
sel[0] => _.IN0
sel[0] => result_node[12].IN0
sel[0] => _.IN0
sel[0] => result_node[11].IN0
sel[0] => _.IN0
sel[0] => result_node[10].IN0
sel[0] => _.IN0
sel[0] => result_node[9].IN0
sel[0] => _.IN0
sel[0] => result_node[8].IN0
sel[0] => _.IN0
sel[0] => result_node[7].IN0
sel[0] => _.IN0
sel[0] => result_node[6].IN0
sel[0] => _.IN0
sel[0] => result_node[5].IN0
sel[0] => _.IN0
sel[0] => result_node[4].IN0
sel[0] => _.IN0
sel[0] => result_node[3].IN0
sel[0] => _.IN0
sel[0] => result_node[2].IN0
sel[0] => _.IN0
sel[0] => result_node[1].IN0
sel[0] => _.IN0
sel[0] => result_node[0].IN0
sel[0] => _.IN0


