{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1461640564692 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition " "Version 15.0.0 Build 145 04/22/2015 Patches 0.01we SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1461640564707 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 25 23:16:04 2016 " "Processing started: Mon Apr 25 23:16:04 2016" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1461640564707 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1461640564707 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta testdac -c testdac " "Command: quartus_sta testdac -c testdac" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1461640564707 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #11" {  } {  } 0 0 "qsta_default_script.tcl version: #11" 0 0 "Quartus II" 0 0 1461640564770 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "8 8 " "Parallel compilation is enabled and will use 8 of the 8 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Quartus II" 0 -1 1461640564957 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1461640564988 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1461640564988 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz    " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz   " {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565426 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" {  } {  } 0 332166 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565426 ""}  } {  } 0 332165 "Entity %1!s!" 0 0 "Quartus II" 0 -1 1461640565426 ""}  } {  } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Quartus II" 0 -1 1461640565426 ""}
{ "Info" "ISTA_SDC_FOUND" "BeMicro_MAX10_top.sdc " "Reading SDC File: 'BeMicro_MAX10_top.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1461640565442 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565489 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Quartus II" 0 -1 1461640565489 ""}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565489 ""} { "Warning" "WSTA_GENERIC_WARNING" "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565489 ""} { "Warning" "WSTA_GENERIC_WARNING" "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[2\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[2\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565489 ""}  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565489 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640565505 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640565505 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Rise) SYS_CLK (Rise) setup and hold " "From SYS_CLK (Rise) to SYS_CLK (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640565505 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Fall) SYS_CLK (Rise) setup and hold " "From SYS_CLK (Fall) to SYS_CLK (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640565505 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Rise) SYS_CLK (Fall) setup and hold " "From SYS_CLK (Rise) to SYS_CLK (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640565505 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Fall) SYS_CLK (Fall) setup and hold " "From SYS_CLK (Fall) to SYS_CLK (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640565505 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1461640565505 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1461640565505 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1461640565520 ""}
{ "Info" "0" "" "Can't run Report Timing Closure Recommendations. The current device family is not supported." {  } {  } 0 0 "Can't run Report Timing Closure Recommendations. The current device family is not supported." 0 0 "Quartus II" 0 0 1461640565535 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.142 " "Worst-case setup slack is 3.142" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.142               0.000 SYS_CLK  " "    3.142               0.000 SYS_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   40.331               0.000 altera_reserved_tck  " "   40.331               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1461640565552 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.683 " "Worst-case hold slack is -0.683" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.683              -1.365 SYS_CLK  " "   -0.683              -1.365 SYS_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.458               0.000 altera_reserved_tck  " "    0.458               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640565552 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.692 " "Worst-case recovery slack is 47.692" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   47.692               0.000 altera_reserved_tck  " "   47.692               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.344 " "Worst-case removal slack is 1.344" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.344               0.000 altera_reserved_tck  " "    1.344               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.564 " "Worst-case minimum pulse width slack is 9.564" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.564               0.000 SYS_CLK  " "    9.564               0.000 SYS_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   37.667               0.000 USER_CLK  " "   37.667               0.000 USER_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.599               0.000 altera_reserved_tck  " "   49.599               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640565566 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1461640565598 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1461640565598 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1461640565629 ""}
{ "Warning" "WTAPI_PRELIMINARY_TIMING" "10M08DAF484C8GES " "Timing characteristics of device 10M08DAF484C8GES are preliminary" {  } {  } 0 334000 "Timing characteristics of device %1!s! are preliminary" 0 0 "Quartus II" 0 -1 1461640565629 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1461640566317 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566457 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Quartus II" 0 -1 1461640566457 ""}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566457 ""} { "Warning" "WSTA_GENERIC_WARNING" "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566457 ""} { "Warning" "WSTA_GENERIC_WARNING" "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[2\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[2\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566457 ""}  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566457 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566457 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566457 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Rise) SYS_CLK (Rise) setup and hold " "From SYS_CLK (Rise) to SYS_CLK (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566457 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Fall) SYS_CLK (Rise) setup and hold " "From SYS_CLK (Fall) to SYS_CLK (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566457 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Rise) SYS_CLK (Fall) setup and hold " "From SYS_CLK (Rise) to SYS_CLK (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566457 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Fall) SYS_CLK (Fall) setup and hold " "From SYS_CLK (Fall) to SYS_CLK (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566457 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1461640566457 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 3.562 " "Worst-case setup slack is 3.562" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566473 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566473 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    3.562               0.000 SYS_CLK  " "    3.562               0.000 SYS_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566473 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   40.730               0.000 altera_reserved_tck  " "   40.730               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566473 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640566473 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1461640566488 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.596 " "Worst-case hold slack is -0.596" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.596              -1.192 SYS_CLK  " "   -0.596              -1.192 SYS_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.411               0.000 altera_reserved_tck  " "    0.411               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566535 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640566535 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 47.818 " "Worst-case recovery slack is 47.818" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566535 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   47.818               0.000 altera_reserved_tck  " "   47.818               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566535 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640566535 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.254 " "Worst-case removal slack is 1.254" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    1.254               0.000 altera_reserved_tck  " "    1.254               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.574 " "Worst-case minimum pulse width slack is 9.574" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.574               0.000 SYS_CLK  " "    9.574               0.000 SYS_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   37.667               0.000 USER_CLK  " "   37.667               0.000 USER_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.621               0.000 altera_reserved_tck  " "   49.621               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640566551 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1461640566574 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1461640566575 ""}
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: altera_internal_jtag  from: tck  to: tckutap " "Cell: altera_internal_jtag  from: tck  to: tckutap" {  } {  } 0 332098 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566975 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Quartus II" 0 -1 1461640566975 ""}
{ "Warning" "WSTA_GENERIC_WARNING" "PLL cross checking found inconsistent PLL clock settings: " "PLL cross checking found inconsistent PLL clock settings:" { { "Warning" "WSTA_GENERIC_WARNING" "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[0\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566975 ""} { "Warning" "WSTA_GENERIC_WARNING" "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[1\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566975 ""} { "Warning" "WSTA_GENERIC_WARNING" "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[2\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000 " "Node: dac_clocks_inst\|altpll_component\|auto_generated\|pll1\|clk\[2\] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000" {  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566975 ""}  } {  } 0 332056 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566975 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566975 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566975 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Rise) SYS_CLK (Rise) setup and hold " "From SYS_CLK (Rise) to SYS_CLK (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566975 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Fall) SYS_CLK (Rise) setup and hold " "From SYS_CLK (Fall) to SYS_CLK (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566975 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Rise) SYS_CLK (Fall) setup and hold " "From SYS_CLK (Rise) to SYS_CLK (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566975 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "SYS_CLK (Fall) SYS_CLK (Fall) setup and hold " "From SYS_CLK (Fall) to SYS_CLK (Fall) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1461640566975 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1461640566975 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 7.433 " "Worst-case setup slack is 7.433" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566986 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566986 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    7.433               0.000 SYS_CLK  " "    7.433               0.000 SYS_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566986 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   46.454               0.000 altera_reserved_tck  " "   46.454               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640566986 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640566986 ""}
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" {  } {  } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1461640566995 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold -0.279 " "Worst-case hold slack is -0.279" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567007 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567007 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   -0.279              -0.558 SYS_CLK  " "   -0.279              -0.558 SYS_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567007 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.110               0.000 altera_reserved_tck  " "    0.110               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567007 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640567007 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 49.430 " "Worst-case recovery slack is 49.430" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567015 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567015 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.430               0.000 altera_reserved_tck  " "   49.430               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567015 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640567015 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.478 " "Worst-case removal slack is 0.478" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567026 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567026 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.478               0.000 altera_reserved_tck  " "    0.478               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567026 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640567026 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 9.218 " "Worst-case minimum pulse width slack is 9.218" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack       End Point TNS Clock  " "    Slack       End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    9.218               0.000 SYS_CLK  " "    9.218               0.000 SYS_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   37.667               0.000 USER_CLK  " "   37.667               0.000 USER_CLK " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567034 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.370               0.000 altera_reserved_tck  " "   49.370               0.000 altera_reserved_tck " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1461640567034 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1461640567034 ""}
{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." {  } {  } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1461640567051 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1461640567866 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1461640567866 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 37 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 37 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "798 " "Peak virtual memory: 798 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1461640568007 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 25 23:16:08 2016 " "Processing ended: Mon Apr 25 23:16:08 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1461640568007 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1461640568007 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1461640568007 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1461640568007 ""}
