Dist/0000700000175100010010000000000012151542740010141 5ustar RobNoneDist/makefile0000700000175100010010000001321012151540220011630 0ustar RobNonePROJECT := ks10 RTL := rtl ISE := ise XILDIR := `cygpath -u '$(XILINX)'` FUSE := $(XILDIR)/ISE_DS/ISE/bin/nt/fuse.exe WCFG := ks10_useriot.wcfg PRJFILE := $(PROJECT).prj TESTBENCH := $(PROJECT)_testbench WORK := work.testbench #LOAD := MAINDEC-10-DSKAA.SEQ #LOAD := MAINDEC-10-DSKAB.SEQ #LOAD := MAINDEC-10-DSKAC.SEQ #LOAD := MAINDEC-10-DSKAD.SEQ #LOAD := MAINDEC-10-DSKAE.SEQ #LOAD := MAINDEC-10-DSKAF.SEQ #LOAD := MAINDEC-10-DSKAG.SEQ #LOAD := MAINDEC-10-DSKAH.SEQ # runs 3.4 ms #LOAD := MAINDEC-10-DSKAI.SEQ #LOAD := MAINDEC-10-DSKAJ.SEQ #LOAD := MAINDEC-10-DSKAK.SEQ #LOAD := MAINDEC-10-DSKAL.SEQ #LOAD := MAINDEC-10-DSKAM.SEQ #LOAD := MAINDEC-10-DSKBA.SEQ # FAIL #LOAD := MAINDEC-10-DSKCA.SEQ #LOAD := MAINDEC-10-DSKCB.SEQ #LOAD := MAINDEC-10-DSKCC.SEQ #LOAD := MAINDEC-10-DSKCD.SEQ #LOAD := MAINDEC-10-DSKCE-RD00.SEQ LOAD := MAINDEC-10-DSKCF-RD00.SEQ #LOAD := MAINDEC-10-DSKEA-RD00.SEQ #LOAD := MAINDEC-10-DSDZA.SEQ #LOAD := fixed.SEQ #LOAD := MAINDEC-10-DSKCG.fixed.txt #LOAD := MAINDEC-10-DSKCG.txt #LOAD := smmon.txt SRC := \ $(RTL)/ks10/utils/utils.v \ $(RTL)/ks10/cpu/useq/crom.v \ $(RTL)/ks10/cpu/useq/drom.v \ $(RTL)/ks10/cpu/useq/skip.v \ $(RTL)/ks10/cpu/useq/stack.v \ $(RTL)/ks10/cpu/useq/dispatch.v \ $(RTL)/ks10/cpu/useq/useq.v \ $(RTL)/ks10/cpu/alu.v \ $(RTL)/ks10/cpu/apr.v \ $(RTL)/ks10/cpu/bus.v \ $(RTL)/ks10/cpu/byte_disp.v \ $(RTL)/ks10/cpu/dbm.v \ $(RTL)/ks10/cpu/dbus.v \ $(RTL)/ks10/cpu/debug.v \ $(RTL)/ks10/cpu/intf.v \ $(RTL)/ks10/cpu/intr.v \ $(RTL)/ks10/cpu/iolatch.v \ $(RTL)/ks10/cpu/ni_disp.v \ $(RTL)/ks10/cpu/pager.v \ $(RTL)/ks10/cpu/pcflags.v \ $(RTL)/ks10/cpu/pf_disp.v \ $(RTL)/ks10/cpu/pxct.v \ $(RTL)/ks10/cpu/ram1kx36.v \ $(RTL)/ks10/cpu/ramfile.v \ $(RTL)/ks10/cpu/regir.v \ $(RTL)/ks10/cpu/scad.v \ $(RTL)/ks10/cpu/timer.v \ $(RTL)/ks10/cpu/timing.v \ $(RTL)/ks10/cpu/vma.v \ $(RTL)/ks10/cpu/cpu.v \ $(RTL)/ks10/csl/csl.v \ $(RTL)/ks10/mem/mem.v \ $(RTL)/ks10/arb/arb.v \ $(RTL)/ks10/uba/dz11/uart/uart_brg.v \ $(RTL)/ks10/uba/dz11/uart/uart_rx.v \ $(RTL)/ks10/uba/dz11/uart/uart_tx.v \ $(RTL)/ks10/uba/dz11/uart/uart_bufrx.v \ $(RTL)/ks10/uba/dz11/uart/uart_buftx.v \ $(RTL)/ks10/uba/dz11/dzfifo.v \ $(RTL)/ks10/uba/dz11/dz11.v \ $(RTL)/ks10/uba/rh11/sd/sd.v \ $(RTL)/ks10/uba/rh11/sd/sdspi.v \ $(RTL)/ks10/uba/rh11/rpxx.v \ $(RTL)/ks10/uba/rh11/sdaddr.v \ $(RTL)/ks10/uba/rh11/rh11.v \ $(RTL)/ks10/uba/uba.v \ $(RTL)/ks10/ks10.v \ $(RTL)/esm/esm_csl.v \ $(RTL)/esm/esm_ks10.v \ $(RTL)/esm/esm_testbench.v # $(RTL)/uba/rh11/sd/sd.v \ INC := \ $(RTL)/ks10/cpu/useq/crom.vh \ $(RTL)/ks10/cpu/useq/drom.vh \ $(RTL)/ks10/cpu/alu.vh \ $(RTL)/ks10/cpu/apr.vh \ $(RTL)/ks10/cpu/pager.vh \ $(RTL)/ks10/cpu/pcflags.vh \ $(RTL)/ks10/cpu/pxct.vh \ $(RTL)/ks10/cpu/regir.vh \ $(RTL)/ks10/cpu/vma.vh \ $(RTL)/ks10/uba/dz11/uart/uart_brg.vh \ $(RTL)/ks10/uba/dz11/dz11.vh \ $(RTL)/ks10/uba/rh11/sd/sdspi.vh \ $(RTL)/ks10/uba/rh11/sd/sd.vh \ $(RTL)/ks10/uba/rh11/rpxx.vh \ $(RTL)/ks10/uba/rh11/rh11.vh \ $(RTL)/ks10/uba/uba.vh \ $(RTL)/ks10/ks10.vh DAT := \ $(RTL)/ks10/cpu/useq/crom.dat \ $(RTL)/ks10/cpu/useq/drom.dat \ $(RTL)/testbench/ssram.dat DOC := \ $(RTL)/status.txt UCF := \ $(RTL)/esm/esm_ks10.ucf BLD := \ $(ISE)/ks10.xise \ $(ISE)/ks10.gise \ $(ISE)/ks10.wcfg asdf : $(INC) $(SRC) $(BLD) $(DAT) $(UCF) $(DOC) echo $(INC) $(SRC) $(BLD) $(DAT) $(UCF) $(DOC) $(RTL)/ks10/cpu/useq/crom.dat : $(RTL)/ks10/cpu/useq/ks10.mcr $(RTL)/ks10/cpu/useq/crom.awk makefile awk -f $(RTL)/ks10/cpu/useq/crom.awk $(RTL)/ks10/cpu/useq/ks10.mcr > $(RTL)/ks10/cpu/useq/crom.dat $(RTL)/ks10/cpu/useq/drom.dat : $(RTL)/ks10/cpu/useq/ks10.mcr $(RTL)/ks10/cpu/useq/drom.awk makefile awk -f $(RTL)/ks10/cpu/useq/drom.awk $(RTL)/ks10/cpu/useq/ks10.mcr > $(RTL)/ks10/cpu/useq/drom.dat $(RTL)/testbench/ssram.dat : $(RTL)/testbench/$(LOAD) $(RTL)/testbench/ssram.awk makefile awk -f $(RTL)/testbench/ssram.awk -vfilename=$(LOAD) $(RTL)/testbench/$(LOAD) > $(RTL)/testbench/ssram.dat clean: rcsclean $(RTL)/* rcsclean $(RTL)/testbench/* rcsclean $(RTL)/esm/* rcsclean $(RTL)/ks10/* rcsclean $(RTL)/ks10/arb/* rcsclean $(RTL)/ks10/csl/* rcsclean $(RTL)/ks10/cpu/* rcsclean $(RTL)/ks10/mem/* rcsclean $(RTL)/ks10/utils/* rcsclean $(RTL)/ks10/uba/dz11/uart/* rcsclean $(RTL)/ks10/uba/dz11/* rcsclean $(RTL)/ks10/uba/rh11/sd/* rcsclean $(RTL)/ks10/uba/rh11/* rcsclean $(RTL)/ks10/uba/* rcsclean $(RTL)/ks10/cpu/useq/* rm -f $(RTL)/ks10/cpu/useq/*.dat rm -f $(RTL)/testbench/*.dat find . -type f -name "*~" | xargs rm -fv archive_src: $(SRC) tar -czvf ks10_src_`date '+%y%m%d'`.tgz $(SRC) archive_all: tar -czvf ks10_all_`date '+%y%m%d'`.tgz * $(ISE)/$(PRJFILE) : makefile echo "Creating "$(ISE)/$(PRJFILE) > /dev/stderr echo "" > $@; for FILE in $(SRC); \ do \ echo 'verilog work "../'$$FILE'"' >> $@; \ done $(ISE)/$(TESTBENCH) : $(ISE)/$(PRJFILE) makefile cd ise; \ $(FUSE) \ -intstyle ise \ -incremental \ -prj $(PRJFILE) \ -o $(TESTBENCH) \ work.testbench test : $(ISE)/$(TESTBENCH).exe $(ISE)/$(TESTBENCH).exe \ -gui \ -intstyle ise \ -tclbatch $(TESTBENCH).cmd \ -wdb $(TESTBENCH).wdb #./t10backup.exe -x smmon.sav -f ks_diag_gs.tap # -prj testbench_beh.prj \ # -lib unisims_ver \ # -lib unimacro_ver \ # -lib xilinxcorelib_ver \ # -lib secureip \ # echo 'verilog work "C:/Xilinx/13.1/ISE_DS/ISE//verilog/src/glbl.v"' >> $@ Dist/rtl/0000700000175100010010000000000012151542771010746 5ustar RobNoneDist/rtl/esm/0000700000175100010010000000000012151542757011536 5ustar RobNoneDist/rtl/esm/esm_csl.v0000700000175100010010000003176012151540232013346 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS10 Console Wrapper for the ESM Reference Design // // Details // // Console Control/Status register: // // The Console Control/Status register controls the operation // of the KS10 and allows the Console to be cognizant of the // status of the KS10 CPU. // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | |GO| |NX| |SR|SS|SE| // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) |SC|SH| |TE|RE|CE| |KI|KR| // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // GO : BUSY. Start Read or Write Transaction // NX : Non-existant memory timeout (Read Only) // SR : Run Switch (momentary) // SS : Single Step Switch (momentary) // SE : Execute Switch (momentary) // SC : Continue Switch (momentary) // SH : Halt Switch (momentary) // TE : Timer Enable // RE : Trap Enable // CE : Cache Enable // KI : KS10 Interrupt (momentary) // KR : KS10 Reset // // Note: // ALL INPUT SIGNALS AND OUTPUT SIGNALS TO THE KS10 MUST BE // SYNCHRONIZED TO THE CPU CLOCK. // // Note: // The Stellaris Microcontroller use little-endian notation where // bit 0 is the LSB. All of the KS10 signal use big-endian // notation where bit 0 is the MSB. // // File // esm_csl.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none module ESMCSL(RESET_N, clk, cslCLK, cslALE, cslAD, cslRD_N, cslWR_N, cslREGADDR, cslREGDATI, cslREGDATO, cslREGIR, cslBUSY, cslNXM, cslGO, cslSTEP, cslRUN, cslEXEC, cslCONT, cslHALT, cslTIMEREN, cslTRAPEN, cslCACHEEN, cslINTRO, cslRESET, rh11DEBUG, cpuHALT, cpuRUN, cpuEXEC, cpuCONT); input RESET_N; // Board Reset input clk; // Board Clock input cslCLK; // Console Clock input cslALE; // Console Address Latch Enable inout [7: 0] cslAD; // Console Multiplexed Address/Data Bus input cslRD_N; // Console Read Strobe input cslWR_N; // Console Write Strobe output [0:35] cslREGIR; // Console Instruction Register output [0:35] cslREGADDR; // Console Address Register input [0:35] cslREGDATI; // Console Data Register In output [0:35] cslREGDATO; // Console Data Register Out input cslBUSY; // Busy input cslNXM; // Nonexistent Memory or Device output cslGO; // GO output cslSTEP; // Step Switch output cslRUN; // Run Switch output cslEXEC; // Execute Switch output cslCONT; // Continue Switch output cslHALT; // Halt switch output cslTIMEREN; // Timer Enable output cslTRAPEN; // Trap Enable output cslCACHEEN; // Cache Enable output cslINTRO; // CSL Interrupt output cslRESET; // CSL Reset // RH11 input [0:35] rh11DEBUG; // RH11 Debug Info // CPU input cpuHALT; // CPU Halt Status input cpuRUN; // CPU Run Status input cpuEXEC; // CPU Exec Status input cpuCONT; // CPU Cont Status // // Input fixups // wire cslRD = ~cslRD_N; wire cslWR = ~cslWR_N; wire rst = ~RESET_N; // // Console Bus Address Latch // `ifdef ALESYNC reg [7:0] cslADDR; always @(posedge cslCLK) begin if (cslRST) cslADDR <= 0; else if (cslALE) cslADDR <= cslAD; end `else reg [7:0] cslADDR; always @(posedge cslALE) begin if (cslRST) cslADDR <= 0; else cslADDR <= cslAD; end `endif // // Synchronize RESET_N to cslCLK Clock Domain // reg cslRST; reg cslRSTD; always @(posedge cslCLK or posedge rst) begin if (rst) begin cslRSTD <= 1; cslRST <= 1; end else begin cslRSTD <= 0; cslRST <= cslRSTD; end end // // Synchronize inputs to the console clock domain // reg nxmd; reg busy; reg halted; reg [0:35] regDATID; reg [0:35] regDEBUG; always @(posedge cslCLK or posedge cslRST) begin if (cslRST) begin nxmd <= 0; busy <= 0; halted <= 0; regDATID <= 0; regDEBUG <= 0; end else begin nxmd <= cslNXM; busy <= cslBUSY; halted <= cpuHALT; regDATID <= cslREGDATI; regDEBUG <= rh11DEBUG; end end // // NXM/NXD // reg nxm; always @(posedge cslCLK or posedge cslRST) begin if (cslRST) nxm <= 0; else begin if (cslWR & (cslADDR == 8'h24) & cslAD[7]) nxm <= 0; else if (nxmd) nxm <= 1; end end // // Write Decoder // // Details: // This device decodes writes from the console processor and builds // 36-bit registers. // // Notes: // The status register is inititalized at power-up with the CSL reset. // // Notes: // This code contains an endian swap. // reg exec; reg timeren; reg trapen; reg cacheen; reg reset; reg [0:35] regIR; reg [0:35] regDATO; reg [0:35] regADDR; always @(posedge cslCLK or posedge cslRST) begin if (cslRST) begin regIR <= 0; regDATO <= 0; regADDR <= 0; exec <= 0; timeren <= 0; trapen <= 0; cacheen <= 0; reset <= 1; end else if (cslWR) // // Decode Write Address from Console Microcontroller // case (cslADDR) // // Address Register // 8'h03 : regADDR[ 0: 3] <= cslAD[3:0]; 8'h04 : regADDR[ 4:11] <= cslAD[7:0]; 8'h05 : regADDR[12:19] <= cslAD[7:0]; 8'h06 : regADDR[20:27] <= cslAD[7:0]; 8'h07 : regADDR[28:35] <= cslAD[7:0]; // // Data Register // 8'h13 : regDATO[ 0: 3] <= cslAD[3:0]; 8'h14 : regDATO[ 4:11] <= cslAD[7:0]; 8'h15 : regDATO[12:19] <= cslAD[7:0]; 8'h16 : regDATO[20:27] <= cslAD[7:0]; 8'h17 : regDATO[28:35] <= cslAD[7:0]; // // Control/Status Register // 8'h25 : begin exec <= cslAD[2]; end 8'h26 : begin timeren <= cslAD[2]; trapen <= cslAD[1]; cacheen <= cslAD[0]; end 8'h27 : begin reset <= cslAD[0]; end // // Console Instruction Register // 8'h33 : regIR[ 0: 3] <= cslAD[3:0]; 8'h34 : regIR[ 4:11] <= cslAD[7:0]; 8'h35 : regIR[12:19] <= cslAD[7:0]; 8'h36 : regIR[20:27] <= cslAD[7:0]; 8'h37 : regIR[28:35] <= cslAD[7:0]; endcase end // // Read Decoder // // Details: // This device decodes reads from the console processor and decodes // the 36-bit registers. // // Notes: // This code contains an endian swap. // reg [0:7] adOUT; always @(cslRD or cslADDR or regADDR or regDATID or regIR or regDEBUG or busy or nxm or halted or exec or timeren or trapen or cacheen or reset) begin // // Decode Read Address from Console Microcontroller // case (cslADDR) // // Address Register // 8'h03 : adOUT <= {4'b0, regADDR[0:3]}; 8'h04 : adOUT <= regADDR[ 4:11]; 8'h05 : adOUT <= regADDR[12:19]; 8'h06 : adOUT <= regADDR[20:27]; 8'h07 : adOUT <= regADDR[28:35]; // // Data Register // 8'h13 : adOUT <= {4'b0, regDATID[0:3]}; 8'h14 : adOUT <= regDATID[ 4:11]; 8'h15 : adOUT <= regDATID[12:19]; 8'h16 : adOUT <= regDATID[20:27]; 8'h17 : adOUT <= regDATID[28:35]; // // Control/Status Register // 8'h23 : adOUT <= {7'b0, busy}; 8'h24 : adOUT <= {7'b0, nxm}; 8'h25 : adOUT <= {3'b0, ~halted, 1'b0, exec, 1'b0, halted}; 8'h26 : adOUT <= {5'b0, timeren, trapen, cacheen}; 8'h27 : adOUT <= {7'b0, reset}; // // Console Instruction Register // 8'h33 : adOUT <= {4'b0, regIR[0:3]}; 8'h34 : adOUT <= regIR[ 4:11]; 8'h35 : adOUT <= regIR[12:19]; 8'h36 : adOUT <= regIR[20:27]; 8'h37 : adOUT <= regIR[28:35]; // // RH11 Debug Register // 8'hfb : adOUT <= {4'b0, regDEBUG[0:3]}; 8'hfc : adOUT <= regDEBUG[ 4:11]; 8'hfd : adOUT <= regDEBUG[12:19]; 8'hfe : adOUT <= regDEBUG[20:27]; 8'hff : adOUT <= regDEBUG[28:35]; // // Everything else // default : adOUT <= 0; endcase end // // Handle bi-directional bus output to Console Microcontroller // assign cslAD = (cslRD) ? adOUT : 8'bz; // // Synchronize outputs to the CPU clock domain. // // Notes: // This code contains an endian swap. // reg cslGO; reg cslSTEP; reg cslRUN; reg cslEXEC; reg cslCONT; reg cslHALT; reg cslTIMEREN; reg cslTRAPEN; reg cslCACHEEN; reg cslINTRO; reg cslRESET; reg [0:35] cslREGIR; reg [0:35] cslREGDATO; reg [0:35] cslREGADDR; always @(posedge clk or posedge rst) begin if (rst) begin cslGO = 0; cslSTEP = 0; cslRUN = 0; cslEXEC = 0; cslCONT = 0; cslHALT = 0; cslTIMEREN = 0; cslTRAPEN = 0; cslCACHEEN = 0; cslINTRO = 0; cslRESET = 0; cslREGIR = 0; cslREGDATO = 0; cslREGADDR = 0; end else begin cslGO = cslWR & (cslADDR == 8'h23) & cslAD[0]; cslRUN = cslWR & (cslADDR == 8'h25) & cslAD[4]; cslSTEP = cslWR & (cslADDR == 8'h25) & cslAD[3]; cslEXEC = exec; cslCONT = cslWR & (cslADDR == 8'h25) & cslAD[1]; cslHALT = cslWR & (cslADDR == 8'h25) & cslAD[0]; cslTIMEREN = timeren; cslTRAPEN = trapen; cslCACHEEN = cacheen; cslINTRO = cslWR & (cslADDR == 8'h27) & cslAD[1]; cslRESET = reset; cslREGIR = regIR; cslREGDATO = regDATO; cslREGADDR = regADDR; end end endmodule Dist/rtl/esm/esm_ks10.ucf0000700000175100010010000001133612151540236013654 0ustar RobNone# # KS10 FPGA # # # Clock Interface # NET "CLK50MHZ" LOC = "B12"; NET "CLK50MHZ" TNM_NET = CLK50MHZ; NET "CLK50MHZ" CLOCK_DEDICATED_ROUTE = FALSE; NET "CLK50MHZ" IOSTANDARD = LVCMOS33; TIMESPEC TS_clk = PERIOD "CLK50MHZ" 50 ns HIGH 40%; # # Reset # NET "RESET_N" LOC = "M24"; NET "RESET_N" IOSTANDARD = LVCMOS33; # # # NET "uCPU/uALU/r*" TIG; # # Console Bus # NET "cslALE" TNM_NET = cslALE; NET "cslALE" CLOCK_DEDICATED_ROUTE = FALSE; TIMESPEC TS_cslALE = PERIOD "cslALE" 100 ns HIGH 50%; INST "cslAD<0>" TNM = BUSIN; INST "cslAD<1>" TNM = BUSIN; INST "cslAD<2>" TNM = BUSIN; INST "cslAD<3>" TNM = BUSIN; INST "cslAD<4>" TNM = BUSIN; INST "cslAD<5>" TNM = BUSIN; INST "cslAD<6>" TNM = BUSIN; INST "cslAD<7>" TNM = BUSIN; INST "cslRD_N" TNM = BUSIN; INST "cslWR_N" TNM = BUSIN; TIMEGRP "BUSIN" OFFSET = IN 20 ns VALID 20 ns BEFORE "cslALE" RISING; # # SSRAM Interface # NET "ssramCLK" LOC = "AA18"; NET "ssramCLKEN" LOC = "AB17"; NET "ssramADV" LOC = "AC15"; NET "ssramBWA_N" LOC = "AA19"; NET "ssramBWB_N" LOC = "Y18"; NET "ssramBWC_N" LOC = "W17"; NET "ssramBWD_N" LOC = "AE21"; NET "ssramOE_N" LOC = "AC16"; NET "ssramWE_N" LOC = "AB18"; NET "ssramCE" LOC = "AF21"; NET "ssramADDR<0>" LOC = "V11"; NET "ssramADDR<1>" LOC = "U12"; NET "ssramADDR<2>" LOC = "AF5"; NET "ssramADDR<3>" LOC = "AE5"; NET "ssramADDR<4>" LOC = "AF6"; NET "ssramADDR<5>" LOC = "AE7"; NET "ssramADDR<6>" LOC = "AA11"; NET "ssramADDR<7>" LOC = "AB10"; NET "ssramADDR<8>" LOC = "AB11"; NET "ssramADDR<9>" LOC = "AA12"; NET "ssramADDR<10>" LOC = "V12"; NET "ssramADDR<11>" LOC = "AD6"; NET "ssramADDR<12>" LOC = "W12"; NET "ssramADDR<13>" LOC = "AD8"; NET "ssramADDR<14>" LOC = "AC9"; NET "ssramADDR<15>" LOC = "AF19"; NET "ssramADDR<16>" LOC = "AE19"; NET "ssramADDR<17>" LOC = "Y16"; NET "ssramADDR<18>" LOC = "AA14"; NET "ssramADDR<19>" LOC = "W16"; NET "ssramADDR<20>" LOC = "AD21"; NET "ssramADDR<21>" LOC = "Y10"; NET "ssramADDR<22>" LOC = "W11"; NET "ssramDATA<0>" LOC = "AA13"; NET "ssramDATA<1>" LOC = "AB13"; NET "ssramDATA<2>" LOC = "AC13"; NET "ssramDATA<3>" LOC = "AC12"; NET "ssramDATA<4>" LOC = "AD12"; NET "ssramDATA<5>" LOC = "AD11"; NET "ssramDATA<6>" LOC = "AC11"; NET "ssramDATA<7>" LOC = "AD10"; NET "ssramDATA<8>" LOC = "AD9"; NET "ssramDATA<9>" LOC = "AD19"; NET "ssramDATA<10>" LOC = "AC19"; NET "ssramDATA<11>" LOC = "AD18"; NET "ssramDATA<12>" LOC = "AD17"; NET "ssramDATA<13>" LOC = "AC17"; NET "ssramDATA<14>" LOC = "AD15"; NET "ssramDATA<15>" LOC = "AB15"; NET "ssramDATA<16>" LOC = "AC14"; NET "ssramDATA<17>" LOC = "AC20"; NET "ssramDATA<18>" LOC = "AE17"; NET "ssramDATA<19>" LOC = "AF17"; NET "ssramDATA<20>" LOC = "AF16"; NET "ssramDATA<21>" LOC = "AE15"; NET "ssramDATA<22>" LOC = "AF15"; NET "ssramDATA<23>" LOC = "AF14"; NET "ssramDATA<24>" LOC = "AD13"; NET "ssramDATA<25>" LOC = "AF13"; NET "ssramDATA<26>" LOC = "AF18"; NET "ssramDATA<27>" LOC = "AE13"; NET "ssramDATA<28>" LOC = "AF12"; NET "ssramDATA<29>" LOC = "AF11"; NET "ssramDATA<30>" LOC = "AE11"; NET "ssramDATA<31>" LOC = "AF10"; NET "ssramDATA<32>" LOC = "AF9"; NET "ssramDATA<33>" LOC = "AE9"; NET "ssramDATA<34>" LOC = "AF8"; NET "ssramDATA<35>" LOC = "AF7"; # # Console Interface # LM3S9B96 is configured for EPI Host Bus # HB8, Mode=ADMUX # NET "cslAD<0>" LOC = "AA26"; // EPI0S0 NET "cslAD<1>" LOC = "AE24"; // EPI0S1 NET "cslAD<2>" LOC = "W24"; // EPI0S2 NET "cslAD<3>" LOC = "AA23"; // EPI0S3 NET "cslAD<4>" LOC = "U26"; // EPI0S4 NET "cslAD<5>" LOC = "Y24"; // EPI0S5 NET "cslAD<6>" LOC = "AB26"; // EPI0S6 NET "cslAD<7>" LOC = "AC26"; // EPI0S7 NET "cslRD_N" LOC = "AA24"; // EPI0S28 NET "cslWR_N" LOC = "T26"; // EPI0S29 NET "cslALE" LOC = "AF24"; // EPI0S30 #NET "cslINTR_N" LOC = # # RS232 Interfaces # NET "TXD<1>" LOC = "D24"; NET "TXD<2>" LOC = "L25"; NET "RXD<1>" LOC = "J26"; NET "RXD<2>" LOC = "K26"; NET "CTS<1>" LOC = "F24"; NET "CTS<2>" LOC = "M26"; NET "RTS<1>" LOC = "J25"; NET "RTS<2>" LOC = "H24"; Dist/rtl/esm/esm_ks10.v0000700000175100010010000002267212151540232013345 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS10 Wrapper for the ESM Reference Design. // // Details // This wrapper allows the KS10 CPU Core to be customized for // various FPGA Evaluation Board. In this implmentation, the // Console Interface and the Memory Interface can be customized. // // The Console Interface is pretty generic. The Console // Implementation can range from a Microcontroller Interface like // the KS10 to a simple front panel with switches and lights like // the KA10 and KI10. // // File // esm_ks10.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none module ESM_KS10(CLK50MHZ, RESET_N, // DZ11 Interfaces TXD1, TXD2, RXD1, RXD2, RTS1, RTS2, CTS1, CTS2, // RH11 Interfaces rh11CD, rh11WP, rh11MISO, rh11MOSI, rh11SCLK, rh11CS, // Console Interfaces cslCLK, cslALE, cslAD, cslRD_N, cslWR_N, cslINTR_N, // SSRAM Interfaces ssramCLK, ssramCLKEN, ssramADV, ssramBWA_N, ssramBWB_N, ssramBWC_N, ssramBWD_N, ssramOE_N, ssramWE_N, ssramCE, ssramADDR, ssramDATA, runLED); input CLK50MHZ; // Clock input RESET_N; // Reset // DZ11 Interfaces input TXD1; // DZ11 RS-232 Transmitted Data #1 input TXD2; // DZ11 RS-232 Transmitted Data #2 output RXD1; // DZ11 RS-232 Received Data #1 output RXD2; // DZ11 RS-232 Received Data #2 input RTS1; // DZ11 RS-232 Request to Send #1 input RTS2; // DZ11 RS-232 Request to Send #2 output CTS1; // DZ11 RS-232 Clear to Send #1 output CTS2; // DZ11 RS-232 Clear to Send #2 // RH11 Interfaces input rh11CD; // RH11 Card Detect input rh11WP; // RH11 Write Protect input rh11MISO; // RH11 Data In output rh11MOSI; // RH11 Data Out output rh11SCLK; // RH11 Clock output rh11CS; // RH11 Chip Select // Console Interfaces input cslCLK; // Console Clock input cslALE; // Console Address Latch Enable inout [7: 0] cslAD; // Console Multiplexed Address/Data Bus input cslRD_N; // Console Read Strobe input cslWR_N; // Console Write Strobe output cslINTR_N; // Console Interrupt // SSRAM Interfaces output ssramCLK; // SSRAM Clock output ssramCLKEN; // SSRAM Clken output ssramADV; // SSRAM Advance output ssramBWA_N; // SSRAM BWA# output ssramBWB_N; // SSRAM BWB# output ssramBWC_N; // SSRAM BWC# output ssramBWD_N; // SSRAM BWD# output ssramOE_N; // SSRAM OE# output ssramWE_N; // SSRAM WE# output ssramCE; // SSRAM CE output [0:22] ssramADDR; // SSRAM Address Bus inout [0:35] ssramDATA; // SSRAM Data Bus // Misc output runLED; // RUN LED // // DZ-11 Interface Stubs // wire [7: 0] dz11CO = 8'hff; // DZ11 Carrier Input wire [7: 0] dz11RI = 8'h00; // DZ11 Ring Input wire [7: 0] dz11DTR; // DZ11 DTR Output wire [7: 0] dz11TXD; // DZ11 TXD wire [7: 0] dz11RXD; // DZ11 RXD // // Console Interfaces // wire [0:35] cslREGADDR; // Console Address Register wire [0:35] cslREGDATI; // Console Data Register In wire [0:35] cslREGDATO; // Console Data Register Out wire [0:35] cslREGIR; // Console Instruction Register wire cslSTEP; // Console Single Step Switch wire cslCONT; // Console Continue Switch wire cslRUN; // Console Run Switch wire cslEXEC; // Console Exec Switch wire cslHALT; // Console Halt Switch wire cslTRAPEN; // Console Trap Enable wire cslTIMEREN; // Console Timer Enable wire cslCACHEEN; // Console Cache Enable wire cslINTRI; // Console Interrupt In wire cslINTRO; // Console Interrupt Out wire cslRESET; // Console Reset wire cslBUSY; // Console Busy wire cslGO; // Console GO wire cslNXM; // Console NXM // // KS10 Outputs // wire cpuHALT; // CPU Halt wire cpuRUN; // CPU Run wire cpuEXEC; // CPU Exec wire cpuCONT; // CPU Cont // // RH11 Outputs // wire [0:35] rh11DEBUG; // // KS10 Processor // KS10 uKS10 (.clk (CLK50MHZ), .rst (~RESET_N), // DZ11 .dz11TXD (dz11TXD), .dz11RXD (dz11RXD), .dz11DTR (dz11DTR), .dz11CO (dz11CO), .dz11RI (dz11RI), // RH11 .rh11CD (rh11CD), .rh11WP (rh11WP), .rh11MISO (rh11MISO), .rh11MOSI (rh11MOSI), .rh11SCLK (rh11SCLK), .rh11CS (rh11CS), .rh11DEBUG (rh11DEBUG), // Console .cslREGADDR (cslREGADDR), .cslREGDATI (cslREGDATI), .cslREGDATO (cslREGDATO), .cslREGIR (cslREGIR), .cslBUSY (cslBUSY), .cslNXM (cslNXM), .cslGO (cslGO), .cslRESET (cslRESET), .cslSTEP (cslSTEP), .cslRUN (cslRUN), .cslEXEC (cslEXEC), .cslCONT (cslCONT), .cslHALT (cslHALT), .cslTIMEREN (cslTIMEREN), .cslTRAPEN (cslTRAPEN), .cslCACHEEN (cslCACHEEN), .cslINTRI (cslINTRI), .cslINTRO (cslINTRO), // CPU .cpuHALT (cpuHALT), .cpuRUN (cpuRUN), .cpuEXEC (cpuEXEC), .cpuCONT (cpuCONT), // Memory .ssramCLK (ssramCLK), .ssramCLKEN (ssramCLKEN), .ssramADV (ssramADV), .ssramBWA_N (ssramBWA_N), .ssramBWB_N (ssramBWB_N), .ssramBWC_N (ssramBWC_N), .ssramBWD_N (ssramBWD_N), .ssramOE_N (ssramOE_N), .ssramWE_N (ssramWE_N), .ssramCE (ssramCE), .ssramADDR (ssramADDR), .ssramDATA (ssramDATA) ); // // Console Wrapper // ESMCSL uESMCSL (.RESET_N (RESET_N), .clk (CLK50MHZ), .cslCLK (cslCLK), .cslALE (cslALE), .cslAD (cslAD), .cslRD_N (cslRD_N), .cslWR_N (cslWR_N), .cslREGADDR (cslREGADDR), .cslREGDATI (cslREGDATO), .cslREGDATO (cslREGDATI), .cslREGIR (cslREGIR), .cslBUSY (cslBUSY), .cslNXM (cslNXM), .cslGO (cslGO), .cslSTEP (cslSTEP), .cslRUN (cslRUN), .cslEXEC (cslEXEC), .cslCONT (cslCONT), .cslHALT (cslHALT), .cslTIMEREN (cslTIMEREN), .cslTRAPEN (cslTRAPEN), .cslCACHEEN (cslCACHEEN), .cslINTRO (cslINTRO), .cslRESET (cslRESET), .rh11DEBUG (rh11DEBUG), .cpuHALT (cpuHALT), .cpuRUN (cpuRUN), .cpuEXEC (cpuEXEC), .cpuCONT (cpuCONT) ); // // DZ11 Fixup // TXD is an output of the FT4232. RXD is an input to the // FT4232. Therefore must twist TXD and RXD here. // assign dz11RXD[1] = TXD2; assign dz11RXD[0] = TXD1; assign RXD2 = dz11TXD[1]; assign RXD1 = dz11TXD[0]; assign dz11RXD[7:2] = dz11TXD[7:2]; assign CTS2 = RTS2; assign CTS1 = RTS1; // // KS10 Interrupt fixup // assign cslINTR_N = ~cslINTRI; // // Run LED // assign runLED = cpuRUN; endmodule Dist/rtl/esm/esm_testbench.v0000700000175100010010000003141012151540232014534 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor Testbench // // Brief // // Details // // Todo // // File // testbench.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `undef SIMCTY `undef SIMSSMON `define EOF 32'hFFFF_FFFF `default_nettype none module testbench; // // Clock and things // reg clk; // Clock reg reset; // Reset wire runLED; // Run LED // // Console Interfaces // wire cslCLK = clk; // Console Clock wire [7:0] cslAD; // Multiplexed Address/Data Bus reg [7:0] cslADOUT; // Address/Data Bus Out wire [7:0] cslADIN; // Data Bus In reg cslALE; // Address Latch Enable reg cslRD_N; // Read Strobe reg cslWR_N; // Write Strobe wire cslINTR_N; // Console Interrupt wire cslINTR = ~cslINTR_N; // // DZ11 Serial Interface // wire TXD1 = 1; // DZ11 RS-232 Received Data #1 wire TXD2 = 1; // DZ11 RS-232 Received Data #2 wire RXD1; // DZ11 RS-232 Transmitted Data #1 wire RXD2; // DZ11 RS-232 Transmitted Data #2 wire RTS1 = 1; // DZ11 RS-232 Request to Send #1 wire RTS2 = 1; // DZ11 RS-232 Request to Send #2 wire CTS1; // DZ11 RS-232 Clear to Send #1 wire CTS2; // DZ11 RS-232 Clear to Send #2 // // RH11 Secure Digital Interface // wire rh11CD; // RH11 Card Detect wire rh11WP; // RH11 Write Protect wire rh11MISO; // RH11 Data In wire rh11MOSI; // RH11 Data Out wire rh11SCLK; // RH11 Clock wire rh11CS; // SD11 Chip Select // // SSRAM // wire ssramCLK; // SSRAM Clock wire [0:22] ssramADDR; // SSRAM Address Bus wire [0:35] ssramDATA; // SSRAM Data Bus wire ssramADV; // SSRAM Advance wire ssramWE_N; // SSRAM Write wire ssramOE_N; // SSRAM OE# wire ssramCE; // SSRAM CE wire ssramCLKEN; // SSRAM Clken wire ssramBWA_N; // SSRAM BWA# wire ssramBWB_N; // SSRAM BWB# wire ssramBWC_N; // SSRAM BWC# wire ssramBWD_N; // SSRAM BWD# // // Data to KS10 // parameter [0:35] valREGSTATUS = 36'o000005_003000; `ifdef SIMSSMON parameter [0:35] valREGCIR = 36'o254000_020000; `else // parameter [0:35] valREGCIR = 36'o254000_030601; // DSKAA-DSKAH parameter [0:35] valREGCIR = 36'o254000_030010; // DSKAI-DSKAM,DSKCF, DSKEA // parameter [0:35] valREGCIR = 36'o254000_030660; // parameter [0:35] valREGCIR = 36'o254000_030620; // DSKCG // parameter [0:35] valREGCIR = 36'o254000_030622; // parameter [0:35] valREGCIR = 36'o254000_020000; // DSQDC `endif // // Register Addresses // parameter [7:0] addrREGADDR = 8'h00; parameter [7:0] addrREGDATA = 8'h10; parameter [7:0] addrREGSTATUS = 8'h20; parameter [7:0] addrREGCIR = 8'h30; // // Task to write to KS10 memory // // Details // Write address. Write data. // task cslWRKS10MEM; input [18:35] address; input [ 0:35] data; begin cslWRITE (addrREGADDR, {18'o010000, address}); cslWRITE (addrREGDATA, data); cslWRITEb(addrREGSTATUS+3, 8'h01); end endtask // // Task to read from KS10 memory // task cslRDKS10MEM; input [18:35] address; output [ 0:35] data; begin cslWRITE (addrREGADDR, {18'o040000, address}); cslWRITEb(addrREGSTATUS+3, 8'h01); #40; cslREAD (addrREGDATA, data); end endtask // // Task to write a word to console register // // Note: // A 36-bit write requires 5 byte operations. // task cslWRITE; input [7: 0] addr; input [0:35] data; begin cslWRITEb(addr+3, {4'b0, data[0:3]}); cslWRITEb(addr+4, data[ 4:11]); cslWRITEb(addr+5, data[12:19]); cslWRITEb(addr+6, data[20:27]); cslWRITEb(addr+7, data[28:35]); #100; end endtask // // Task to read word from console register // // Note: // A 36-bit read requires 5 byte operations. // task cslREAD; input [7:0] addr; output reg [0:35] data; begin cslREADb(addr+3, data[ 0: 3]); cslREADb(addr+4, data[ 4:11]); cslREADb(addr+5, data[12:19]); cslREADb(addr+6, data[20:27]); cslREADb(addr+7, data[28:35]); #100; end endtask // // Task to write byte to console register // task cslWRITEb; input [7:0] addr; input [7:0] data; begin #50 cslADOUT = addr; #5 cslALE = 1; #5 cslADOUT = data; #5 cslALE = 0; #5 cslWR_N = 0; #50 cslWR_N = 1; end endtask // // Task to read byte from console register // task cslREADb; input [7:0] addr; output reg [7:0] data; begin #5 cslADOUT = addr; #5 cslALE = 1; #5 cslALE = 0; #5 cslRD_N = 0; #25 data = cslAD; #25 cslRD_N = 1; end endtask // // Initialization // reg [0:35] temp; initial begin $display("KS10 Simulation Starting"); // // Initial state // clk = 0; reset = 1; cslALE = 0; cslWR_N = 1; cslRD_N = 1; // // Release reset at 95 nS // #95 reset = 1'b0; // // Write to Console Instruction Register // cslWRITE(addrREGCIR, valREGCIR); // // Write to Control/Status Register // Set EXEC, RUN, and release RESET // cslWRITE(addrREGSTATUS, valREGSTATUS); // // Readback Console Instruction Register // cslREAD(addrREGCIR, temp); // // Initialize Console Status // cslWRKS10MEM(18'o000031, 36'b0); cslWRKS10MEM(18'o000036, 36'b0); cslWRKS10MEM(18'o025741, 36'b0); cslWRKS10MEM(18'o026040, 36'b0); cslWRKS10MEM(18'o030024, 36'b0); cslWRKS10MEM(18'o030037, 36'b0); end // // Clock generator // // Details // Clock is inverted every ten nS // always begin #10 clk = ~clk; end assign cslAD = (~cslRD_N) ? 8'bz : cslADOUT; // // KS10 // ESM_KS10 uKS10 (.CLK50MHZ (clk), .RESET_N (~reset), // DZ11 Interfaces .TXD1 (TXD1), .TXD2 (TXD2), .RXD1 (RXD1), .RXD2 (RXD2), .RTS1 (RTS1), .RTS2 (RTS2), .CTS1 (CTS1), .CTS2 (CTS2), // RH11 Interfaces .rh11CD (rh11CD), .rh11WP (rh11WP), .rh11MISO (rh11MISO), .rh11MOSI (rh11MOSI), .rh11SCLK (rh11SCLK), .rh11CS (rh11CS), // Console Interfaces .cslCLK (cslCLK), .cslALE (cslALE), .cslAD (cslAD), .cslRD_N (cslRD_N), .cslWR_N (cslWR_N), .cslINTR_N (cslINTR_N), // SSRAM Interfaces .ssramCLK (ssramCLK), .ssramCLKEN (ssramCLKEN), .ssramADV (ssramADV), .ssramBWA_N (ssramBWA_N), .ssramBWB_N (ssramBWB_N), .ssramBWC_N (ssramBWC_N), .ssramBWD_N (ssramBWD_N), .ssramOE_N (ssramOE_N), .ssramWE_N (ssramWE_N), .ssramCE (ssramCE), .ssramADDR (ssramADDR), .ssramDATA (ssramDATA), .runLED (runLED) ); // // Display run/halt status // always @(negedge runLED) $display("KS10 CPU Halted at t = %f us.", $time / 1.0e3); always @(posedge runLED) $display("KS10 CPU Unhalted at t = %f us", $time / 1.0e3); // // Handle Startup. // // Details // The Microcode will always halt at startup. Catch the halt // at startup (only). When this occurs momentarily push the // continue button to continue execution. Otherwise let the // KS10 halt. // always @(negedge runLED) begin if ($time > 13000 && $time < 15000) begin cslWRITEb(8'h25, 8'h16); cslWRITEb(8'h25, 8'h14); end end // // PDP10 Memory Initialization // // Note: // We initialize the PDP10 memory with the diagnostic // code. This saves having to figure out how to load // the code into memory by some other means. // // Object code is extracted from the listing file by a // 'simple' AWK script and is included below. // reg [0:35] SSRAM [0:32767]; initial begin `include "../testbench/ssram.dat" end // // Synchronous RAM // // Details // This is KS10 memory. // // Note: // Only 32K is implemented. This is sufficient to run the // MAINDEC diagnostics. Adding more memory makes the // simulation run very slow. // // FIXME // This is temporary // reg [0:14] rd_addr; wire [0:14] wr_addr = ssramADDR[8:22]; always @(negedge clk or posedge reset) begin if (reset) ; else if (~ssramWE_N) SSRAM[wr_addr] <= ssramDATA; rd_addr <= wr_addr; end assign ssramDATA = (ssramWE_N) ? SSRAM[rd_addr] : 36'bz; `ifdef SIMCTY // // File IO // integer cty_ofile; integer cty_ifile; initial begin cty_ofile = $fopen("cty_out.txt", "w"); cty_ifile = $fopen("cty_in.txt", "r"); #1500000; $fclose(cty_ofile); $fclose(cty_ifile); $finish; end // // CTY Output Processing // // Note: // A Console Interrupt (cslINTR asserted) may indicate that a // character is available to print or that a character can be // accepted by the KS10, or both, or neither. // reg [0:35] dataCOUT; parameter [18:35] addrCOUT = 18'o000033; always @(posedge clk or posedge reset) begin if (reset) dataCOUT <= 36'b0; else if (cslINTR) begin //$display("KS10 CPU has interrupted the console at t = %f us", $time / 1.0e3); // // Read CTYOUT Memory Location // cslRDKS10MEM(addrCOUT, dataCOUT); // // Print character if character is available. // Zero the flag when done printing. // if (dataCOUT[27]) begin if ((dataCOUT[28:35] >= 8'h20) && (dataCOUT[28:35] < 8'h7f)) $display("KS10 CTY Output: \"%s\"", dataCOUT[28:35]); else $display("KS10 CTY Output: \"%02x\"", dataCOUT[28:35]); $fwrite(cty_ofile, "%s", dataCOUT[28:35]); cslWRKS10MEM(addrCOUT, 36'b0); end end end `endif endmodule Dist/rtl/ks10/0000700000175100010010000000000012151543322011515 5ustar RobNoneDist/rtl/ks10/arb/0000700000175100010010000000000012151543053012262 5ustar RobNoneDist/rtl/ks10/arb/arb.v0000700000175100010010000002407412151540230013221 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS10 Bus Arbiter // // Details // This device is the KS10 Bus Arbiter and Bus Multiplexer // // File // arb.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `include "../cpu/vma.vh" module ARB(clk, cpuREQI, cpuACKO, cpuADDRI, cpuDATAI, cpuDATAO, cslREQI, cslREQO, cslACKI, cslACKO, cslADDRI, cslDATAI, cslDATAO, ubaREQI, ubaREQO, ubaACKI, ubaACKO, uba0ADDRI, uba1ADDRI, uba2ADDRI, uba3ADDRI, uba0DATAI, uba1DATAI, uba2DATAI, uba3DATAI, ubaDATAO, memREQO, memACKI, memDATAI, memDATAO, arbADDRO); input clk; // Clock input cpuREQI; // CPU Bus Request output cpuACKO; // CPU Bus Acknowledge input [0:35] cpuADDRI; // CPU Address input [0:35] cpuDATAI; // CPU Data In output [0:35] cpuDATAO; // CPU Data Out input cslREQI; // CSL Bus Request In output cslREQO; // CSL Bus Request Out input cslACKI; // CSL Bus Acknowledge In output cslACKO; // CSL Bus Acknowledge Out input [0:35] cslADDRI; // CSL Address In input [0:35] cslDATAI; // CSL Data In output [0:35] cslDATAO; // CSL Data Out input [0: 3] ubaREQI; // UBA Bus RequestIn output ubaREQO; // UBA Bus Request Out input [0: 3] ubaACKI; // UBA Bus Acknowledge In output [0: 3] ubaACKO; // UBA Bus Acknowledge Out input [0:35] uba0ADDRI; // UBA 0 Address In input [0:35] uba1ADDRI; // UBA 1 Address In input [0:35] uba2ADDRI; // UBA 2 Address In input [0:35] uba3ADDRI; // UBA 3 Address In input [0:35] uba0DATAI; // UBA 0 Data In input [0:35] uba1DATAI; // UBA 1 Data In input [0:35] uba2DATAI; // UBA 2 Data In input [0:35] uba3DATAI; // UBA 3 Data In output [0:35] ubaDATAO; // UBA Data Out output memREQO; // MEM Bus Request Out input memACKI; // MEM Bus Acknowledge In input [0:35] memDATAI; // MEM Data In output [0:35] memDATAO; // MEM Data Out output [0:35] arbADDRO; // ARB Address // // Bus Address Flags // wire vmaPHYSICAL = `vmaPHYSICAL(cpuADDRI); wire vmaIOCYCLE = `vmaIOCYCLE(cpuADDRI); wire vmaVECTORCYCLE = `vmaVECTORCYCLE(cpuADDRI); wire vmaWRUCYCLE = `vmaWRUCYCLE(cpuADDRI); // // Build Vector // wire [0:35] ubaADDR[0:3] = {uba0ADDRI, uba1ADDRI, uba2ADDRI, uba3ADDRI}; wire [0:35] ubaDATA[0:3] = {uba0DATAI, uba1DATAI, uba2DATAI, uba3DATAI}; // // Bus Request Arbitration // // Details: // Console has highest priority // Unibus has next priority // CPU has lowest priority // reg cpuACKO; reg cslACKO; reg cslREQO; reg memREQO; reg ubaREQO; reg [0: 3] ubaACKO; reg [0:35] cslDATAO; reg [0:35] cpuDATAO; reg [0:35] memDATAO; reg [0:35] ubaDATAO; reg [0:35] arbADDRO; always @(cpuREQI or cpuADDRI or cpuDATAI or cpuDATAO or cslREQI or cslACKI or cslADDRI or cslDATAI or ubaREQI or ubaACKI or ubaADDR[0] or ubaADDR[1] or ubaADDR[2] or ubaADDR[3] or ubaDATA[0] or ubaDATA[1] or ubaDATA[2] or ubaDATA[3] or memACKI or memDATAI or vmaPHYSICAL or vmaIOCYCLE or vmaWRUCYCLE) begin cpuACKO = 0; cslREQO = 0; cslACKO = 0; ubaREQO = 0; ubaACKO = 0; memREQO = 0; arbADDRO = 36'b0; cslDATAO = 36'bx; cpuDATAO = 36'bx; memDATAO = 36'bx; ubaDATAO = 36'bx; // // Bus Request from the Console // // Details // The console can access the memory or the unibus // if (cslREQI) begin ubaREQO = 1; memREQO = 1; arbADDRO = cslADDRI; cpuDATAO = cslDATAI; memDATAO = cslDATAI; ubaDATAO = cslDATAI; if (memACKI) begin cslACKO = 1; cslDATAO = memDATAI; end else if (ubaACKI[0]) begin cslACKO = 1; cslDATAO = ubaDATA[0]; end else if (ubaACKI[1]) begin cslACKO = 1; cslDATAO = ubaDATA[1]; end else if (ubaACKI[2]) begin cslACKO = 1; cslDATAO = ubaDATA[2]; end else if (ubaACKI[3]) begin cslACKO = 1; cslDATAO = ubaDATA[3]; end end // // Bus Request from the Unibus #0 // // Details // The unibus can access the memory // else if (ubaREQI[0]) begin memREQO = 1; arbADDRO = ubaADDR[0]; cslDATAO = ubaDATA[0]; cpuDATAO = ubaDATA[0]; memDATAO = ubaDATA[0]; if (memACKI) begin ubaACKO[0] = 1; ubaDATAO = memDATAI; end end // // Bus Request from the Unibus #1 // // Details // The unibus can access the memory // else if (ubaREQI[1]) begin memREQO = 1; arbADDRO = ubaADDR[1]; cslDATAO = ubaDATA[1]; cpuDATAO = ubaDATA[1]; memDATAO = ubaDATA[1]; if (memACKI) begin ubaACKO[1] = 1; ubaDATAO = memDATAI; end end // // Bus Request from the Unibus #2 // // Details // The unibus can access the memory // else if (ubaREQI[2]) begin memREQO = 1; arbADDRO = ubaADDR[2]; cslDATAO = ubaDATA[2]; cpuDATAO = ubaDATA[2]; memDATAO = ubaDATA[2]; if (memACKI) begin ubaACKO[2] = 1; ubaDATAO = memDATAI; end end // // Bus Request from the Unibus #3 // // Details // The unibus can access the memory // else if (ubaREQI[3]) begin memREQO = 1; arbADDRO = ubaADDR[3]; cslDATAO = ubaDATA[3]; cpuDATAO = ubaDATA[3]; memDATAO = ubaDATA[3]; if (memACKI) begin ubaACKO[3] = 1; ubaDATAO = memDATAI; end end // // Bus Request from the CPU // // Details // The CPU can access the memory, unibus or // console. // else if (cpuREQI) begin cslREQO = 1; ubaREQO = 1; memREQO = 1; arbADDRO = cpuADDRI; cslDATAO = cpuDATAI; memDATAO = cpuDATAI; ubaDATAO = cpuDATAI; if (memACKI) begin cpuACKO = 1; cpuDATAO = memDATAI; end else if (ubaACKI[0]) begin cpuACKO = 1; cpuDATAO = ubaDATA[0]; end else if (ubaACKI[1]) begin cpuACKO = 1; cpuDATAO = ubaDATA[1]; end else if (ubaACKI[2]) begin cpuACKO = 1; cpuDATAO = ubaDATA[2]; end else if (ubaACKI[3]) begin cpuACKO = 1; cpuDATAO = ubaDATA[3]; end else if (cslACKI) begin cpuACKO = 1; cpuDATAO = cslDATAI; end // // Ack an otherwise un-acked WRU cycle // WRU Cycles really aren't arbitrated. // else if (vmaPHYSICAL & vmaIOCYCLE & vmaWRUCYCLE) begin cpuACKO = 1; cpuDATAO = 36'b0; end end end // // Whine about unacked bus cycles // `ifndef SYNTHESIS always @(posedge clk) begin if (cpuREQI & ~cpuACKO) begin $display(""); $display("Unacknowledged bus cycle. Addr Bus = %012o", cpuADDRI); $display(""); end end `endif endmodule Dist/rtl/ks10/cpu/0000700000175100010010000000000012151543346012312 5ustar RobNoneDist/rtl/ks10/cpu/alu.v0000700000175100010010000007325012151540224013264 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // AM2901 ALU // // Details // // Note // The KS10 ALU implementation uses ten cascaded am2901 4-bit // slices. Some quick study showed that this did not work // well with an FPGA implemenation. Most FPGAs have optimized // (very fast) carry logic to support counters and adders. It // turns out that the synthesis tools can't infer from the // description of the 4-bit slices that a single 40-bit carry // chain exists from the LSB to the MSB. Therefore this ALU // is implemented as two 20-bit ALUs. The two 20-bit ALUs // are required because the two ALU halves must operate // together forming a single 40-bit ALU and must operate // separately to form two independant registers. // // Note // The ALU bit numbering on the schematic is [-2,-1,0:37]. // This doesn't work at all for verilog. Therefore the // bit numbering is [0:39]. // // File // alu.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "useq/crom.vh" module ALU(clk, rst, clken, crom, aluIN, aluFLAGS, aluOUT, debugADDR, debugDATA); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock enable input [0:cromWidth-1] crom; // Control ROM Data input [0:35] aluIN; // Bus input output [0: 8] aluFLAGS; // ALU Flags output [0:35] aluOUT; // ALU Output input [0: 3] debugADDR; // DEBUG Address output [0:35] debugDATA; // DEBUG Data // // Microcode fields // // Note // These temporaries are created so I can see the microcode fields // in the simulator. The synthesis optimizer deletes them. // reg [0:39] f; // ALU Output reg [0:39] q; // Q Register Output wire [0: 2] fun = `cromFUN; // ALU Function wire [0: 2] lsrc = `cromLSRC; // ALU Source (Left Side) wire [0: 2] rsrc = `cromRSRC; // ALU Source (Right Size) wire [0: 2] dst = `cromDST; // ALU Destination wire lclken = `cromLCLKEN; // ALU CLock (Left Side) wire rclken = `cromRCLKEN; // ALU Clock (Right Side) wire [0: 3] aa = `cromALU_A; // ALU DPRAM A Address wire [0: 3] ba = `cromALU_B; // ALU DPRAM B Address wire [0: 2] shstyle = `cromSPEC_SHSTYLE; // ALU Shift Mode // // Carry Inhibit // // Details // Inhibit the carry from right half of the ALU to left half of // the ALU // wire specCRY18INH = `cromSPEC_EN_40 & (`cromSPEC_SEL == `cromSPEC_SEL_CRY18INH); // // ALU Register Write // // Note // The following ALU destinations write data into the ALU // registers. // wire write = ((dest ==`cromDST_RAMA) || (dest ==`cromDST_RAMF) || (dest ==`cromDST_RAMQD) || (dest ==`cromDST_RAMQU) || (dest ==`cromDST_RAMD) || (dest ==`cromDST_RAMU)); // // Destination Address Munging // // Note // DST[1] is inverted. // // When the ALU is configured for shift operations, the dst[1] // signal selects between right shifts and left shifts. // // In the KS10, the dst[1] selects tri-state muxes that // implement the right-shift and left-shift operations. // This isn't necessary on the FPGA implementation because // there aren't any tristate pins on the ALU. I just don't // want to change the microcode. So it stays. // // Trace // DPE5/E62 // wire [0:2] dest = {dst[0], ~dst[1], dst[2]}; // // Function Munging // // Note // FUN[2] is munged on DPE5 // // When fun[0] and fun[1] are both zero, fun[2] selects // between add and subract operations. This is used in // the divide implementation and the multiprecision // operations. // // Trace // DPE5/E62 // DPE5/E5 // wire [0:2] func = {fun[0], fun[1], funct_02}; // // Input Sign Extension // // Details // The ALU is 40-bits wide. The input is sign extended from // 36 bits to 38 bits and two bits of zero padding are added to // the right. // // Trace // DPE1/E29 (MSB/Sign Extension) // DPE2/E157 (LSB/Zero pad) // wire [0:39] dd = {aluIN[0], aluIN[0], aluIN[0:35], 2'b00}; // // Shifter Operations: // // Details // The am2901s are wired together to perform specific shift // operation controlled by the cromSPEC_SHSTYLE microcode // field. The ASCII art pictures below detail the various // shifter modes. // // Note // All of the F shifter logic is external to the am2901s. // // Shift Left Operations // // +--------- F shifter --------+ +--------- Q shifter --------+ // | | | | // // multi_shift // | // +----+ +----------+ | +----+ +----------+ // NORM |0123|<------|4 39|<-+ |0123|<------|4 39|<---- 0 // +----+ +----------+ +----+ +----------+ // // +------+ // | | // +----+ | +----------+ +----+ +----------+ // ZER0 |0123|<-+ |4 39|<---- 0 |0123|<------|4 39|<---- 0 // +----+ +----------+ +----+ +----------+ // // +------+ // | | // +----+ | +----------+ +----+ +----------+ // ONES |0123|<-+ |4 39|<---- 1 |0123|<------|4 39|<---- 1 // +----+ +----------+ +----+ +----------+ // // +------+ +---------------+ +---------------+ // | | | | | | // +----+ | | +----------+ | +----+ | +----------+ | // ROT |0123|<-+ +-|4 39|<-+ |0123|<----+-|4 39|<-+ // +----+ +----------+ +----+ +----------+ // // +------+ // | | // +----+ | +----------+ +----+ +----------+ // ASHC |0123|<-+ |4 39|<----+ |0123|<----+-|4 39|<---- 0 // +----+ +----------+ | +----+ | +----------+ // | | // +-----------------+ // // +----+ +----------+ +----+ +----------+ // LSHC |0123|<------|4 39|<----+ |0123|<----+-|4 39|<---- 0 // +----+ +----------+ | +----+ | +----------+ // | | // +-----------------+ // // +----+ +----------+ +----+ +----------+ // DIV |0123|<------|4 39|<----+ |0123|<----+-|4 39|<---- divide_shift // +----+ +----------+ | +----+ | +----------+ // | | // +-----------------+ // // +------+ +----------------------------------------------------+ // | | | | // +----+ | | +----------+ +----+ +----------+ | // ROTC |0123|<-+ +-|4 39|<----+ |0123|<----+-|4 39|<-+ // +----+ +----------+ | +----+ | +----------+ // | | // +-----------------+ // // Shift Right Operations // // +--------- F shifter --------+ +--------- Q shifter --------+ // | | | | // // +---+ 0 // | | | // | +----+ +----------+ | +----+ +----------+ // NORM +->|0123|------>|4 39| +->|0123|------>|4 39| // +----+ +----------+ +----+ +----------+ // // +---+ 0 0 0 // | | | | | // | +----+ | +----------+ | +----+ | +----------+ // ZEROS +->|0123| +->|4 39| +->|0123| +->|4 39| // +----+ +----------+ +----+ +----------+ // // +---+ 1 0 1 // | | | | | // | +----+ | +----------+ | +----+ | +----------+ // ONES +->|0123| +->|4 39| +->|0123| +->|4 39| // +----+ +----------+ +----+ +----------+ // // +---+ +---------------+ 0 +---------------+ // | | | | | | | // | +----+ | +----------+ | | +----+ | +----------+ | // ROT +->|0123| +->|4 39|-+ +->|0123| +->|4 39|-+ // +----+ +----------+ +----+ +----------+ // // +---+ 0 // | | | // | +----+ +----------+ | +----+ +----------+ // ASHC +->|0123|------>|4 39|-----+ +->|0123| +->|4 39| // +----+ +----------+ | +----+ | +----------+ // | | // +----------------+ // // +---+ 0 0 // | | | | // | +----+ | +----------+ | +----+ +----------+ // LSHC +->|0123| +->|4 39|-----+ +->|0123| +->|4 39| // +----+ +----------+ | +----+ | +----------+ // | | // +----------------+ // // +---+ 1 0 // | | | | // | +----+ | +----------+ | +----+ +----------+ // DIV +->|0123| +->|4 39|-----+ +->|0123| +->|4 39| // +----+ +----------+ | +----+ | +----------+ // | | // +----------------+ // // +---+ +----------------------------------------------------+ // | | | 0 | // | +----+ | +----------+ | +----+ +----------+ | // ROTC +->|0123| +->|4 39|-----+ +->|0123| +->|4 39|-+ // +----+ +----------+ | +----+ | +----------+ // | | // +----------------+ // Trace: // DPE1/E12 // DPE1/E20 // DPE1/E41 // DPE1/E48 // DPE1/E71 // reg [0:39] bdi; always @(f or q or dest or shstyle or multi_shift) begin if (dest == `cromDST_RAMQU || dest == `cromDST_RAMU) case (shstyle) `cromSPEC_SHSTYLE_NORM: bdi = {f[1:3], f[4], f[5:39], multi_shift}; `cromSPEC_SHSTYLE_ZERO: bdi = {f[1:3], f[0], f[5:39], 1'b0}; `cromSPEC_SHSTYLE_ONES: bdi = {f[1:3], f[0], f[5:39], 1'b1}; `cromSPEC_SHSTYLE_ROT: bdi = {f[1:3], f[0], f[5:39], f[4]}; `cromSPEC_SHSTYLE_ASHC: bdi = {f[1:3], f[0], f[5:39], q[4]}; `cromSPEC_SHSTYLE_LSHC: bdi = {f[1:3], f[4], f[5:39], q[4]}; `cromSPEC_SHSTYLE_DIV: bdi = {f[1:3], f[4], f[5:39], q[4]}; `cromSPEC_SHSTYLE_ROTC: bdi = {f[1:3], f[0], f[5:39], q[4]}; endcase else if (dest == `cromDST_RAMQD || dest == `cromDST_RAMD) case (shstyle) `cromSPEC_SHSTYLE_NORM: bdi = {f[0], f[0:2], f[3], f[4:38]}; `cromSPEC_SHSTYLE_ZERO: bdi = {f[0], f[0:2], 1'b0, f[4:38]}; `cromSPEC_SHSTYLE_ONES: bdi = {f[0], f[0:2], 1'b1, f[4:38]}; `cromSPEC_SHSTYLE_ROT: bdi = {f[0], f[0:2], f[39], f[4:38]}; `cromSPEC_SHSTYLE_ASHC: bdi = {f[0], f[0:2], f[3], f[4:38]}; `cromSPEC_SHSTYLE_LSHC: bdi = {f[0], f[0:2], 1'b0, f[4:38]}; `cromSPEC_SHSTYLE_DIV: bdi = {f[0], f[0:2], 1'b1, f[4:38]}; `cromSPEC_SHSTYLE_ROTC: bdi = {f[0], f[0:2], q[39], f[4:38]}; endcase else bdi = f; end // // ALU RAM Write Port // // Note // The left side and right side of the ALU can be independantly // clocked and updated. // reg [0:39] aluRAM [0:15]; always @(posedge clk or posedge rst) begin if (rst) ; else if (clken) begin if (lclken & write) aluRAM[ba][ 0:19] <= bdi[ 0:19]; if (rclken & write) aluRAM[ba][20:39] <= bdi[20:39]; end end // // ALU RAM Read Port(s) // // Details // The am2901 latches the addresses when the clock is low. These latches // would be a problem for an FPGA design. Latching the address lines is // not necessary anyway because the RAM address lines come directly from // the CROM which is already registered. We'll abosorb the address latch // into the CROM register. // // Note: // This asynchronous read (and asynchronous reset) causes the RAM to be // built out of distributed RAM or flip-flops. If this turns into a too // wasteful (576 flip-flops), we can pipeline the CROM register: use the // early CROM to set the read address the synchronous RAM and use the // pipelined delayed CROM for everything else. When combined, the clock // delayed output of the synchronous RAM would be pipelined correctly // with the rest of the CROM. // // Since the registers are implemented in flip-flops, it is no problem // to add a third port to the ALU RAM for debugging or a front panel // interface. // wire [0:39] ad = aluRAM[aa]; wire [0:39] bd = aluRAM[ba]; wire [0:35] cd = aluRAM[debugADDR][2:37]; // // Q Register Shifter // // Note: // All of the Q shifer logic is external to the am2901s. // reg [0:39] qi; always @(f or q or dest or shstyle or divide_shift) begin case (dest) `cromDST_RAMQU: case (shstyle) `cromSPEC_SHSTYLE_NORM: qi <= {q[1:39], 1'b0}; `cromSPEC_SHSTYLE_ZERO: qi <= {q[1:39], 1'b0}; `cromSPEC_SHSTYLE_ONES: qi <= {q[1:39], 1'b1}; `cromSPEC_SHSTYLE_ROT: qi <= {q[1:39], q[4]}; `cromSPEC_SHSTYLE_ASHC: qi <= {q[1:39], 1'b0}; `cromSPEC_SHSTYLE_LSHC: qi <= {q[1:39], 1'b0}; `cromSPEC_SHSTYLE_DIV: qi <= {q[1:39], divide_shift}; `cromSPEC_SHSTYLE_ROTC: qi <= {q[1:39], f[4]}; endcase `cromDST_RAMQD: case (shstyle) `cromSPEC_SHSTYLE_NORM: qi <= {1'b0, q[0:2], q[3], q[4:38]}; `cromSPEC_SHSTYLE_ZERO: qi <= {1'b0, q[0:2], 1'b0, q[4:38]}; `cromSPEC_SHSTYLE_ONES: qi <= {1'b0, q[0:2], 1'b1, q[4:38]}; `cromSPEC_SHSTYLE_ROT: qi <= {1'b0, q[0:2], q[39], q[4:38]}; `cromSPEC_SHSTYLE_ASHC: qi <= {1'b0, q[0:2], f[39], q[4:38]}; `cromSPEC_SHSTYLE_LSHC: qi <= {1'b0, q[0:2], f[39], q[4:38]}; `cromSPEC_SHSTYLE_DIV: qi <= {1'b0, q[0:2], f[39], q[4:38]}; `cromSPEC_SHSTYLE_ROTC: qi <= {1'b0, q[0:2], f[39], q[4:38]}; endcase `cromDST_QREG: qi <= f; `cromDST_NOP, `cromDST_RAMA, `cromDST_RAMF, `cromDST_RAMD, `cromDST_RAMU: qi <= q; endcase end // // Q Register // // Details // The left side and right side of the Q Register can be // independantly clocked and updated. I'm not sure // if the microcode does that, or not. // always @(posedge clk or posedge rst) begin if (rst) q[ 0:39] <= 40'b0; else if (clken) begin if (lclken) q[ 0:19] <= qi[ 0:19]; if (rclken) q[20:39] <= qi[20:39]; end end // // ALU Left R Source Selector // // Details // This selects source for the "R" input to the left-half of // the ALU. // reg [0:39] r; always @(ad or dd or lsrc) begin case (lsrc) `cromSRC_AQ, `cromSRC_AB: r[0:19] = ad[0:19]; `cromSRC_ZQ, `cromSRC_ZB, `cromSRC_ZA: r[0:19] = 20'b0; `cromSRC_DA, `cromSRC_DQ, `cromSRC_DZ: r[0:19] = dd[0:19]; endcase end // // ALU Right R Source Selector // // Details // This selects source for the "R" input to the right-half of // the ALU. // always @(ad or dd or rsrc) begin case (rsrc) `cromSRC_AQ, `cromSRC_AB: r[20:39] = ad[20:39]; `cromSRC_ZQ, `cromSRC_ZB, `cromSRC_ZA: r[20:39] = 20'b0; `cromSRC_DA, `cromSRC_DQ, `cromSRC_DZ: r[20:39] = dd[20:39]; endcase end // // ALU Left S Source Selector // // Details // This selects source for the "S" input to the left-half of // the ALU. // reg [0:39] s; always @(ad or bd or q or lsrc) begin case (lsrc) `cromSRC_AQ, `cromSRC_ZQ, `cromSRC_DQ: s[0:19] = q[0:19]; `cromSRC_AB, `cromSRC_ZB: s[0:19] = bd[0:19]; `cromSRC_ZA, `cromSRC_DA: s[0:19] = ad[0:19]; `cromSRC_DZ: s[0:19] = 20'b0; endcase end // // ALU Right S Source Selector // // Details // This selects source for the "S" input to the right-half of // the ALU. // always @(ad or bd or q or rsrc) begin case (rsrc) `cromSRC_AQ, `cromSRC_ZQ, `cromSRC_DQ: s[20:39] = q[20:39]; `cromSRC_AB, `cromSRC_ZB: s[20:39] = bd[20:39]; `cromSRC_ZA, `cromSRC_DA: s[20:39] = ad[20:39]; `cromSRC_DZ: s[20:39] = 20'b0; endcase end // // ALU Proper // // Details // The ALU is somewhat optimized so that the carry chain can // be optimized. Instead of adding logic into the middle of // of the carry to separate the left half and the right half // of the ALU, the left half, the right half, and the whole // ALU are calculated in parallel. // reg [0:3] g; // ALU Partial Sum reg co; // Carry out of left half reg go; // Partial sum for calculating CRY2 wire ci = carry_in; // Carry into right half reg bb; // Bit Bucket always @(r or s or ci or specCRY18INH or func) begin co = 1'b0; go = 1'b0; g = 4'b0; case (func) `cromFUN_ADD: begin {go, g[ 0: 3]} = {1'b0, r[ 0: 3]} + {1'b0, s[ 0: 3]}; if (specCRY18INH) begin {bb, f[20:39]} = {1'b0, r[20:39]} + {1'b0, s[20:39]} + ci; // Right Half {co, f[ 0:19]} = {1'b0, r[ 0:19]} + {1'b0, s[ 0:19]}; // Left Half (assumes no carry) end else begin {co, f[ 0:39]} = {1'b0, r[ 0:39]} + {1'b0, s[ 0:39]} + ci; // Whole ACC end end `cromFUN_SUBR: begin {go, g[ 0: 3]} = {1'b0, ~r[ 0: 3]} + {1'b0, s[ 0: 3]}; if (specCRY18INH) begin {bb, f[20:39]} = {1'b0, ~r[20:39]} + {1'b0, s[20:39]} + ci; // Right Half {co, f[ 0:19]} = {1'b0, ~r[ 0:19]} + {1'b0, s[ 0:19]}; // Left Half (assumes no carry) end else begin {co, f[ 0:39]} = {1'b0, ~r[ 0:39]} + {1'b0, s[ 0:39]} + ci; // Whole ACC end end `cromFUN_SUBS: begin {go, g[ 0: 3]} = {1'b0, r[ 0: 3]} + {1'b0, ~s[ 0: 3]}; if (specCRY18INH) begin {bb, f[20:39]} = {1'b0, r[20:39]} + {1'b0, ~s[20:39]} + ci; // Right Half {co, f[ 0:19]} = {1'b0, r[ 0:19]} + {1'b0, ~s[ 0:19]}; // Left Half (assumes no carry) end else begin {co, f[ 0:39]} = {1'b0, r[ 0:39]} + {1'b0, ~s[ 0:39]} + ci; // Whole ACC end end `cromFUN_ORRS: f = r | s; `cromFUN_ANDRS: f = r & s; `cromFUN_NOTRS: f = ~r & s; `cromFUN_EXOR: f = r ^ s; `cromFUN_EXNOR: f = ~(r ^ s); endcase end // // ALU Sign outputs // wire aluLSIGN = f[ 0]; wire aluRSIGN = f[20]; // // ALU Zero outputs // wire aluLZERO = f[ 0:19] == 20'b0; wire aluRZERO = f[20:39] == 20'b0; // // Arithmetic Overflow (aluAOV) // // Details // Arithmetic overflow occurs when the sign is different than // the MSB // // Trace // DPE9/E26 // wire aluAOV = aluLSIGN != f[2]; // // aluCRY0 // // Details // This is the carry form ALU bit -2 (Verilog bit 0). // In the KS10, this signal comes from the carry skippers. In // the FPGA implementation, the 'co' signal comes directly from // the ALU serial carry from the MSB. // // Note that the CRY0 doesn't actually come from bit 0: it comes // from bit (-2) using KS10 numbering. Because the top two bits // are sign extensions, they are equivalent. A carry from bit 0 // will cause a carry into bit (-1) and a carry from bit (-1) // will cause a carry into bit (-2). // wire aluCRY0 = co; // // aluCRY1 // // Details // A carry from bit 1 must have occured if the Arithmetic // Overflow bit is different than the carry from bit 0. // // Trace: // DPE9/E26 // wire aluCRY1 = aluAOV != aluCRY0; // aluCRY2: // // Details // This is the carry from ALU bit 2 into ALU bit 1. In Verilog // numbering (see notes at top of file), this is a carry from // ALU bit 4 into ALU bit 3. We don't really have access to // the carry from ALU bit 4, but we infer it by recalculating // the 4 MSBs with the carry cleared, and checking to see if it // yields the same results as the full calculation. If either // the carry or the top four bits are different, there must have // been a carry from ALU bit 2. // wire aluCRY2 = ((go != co) | (f[0:3] != g[0:3])); // // QR37 // // Details // This is what is shifted out of the LSB of the Q Register and // is used by the multiplication implementation. I.e., it goes // to the multiplication dispatch logic to control whether to // add (or not) the partial product. // // Note // This is actually QR39 using Verilog numbering. // reg flagQR37; // // ALU Flag State Register // // Details // These registers store ALU state from one microinstruction to // the next. This state facilates the implementation of multi- // word shifts as well as mutiplication and divide operations. // // Trace // DPE5/E28 // reg flagFL02; reg flagCARRY02; reg flagFUNCT02; reg flagCARRYOUT; always @(posedge clk or posedge rst) begin if (rst) begin flagFL02 <= 1'b0; flagQR37 <= 1'b0; flagCARRY02 <= 1'b0; flagFUNCT02 <= 1'b0; flagCARRYOUT <= 1'b0; end else begin flagFL02 <= bdi[3]; flagQR37 <= q[39]; flagCARRY02 <= aluCRY2; flagFUNCT02 <= funct_02; flagCARRYOUT <= aluCRY0; end end // // Shifter Configuration // // Details // This logic contains special connections to the shifter that // support multishift and divide operations. // // The special operations are controlled by the `cromMULTIPREC // and `cromDIVIDE microcode fields. // // Trace // DPE5/E4 // DPE5/E5 // DPE5/E6 // DPE5/E62 // DPE5/E70 // reg multi_shift; reg divide_shift; reg carry_in; reg funct_02; always @(crom or flagFL02 or flagCARRY02 or flagFUNCT02 or flagCARRYOUT or fun[2]) begin // // Multiprecision operations // if (`cromMULTIPREC) begin multi_shift <= flagFL02; divide_shift <= 1'b0; carry_in <= flagCARRY02 | `cromCRY38; funct_02 <= flagFUNCT02 | fun[2]; end // // Divide operations // else if (`cromDIVIDE) begin multi_shift <= 1'b0; divide_shift <= flagCARRYOUT; carry_in <= flagCARRYOUT | `cromCRY38; funct_02 <= flagCARRYOUT | fun[2]; end // // Nothing special. Carry in is controlled by microcode. // Everything else special is disabled. // else begin multi_shift <= 1'b0; divide_shift <= 1'b0; carry_in <= `cromCRY38; funct_02 <= fun[2]; end end // // ALU Destination Selector // // Details // Select ALU output and truncate output bus from 40 bits to 36 // bits. // assign aluOUT = (dest ==`cromDST_RAMA) ? ad[2:37] : f[2:37]; // // ALU Register Debug Data // assign debugDATA = cd; // // ALU Flags // assign aluFLAGS[0] = flagQR37; assign aluFLAGS[1] = aluLZERO; assign aluFLAGS[2] = aluRZERO; assign aluFLAGS[3] = aluLSIGN; assign aluFLAGS[4] = aluRSIGN; assign aluFLAGS[5] = aluAOV; assign aluFLAGS[6] = aluCRY0; assign aluFLAGS[7] = aluCRY1; assign aluFLAGS[8] = aluCRY2; endmodule Dist/rtl/ks10/cpu/alu.vh0000700000175100010010000000406712151540222013432 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Arithmetic Logic Unit (ALU) Flag Definitions // // Details // Contains definitions that are useful to access ALU Flags // // File // alu.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __ALU_VH `define __ALU_VH // // ALU Flags // `define aluQR37(reg) (reg[0]) // ALU Q Register LSB `define aluLZERO(reg) (reg[1]) // ALU left-half is zero `define aluRZERO(reg) (reg[2]) // ALU right-half is zero `define aluLSIGN(reg) (reg[3]) // ALU left-half sign `define aluRSIGN(reg) (reg[4]) // ALU right-half sign `define aluAOV(reg) (reg[5]) // ALU arithmetic overflow `define aluCRY0(reg) (reg[6]) // ALU carry into bit 0 `define aluCRY1(reg) (reg[7]) // ALU carry into bit 1 `define aluCRY2(reg) (reg[8]) // ALU carry into bit 2 `define aluSIGN(reg) (reg[3]) `define aluZERO(reg) ((reg[1]) & (reg[2])) `endif Dist/rtl/ks10/cpu/apr.v0000700000175100010010000002023612151540224013261 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // APR Device // // Details // // File // apr.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "useq/crom.vh" module APR(clk, rst, clken, crom, dp, nxmINTR, cslINTR, aprFLAGS, aprINTR); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [ 0:cromWidth-1] crom; // Control ROM Data input [ 0:35] dp; // Data path input nxmINTR; // Non existant memory interrupt input cslINTR; // Interrupt from Console output [22:35] aprFLAGS; // APR Flags output [ 1: 7] aprINTR; // APR Interrupt Request // // Microcode Decode // wire specLOADAPR = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_LOADAPR); wire specAPRFLAGS = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_APRFLAGS); // // APR Flag Register 24 // // Note // This is strictly a software interrupt. // // Trace // DPMB/E159 // reg flag24; always @(posedge clk or posedge rst) begin if (rst) flag24 <= 1'b0; else if (clken & specAPRFLAGS) flag24 <= dp[24]; end // // APR Flag Register 25 // // Note // This KS10 can set this bit to generate an interrupt to the // KS10 console. // // Trace // DPMB/E159 // reg flag25; always @(posedge clk or posedge rst) begin if (rst) flag25 <= 1'b0; else if (clken & specAPRFLAGS) flag25 <= dp[25]; end // // APR Flag Register 26 // // Note // This interrupt indicates that an power fail condition // exists. This interrupt is not implemented. // // Trace // DPMB/E158 // reg flag26; always @(posedge clk or posedge rst) begin if (rst) flag26 <= 1'b0; else if (clken & specAPRFLAGS) flag26 <= dp[26]; end // // APR Flag Register 27 // // Note // This interrupt indicates that non-existant memory has been // accessed. // // Trace // DPMB/E139 // reg flag27; always @(posedge clk or posedge rst) begin if (rst) flag27 <= 1'b0; else if (nxmINTR) flag27 <= 1'b1; else if (clken & specAPRFLAGS) flag27 <= dp[27]; end // // APR Flag Register 28 // // Note // This interrupt indicates that an uncorrectable memory error // has occurred. This is not implemented in the FPGA. // // Trace // DPMB/E139 // reg flag28; always @(posedge clk or posedge rst) begin if (rst) flag28 <= 1'b0; else if (clken & specAPRFLAGS) flag28 <= dp[28]; end // // APR Flag Register 29 // // Note // This interrupt indicates that an correctable memory error // has occurred. This is not implemented in the FPGA. // // Trace // DPMB/E147 // reg flag29; always @(posedge clk or posedge rst) begin if (rst) flag29 <= 1'b0; else if (clken & specAPRFLAGS) flag29 <= dp[29]; end // // APR Flag Register 30 // // Note // This interrupt indicates that an interval timer interrup // has occurred. This microcode manages this bit. // // Trace // DPMB/E147 // reg flag30; always @(posedge clk or posedge rst) begin if (rst) flag30 <= 1'b0; else if (clken & specAPRFLAGS) flag30 <= dp[30]; end // // APR Flag Register 31 // // Note // This interrupt indicates that the Console has requested // a KS10 Interrupt. // // Trace // DPMB/E158 // reg flag31; always @(posedge clk or posedge rst) begin if (rst) flag31 <= 1'b0; else if (cslINTR) flag31 <= 1'b1; else if (clken & specAPRFLAGS) flag31 <= dp[31]; end // // APR Enable Register // // Trace // DPMB/E123 // DPMB/E132 // DPEB/E173 // reg flagTRAPEN; // Trap Enable reg flagPAGEEN; // Paging Enable reg [24:31] flagAPREN; // APR Enable reg flagSWINT; // Software Interrupt reg [ 0: 2] flagINTR; // APR Interrupt Request always @(posedge clk or posedge rst) begin if (rst) begin flagTRAPEN <= 1'b0; flagPAGEEN <= 1'b0; flagAPREN <= 8'b0; flagSWINT <= 1'b0; flagINTR <= 3'b0; end else if (clken & specLOADAPR) begin flagTRAPEN <= dp[22]; flagPAGEEN <= dp[23]; flagAPREN <= dp[24:31]; flagSWINT <= dp[32]; flagINTR <= dp[33:35]; end end // // APR Interrupt Mask // // Details // This masks the disabled interrupts. // // Trace // DPMB/E154 // DPMB/E161 // DPMB/E168 // DPMB/E174 // wire flagINTREQ = ((flag24 & flagAPREN[24]) || (flag25 & flagAPREN[25]) || (flag26 & flagAPREN[26]) || (flag27 & flagAPREN[27]) || (flag28 & flagAPREN[28]) || (flag29 & flagAPREN[29]) || (flag30 & flagAPREN[30]) || (flag31 & flagAPREN[31]) || (flagSWINT)); // // APR Interrupt Request // // Details // The APR can request interrupts. // // Trace // DPEB/E166 // reg [1:7] aprINTR; always @(flagINTREQ or flagINTR) begin aprINTR <= 7'b0000000; if (flagINTREQ) case (flagINTR) 3'b000 : aprINTR <= 7'b0000000; 3'b001 : aprINTR <= 7'b1000000; 3'b010 : aprINTR <= 7'b0100000; 3'b011 : aprINTR <= 7'b0010000; 3'b100 : aprINTR <= 7'b0001000; 3'b101 : aprINTR <= 7'b0000100; 3'b110 : aprINTR <= 7'b0000010; 3'b111 : aprINTR <= 7'b0000001; default: aprINTR <= 7'b0000000; endcase end // // FIXUPS // assign aprFLAGS[22] = flagTRAPEN; assign aprFLAGS[23] = flagPAGEEN; assign aprFLAGS[24] = flag24; assign aprFLAGS[25] = flag25; assign aprFLAGS[26] = flag26; assign aprFLAGS[27] = flag27; assign aprFLAGS[28] = flag28; assign aprFLAGS[29] = flag29; assign aprFLAGS[30] = flag30; assign aprFLAGS[31] = flag31; assign aprFLAGS[32] = flagINTREQ; assign aprFLAGS[33] = 1'b1; assign aprFLAGS[34] = 1'b1; assign aprFLAGS[35] = 1'b1; endmodule Dist/rtl/ks10/cpu/apr.vh0000700000175100010010000000414412151540222013427 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Arithmetic Processor (APR) Flags Definitions // // Details // Contains definitions that are useful to access APR Flags // // File // apr.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __APR_VH `define __APR_VH // // APR Flags // `define flagTRAPEN(reg) (reg[22]) // Traps are enabled `define flagPAGEEN(reg) (reg[23]) // Paging is enabled `define flag24(reg) (reg[24]) // Flag 24 `define flagCSL(reg) (reg[25]) // KS10 Interrupt to Console `define flagPWR(reg) (reg[26]) // Power fail `define flagNXM(reg) (reg[27]) // Non existent memory `define flagBADDATA(reg) (reg[28]) // Bad memory data (not implemented) `define flagCORDATA(reg) (reg[29]) // Corrected memory data (not implemented) `define flag30(reg) (reg[30]) // Flag 30 `define flag31(reg) (reg[31]) // Console Interrupt to KS10 `define flagINTREQ(reg) (reg[32]) // Interrupt Request `endif Dist/rtl/ks10/cpu/bus.v0000700000175100010010000002225312151540224013271 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS10 Bus Interface // // Details // The protocol is not the same as the KS10 // // The first 7 bis are the Bus Command Bits // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // Memory Write | VMA Flags | Memory Address | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // Memory Read | VMA Flags | Memory Address | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // RMW Memory | VMA Flags | Memory Address | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // IO Write | VMA Flags | DEV NO | Register Address | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // IO Write Byte | VMA Flags | DEV NO | Register Address | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // IO Read | VMA Flags | DEV NO | Register Address | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +-+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // Read Controller| VMA Flags | | PI NO | Unused | // Number +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // Read Intr Vect | VMA Flags | DEV NO | Unused | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // // File // bus.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "apr.vh" `include "vma.vh" `include "useq/crom.vh" module BUS(clk, rst, clken, crom, dp, vmaEXTENDED, vmaFLAGS, vmaADDR, pageADDR, aprFLAGS, cpuDATAO, cpuADDRO, cpuREQO, cpuACKI, curINTP, memWAIT, nxmINTR); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock enable input [ 0:cromWidth-1] crom; // Control ROM Data input [ 0:35] dp; // Data path input vmaEXTENDED; // Extended VMA input [ 0:13] vmaFLAGS; // VMA Flags input [14:35] vmaADDR; // Virtual Memory Address input [16:26] pageADDR; // Page Address input [22:35] aprFLAGS; // APR Flags output [ 0:35] cpuDATAO; // CPU Data Out output [ 0:35] cpuADDRO; // CPU Address Out output cpuREQO; // CPU Request input cpuACKI; // CPU Bus Acknowledge input [ 0: 2] curINTP; // Current Interrupt Priority output memWAIT; // Wait for Memory output nxmINTR; // Non-existant Memory Interrupt // // APR Flags // wire flagPAGEEN = `flagPAGEEN(aprFLAGS); // // VMA Flags // wire vmaREADCYCLE = `vmaREADCYCLE(vmaFLAGS); wire vmaWRTESTCYCLE = `vmaWRTESTCYCLE(vmaFLAGS); wire vmaWRITECYCLE = `vmaWRITECYCLE(vmaFLAGS); wire vmaPHYSICAL = `vmaPHYSICAL(vmaFLAGS); wire vmaWRUCYCLE = `vmaWRUCYCLE(vmaFLAGS); wire vmaVECTORCYCLE = `vmaVECTORCYCLE(vmaFLAGS); // // Paged Reference // wire pagedREF = ~vmaPHYSICAL & flagPAGEEN; // // Data Output // assign cpuDATAO[0:35] = dp[0:35]; // // Address Output // reg [0:35] cpuADDRO; always @(pagedREF or vmaEXTENDED or vmaFLAGS or vmaADDR or pageADDR or vmaWRUCYCLE or curINTP) begin if (pagedREF) cpuADDRO <= {vmaFLAGS, vmaADDR[14:15], pageADDR[16:26], vmaADDR[27:35]}; else begin if (vmaWRUCYCLE) cpuADDRO[0:35] <= {vmaFLAGS, 1'b0, curINTP, vmaADDR[18:35]}; else begin if (vmaEXTENDED) cpuADDRO <= {vmaFLAGS, vmaADDR}; else cpuADDRO <= {vmaFLAGS, 4'b0000, vmaADDR[18:35]}; end end end // // Bus Request on the various cycles // assign cpuREQO = vmaREADCYCLE | vmaWRITECYCLE | vmaWRTESTCYCLE | vmaWRUCYCLE | vmaVECTORCYCLE; // // Bus Monitor // // Details // Wait for Bus ACK on bus accesses. Generate a NXM Interrupt // on a bus timeout. // localparam [0:3] tNXM = 14; localparam [0:3] tDONE = 15; reg [0:3] timeout; always @(posedge clk or posedge rst) begin if (rst) timeout <= 0; else begin if (cpuREQO & ~cpuACKI) begin if (timeout != tDONE) timeout <= timeout + 1'b1; end else timeout <= 0; end end // // Wait for memory (REQ with no ACK) unless the bus has // timed out. // assign memWAIT = ((cpuREQO & ~cpuACKI & (timeout != tNXM)) & (cpuREQO & ~cpuACKI & (timeout != tDONE))); // // Generate an NXM trap // assign nxmINTR = (timeout == tNXM); endmodule Dist/rtl/ks10/cpu/byte_disp.v0000700000175100010010000000502112151540224014454 0ustar RobNone//////////////////////////////////////////////////////////////////// //! //! KS-10 Processor //! //! \brief //! Byte Dispatch //! //! \details //! When the Datapath has a byte pointer and the byte size //! indication is 7 (most common byte size) and the bytes //! are zero aligned, then this hardware is enabled to speed //! byte manipulation. //! //! \todo //! //! \file //! byte_disp.v //! //! \author //! Rob Doyle - doyle (at) cox (dot) net //! //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none module BYTE_DISP(dp, dispBYTE); input [0:35] dp; // Data path output reg [8:11] dispBYTE; // Byte dispatch // // BYTE DISP // // Details // The first 6 bits in DP are the position, the second 6 bits // in DP are the size. This is derived from the byte pointer // format of the PDP10. // // Trace // DPE3/E77 // DPE3/E16 // DPE3/E10 // DPE3/E9 // wire [0:5] pos = dp[0: 5]; wire [0:5] size = dp[6:11]; always @(pos, size) begin if (size == 7) case (pos) 1 : dispBYTE = 7; 8 : dispBYTE = 5; 15 : dispBYTE = 4; 22 : dispBYTE = 2; 29 : dispBYTE = 1; default: dispBYTE = 0; endcase else dispBYTE = 0; end endmodule Dist/rtl/ks10/cpu/cpu.v0000700000175100010010000003636512151540230013275 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS10 CPU // // Details // // File // cpu.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "useq/crom.vh" `include "useq/drom.vh" `include "apr.vh" module CPU(clk, rst, cslRESET, cslSTEP, cslRUN, cslEXEC, cslCONT, cslHALT, cslTIMEREN, cslTRAPEN, cslCACHEEN, cslINTRI, cslINTRO, ubaINTR, cpuREQO, cpuACKI, cpuADDRO, cpuDATAI, cpuDATAO, cpuHALT, cpuRUN, cpuEXEC, cpuCONT); parameter cromWidth = `CROM_WIDTH; parameter dromWidth = `DROM_WIDTH; input clk; // Clock input rst; // Reset // Console input cslRESET; // CPU Reset input cslSTEP; // Single Step input cslRUN; // Run input cslEXEC; // Execute input cslCONT; // Continue input cslHALT; // HALT input cslTIMEREN; // Timer Enable input cslTRAPEN; // Enable Traps input cslCACHEEN; // Enable Cache input cslINTRI; // Console Interrupt to CPU output cslINTRO; // CPU Interrupt to Console // UBA input [ 1: 7] ubaINTR; // Unibus Interrupt Request // CPU output cpuREQO; // CPU Bus Request input cpuACKI; // Bus Acknowledge output [ 0:35] cpuADDRO; // CPU Addr and Flags input [ 0:35] cpuDATAI; // Bus Data Input output [ 0:35] cpuDATAO; // CPU Data Output output cpuHALT; // CPU Halt Status output cpuRUN; // CPU Run Status output cpuEXEC; // CPU Exec Status output cpuCONT; // CPU Cont Status // // ROMS // wire [0:cromWidth-1] crom; // Control ROM wire [0:dromWidth-1] drom; // Dispatch ROM // // Flags // wire memory_cycle = 0; // FIXME wire iolatch; // FIXME wire opJRST0; // JRST 0 Instruction wire skipJFCL; // JFCL Instruction wire trapCYCLE; // Trap Cycle // // Interrupts // wire cpuINTR; // Extenal Interrupt wire nxmINTR; // Non-existent memory interrupt wire [ 0: 2] reqINTP; // Requested Interrupt Priority wire [ 0: 2] curINTP; // Current Interrupt Priority wire [ 1: 7] aprINTR; // APR Interrupt Request // // PXCT // wire prevEN; // Conditionally use Previous Context wire [ 0: 5] acBLOCK; // AC Block // // ALU Flags // wire [ 0: 8] aluFLAGS; // ALU Flags // // PC Flags // wire [ 0:17] pcFLAGS; // PC Flags // // APR Flags // wire [22:35] aprFLAGS; // Arithmetic Processor Flags // // VMA Registers // wire [14:35] vmaADDR; // VMA Address wire [ 0:13] vmaFLAGS; // VMA Flags wire vmaEXTENDED; // Extended VMA // // Paging // wire pageFAIL; // Page Fail wire [16:26] pageADDR; // Page Address wire [ 0: 3] pageFLAGS; // Page Flags // // Timer // wire timerINTR; // Timer Interrupt wire [18:35] timerCOUNT; // Millisecond timer // // Instruction Register IR // wire [ 0:17] regIR; // Instruction Register (IR) wire xrPREV; // XR is previous // // Cache // wire cacheHIT = 0; // FIXME: Cache not implemented. // // Busses // wire [ 0:35] dp; // ALU output bus wire [ 0:35] dbus; // DBUS Mux output wire [ 0:35] dbm; // DBM Mux output wire [ 0:35] ramfile; // RAMFILE output // // SCAD, SC, and FE // wire [ 0: 9] scad; wire scSIGN; // Step Count Sign wire feSIGN; // Floating-point exponent Sign // // Dispatches // wire [ 8:11] dispNI; // Next Instruction Dispatch wire [ 8:11] dispPF; // Page Fail Dispatch wire [ 8:11] dispBYTE; // Byte Dispatch wire [ 8:11] dispSCAD; // SCAD Dispatch wire [ 0:11] dispDIAG = 0; // Diagnostic Dispatch // // DEBUG // wire [0: 3] debugADDR; // DEBUG Address wire [0:35] debugDATA; // DEBUG Data // // Timing // wire clkenDP; // Clock Enable for Datapaths wire clkenCR; // Clock Enable for Control ROM wire memWAIT; // Wait for memory // // Timing and Wait States // TIMING uTIMING (.clk (clk), .rst (rst), .crom (crom), .feSIGN (feSIGN), .clkenDP (clkenDP), .clkenCR (clkenCR), .memWAIT (memWAIT) ); // // Arithmetic Logic Unit // ALU uALU (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .aluIN (dbus), .aluFLAGS (aluFLAGS), .aluOUT (dp), .debugADDR (debugADDR), .debugDATA (debugDATA) ); // // APR // APR uAPR (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .dp (dp), .nxmINTR (nxmINTR), .cslINTR (cslINTRI), .aprFLAGS (aprFLAGS), .aprINTR (aprINTR) ); // // Byte Dispatch // BYTE_DISP uBYTE_DISP (.dp (dp), .dispBYTE (dispBYTE) ); // // Memory/IO Bus // BUS uBUS (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .dp (dp), .vmaEXTENDED (vmaEXTENDED), .vmaFLAGS (vmaFLAGS), .vmaADDR (vmaADDR), .pageADDR (pageADDR), .aprFLAGS (aprFLAGS), .cpuDATAO (cpuDATAO), .cpuADDRO (cpuADDRO), .cpuREQO (cpuREQO), .cpuACKI (cpuACKI), .curINTP (curINTP), .memWAIT (memWAIT), .nxmINTR (nxmINTR) ); // // Data Bus // DBM uDBM (.crom (crom), .dp (dp), .scad (scad), .dispPF (dispPF), .aprFLAGS (aprFLAGS), .timerCOUNT (timerCOUNT), .vmaFLAGS (vmaFLAGS), .vmaADDR (vmaADDR), .cpuDATAI (cpuDATAI), .dbm (dbm) ); // // DEBUG // DEBUG uDEBUG (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .debugDATA (debugDATA), .debugADDR (debugADDR) ); // // DBUS MUX // DBUS uDBUS (.crom (crom), .cacheHIT (cacheHIT), .reqINTP (reqINTP), .vmaFLAGS (vmaFLAGS), .vmaADDR (vmaADDR), .pcFLAGS (pcFLAGS), .dp (dp), .ramfile (ramfile), .dbm (dbm), .dbus (dbus) ); // // Dispatch ROM // DROM uDROM (.clk (clk), .rst (rst), .clken (clkenDP), .dbus (dbus), .crom (crom), .drom (drom) ); // // Interrupt Controller // INTR uINTR (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .dp (dp), .flagINTREQ (`flagINTREQ(aprFLAGS)), .aprINTR (aprINTR), .ubaINTR (ubaINTR), .reqINTP (reqINTP), .curINTP (curINTP), .cpuINTR (cpuINTR) ); // // INTF // Console Interface // INTF uINTF (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .cslRUN (cslRUN), .cslCONT (cslCONT), .cslEXEC (cslEXEC), .cslHALT (cslHALT), .cpuRUN (cpuRUN), .cpuCONT (cpuCONT), .cpuEXEC (cpuEXEC), .cpuHALT (cpuHALT) ); // // IO Latch // IOLATCH uIOLATCH (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .vmaFLAGS (vmaFLAGS), .iolatch (iolatch) ); // // Instruction Register // regIR uIR (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .dbus (dbus), .prevEN (prevEN), .regIR (regIR), .xrPREV (xrPREV), .opJRST0 (opJRST0) ); // // Microsequencer // USEQ uUSEQ (.clk (clk), .rst (cslRESET), .clken (clkenCR), .dp (dp), .pageFAIL (pageFAIL), .cpuINTR (cpuINTR), .cpuEXEC (cpuEXEC), .cpuCONT (cpuCONT), .iolatch (iolatch), .timerINTR (timerINTR), .trapCYCLE (trapCYCLE), .scSIGN (scSIGN), .aluFLAGS (aluFLAGS), .opJRST0 (opJRST0), .skipJFCL (skipJFCL), .dispDIAG (dispDIAG), .dispPF (dispPF), .dispNI (dispNI), .dispBYTE (dispBYTE), .dispSCAD (dispSCAD), .regIR (regIR), .pcFLAGS (pcFLAGS), .drom (drom), .crom (crom) ); // // Next Instruction Dispatch // NI_DISP uNI_DISP (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .aprFLAGS (aprFLAGS), .pcFLAGS (pcFLAGS), .cslTRAPEN (cslTRAPEN), .cpuRUN (cpuRUN), .memory_cycle (memory_cycle), .dispNI (dispNI), .trapCYCLE (trapCYCLE) ); // // Page Tables // PAGER uPAGER (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .drom (drom), .dp (dp), .vmaADDR (vmaADDR), .vmaFLAGS (vmaFLAGS), .pageFLAGS (pageFLAGS), .pageADDR (pageADDR) ); // // PC Flags // PCFLAGS uPCFLAGS (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .dp (dp), .scad (scad), .regIR (regIR), .aluFLAGS (aluFLAGS), .pcFLAGS (pcFLAGS), .skipJFCL (skipJFCL) ); // // Page Fail Dispatch // PF_DISP uPF_DISP (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .drom (drom), .dp (dp), .vmaFLAGSx (vmaFLAGS), .vmaADDRx (vmaADDR), .aprFLAGS (aprFLAGS), .pageFLAGS (pageFLAGS), .cpuINTR (cpuINTR), .nxmINTR (nxmINTR), .timerINTR (timerINTR), .pageFAIL (pageFAIL), .dispPF (dispPF) ); // // PXCT // Previous context PXCT uPXCT (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .dp (dp), .prevEN (prevEN), .acBLOCK (acBLOCK) ); // // RAMFILE // RAMFILE uRAMFILE (.clk (clk), .rst (rst), .clken (1'b1), .crom (crom), .drom (drom), .dbus (dbus), .regIR (regIR), .xrPREV (xrPREV), .vmaFLAGS (vmaFLAGS), .vmaADDR (vmaADDR), .acBLOCK (acBLOCK), .ramfile (ramfile) ); // // SCAD // SCAD uSCAD (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .dp (dp), .scSIGN (scSIGN), .feSIGN (feSIGN), .scad (scad), .dispSCAD (dispSCAD) ); // // One millisecond (more or less) interval timer. // TIMER uTIMER (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .timerEN (cslTIMEREN), .timerINTR (timerINTR), .timerCOUNT (timerCOUNT) ); // // VMA // VMA uVMA (.clk (clk), .rst (rst), .clken (clkenDP), .crom (crom), .drom (drom), .dp (dp), .cpuEXEC (cpuEXEC), .prevEN (prevEN), .pcFLAGS (pcFLAGS), .vmaEXTENDED (vmaEXTENDED), .vmaFLAGS (vmaFLAGS), .vmaADDR (vmaADDR) ); // // KS10 Interrupt to Console // assign cslINTRO = `flagCSL(aprFLAGS); endmodule Dist/rtl/ks10/cpu/dbm.v0000700000175100010010000001130212151540224013233 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // DBM Multiplexer // // Details // // File // dbm.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "useq/crom.vh" module DBM(crom, dp, scad, dispPF, aprFLAGS, timerCOUNT, vmaFLAGS, vmaADDR, cpuDATAI, dbm); parameter cromWidth = `CROM_WIDTH; input [ 0:cromWidth-1] crom; // Control ROM Data input [ 0:35] dp; // Datapath input [ 0: 9] scad; // SCAD input [ 8:11] dispPF; // Page Fail Dispatch input [22:35] aprFLAGS; // APR Flags input [18:35] timerCOUNT; // Timer Count input [ 0:13] vmaFLAGS; // VMA Flags input [14:35] vmaADDR; // VMA Address input [ 0:35] cpuDATAI; // Memory Bus Data output [ 0:35] dbm; // DBM output // // DBM Bus Mux // // Details // Special logic is available for grabbing BYTES from the // dp bus. // // Trace // Select Logic // DPM1/E94 // DPM1/E72 // DPM1/E86 // DBM[0:6] MUX // DPM1/E58 // DPM1/E42 // DPM1/E34 // DPM1/E65 // DPM1/E50 // DPM1/E49 // DPM1/E57 // DBM[7:13] MUX // DPM1/E64 // DPM1/E59 // DPM1/E80 // DPM1/E73 // DPM1/E79 // DPM1/E81 // DPM1/E98 // DBM[14:20] MUX // DPM1/E88 // DPM1/E89 // DPM1/E95 // DPM1/E96 // DPM2/E104 // DPM2/E105 // DPM2/E106 // DBM[21:27] MUX // DPM2/E112 // DPM2/E113 // DPM2/E120 // DPM2/E128 // DPM2/E143 // DPM2/E129 // DPM2/E121 // DBM[28:35] MUX // DPM2/E173 // DPM2/E151 // DPM2/E166 // DPM2/E167 // DPM2/E172 // DPM2/E187 // DPM2/E165 // DPM2/E188 // reg [0:35] dbm; always @(crom or scad or dispPF or aprFLAGS or dp or timerCOUNT or vmaFLAGS or vmaADDR or cpuDATAI) begin case (`cromDBM_SEL) `cromDBM_SEL_SCADPFAPR: dbm = {scad[1:9], 8'b11111111, scad[0], dispPF, aprFLAGS}; `cromDBM_SEL_BYTES : dbm = {scad[1:7], scad[1:7], scad[1:7], scad[1:7], scad[1:7], dp[35]}; `cromDBM_SEL_EXPTIME : dbm = {1'b0, scad[2:9], dp[9:17], timerCOUNT[18:35]}; `cromDBM_SEL_DP : case (`cromSPEC_SELBYTE) `cromSPEC_SELBYTE_1 : dbm = {scad[1:7], dp[ 7:13], dp[14:20], dp[21:27], dp[28:34], dp[35]}; `cromSPEC_SELBYTE_2 : dbm = {dp[ 0: 6], scad[1:7], dp[14:20], dp[21:27], dp[28:34], dp[35]}; `cromSPEC_SELBYTE_3 : dbm = {dp[ 0: 6], dp[ 7:13], scad[1:7], dp[21:27], dp[28:34], dp[35]}; `cromSPEC_SELBYTE_4 : dbm = {dp[ 0: 6], dp[ 7:13], dp[14:20], scad[1:7], dp[28:34], dp[35]}; `cromSPEC_SELBYTE_5 : // dbm = {dp[ 0: 6], dp[ 7:13], dp[14:20], dp[21:27], scad[1:7], dp[35]}; dbm = {28'b0, scad[1:7], 1'b0}; default: dbm = dp[0:35]; endcase `cromDBM_SEL_DPSWAP : dbm = {dp[18:35], dp[0:17]}; `cromDBM_SEL_VMA : dbm = {vmaFLAGS[0:13], vmaADDR[14:35]}; `cromDBM_SEL_MEM : dbm = cpuDATAI[0:35]; `cromDBM_SEL_NUM : dbm = {`cromNUM, `cromNUM}; endcase end endmodule Dist/rtl/ks10/cpu/dbus.v0000700000175100010010000000776512151540224013450 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // DBUS Multiplexer // // Details // // File // dbus.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "vma.vh" `include "useq/crom.vh" module DBUS(crom, cacheHIT, reqINTP, vmaADDR, vmaFLAGS, pcFLAGS, dp, ramfile, dbm, dbus); parameter cromWidth = `CROM_WIDTH; input [0:cromWidth-1] crom; // Control ROM Data input cacheHIT; // Cache Hit input [ 0: 2] reqINTP; // Requested Interrupt Priority input [ 0:13] vmaFLAGS; // Virtual Memory Flags input [14:35] vmaADDR; // Virtual Memory Address input [ 0:17] pcFLAGS; // PC Flags in Left Half input [ 0:35] dp; // Datapath input [ 0:35] ramfile; // Ramfile input [ 0:35] dbm; // Databus Mux output reg [ 0:35] dbus; // DBus // // VMA Flags // wire vmaREADCYCLE = `vmaREADCYCLE(vmaFLAGS); wire vmaPHYSICAL = `vmaPHYSICAL(vmaFLAGS); // // AC Reference // // Details: // True when addressing lowest 16 addresses using and not // physical addressing. References to the ACs are never // physical. // // Trace // DPM4/E160 // DPM4/E168 // DPM4/E191 // wire vmaACREF = ~vmaPHYSICAL & (vmaADDR[18:31] == 14'b0); // // Force RAMFILE // // Details // This signal is asserted on an AC reference or a cache hit. // When asserted during a read cycle, the DBM mux causes the // RAMFILE to be read instead of main memory. // // Fixme // I'm not sure why I had to hack this to exclude address // 1146. // // Trace // DPM5/E14 // DPM5/E38 // wire forceRAMFILE = ((vmaACREF & vmaREADCYCLE & (crom[0:11] != 12'o1146) & (crom[0:11] != 12'o3666)) | (cacheHIT & vmaREADCYCLE)); // // DBM // // Details // This is a simple 4-way 36-bit multiplexer. // // Trace // DPE3/E34 // DPE3/E35 // DPE3/E40 // DPE3/E56 // DPE3/E63 // DPE3/E70 // DPE3/E72 // DPE3/E73 // DPE3/E87 // DPE3/E100 // always @(`cromDBUS_SEL or pcFLAGS or dp or ramfile or dbm or forceRAMFILE or reqINTP or vmaADDR) begin case (`cromDBUS_SEL) `cromDBUS_SEL_FLAGS: dbus = {pcFLAGS, 1'b0, reqINTP, 4'b1111, vmaADDR[26:35]}; `cromDBUS_SEL_DP: dbus = dp; `cromDBUS_SEL_RAMFILE: dbus = ramfile; `cromDBUS_SEL_DBM: if (forceRAMFILE) dbus = ramfile; else dbus = dbm; endcase end endmodule Dist/rtl/ks10/cpu/debug.v0000700000175100010010000000562212151540224013567 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Debug Hack // // Details // // Todo // // File // debug.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "useq/crom.vh" module DEBUG(clk, rst, clken, crom, debugDATA, debugADDR); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [0:cromWidth-1] crom; // Control ROM Data input [0:35] debugDATA; // DEBUG Data output [0: 3] debugADDR; // DEBUG Address // // Microcode Decode // `ifndef SYNTHESIS wire loadIR = `cromSPEC_EN_40 & (`cromSPEC_SEL == `cromSPEC_SEL_LOADIR); // // Print the Program Counter // // Details: // The program counter is modified by instructions in various // stages of the microcode. A modified PC does not mean that // the instruction was actually executed. For example, the // PC is always incremented after the instruction is fetched // but the PC may be modified (again) later by a branch // instruction. // // This code prints the program counter when the instruction // register is loaded. This occurs once during the instruction // execution. // reg [0:35] PC; always @(posedge clk or posedge rst) begin if (rst) PC <= 18'b0; else if (loadIR) begin PC <= debugDATA; $display("debug: PC is %06o", debugDATA[18:35]); end end `endif // // PC is Register #1 in the ALU // assign debugADDR = 4'b0001; endmodule Dist/rtl/ks10/cpu/intf.v0000700000175100010010000001016312151540224013435 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Console Interface // // Details // // File // intf.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "useq/crom.vh" module INTF(clk, rst, clken, crom, cslRUN, cslCONT, cslEXEC, cslHALT, cpuRUN, cpuCONT, cpuEXEC, cpuHALT); parameter cromWidth = `CROM_WIDTH; input clk; // clock input rst; // reset input clken; // clock enable input [0:cromWidth-1] crom; // Control ROM Data input cslRUN; // Console Run Switch input cslCONT; // Console Continue Switch input cslEXEC; // Console Execute Switch input cslHALT; // Console Halt Switch output reg cpuRUN; // CPU Run Status output reg cpuCONT; // CPU Continue Status output reg cpuEXEC; // CPU Execute Status output reg cpuHALT; // CPU Halt Status // // Spec Decoder // CRA2/E97 // wire specCONS = `cromSPEC_EN_10 & (`cromSPEC_SEL == `cromSPEC_SEL_CONS); // // HALT Status // // Trace // CSL4/E161 // CSL4/E162 // CSL4/E168 // always @(posedge clk or posedge rst) begin if (rst) cpuHALT <= 0; else if (clken) begin if (specCONS & `cromCONS_SET_HALT) cpuHALT <= 1; else if (specCONS & `cromCONS_CLR_HALT) cpuHALT <= 0; end end // // RUN Status // // Trace // CSL4/E98 // CSL4/E135 // always @(posedge clk or posedge rst) begin if (rst) cpuRUN <= 0; else if (clken) begin if (cslRUN) cpuRUN <= 1; else if (specCONS & `cromCONS_CLR_RUN) cpuRUN <= 0; end end // // EXECUTE Status // // Trace // CSL4/E149 // CSL4/E168 // always @(posedge clk or posedge rst) begin if (rst) cpuEXEC <= 0; else if (clken) begin if (cslEXEC) cpuEXEC <= 1; else if (specCONS & `cromCONS_CLR_EXEC) cpuEXEC <= 0; end end // // CONTINUE Status // // Trace // CSL4/E168 // CSL4/E171 // always @(posedge clk or posedge rst) begin if (rst) cpuCONT <= 0; else if (clken) begin if (cslCONT) cpuCONT <= 1; else if (specCONS & `cromCONS_CLR_CONT) cpuCONT <= 0; end end endmodule Dist/rtl/ks10/cpu/intr.v0000700000175100010010000001327612151540224013461 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Priority Interrupt // // Details // // Note // The highest priority is interrupt 1, the lower priority is // interrupt 7. // // File // intr.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "useq/crom.vh" module INTR(clk, rst, clken, crom, dp, flagINTREQ, ubaINTR, aprINTR, reqINTP, curINTP, cpuINTR); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock enable input [0:cromWidth-1] crom; // Control ROM Data input [0:35] dp; // Data path input flagINTREQ; // Interrupt Request input [1: 7] aprINTR; // Arithmetic Processor request input [1: 7] ubaINTR; // Unibus request output [0: 2] reqINTP; // Requested Interrupt Priority output [0: 2] curINTP; // Current Prioity Interrupt number output cpuINTR; // Interrupt Request // // Microcode Decode // wire specLOADPI = `cromSPEC_EN_40 & (`cromSPEC_SEL == `cromSPEC_SEL_LOADPI); // // Datapath Interface // // Details // The microcode keeps track of the current interrupt priority // and the interrupt mask. // // Trace // DPEB/E175 // DPEB/E126 // DPEB/E140 // reg intrEN; // Interrupts are enabled reg [1:7] actINTR; // Interrupt mask reg [1:7] curINTR; // Current interrupt level reg [1:7] swINTR; // Software interrupt always @(posedge clk or posedge rst) begin if (rst) begin actINTR <= 0; intrEN <= 0; curINTR <= 0; swINTR <= 0; end else if (clken & specLOADPI) begin actINTR <= ~dp[29:35]; intrEN <= ~dp[28]; curINTR <= ~dp[21:27]; swINTR <= ~dp[11:17]; end end // // Interrupt Enable / Masking // // Details // Interrupts come from Unibus (UBA) or the Arithmetic // Processor (APR), or the microcode software (SW). // // The software interrupts are not masked. // // Trace // DPEB/E174 // DPEB/E168 // DPEB/E154 // DPEB/E161 // wire [1:7] reqINTR = ((ubaINTR[1:7] | aprINTR[1:7]) & actINTR[1:7]) | swINTR[1:7]; // // Requested Interrupt Priority // // Details // The MSB is present to represent that no interrupt is active. // // Trace // DPEB/E147 // wire [0:3] reqPRIORITY = (~intrEN ? 4'b1000 : // Disabled reqINTR[1] ? 4'b0001 : // Highest priority reqINTR[2] ? 4'b0010 : reqINTR[3] ? 4'b0011 : reqINTR[4] ? 4'b0100 : reqINTR[5] ? 4'b0101 : reqINTR[6] ? 4'b0110 : reqINTR[7] ? 4'b0111 : // Lowest priority 4'b1000); // Nothing active assign reqINTP = reqPRIORITY[1:3]; // // Current Interrupt Priority // // Details // The MSB is present to represent that no interrupt is active. // // Trace // DPEB/E134 // wire [0:3] curPRIORITY = (curINTR[1] ? 4'b0001 : // Highest priority curINTR[2] ? 4'b0010 : curINTR[3] ? 4'b0011 : curINTR[4] ? 4'b0100 : curINTR[5] ? 4'b0101 : curINTR[6] ? 4'b0110 : curINTR[7] ? 4'b0111 : // Lowest priority 4'b1000); // Nothing active assign curINTP = curPRIORITY[1:3]; // // Interrupt Request // // Details // If the requested interrupt priority is higher than the // current interrupt priority, an interrupt to the CPU is // generated. // // Trace // DPEB/E148 // DPEB/E167 // reg cpuINTR; always @(posedge clk or posedge rst) begin if (rst) cpuINTR <= 0; else if (clken) cpuINTR <= (reqPRIORITY < curPRIORITY); end endmodule Dist/rtl/ks10/cpu/iolatch.v0000700000175100010010000001043412151540226014123 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // IO Latch // // Details // The IO Latch is a vestige of the Unibus IO implementation of // the DEC KS10. In the DEC KS10 implementation, the KS10 // backplane bus is synchronous while the Unibus IO bus is // asynchronous. The IO Latch synchronized the backplane bus // and KS10 microcode to the Unibus. The IO Latch was asserted // by the microcode when a Unibus IO transaction was asserted and // negated by the IO device when the IO transaction completed. // // The KS10 FPGA is implemented quite differently. In this // design, both the KS10 backplane bus and the IO bus are // synchronous and the IO Latch is not necessary. The normal // KS10 backplane bus handshaking works for IO bus transactions // just like for memory transactions. // // Even though this is true, the microcode verifies that the IO // Latch is asserted and waits until the IO Latch is negated - // therefore the IO Latch needs to be implemented. // // This code implements the IO Latch as a non-retriggerable // one-shot state machine that is asserted by the microcode and // clears after a few clock cycles. This 'fakes-out' the // microcode. // // Ideally the IO Latch functionality should be removed from the // microcode. // // File // iolatch.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "useq/crom.vh" `include "vma.vh" module IOLATCH(clk, rst, clken, crom, vmaFLAGS, iolatch); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [0:cromWidth-1] crom; // Control ROM Data input [0:13] vmaFLAGS; // VMA Flags output iolatch; // IO Latch // // State definition // parameter [0:1] stateIDLE = 0, // Waiting for IO Cycle stateDELAY1 = 1, // Delay stateDELAY2 = 2, // Delay stateWAIT = 3; // IO Latch cleared, wait for IO Cycle to complete // // VMA Flags // wire vmaIOCYCLE = `vmaIOCYCLE(vmaFLAGS); // // IO Latch // // Trace // DPEA/E99 // DPEA/E93 // reg [0:1] state; reg iolatch; always @(posedge clk or posedge rst) begin if (rst) begin iolatch <= 0; state <= stateIDLE; end else if (clken) case (state) stateIDLE: if (vmaIOCYCLE) begin iolatch <= 1; state <= stateDELAY1; end stateDELAY1: state <= stateDELAY2; stateDELAY2: begin iolatch <= 0; state <= stateWAIT; end stateWAIT: if (~vmaIOCYCLE) state <= stateIDLE; endcase end endmodule Dist/rtl/ks10/cpu/ni_disp.v0000700000175100010010000000727512151540226014136 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Next Instruction Dispatch // // Details // This is a 16-way dispatch base on the next instruction. // // Todo // // File // ni_disp.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "apr.vh" `include "pcflags.vh" `include "useq/crom.vh" module NI_DISP (clk, rst, clken, crom, aprFLAGS, pcFLAGS, cslTRAPEN, cpuRUN, memory_cycle, dispNI, trapCYCLE); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [ 0:cromWidth-1] crom; // Control ROM Data input [ 0:17] pcFLAGS; // PC Flags input [22:35] aprFLAGS; // APR Flags input cslTRAPEN; // Console Trap Enable input cpuRUN; // Run input memory_cycle;// Memory Cycle output [ 8:11] dispNI; // Next Instruction dispatch output trapCYCLE; // Trap Cycle // // Microcode Decode // wire specNICOND = `cromSPEC_EN_10 & (`cromSPEC_SEL == `cromSPEC_SEL_LOADNICOND); // // APR Flags // wire flagTRAPEN = `flagTRAPEN(aprFLAGS); // // PC Flags // wire flagTRAP2 = `flagTRAP2(pcFLAGS); wire flagTRAP1 = `flagTRAP1(pcFLAGS); // // NICOND Dispatch // // Trace // CRA2/E147 // reg [8:11] dispNI; always @(cslTRAPEN or flagTRAPEN or flagTRAP1 or flagTRAP2 or cpuRUN or memory_cycle) begin if (cslTRAPEN & flagTRAPEN) if (flagTRAP1 & flagTRAP2) dispNI[9:11] = 3'd1; else if (flagTRAP2) dispNI[9:11] = 3'd2; else if (flagTRAP1) dispNI[9:11] = 3'd3; else if (~cpuRUN) dispNI[9:11] = 3'd5; else dispNI[9:11] = 3'd7; else dispNI[9:11] = 3'd7; dispNI[8] = memory_cycle; end // // Trap Cycle // // Trace // CRA2/E159 // reg trapCYCLE; always @(posedge clk or posedge rst) begin if (rst) trapCYCLE <= 0; else if (clken & specNICOND) begin if ((cslTRAPEN & flagTRAPEN & flagTRAP1) | (cslTRAPEN & flagTRAPEN & flagTRAP2)) trapCYCLE <= 1; else trapCYCLE <= 0; end end endmodule Dist/rtl/ks10/cpu/pager.v0000700000175100010010000001636312151540226013605 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Pager // // Details // The page table translates virtual addresses/page numbers to // phyical addresses/page numbers. There are 512 virtual pages // which map to 2048 pages. // // 18 26 27 35 // +--------------------+------------------------+ // |Virtual Page Number | Word Number | // +--------------------+------------------------+ // | | // | | // \ / | // +-------+-------+ | // | Page | | // | Translation | | // +-------+-------+ | // | | // | | // \ / \ / // +------------------------+------------------------+ // | Physical Page Number | Word Number | // +------------------------+------------------------+ // 16 26 27 35 // // // Note // The Page Tables use asynchronous memory which won't work // in an FPGA. Since the Page Table is addressed by the VMA // register and the VMA register is loaded synchronously, we // can absorb the VMA register into the Page Table Memory // addressing. // // File // pager.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details.S // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "vma.vh" `include "useq/crom.vh" `include "useq/drom.vh" module PAGER(clk, rst, clken, crom, drom, dp, vmaFLAGS, vmaADDR, pageFLAGS, pageADDR); parameter cromWidth = `CROM_WIDTH; parameter dromWidth = `DROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [ 0:cromWidth-1] crom; // Control ROM Data input [ 0:dromWidth-1] drom; // Dispatch ROM Data input [ 0:35] dp; // Data path input [0 :13] vmaFLAGS; // VMA Flags input [14:35] vmaADDR; // Virtural address output [ 0: 3] pageFLAGS; // Page Flags output [16:26] pageADDR; // Page Address // // vmaFLAGS // wire pageinUSER = `vmaUSER(vmaFLAGS); // // VMA Logic // // Details // During a page table sweep, both specPAGESWEEP and specPAGEWRITE are asserted // simultaneously. // // Trace // DPE5/E76 // DPE6/E53 // wire specPAGESWEEP = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_CLRCACHE ); wire specPAGEWRITE = `cromSPEC_EN_10 & (`cromSPEC_SEL == `cromSPEC_SEL_PAGEWRITE); // // // wire vmaEN = ((`cromMEM_CYCLE & `cromMEM_LOADVMA ) | (`cromMEM_CYCLE & `cromMEM_AREAD & `dromVMA) | (specPAGESWEEP)); // // Sweep and Page Write // // Details: // These signals occur on the cycle before they are required. // // Trace: // DPM4/E184 // DPMC/E3 // reg pageSWEEP; reg pageWRITE; always @(posedge clk or posedge rst) begin if (rst) begin pageSWEEP <= 0; pageWRITE <= 0; end else if (clken) begin pageSWEEP <= specPAGESWEEP; pageWRITE <= specPAGEWRITE; end end // // Table Address // wire [0:7] tableAddr = dp[19:26]; // // Page Table Write // wire pageinVALID = dp[18]; wire pageinWRITEABLE = dp[21]; wire pageinCACHEABLE = dp[22]; wire [16:26] pageinADDR = dp[25:35]; wire [ 0: 3] pageinFLAGS = {pageinVALID, pageinWRITEABLE, pageinCACHEABLE, pageinUSER}; // // Page Table Write // // Details // The page tables perform the virtual address to physical // address translation using a lookup table that is addressed // by the virtual address. // // Notes // This has been converted to synchronous memory. // The page table address is set when the vma address is set // // The page table is interleaved with odd and even memories // so that the memory can be swept two entries at a time. // // Page parity is not implemented. // // Trace // Even Memory // DPM6/E130 // DPM6/E154 // DPM6/E162 // DPM6/E184 // Odd Memory // DPM6/E138 // DPM6/E146 // DPM6/E176 // DPM6/E192 // reg [ 0:14] pageTABLE1[0:255]; reg [ 0:14] pageTABLE2[0:255]; always @(posedge clk or posedge rst) begin if (rst) ; else if (clken & vmaEN) begin if (pageWRITE) begin if (~dp[18] | pageSWEEP) pageTABLE1[tableAddr] <= {pageinFLAGS, pageinADDR}; if ( dp[18] | pageSWEEP) pageTABLE2[tableAddr] <= {pageinFLAGS, pageinADDR}; end end end // // Page Table Read // reg pageVALID; reg pageWRITEABLE; reg pageCACHEABLE; reg pageUSER; reg [16:26] pageADDR; always @(posedge clk or posedge rst) begin if (rst) begin pageVALID <= 0; pageWRITEABLE <= 0; pageCACHEABLE <= 0; pageUSER <= 0; pageADDR <= 0; end else if (clken & vmaEN) begin if(dp[18]) {pageVALID, pageWRITEABLE, pageCACHEABLE, pageUSER, pageADDR} <= pageTABLE2[tableAddr]; else {pageVALID, pageWRITEABLE, pageCACHEABLE, pageUSER, pageADDR} <= pageTABLE1[tableAddr]; end end // // Page Flags // assign pageFLAGS = {pageVALID, pageWRITEABLE, pageCACHEABLE, pageUSER}; endmodule Dist/rtl/ks10/cpu/pager.vh0000700000175100010010000000317712151540222013750 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Pager Flags Definitions // // Details // Contains definitions that are useful to access Page Flags // // File // pager.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __PAGER_VH `define __PAGER_VH // // Page Flags // `define pageVALID(reg) (reg[0]) // Page is valid `define pageWRITEABLE(reg) (reg[1]) // Page is writeable `define pageCACHEABLE(reg) (reg[2]) // Page is cacheable `define pageUSER(reg) (reg[3]) // Page is user mode `endif Dist/rtl/ks10/cpu/pcflags.v0000700000175100010010000003647312151540226014132 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // PC Flags // // Details // The KS10 flags are defined as: // // 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 // +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ // USER |AOV |CRY0|CRY1| FOV| FPD|USER|USER| PUB| |TRAP|TRAP| FXU| NO | | | | | | // | | | | | | | IO | | | 2 | 1 | | DIV| | | | | | // +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ // EXEC | PCP|CRY0|CRY1| FOV| FPD|USER| PCU| PUB| |TRAP|TRAP| FXU| NO | | | | | | // | * | | | | | | | | | 2 | 1 | | DIV| | | | | | // +----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+ // // AOV - Overflow // CRY0 - Carry out of bit 0. // CRY1 - Carry out of bit 1. // FOV - Floating-point overflow. // FPD - First part done. // USER - // USERIO - // PUB - Public. // Not implemented on the KS10. Bit seven always // indicates 0. // TRAP2 - Trap 2. // TRAP1 - Trap 1. // FXU - Floating-point underflow. // NODIV - No Divide. // *PCP - Previous Context Public // Not implemented on the KS10. Bit zero always // indicates AOV. // PCU - Previous Context User // // Overflow occurs if CRY0 and CRY1 differ. // // Note // The logic has been simplified by recognizing that // selPCFLAGS, selEXPTEST, and selASHTEST are mutually // exclusive. // // Note // In the original circuitry the Control ROM (microcode) // was supplied to this module via the dbm input. This // has been replaced by a direct connection to the Control // ROM. Presumably this was done because of circuit board // interconnection limitations. // // File // pcflags.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source fiit under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "useq/crom.vh" `include "alu.vh" `include "regir.vh" module PCFLAGS(clk, rst, clken, crom, dp, scad, regIR, aluFLAGS, pcFLAGS, skipJFCL); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [0:cromWidth-1] crom; // Control ROM Data input [0:35] dp; // Data path input [0: 9] scad; // SCAD input [0:17] regIR; // Instruction Register input [0: 8] aluFLAGS; // ALU Flags output [0:17] pcFLAGS; // Flags output skipJFCL; // JFCL Skip // // ALU Flags // wire aluAOV = `aluAOV(aluFLAGS); wire aluCRY0 = `aluCRY0(aluFLAGS); wire aluCRY1 = `aluCRY1(aluFLAGS); // // Flags Registers // reg flagAOV; // Overflow reg flagCRY0; // Carry 0 reg flagCRY1; // Carry 1 reg flagFOV; // Floating-point overflow reg flagFPD; // First part done reg flagUSER; // User mode reg flagUSERIO; // User IO or User IOT reg flagTRAP2; // Trap 2 reg flagTRAP1; // Trap 1 reg flagFXU; // Floating-point underflow reg flagNODIV; // Divide failure // // DP Inputs // // Details // When `cromADFLAGS is asserted, the dp bus has the contents of // the last ALU operation. In this mode dpOV, dpCRY0, dpCRY1, // are use to update the flags. // // When `cromLDFLAGS is asserted, the dp bus is used by the // microcode to directly modify the flags. // wire dpOV = dp[ 0]; // Overflow flag wire dpCRY0 = dp[ 1]; // Carry 0 wire dpCRY1 = dp[ 2]; // Carry 1 wire dpFOV = dp[ 3]; // Floating-point overflow wire dpFPD = dp[ 4]; // First Part Done wire dpUSER = dp[ 5]; // USER wire dpUSERIO = dp[ 6]; // USER IO wire dpTRAP2 = dp[ 9]; // Trap 2 wire dpTRAP1 = dp[10]; // Trap 1 wire dpFXU = dp[11]; // Floating-point underflow wire dpNODIV = dp[12]; // No divide // // DPE9/E27 // DPE9/E83 // wire selPCFLAGS = `cromSPEC_EN_40 & (`cromSPEC_SEL == `cromSPEC_SEL_PCFLAGS); wire selEXPTEST = `cromSPEC_EN_40 & (`cromSPEC_SEL == `cromSPEC_SEL_EXPTEST); wire selASHTEST = `cromSPEC_EN_40 & (`cromSPEC_SEL == `cromSPEC_SEL_ASHTEST); // // JFCL // See JFCL Instruction Format. // DPE9/E85 // DPE9/E92 // wire [9:12] JFCL; wire [9:12] regIR_AC = `IR_AC(regIR); assign JFCL[ 9] = selPCFLAGS & `cromJFCLFLAGS & flagAOV & regIR_AC[ 9]; assign JFCL[10] = selPCFLAGS & `cromJFCLFLAGS & flagCRY0 & regIR_AC[10]; assign JFCL[11] = selPCFLAGS & `cromJFCLFLAGS & flagCRY1 & regIR_AC[11]; assign JFCL[12] = selPCFLAGS & `cromJFCLFLAGS & flagFOV & regIR_AC[12]; // // JFCL Skip // // Trace // DPE9/E77 // assign skipJFCL = JFCL[9] | JFCL[10] | JFCL[11] | JFCL[12]; // // Arithmetic Overflow Flag (AOV) // // Details: // AOV is set on an ALU overflow. Arithmetic Overflow occurs if // CRY0 and CRY1 differ. A subsequent operation that does not // generate an ALU Overflow will not clear the AOV flag. // AOV is set by SETAOV in microcode. // AOV is cleared by JFCL 9. // AOV is modified by dp. // // Trace // DPE9/E17 // DPE9/E26 // DPE9/E33 // DPE9/E78 // DPE9/E92 // DPE8/E98 // always @(posedge clk or posedge rst) begin if (rst) flagAOV <= 1'b0; else if (clken) begin if (selASHTEST) flagAOV <= (dpCRY0 != dpCRY1); else if (selEXPTEST) flagAOV <= scad[1]; else if (selPCFLAGS) begin if (`cromSETOV) flagAOV <= 1'b1; else if (`cromADFLAGS & aluAOV) flagAOV <= 1'b1; else if (JFCL[9]) flagAOV <= 1'b0; else if (`cromLDFLAGS) flagAOV <= dpOV; end end end // // Carry 0 Flag (CRY0) // // Details: // CRY 0 is set on an ALU Carry 0. A subsequent operation that // does not generate an ALU Carry 0 will not clear the CRY0 // flag. // CRY 0 is cleared by JFCL 10 // CRY 0 is modified by dp. // // Trace // DPE9/E17 // DPE9/E25 // DPE9/E32 // always @(posedge clk or posedge rst) begin if (rst) flagCRY0 <= 1'b0; else if (clken & selPCFLAGS) begin if (`cromADFLAGS & aluCRY0) flagCRY0 <= 1'b1; else if (JFCL[10]) flagCRY0 <= 1'b0; else if (`cromLDFLAGS) flagCRY0 <= dpCRY0; end end // // Carry 1 Flag (CRY1) // // Details: // CRY 1 is set on an ALU Carry 1. A subsequent operation that // does not generate an ALU Carry 1 will not clear the CRY1 // flag. // CRY 1 is cleared by JFCL 11 // CRY 1 is modified by dp. // // Trace // DPE9/E17 // DPE9/E25 // DPE9/E32 // always @(posedge clk or posedge rst) begin if (rst) flagCRY1 <= 1'b0; else if (clken & selPCFLAGS) begin if (`cromADFLAGS & aluCRY1) flagCRY1 <= 1'b1; else if (JFCL[11]) flagCRY1 <= 1'b0; else if (`cromLDFLAGS) flagCRY1 <= dpCRY1; end end // // Floating-point Overflow Flag (FOV) // // Details: // FOV is set on an Floating-point overflow. A floatint-point // oerration that does not overflow will not clear the FOV flag. // FOV is cleared by JFCL 12 // FOV is modified by dp. // // Trace // DPE9/E26 // DPE9/E33 // DPE9/E32 // DPE9/E78 // always @(posedge clk or posedge rst) begin if (rst) flagFOV <= 1'b0; else if (clken) begin if (selEXPTEST) flagFOV <= scad[1]; else if (selPCFLAGS) begin if (JFCL[12]) flagFOV <= 1'b0; else if (`cromSETFOV) flagFOV <= 1'b1; else if (`cromLDFLAGS) flagFOV <= dpFOV; end end end // // First Part Done Flag (FPD) // // Note // The Clear operation has priority over the Set operation. // The Set operation has priority over the Load operation. // // Trace // DPE9/E17 // DPE9/E32 // DPE8/E54 // always @(posedge clk or posedge rst) begin if (rst) flagFPD <= 1'b0; else if (clken & selPCFLAGS) begin if (`cromCLRFPD) flagFPD <= 1'b0; else if (`cromSETFPD) flagFPD <= 1'b1; else if (`cromLDFLAGS) flagFPD <= dpFPD; else flagFPD <= flagFPD; end end // // USER Flag // // Trace // DPE9/E32 // DPE9/E33 // always @(posedge clk or posedge rst) begin if (rst) flagUSER <= 1'b0; else if (clken & selPCFLAGS) begin if (`cromLDFLAGS) flagUSER <= dpUSER; else if (`cromHOLDUSER) flagUSER <= flagUSER; else flagUSER <= 1'b0; end end // // USERIO Flag // // Verification // This is tested by MAINDEC-10-DSKAH // // Trace // DPE9/E53 // DPE9/E54 // DPE9/E60 // always @(posedge clk or posedge rst) begin if (rst) flagUSERIO <= 1'b0; else if (clken & selPCFLAGS) flagUSERIO <= ((~flagUSER & dpUSERIO & `cromLDFLAGS ) | (flagUSERIO & ~`cromLDFLAGS ) | (flagUSER & `cromSETPCU ) | (flagUSERIO & dpUSERIO & `cromHOLDUSER & `cromLDFLAGS )); end // // TRAP2 Flag // // Trace // DPE9/E60 // DPE9/E68 // always @(posedge clk or posedge rst) begin if (rst) flagTRAP2 <= 1'b0; else if (clken & selPCFLAGS) begin if (`cromSETTRAP2) flagTRAP2 <= 1'b1; else if (`cromLDFLAGS) flagTRAP2 <= dpTRAP2; else flagTRAP2 <= 1'b0; end end // // TRAP1 Flag // // Notes // An arithmetic overflow occurs if CRY0 and CRY1 differ which // also sets the TRAP1 flag. // // Trace // DPE9/E26 // DPE9/E33 // DPE9/E78 // DPE9/E85 // DPE9/E98 // always @(posedge clk or posedge rst) begin if (rst) flagTRAP1 <= 1'b0; else if (clken) begin if (selASHTEST) flagTRAP1 <= (dpCRY0 != dpCRY1); else if (selEXPTEST) flagTRAP1 <= scad[1]; else if (selPCFLAGS) begin if (`cromSETTRAP1) flagTRAP1 <= 1'b1; else if (`cromADFLAGS) flagTRAP1 <= aluAOV; else if (`cromLDFLAGS) flagTRAP1 <= dpTRAP1; else flagTRAP1 <= 1'b0; end end end // // Floating-point Underflow Flag (FXU) // // Trace // DPE9/E69 // DPE9/E78 // DPE9/E84 always @(posedge clk or posedge rst) begin if (rst) flagFXU <= 1'b0; else if (clken) begin if (selEXPTEST) flagFXU <= scad[0]; else if (selPCFLAGS) begin if (`cromLDFLAGS) flagFXU <= dpFXU; else flagFXU <= flagFXU; end end end // // NODIV Flag // // Trace // DPE9/E9 // DPE9/E60 // DPE9/E69 // always @(posedge clk or posedge rst) begin if (rst) flagNODIV <= 1'b0; else if (clken & selPCFLAGS) begin if (`cromSETNODIV) flagNODIV <= 1'b1; else if (`cromLDFLAGS) flagNODIV <= dpNODIV; else flagNODIV <= flagNODIV; end end // // Output fixups // assign pcFLAGS[ 0] = flagAOV; assign pcFLAGS[ 1] = flagCRY0; assign pcFLAGS[ 2] = flagCRY1; assign pcFLAGS[ 3] = flagFOV; assign pcFLAGS[ 4] = flagFPD; assign pcFLAGS[ 5] = flagUSER; assign pcFLAGS[ 6] = flagUSERIO; assign pcFLAGS[ 7] = 1'b0; assign pcFLAGS[ 8] = 1'b0; assign pcFLAGS[ 9] = flagTRAP2; assign pcFLAGS[10] = flagTRAP1; assign pcFLAGS[11] = flagFXU; assign pcFLAGS[12] = flagNODIV; assign pcFLAGS[13] = 1'b0; assign pcFLAGS[14] = 1'b0; assign pcFLAGS[15] = 1'b0; assign pcFLAGS[16] = 1'b0; assign pcFLAGS[17] = 1'b0; endmodule Dist/rtl/ks10/cpu/pcflags.vh0000700000175100010010000000417412151540222014267 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Program Counter (PC) Flags Definitions // // Details // Contains definitions that are useful to access PC Flags // // File // pcflags.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __PCFLAGS_VH `define __PCFLAGS_VH // // PC Flags // `define flagAOV(reg) (reg[ 0]) // Arithmetic overflow `define flagCRY0(reg) (reg[ 1]) // Carry into bit 0 `define flagCRY1(reg) (reg[ 2]) // Carry into bit 1 `define flagFOV(reg) (reg[ 3]) // Floating-poing overflow `define flagFPD(reg) (reg[ 4]) // First Part Done `define flagUSER(reg) (reg[ 5]) // User Mode `define flagUSERIO(reg) (reg[ 6]) // User mode IO instructions `define flagPCU(reg) (reg[ 6]) // Previous Context User `define flagTRAP2(reg) (reg[ 9]) // Trap2 `define flagTRAP1(reg) (reg[10]) // Trap1 `define flagFXU(reg) (reg[11]) // Floating-point underflow `define flagNODIV(reg) (reg[12]) // Divide failure `endif Dist/rtl/ks10/cpu/pf_disp.save.v0000700000175100010010000002433112132116704015061 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Page Fail Dispatch // // Details // See comments in microcode at PAGE-FAIL entry point. // // The dispatch is via "DP LEFT". The dispatch into the CROM // Address (see DISP/PAGE FAIL=63) is never used. It looks // like the traces are delete from the board. // // The microcode has the following dispatches defined: // // 0001: Timer or External Interrupt // 0011: Bad Data (Not implemented) // 0101: NXM (Non-existant Memory) // 0111: NXM and Bad Data (Not implemented) // 1000: Write Violation // 1001: Timer and Page Fail // 1010: Page not valid // 1011: Exec/User Mismatch // // The the Page Fail dispatch is actually a combination of a // Dispatch and a Skip operating simulataneously. // // File // pf_disp.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details.S // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "apr.vh" `include "vma.vh" `include "pager.vh" `include "useq/crom.vh" `include "useq/drom.vh" module PF_DISP(clk, rst, clken, crom, drom, dp, vmaFLAGS, vmaADDR, aprFLAGS, pageFLAGS, cpuINTR, nxmINTR, timerINTR, pageFAIL, dispPF); parameter cromWidth = `CROM_WIDTH; parameter dromWidth = `DROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [ 0:cromWidth-1] crom; // Control ROM Data input [ 0:dromWidth-1] drom; // Dispatch ROM Data input [ 0:35] dp; // Datapath input [ 0:13] vmaFLAGS; // Virtual Memory Flags input [14:35] vmaADDR; // Virtual Memory Address input [22:35] aprFLAGS; // APR Flags input [ 0: 3] pageFLAGS; // Page Flags input timerINTR; // Timer Interrupt input cpuINTR; // CPU Interrupt input nxmINTR; // NXM Interrupt output pageFAIL; // Page Fail output [ 0: 3] dispPF; // Page Fail Dispatch // // Microcode decode // // Note // specMEMCLR and specMEMWAIT can be asserted simultaneously. // // Trace // DPMA/E2 // DPMA/E8 // DPE5/E1 // wire specMEMCLR = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_MEMCLR ); wire specMEMWAIT = `cromSPEC_EN_10 & (`cromSPEC_SEL == `cromSPEC_SEL_MEMWAIT); wire specSWEEP = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_CLRCACHE); // // aprFLAGS // wire flagPAGEEN = `flagPAGEEN(aprFLAGS); // Paging is enabled // // vmaFLAGS // wire vmaUSER = `vmaUSER(vmaFLAGS); // VMA User wire vmaREADCYCLE = `vmaREADCYCLE(vmaFLAGS); // Read Cycle (IO or Memory) wire vmaWRTESTCYCLE = `vmaWRTESTCYCLE(vmaFLAGS); // Write Test Cycle wire vmaWRITECYCLE = `vmaWRITECYCLE(vmaFLAGS); // Write Cycle (IO or Memory) wire vmaPHYSICAL = `vmaPHYSICAL(vmaFLAGS); // VMA Physical // // Page Flags // wire pageVALID = `pageVALID(pageFLAGS); // Page is valid wire pageWRITEABLE = `pageWRITEABLE(pageFLAGS); // Page is writeable wire pageUSER = `pageUSER(pageFLAGS); // Page is user mode // // AC Reference // // Details // True when addressing lowest 16 addresses using and not // physical addressing. References to the ACs are never // physical. // // Trace // DPM4/E160 // DPM4/E168 // DPM4/E191 // wire vmaACREF = ~vmaPHYSICAL & (vmaADDR[18:31] == 14'b0); // // vmaEN // // Trace // DPE5/E53 // DPE5/E76 // wire vmaEN = ((`cromMEM_CYCLE & `cromMEM_LOADVMA ) | (`cromMEM_CYCLE & `cromMEM_AREAD & `dromVMA) | (specSWEEP)); // // vmaJUSTLOADED // // Details // This prevents an immediate PAGE FAIL after the VMA has been // updated. This only is asserted for a single clock cycle. // // Trace // DPMC/E10 // `ifdef broken wire vmaJUSTLOADED = vmaEN; reg vmaJUSTLOADED; always @(posedge clk or posedge rst) begin if (rst) vmaJUSTLOADED <= 0; else if (clken) vmaJUSTLOADED <= vmaEN; end `endif // `ifdef broken wire vmaJUSTLOADED = 0; // // Read/Write Enable // // Trace // DPM5/E48 // reg readENABLE; reg writeENABLE; always @(crom or drom or dp) begin if (`cromMEM_AREAD) begin readENABLE <= `dromREADCYCLE; writeENABLE <= `dromWRITECYCLE; end else if (`cromMEM_DPFUNC) begin readENABLE <= dp[3]; writeENABLE <= dp[5]; end else begin readENABLE <= `cromMEM_READCYCLE; writeENABLE <= `cromMEM_WRITECYCLE; end end // // Interrupts // // Trace // DPM6/E9 // wire anyINTR = (cpuINTR | timerINTR | nxmINTR); // // pagingOK // // Details: // This logic enables Page Fail dispatch. Paging is enabled when: // 1. Paging is enabled // 2. The reference is not to an AC. ACs are always physical. // 3. The reference it not a physical address. // 4. An interrupt or error is not being handled. // // Trace: // DPM6/E47 // wire pagingOK = flagPAGEEN & ~vmaACREF & ~vmaPHYSICAL & ~anyINTR; // // Memory Enable // // Trace // DPM5/E118 // wire memENABLE = ((`cromMEM_CYCLE & `cromMEM_WAIT ) | (`cromMEM_CYCLE & `cromMEM_BWRITE & `dromCOND_FUNC)); // // Memory Cycle // // Trace // DPM5/E17 // DPM5/E5 // DPM6/E16 // wire memoryCYCLE = ((memENABLE & readENABLE ) | (memENABLE & writeENABLE)); // // Page Fail Dispatch // // Details: // This logic generates a PAGE FAIL dispatch into the microcode. // Actually PAGE FAIL is a misnomer because the PAGE FAIL // dispatch also handles External Interrupts, Timer Interrupts, // and NXM Interrupts, Uncorrectable Memory Interrupts, (not // implemented) and Page Failures. // // The PAGE-FAIL dispatch operates as follows: // 1. This module creates the pageFAIL signal coincident with // Memory Reads and Memory Write Test bus cycles. This will // be explained below. // 2. The Microsequencer dispatches to address 3777 which is // hard coded into the microsequencer address logic. // 3. The Microsequencer also stores the address of the Read // or Write Test microcode operations. // 4. The PAGE-FAIL code runs. The microcode will handle the // various causes of the dispatch. // 5. Eventually the microcode returns and re-executes the // instruction that caused the page fail dispatch. // // As explained above, when a operation causes a page failure, // the KS10 CPU executes the Page Fill microcode and then // re-executes the instruction that caused the Page Failure. // // Trace: // DPM6/E41 // DPM6/E47 // DPM6/E115 // DPM6/E124 // reg [0:3] pfDISP; always @(pagingOK or pageVALID or pageUSER or vmaUSER or vmaWRTESTCYCLE or pageWRITEABLE) begin if (pagingOK) begin // // Page not valid/present // if (~pageVALID) pfDISP = 4'b1010; // // EXEC / USER Mismatch // else if (pageUSER != vmaUSER) pfDISP = 4'b1011; // // Write Violation // else if (vmaWRTESTCYCLE & ~pageWRITEABLE) pfDISP = 4'b1000; // // Everything else // else pfDISP = 4'b0001; end else pfDISP = 4'b0001; end // // Interrupt Dispatch // wire [0:3] intrDISP = {anyINTR, nxmINTR, 2'b0}; // // Mung Page Fail Dispatch and Interrupt Dispatch together. // assign dispPF = (pfDISP | intrDISP); // // Create pageFAIL signal. This must only be asserted // for a single clock cycle (to jam the page fail address // into the microsequencer address). // `define PAGEFAIL `ifdef PAGEFAIL assign pageFAIL = ((memoryCYCLE & ~vmaJUSTLOADED & (pfDISP != 4'b0001)) | (memoryCYCLE & ~vmaJUSTLOADED & anyINTR )); `else assign pageFAIL = 0; `endif endmodule Dist/rtl/ks10/cpu/pf_disp.v0000700000175100010010000002627212151540226014133 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Page Fail Dispatch // // Details // See comments in microcode at PAGE-FAIL entry point. // // The dispatch is via "DP LEFT". The dispatch into the CROM // Address (see DISP/PAGE FAIL=63) is never used. It looks // like the traces are delete from the board. // // The microcode has the following dispatches defined: // // DISP PRI Description // 0001 Timer or External Interrupt // 0011 Bad Data (Not implemented) // 0101 NXM (Non-existant Memory) // 0111 NXM and Bad Data (Not implemented) // 1000 2 Write Violation (Not writeable on write test) // 1001 Timer and Page Fail // 1010 0 Page not valid // 1011 1 Exec/User Mismatch // // The the Page Fail dispatch is actually a combination of a // Dispatch and a Skip operating simulataneously. // // Important things: // 1. The pageFAIL signal must be asserted on the cycle before // the memory access. This will vector the microcode to // Page Fail handler (location 7777 PAGE_FAIL:) during the // memory cycle. // File // pf_disp.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details.S // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "apr.vh" `include "vma.vh" `include "pager.vh" `include "useq/crom.vh" `include "useq/drom.vh" module PF_DISP(clk, rst, clken, crom, drom, dp, vmaFLAGSx, vmaADDRx, aprFLAGS, pageFLAGS, cpuINTR, nxmINTR, timerINTR, pageFAIL, dispPF); parameter cromWidth = `CROM_WIDTH; parameter dromWidth = `DROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [ 0:cromWidth-1] crom; // Control ROM Data input [ 0:dromWidth-1] drom; // Dispatch ROM Data input [ 0:35] dp; // Datapath input [ 0:13] vmaFLAGSx; // Virtual Memory Flags input [14:35] vmaADDRx; // Virtual Memory Address input [22:35] aprFLAGS; // APR Flags input [ 0: 3] pageFLAGS; // Page Flags input timerINTR; // Timer Interrupt input cpuINTR; // CPU Interrupt input nxmINTR; // NXM Interrupt output pageFAIL; // Page Fail output [ 0: 3] dispPF; // Page Fail Dispatch // // Microcode decode // // Trace // DPMA/E2 // DPMA/E8 // DPE5/E1 // wire specMEMCLR = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_MEMCLR ); wire specSWEEP = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_CLRCACHE); // // aprFLAGS // wire flagPAGEEN = `flagPAGEEN(aprFLAGS); // Paging is enabled // // Page Flags // wire pageVALID = `pageVALID(pageFLAGS); // Page is valid wire pageWRITEABLE = `pageWRITEABLE(pageFLAGS); // Page is writeable wire pageUSER = `pageUSER(pageFLAGS); // Page is user mode // // vmaEN // // Trace // DPE5/E53 // DPE5/E76 // wire vmaEN = ((`cromMEM_CYCLE & `cromMEM_LOADVMA ) | (`cromMEM_CYCLE & `cromMEM_AREAD & `dromVMA) | (specSWEEP)); // // Memory Enable // // Trace // DPM5/E118 // wire memEN = ((`cromMEM_CYCLE & `cromMEM_WAIT ) | (`cromMEM_CYCLE & `cromMEM_BWRITE & `dromCOND_FUNC)); // // vmaFLAGS // wire [14:35] vmaADDR = dp[14:35]; // VMA Address wire vmaUSER = vmaEN & dp[0]; // VMA User wire vmaPHYSICAL = vmaEN & dp[8]; // VMA is physical wire vmaVIRTUAL = vmaEN & ~dp[8]; // VMA is virtual // // AC Reference // // Details // True when addressing lowest 16 addresses using and not // physical addressing. References to the ACs are never // physical. // // Trace // DPM4/E160 // DPM4/E168 // DPM4/E191 // wire vmaACREF = (vmaADDR[18:31] == 0); // // debug // wire debugREADCYCLE = `vmaREADCYCLE(vmaFLAGSx); // Read Cycle (IO or Memory) wire debugWRTESTCYCLE = `vmaWRTESTCYCLE(vmaFLAGSx); // Write Test Cycle wire debugWRITECYCLE = `vmaWRITECYCLE(vmaFLAGSx); // Write Cycle (IO or Memory) // // vmaJUSTLOADED // // Details // This prevents an immediate PAGE FAIL after the VMA has been // updated. This only is asserted for a single clock cycle. // // Trace // DPMC/E10 // `ifdef broken wire vmaJUSTLOADED = vmaEN; reg vmaJUSTLOADED; always @(posedge clk or posedge rst) begin if (rst) vmaJUSTLOADED <= 0; else if (clken) vmaJUSTLOADED <= vmaEN; end `endif // `ifdef broken wire vmaJUSTLOADED = 0; // // Read/Write Enable // // Trace // DPM5/E48 // reg readENABLE; reg writetestENABLE; reg writeENABLE; always @(crom or drom or dp) begin if (memEN) begin if (`cromMEM_AREAD) begin readENABLE <= `dromREADCYCLE; writetestENABLE <= `dromWRTESTCYCLE; writeENABLE <= `dromWRITECYCLE; end else if (`cromMEM_DPFUNC) begin readENABLE <= dp[3]; writetestENABLE <= dp[4]; writeENABLE <= dp[5]; end else begin readENABLE <= `cromMEM_READCYCLE; writetestENABLE <= `cromMEM_WRTESTCYCLE; writeENABLE <= `cromMEM_WRITECYCLE; end end else begin readENABLE <= 0; writetestENABLE <= 0; writeENABLE <= 0; end end // // pagingACCESS // // Details: // This logic enables Page Fail dispatch. Paging is enabled when: // // Trace: // DPM6/E47 // //wire pagedACCESS = ~vmaACREF & ~vmaPHYSICAL; // // Page Fail Dispatch // // Details: // This logic generates a PAGE FAIL dispatch into the microcode. // Actually PAGE FAIL is a misnomer because the PAGE FAIL // dispatch also handles External Interrupts, Timer Interrupts, // and NXM Interrupts, Uncorrectable Memory Interrupts, (not // implemented) and Page Failures. // // The PAGE-FAIL dispatch operates as follows: // 1. This module creates the pageFAIL signal coincident with // Memory Reads and Memory Write Test bus cycles. This will // be explained below. // 2. The Microsequencer dispatches to address 7777 (or 3777) which is // hard coded into the microsequencer address logic. // 3. The Microsequencer also stores the address of the Read // or Write Test microcode operations. // 4. The PAGE-FAIL code runs. The microcode will handle the // various causes of the dispatch. // 5. Eventually the microcode returns and re-executes the // instruction that caused the page fail dispatch. // // As explained above, when a operation causes a page failure, // the KS10 CPU executes the Page Fill microcode and then // re-executes the instruction that caused the Page Failure. // // Interrupts have a higher priority than page failures. // // Paging is enabled when: // 1. Paging is enabled // 2. The reference is not to an AC. ACs are always physical. // 3. The reference it not a physical address. // // Trace: // DPM6/E41 // DPM6/E47 // DPM6/E115 // DPM6/E124 // reg [0:3] pfDISP; always @(nxmINTR or cpuINTR or timerINTR or vmaPHYSICAL or vmaVIRTUAL or flagPAGEEN or vmaADDR or pageVALID or pageUSER or vmaUSER or writetestENABLE or pageWRITEABLE) begin // // Non-existent Memory // if (nxmINTR) pfDISP = 4'b0101; // // CPU Interrupt // else if (cpuINTR & vmaPHYSICAL) pfDISP = 4'b0001; // // Timer Interrupt // else if (timerINTR & vmaPHYSICAL) pfDISP = 4'b0001; // // Page not valid/present // else if (flagPAGEEN & vmaVIRTUAL & (vmaADDR[18:31] != 0) & ~pageVALID) pfDISP = 4'b1010; // // EXEC / USER Mismatch // else if (flagPAGEEN & vmaVIRTUAL & (vmaADDR[18:31] != 0) & (pageUSER != vmaUSER)) pfDISP = 4'b1011; // // Write Violation // else if (flagPAGEEN & vmaVIRTUAL & (vmaADDR[18:31] != 0) & writetestENABLE & ~pageWRITEABLE) pfDISP = 4'b1000; // // No Page Failure or Interrupt // else pfDISP = 4'b0000; end // // Create pageFAIL signal. This must only be asserted // for a single clock cycle (to jam the page fail address // into the microsequencer address). // wire PF = (readENABLE | writeENABLE) & ~vmaJUSTLOADED & (pfDISP != 0); reg [0:3] dispPF; always @(posedge clk or posedge rst) begin if (rst) dispPF <= 0; else if (clken) begin if (PF) dispPF <= pfDISP; else if (specMEMCLR) dispPF <= 0; end end //`define PAGEFAIL `ifdef PAGEFAIL assign pageFAIL = PF; `else assign pageFAIL = 0; `endif endmodule Dist/rtl/ks10/cpu/pxct.v0000700000175100010010000001552112151540226013460 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // PXCT // // Details // // Note // For a really good explanation of these bits see Mike Eulers // Interoffice Memorandum on Extended Addressing. // // It is available from: // // // The following information is extracted from that document // verbatim. // // Bit References made in previous context if bit is 1 // // 9 (E1) Effective address calculation of instruction // (index registers, indirect words). // // 10 (D1) Memory operands specified by EA, whether fetch // or store (e.g, PUSH source, POP or BLT // destination); byte pointer. // // 11 (E2) Effective address calculation of byte pointer; // source in EXTEND (e.g., XBLT or MOVSLJ source); // effective address calculation of source byte // pointer in EXTEND (MOVSLJ). // // 12 (D2) Byte data; source in BLT; destination in EXTEND // (e.g., XBLT or MOVSLJ destination); effective // address calculation of destination byte pointer // in EXTEND (MOVSLJ). // // File // pxct.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "useq/crom.vh" module PXCT(clk, rst, clken, crom, dp, prevEN, acBLOCK); parameter cromWidth = `CROM_WIDTH; input clk; // clock input rst; // reset input clken; // clock enable input [0:cromWidth-1] crom; // Control ROM Data input [0:35] dp; // Data Path output prevEN; // Previous Enable output [0: 5] acBLOCK; // Blocks // // Microcode fields // wire specACBLK = `cromSPEC_EN_40 & (`cromSPEC_SEL == `cromSPEC_SEL_LOADACBLK); wire specPXCTEN = `cromSPEC_EN_10 & (`cromSPEC_SEL == `cromSPEC_SEL_PXCTEN ); wire specPXCTOFF = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_PXCTOFF ); wire [0:2] memPXCTSEL = `cromMEM_PXCTSEL; // // AC Block Selection // // Details // This register holds the current AC block and the // previous AC block. The PXCT selects between the // two. // // Trace // DPE5/E308 // reg [0: 2] currBLOCK; // Current Block reg [0: 2] prevBLOCK; // Previous Block always @(posedge clk or posedge rst) begin if (rst) begin currBLOCK <= 3'b0; prevBLOCK <= 3'b0; end else if (clken & specACBLK) begin currBLOCK <= dp[6: 8]; prevBLOCK <= dp[9:11]; end end // // PCXT Register // // Details: // The microcode saves the AC field of the XCT instruction into // this register. The PXCT state is used in the operation // that follows. // // Note: // specPXCTEN and specPXCTOFF can occur simultaneously or // independantly. // // Trace: // DPMA/E71 // DPMA/E78 // DPMA/E2 // reg enPXCT; reg [9:12] pxct; always @(posedge clk or posedge rst) begin if (rst) begin enPXCT <= 1'b0; // Enable PXCT pxct <= 4'b0; // PXCT Bits end else if (clken & specPXCTEN) begin enPXCT <= ~specPXCTOFF; // Enable PXCT pxct[ 9] <= dp[ 9]; // PXCT E1 Bit pxct[10] <= dp[10]; // PXCT D1 Bit pxct[11] <= dp[11]; // PXCT E2 Bit pxct[12] <= dp[12]; // PXCT D2 Bit end end // // PXCT AC Field Decode // // Details: // The use of previous context (prevEN) is a function of AC // field of the XCT opcode and the type of memory operation // being performed. // // The microcode indexes this device with the type of // memory operation (memPXCTSEL) and this device examines // the AC field of the XCT instruction (pxct[9:12]) to // determine if previous context is applicable to this // specific memory operation, or not. // // See additional information in file header. // // Trace: // DPMA/E62 // DPMA/E63 // reg prevEN; always @(pxct or enPXCT or memPXCTSEL) begin if (enPXCT) case (memPXCTSEL) 0: prevEN <= 1'b0; // Current 1: prevEN <= pxct[ 9]; // E1: PXCT EA 2: prevEN <= pxct[10] & pxct[9]; // Not used 3: prevEN <= pxct[10]; // D1: PXCT DATA or // PXCT BLT DEST 4: prevEN <= pxct[11] & pxct[9]; // BIS-SRC-EA 5: prevEN <= pxct[11]; // E2: PXCT BYTE PTR EA or // PXCT EXTEND EA 6: prevEN <= pxct[12] & pxct[9]; // BIS-DST-EA 7: prevEN <= pxct[12]; // D2: PXCT BYTE DATA or // PXCT STACK WORD or // PXCT BLT SRC endcase else prevEN <= 1'b0; // Current end // // Fixups // assign acBLOCK[0:2] = currBLOCK; assign acBLOCK[3:5] = prevBLOCK; endmodule Dist/rtl/ks10/cpu/pxct.vh0000700000175100010010000000304512151540222013622 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Previous Context (PXCT) Block Definitions // // Details // Contains definitions that are useful to access APR Flags // // File // pxct.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __PXCT_VH `define __PXCT_VH // // PXCT Blocks // `define currBLOCK(reg) (reg[0:2]) // Current AC Block `define prevBLOCK(reg) (reg[3:5]) // Previous AC Block `endif Dist/rtl/ks10/cpu/ram1kx36.v0000700000175100010010000000646212151540226014062 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // RAM 1Kx36 // // Details // // Note // // Todo // // File // ram1kx36.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none module RAM1Kx36(clk, rst, clken, wr, addr, din, dout); input clk; // Clock input rst; // Reset input clken; // Clock enable input wr; // Write input [0: 9] addr; // Address input [0:35] din; // Data in output [0:35] dout; // Data out // // RAM 1kx36 // // FIXME: // The fall edge clock on the RAM is a hack but it is good enough // for simulation and until I figure out what to do here. // It will create synthesis issues. // // Note: // There are places when the KS10 microcode reads uninitialized // RAMFILE contents (TTG, for one). This halts the simulation. // Therefore this implementation includes code to initialized // the RAMFILE contents for simulation purposes. // // Trace // DPE7/E906, DPE7/E907, DPE7/E908, DPE7/E909, DPE7/E910, DPE7/E911 // DPE7/E912, DPE7/E913, DPE7/E914, DPE7/E915, DPE7/E916, DPE7/E917 // DPE7/E918, DPE7/E919, DPE7/E920, DPE7/E921, DPE7/E922, DPE7/E923 // DPE7/E806, DPE7/E807, DPE7/E808, DPE7/E809, DPE7/E810, DPE7/E811 // DPE7/E812, DPE7/E813, DPE7/E814, DPE7/E815, DPE7/E816, DPE7/E817 // DPE7/E818, DPE7/E819, DPE7/E820, DPE7/E821, DPE7/E822, DPE7/E823 // `ifndef SYNTHESIS integer i; `endif reg [0:35] ram [0:1023]; reg [0: 9] rd_addr; always @(negedge clk or posedge rst) begin if (rst) begin `ifdef SYNTHESIS ; `else for (i = 0; i < 1024; i = i + 1) begin ram[i] <= 0; end // Initialize Stack Pointer ram[15] <= 36'o777577_030303; `endif end else if (clken) begin if (wr) ram[addr] <= din; rd_addr <= addr; end end assign dout = ram[rd_addr]; endmodule Dist/rtl/ks10/cpu/ramfile.v0000700000175100010010000002067412151540226014126 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Ramfile // // Details // // Note // // +------+----------------+ // | 1777 | | // | | Cache | // | 1000 | | // +------+----------------+ // | 0777 | | // | | Workspace | // | 0200 | | // +------+----------------+ // | 0177 | | // | | AC Block 7 | // | 0160 | | // +------+----------------+ // | 0067 | | // | | AC Block 6 | // | 0140 | | // +------+----------------+ // | 0037 | | // | | AC Block 5 | // | 0120 | | // +------+----------------+ // | 0117 | | // | | AC Block 4 | // | 0100 | | // +------+----------------+ // | 0077 | | // | | AC Block 3 | // | 0060 | | // +------+----------------+ // | 0057 | | // | | AC Block 2 | // | 0040 | | // +------+----------------+ // | 0037 | | // | | AC Block 1 | // | 0020 | | // +------+----------------+ // | 0017 | | // | | AC Block 0 | // | 0000 | | // +------+----------------+ // // Note // In the original circuitry the Control ROM (microcode) // was supplied to this module via the dbm input. This // has been replaced by a direct connection to the Control // ROM. Presumably this was done because of circuit board // interconnection limitations. // // Todo // // File // ramfile.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "vma.vh" `include "pxct.vh" `include "regir.vh" `include "useq/crom.vh" `include "useq/drom.vh" module RAMFILE(clk, rst, clken, crom, drom, dbus, regIR, xrPREV, vmaFLAGS, vmaADDR, acBLOCK, ramfile); parameter cromWidth = `CROM_WIDTH; parameter dromWidth = `DROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock enable input [ 0:cromWidth-1] crom; // Control ROM Data input [ 0:dromWidth-1] drom; // Dispatch ROM Data input [ 0:35] dbus; // DBUS Input input [ 0:17] regIR; // Instruction Register input xrPREV; // XR Previous input [ 0:13] vmaFLAGS; // Virtual Memory Flags input [14:35] vmaADDR; // Virtual Memory Address input [ 0: 5] acBLOCK; // AC Blocks output [ 0:35] ramfile; // RAMFILE output // // IR Fields // wire [ 9:12] regIR_AC = `IR_AC(regIR); // Instruction Register AC Field wire [14:17] regIR_XR = `IR_XR(regIR); // Instruction Register XR Field // // VMA Flags // wire vmaWRITECYCLE = `vmaWRITECYCLE(vmaFLAGS); wire vmaPHYSICAL = `vmaPHYSICAL(vmaFLAGS); wire vmaPREVIOUS = `vmaPREVIOUS(vmaFLAGS); // // AC Reference // // Details: // True when addressing lowest 16 addresses using and not // physical addressing. References to the ACs are never // physical. // // Trace // DPM4/E160 // DPM4/E168 // DPM4/E191 // wire vmaACREF = ~vmaPHYSICAL & (vmaADDR[18:31] == 14'b0); // // AC Blocks // wire [0:2] currBLOCK = `currBLOCK(acBLOCK); // Current AC Block wire [0:2] prevBLOCK = `prevBLOCK(acBLOCK); // Previous AC Block // // Address Mux // // Details // This mux provide the address for various RAMFILE // operations. Operations can be: // // Access to the RAMFILE ACs are selected using the // AC field of the instruction. // // 1. Access to an AC in the current context using // the AC field of the instruction. // 2. Access to an AC in the current context using // the XR field of the instruction. // 3. Access to an AC in the previous context using // the XR field of the instruction. // 4. Access to an AC in the current context using // a plain address. // 5. Access to an AC in the previous context using // a plain address. // 6. Access to RAMFILE storage. // 7. Access to the cache // // Note: // The KS10 used {dbm[26:28], dbm[11:17]} for the // cromRAMADDR_SEL_NUM case below. Since the number // field in on both halves of the dbm, this is // equivalent to dbm[8:17]. This has been replaced // by a direct connection to the CROM. // // This was a 74LS181 ALU in the KS10. Only the part of // that device that is used is implemented. This adder is // controlled by one of the overloaded usages of the CROM // number field. // // Trace // DPE6/E3 // DPE6/E6 // DPE6/E7 // DPE6/E8 // DPE6/E13 // DPE6/E14 // DPE6/E15 // DPE6/E16 // DPE6/E21 // DPE6/E22 // DPE6/E23 // DPE6/E24 // DPE6/E79 // reg [0:9] addr; always@(crom or currBLOCK or prevBLOCK or regIR_AC or regIR_XR or xrPREV or vmaACREF or vmaPREVIOUS or vmaADDR) begin case(`cromRAMADDR_SEL) `cromRAMADDR_SEL_AC: addr = {3'b0, currBLOCK, regIR_AC }; `cromRAMADDR_SEL_ACOPNUM: case (`cromACALU_FUN) 6'o25 : addr = {3'b0, currBLOCK, `cromACALU_NUM}; 6'o62 : addr = {3'b0, currBLOCK, `cromACALU_NUM + regIR_AC}; default: addr = {3'b0, currBLOCK, `cromACALU_NUM}; endcase `cromRAMADDR_SEL_XR: begin if (xrPREV) addr = {3'b0, prevBLOCK, regIR_XR}; else addr = {3'b0, currBLOCK, regIR_XR}; end `cromRAMADDR_SEL_VMA: begin if (vmaACREF) begin if (vmaPREVIOUS) addr = {3'b0, prevBLOCK, vmaADDR[32:35]}; else addr = {3'b0, currBLOCK, vmaADDR[32:35]}; end else addr = {1'b1, vmaADDR[27:35]}; end `cromRAMADDR_SEL_RAM: addr = vmaADDR[26:35]; `cromRAMADDR_SEL_NUM: addr = `cromSNUM; default: addr = 9'b0; endcase end // // RAMFILE WRITE // // Todo // FIXME: This is a work-in-progess. // // Trace // DPE5/E119 // DPMA/E22 // DPMA/E54 // wire ramfileWRITE = ((vmaACREF & vmaWRITECYCLE) | (`cromFMWRITE)); // // RAMFILE MEMORY // wire [0:35] dout; RAM1Kx36 uRAM1Kx36 (.clk(clk), .rst(rst), .clken(clken), .wr(ramfileWRITE), .addr(addr), .din(dbus), .dout(ramfile) ); endmodule Dist/rtl/ks10/cpu/regir.v0000700000175100010010000000665712151540226013624 0ustar RobNone//////////////////////////////////////////////////////////////////// //! //! KS-10 Processor //! //! \brief //! Instruction Register (IR) //! //! \details //! //! \todo //! //! \file //! ir.v //! //! \author //! Rob Doyle - doyle (at) cox (dot) net //! //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "useq/crom.vh" module regIR(clk, rst, clken, crom, dbus, prevEN, regIR, xrPREV, opJRST0); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [0:cromWidth-1] crom; // Control ROM Data input [0:35] dbus; // Input Bus input prevEN; // Previous Enable output [0:17] regIR; // Instruction register output xrPREV; // XR Previous output opJRST0; // JRST Instruction // // Microcode Decode // // Note: // 'loadIR' and 'loadXR' can occur simultaneously. Therefore // both parts of the IR register can be loaded simultaneously. // wire loadIR = `cromSPEC_EN_40 & (`cromSPEC_SEL == `cromSPEC_SEL_LOADIR); wire loadXR = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_LOADXR); // // Instruction Register and AC Selection. // // Trace // DPEA/E55 // DPEA/E64 // DPEA/E93 // DPEA/E99 // reg [0:17] regIR; reg xrPREV; always @(posedge clk or posedge rst) begin if (rst) begin regIR <= 18'b0; xrPREV <= 1'b0; end else if (clken) begin if (loadIR) begin regIR[ 0:12] <= dbus[ 0:12]; end if (loadXR) begin regIR[13:17] <= dbus[13:17]; xrPREV <= prevEN; end end end // // JRST 0 decode // // Details // This decodes a JRST 0 instruction. // // Trace // DPEA/E54 // DPEA/E61 // DPE1/E62 // wire [0: 8] irOPCODE = regIR[0: 8]; wire [9:12] irAC = regIR[9:12]; assign opJRST0 = ((irOPCODE == 9'o254) & (irAC == 4'b0)); endmodule Dist/rtl/ks10/cpu/regir.vh0000700000175100010010000000347512151540222013763 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Instruction Register (IR) Definitions // // Details // Contains definitions that are useful to access IR fields // // File // regir.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __REGIR_VH `define __REGIR_VH // // IR Register Field Access // `define IR_OPCODE(reg) (reg[ 0: 8]) // IR opcode Field `define IR_AC(reg) (reg[ 9:12]) // IR AC field `define IR_I(reg) (reg[ 13]) // IR I field `define IR_XR(reg) (reg[14:17]) // IR XR field `define acZERO(reg) (reg[ 9:12] == 4'b0000) // AC field is zero `define xrZERO(reg) (reg[14:17] == 4'b0000) // XR field is zero `endif Dist/rtl/ks10/cpu/scad.v0000700000175100010010000001641512151540226013417 0ustar RobNone//////////////////////////////////////////////////////////////////// //! //! KS-10 Processor //! //! \brief //! Step Count Adder //! //! \details //! //! \todo //! //! \file //! scad.v //! //! \author //! Rob Doyle - doyle (at) cox (dot) net //! //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "useq/crom.vh" module SCAD(clk, rst, clken, crom, dp, feSIGN, scSIGN, scad, dispSCAD); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [0:cromWidth-1] crom; // Control ROM Data input [0:35] dp; // Data path output feSIGN; // FE Sign output scSIGN; // SC Sign output [0: 9] scad; // SCAD output [8:11] dispSCAD; // SCAD Dispatch // // CROM interface // wire [0:2] fun = `cromSCAD_FUN; // SCAN Function wire [0:2] asel = `cromSCAD_ASEL; // SCAD B Input wire [0:1] bsel = `cromSCAD_BSEL; // SCAD A Input wire [0:9] snum = `cromSNUM; // Small number field wire loadSC = `cromLOADSC; // Load SC wire loadFE = `cromLOADFE; // Load FE // // SCADA MUX // // Details: // This mux provides one input to the SCAD ALU. // // Trace: // DPM3/E28 // DPM3/E51 // DPM3/E67 // DPM3/E68 // DPM3/E75 // DPM3/E83 // DPM3/E91 // DPM3/E99 // DPM3/E100 // DPM3/E107 // reg [0: 9] scadA; always @(asel or sc or snum or dp) begin case (asel) `cromSCAD_ASEL_SC: scadA <= sc[0:9]; `cromSCAD_ASEL_SNUM: scadA <= snum[0:9]; `cromSCAD_ASEL_PTR44: scadA <= {sc[0], 6'o44, dp[6], sc[8:9]}; `cromSCAD_ASEL_BYTE1: scadA <= {snum[0], dp[ 0: 6], snum[8:9]}; `cromSCAD_ASEL_BYTE2: scadA <= {sc[0], dp[ 7:13], sc[8:9]}; `cromSCAD_ASEL_BYTE3: scadA <= {snum[0], dp[14:20], snum[8:9]}; `cromSCAD_ASEL_BYTE4: scadA <= {sc[0], dp[21:27], sc[8:9]}; `cromSCAD_ASEL_BYTE5: scadA <= {snum[0], dp[28:34], snum[8:9]}; endcase end // // SCADB Mux // // Details: // This mux provides the other input to the SCAD ALU. // // Trace: // DPM3/E36 // DPM3/E60 // DPM3/E75 // DPM3/E84 // reg [0:9] scadB; always @(bsel or fe or dp) begin case (bsel) `cromSCAD_BSEL_FE: scadB <= fe[0:9]; `cromSCAD_BSEL_EXP: if (dp[0]) scadB <= {2'b00, ~dp[1:8]}; else scadB <= {2'b00, dp[1:8]}; `cromSCAD_BSEL_SHIFT: scadB <= {dp[18], dp[18], dp[28:35]}; `cromSCAD_BSEL_SIZE: scadB <= {1'b0, dp[6:11], 3'b0}; endcase end // // SCAD ALU: // // Details: // The 74LS181 ALUs implment 16 functions. Only 8 functions // are used. Therefore this is a bunch of logic to map the // microcode into the ALU function. // // Notes: // This is positive logic. Be sure to use the right table in // the 74ls181 data sheet. // // Be sure to notice that the CY# input to the ALU is tied to // FUN2 // // The SCAD Carry Skipper DPM4/E704 does not need to be // implemented. The FPGA carry logic does not require // parallel carries for this level of performance. // // The following truth table is derived from the circuit // diagram. // // +-------------+-+-------------------------+---------------+ // | FUN FUN FUN | | ALU ALU ALU ALU ALU ALU | | // | 0 1 2 | | 8 4 2 1 CY M | Descripton | // +-------------+-+-------------------------+---------------+ // | 0 0 0 | | 1 1 0 0 1 0 | F = A + A | // | 0 0 1 | | 1 1 1 0 0 1 | F = A | B | // | 0 1 0 | | 0 1 1 0 1 0 | F = A - B - 1 | // | 0 1 1 | | 0 1 1 0 0 0 | F = A - B | // | 1 0 0 | | 1 0 0 1 1 0 | F = A + B | // | 1 0 1 | | 1 0 1 1 0 1 | F = A & B | // | 1 1 0 | | 1 1 1 1 1 0 | F = A - 1 | // | 1 1 1 | | 1 1 1 1 0 0 | F = A | // +-------------+-+-------------------------+---------------+ // // Funny enough, this matches the microcode. // // Trace: // DPM3/E5 // DPM3/E19 // DPM3/E22 // DPM3/E20 // DPM3/E24 // reg [0:9] scad; always @(fun or scadA or scadB) begin case (fun) `cromSCAD_A_PLUS_A: scad <= scadA + scadA; `cromSCAD_A_OR_B: scad <= scadA | scadB; `cromSCAD_A_MINUS_B_1: scad <= scadA - scadB - 1'b1; `cromSCAD_A_MINUS_B: scad <= scadA - scadB; `cromSCAD_A_PLUS_B: scad <= scadA + scadB; `cromSCAD_A_AND_B: scad <= scadA & scadB; `cromSCAD_A_MINUS_1: scad <= scadA - 1'b1; `cromSCAD_A: scad <= scadA; endcase end // // FE Register // // Details: // Floating-point exponent // // Trace // DPM4/E44 // DPM4/E52 // reg [0:9] fe; always @(posedge clk or posedge rst) begin if (rst) fe <= 9'b0; else if (clken & loadFE) fe <= scad; end // // SC Register // // Details: // Step Counter // // Trace // DPM4/E35 // DPM4/E43 // reg [0:9] sc; always @(posedge clk or posedge rst) begin if (rst) sc <= 9'b0; else if (clken & loadSC) sc <= scad; end // // FE Sign and SC Sign // assign feSIGN = fe[0]; assign scSIGN = sc[0]; // // SCAD Dispatch // assign dispSCAD = (scad[0]) ? 4'b0010 : 4'b0000; endmodule Dist/rtl/ks10/cpu/timer.v0000700000175100010010000001403612151540226013622 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Timer // // Details // The original KS10 interval timer was 12 bits and operated // with a 4.096 MHz clock. The 12-bit timer generates an // interrupt exactly every one millisecond. // // This did not work well in practice. The RDTIME instruction // needs to convert timer output to time in 10 us increment // which would require a division by 40.96. Therefore the // timer frequency was changed to 4.100 MHz and the microcode // does a division by 41 to support the RDTIME instruction. // // You can find the details of KS10 timer design (and it's // problems) in a DEC memo authored by Dan Murphy entitled // "Clocks for Dolphin" on bitsavers.org // // The KS10 would benefit from two timers, one clocked every // 10 microseconds and another clocked every 1 ms, supported // by updated microcode. // // Note // This timer code has been extensively re-written to remove // the 4.1 MHz clock and use the 50 MHz master clock. // // IF YOU CHANGE THE CLOCK FREQUENCY FROM 50 MHZ YOU MUST // CHANGE THE CONSTANTS ks10.vh FOR THE TIMER TO WORK // CORRECTLY. // // File // timer.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "useq/crom.vh" `include "../ks10.vh" module TIMER(clk, rst, clken, crom, timerEN, timerINTR, timerCOUNT); parameter cromWidth = `CROM_WIDTH; parameter CLKFRQ = `CLKFRQ; parameter TIMFRQ = 4.1e6; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [0:cromWidth-1] crom; // Control ROM Data input timerEN; // Timer Enable output timerINTR; // Timer Interrupt output [18:35] timerCOUNT; // Timer output // // Microcode Decode // wire timerRST = `cromSPEC_EN_10 & (`cromSPEC_SEL == `cromSPEC_SEL_CLR1MSEC); // // Frequency Divider // // Detail: // This creates the required 4.1 MHz 'clock' for the KS10 timer. // // Note: // This is an implementation of a Fractional N divider using an // accumulator. // // 32-bit was chosen because at 32-bits, the frequency error // from the frequency division approximation is less than the // frequency error of the clock generator crystal. // // Increment = round-to-integer(2**32 * 4.1 MHz / 50.0 MHz) // // Everytime this 32-bit counter overflows, it is time to // increment the interval timer. // // The use of an accumulator instead of divider keeps the // average output frequency correct. IOW, the accumulator // maintains the fractional time when the count overflows. // reg [0:31] accum; reg carry; wire [0:31] incr = (2.0**32.0) * TIMFRQ / CLKFRQ; always @(posedge clk or posedge rst) begin if (rst) {carry, accum} = 33'b0; else {carry, accum} = {1'b0, accum} + {1'b0, incr}; end wire timerINC = carry; // // Timer // // Details: // This is the one millisecond interval timer. Most of the // timer is implemented in microcode. // // Note: // In the KS10, the timer has the up/down pin wired to the // reset signal. This doesn't make any sense. I have not // implemented this. // // Trace: // DPMC/E180 // DPMC/E181 // DPMC/E189 // reg [0:11] count; always @(posedge clk or posedge rst) begin if (rst) count <= 12'b0; else if (timerEN & timerINC) count <= count + 1'b1; end // // Timer Interrupt // // Details // The timerINTR signal is asserted on a timer overflow; i.e., // when MSB changes from '1' to '0'. // // Note: // Resetting the interrupt has priority over setting the // interrupt. // // Trace: // DPMC/E1 // DPMC/E3 // DPMC/E56 // reg timerMSB; reg intr; always @(posedge clk or posedge rst) begin if (rst) begin intr <= 0; timerMSB <= 0; end else if (clken) begin if (timerRST) intr <= 0; else if (timerEN & ~count[0] & timerMSB) intr <= 1; timerMSB <= count[0]; end end // // Fixups // The KS10 does not use the two LSBS of the timer. The upper // 6-bits are also not significant. The microcode seems to // read all of the bits and does not perform any masking. // assign timerCOUNT[18:23] = 6'b0; assign timerCOUNT[24:33] = count[0:9]; assign timerCOUNT[34:35] = 2'b0; assign timerINTR = intr; endmodule Dist/rtl/ks10/cpu/timing.v0000700000175100010010000000627512151540226013777 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Read/Write Timing // // Details // // File // timing.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "useq/crom.vh" `include "useq/drom.vh" module TIMING(clk, rst, crom, feSIGN, clkenDP, clkenCR, memWAIT); parameter cromWidth = `CROM_WIDTH; parameter dromWidth = `DROM_WIDTH; input clk; // Clock input rst; // Reset input [0:cromWidth-1] crom; // Control ROM Data input feSIGN; // FE Sign output clkenDP; // Clock Enable output clkenCR; // Clock Enable Microsequencer input memWAIT; // Memory Wait // // Fast Shift // // Details: // The KS10 fast shifts while the FE is negative. // // Note: // The obvious implementation shifts one count too many and // shifts by one when the count is zero. This is very counter- // intuitive. // // Be careful. When the shift count is zero (FE = -1 or 1777) // no shifts should be peformed. // // FIXME: // This crazy fast shift stuff should be replaced by a microcode hack. // The FPGA doesn't really require this fast shift implementation. // // Trace // CSL5/E33 // CSL5/E44 // CSL5/E45 // CSL5/E52 // CSL5/E53 // CSL5/E54 // CSL5/E71 // reg done; always @(posedge clk or posedge rst) begin if (rst) done = 1'b0; else done = feSIGN & `cromMULTISHIFT; end // // Clock enables // // Details // In the KS10, the Control ROM (KS10 CRA/M) and the Data Path // (KS10 DPE/M) are clock enabled independantly. // // Trace // CSL5/E33 // CSL5/E54 // assign clkenCR = ~((`cromMULTISHIFT & feSIGN) | memWAIT); assign clkenDP = ~((`cromMULTISHIFT & ~feSIGN) | (done & clkenCR) | memWAIT); endmodule Dist/rtl/ks10/cpu/useq/0000700000175100010010000000000012151543355013267 5ustar RobNoneDist/rtl/ks10/cpu/useq/crom.awk0000700000175100010010000000217712151540232014734 0ustar RobNoneBEGIN { FS="[, ; ]"; printf "//\n"; printf "//\n"; printf "// CROM.DAT\n"; printf "// This code is extracted from the KS10 microcode listing by an\n"; printf "// AWK script. DO NOT EDIT THIS FILE!\n"; printf "//\n"; printf "//\n"; printf "\n"; } /U [0-7][0-7][0-7][0-7], / { #print $4 " " $5 " " $6 " " $7 " " $8 " " $9 " " $10 " " $11 " " $12 "// " $2 i = strtonum("0" $2) MAP2[i] = $2; MAP[4,i] = $4; MAP[5,i] = $5; MAP[6,i] = $6; MAP[7,i] = $7; MAP[8,i] = $8; MAP[9,i] = $9; MAP[10,i] = $10; MAP[11,i] = $11; MAP[12,i] = $12; } END { for (i = 0; i < 04000; i++) { if (strtonum("0" MAP2[i]) == i) { printf " CROM[%4d] = 108'o%s_%s_%s_%s_%s_%s_%s_%s_%s;\n", i, MAP[ 4,i], MAP[ 5,i], MAP[ 6,i], MAP[ 7,i], MAP[ 8,i], MAP[ 9,i], MAP[10,i], MAP[11,i], MAP[12,i] } else { printf " CROM[%4d] = 108'o%s_%s_%s_%s_%s_%s_%s_%s_%s; // Unused\n", i, "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000", "0000" } } } Dist/rtl/ks10/cpu/useq/crom.dat0000700000175100010010000046056112151540234014731 0ustar RobNone// // // CROM.DAT // This code is extracted from the KS10 microcode listing by an // AWK script. DO NOT EDIT THIS FILE! // // CROM[ 0] = 108'o0002_3771_0012_4374_4007_0700_0000_0037_7777; CROM[ 1] = 108'o3676_3333_0004_7174_4007_0700_0410_0000_0212; CROM[ 2] = 108'o0013_3445_1212_4174_4007_0700_0000_0000_0000; CROM[ 3] = 108'o0100_4751_1203_4374_4007_0700_0000_0037_6000; CROM[ 4] = 108'o2476_4443_0000_4174_4107_0640_0000_0000_0062; CROM[ 5] = 108'o0004_4443_0000_4174_4007_0660_0000_0000_0000; CROM[ 6] = 108'o3412_4443_0000_4174_4007_0700_0010_0000_0000; CROM[ 7] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 8] = 108'o0560_3771_0004_1276_6007_0701_0010_0000_1444; CROM[ 9] = 108'o0024_3771_0004_7274_4007_0701_0000_0000_0227; CROM[ 10] = 108'o0324_3333_0005_6174_4007_0700_0400_0000_0000; CROM[ 11] = 108'o0053_3551_1212_4374_4007_0700_0000_0000_0001; CROM[ 12] = 108'o1400_3333_0005_4174_4007_0571_0000_0000_0000; CROM[ 13] = 108'o1116_7441_0303_4174_4007_0700_0000_0000_0000; CROM[ 14] = 108'o1123_6551_0303_0274_4007_0700_0000_0000_0000; CROM[ 15] = 108'o1123_3551_0303_0274_4007_0700_0000_0000_0000; CROM[ 16] = 108'o2746_4221_0002_4174_0007_0700_0010_0000_0000; CROM[ 17] = 108'o3000_3446_0606_4174_4007_0700_0010_0000_0000; CROM[ 18] = 108'o3541_3333_0002_4175_5007_0701_0210_0000_0002; CROM[ 19] = 108'o3667_0111_0704_4170_4007_0700_0210_0023_1016; CROM[ 20] = 108'o3700_4223_0000_4364_4277_0700_0210_0000_0010; CROM[ 21] = 108'o1176_3333_0004_4174_4007_0621_0000_0000_0000; CROM[ 22] = 108'o2475_4443_0000_4174_4107_0700_0000_0000_0074; CROM[ 23] = 108'o2740_4751_1205_4374_4007_0700_0000_0000_0430; CROM[ 24] = 108'o0002_3773_0000_2274_4464_1700_0000_0001_0004; CROM[ 25] = 108'o3000_3446_0606_4174_4007_0700_0010_0000_0000; CROM[ 26] = 108'o0002_3333_0002_4174_4464_1700_0000_0001_0004; CROM[ 27] = 108'o3060_4443_0000_4174_4007_0700_0010_0000_0000; CROM[ 28] = 108'o2556_0551_0202_2270_4007_0700_0200_0004_0012; CROM[ 29] = 108'o2760_3445_0403_4174_4007_0700_0000_0000_0000; CROM[ 30] = 108'o2556_3443_0200_4174_4007_0700_0200_0004_0112; CROM[ 31] = 108'o0555_4443_0000_4174_4467_0700_0000_0051_1000; CROM[ 32] = 108'o0000_3771_0003_4365_5001_2700_0200_0000_0002; CROM[ 33] = 108'o0000_3771_0003_0276_6001_2700_0000_0000_0000; CROM[ 34] = 108'o0401_3771_0003_4365_5007_0700_0200_0000_0002; CROM[ 35] = 108'o0415_3771_0003_0276_6007_0700_0000_0000_0000; CROM[ 36] = 108'o0000_3333_0003_4174_4001_2530_3000_0041_5777; CROM[ 37] = 108'o0416_3772_0000_1275_5007_0701_0000_0000_1441; CROM[ 38] = 108'o0372_3770_0303_4344_4007_0700_0000_0000_0000; CROM[ 39] = 108'o0372_3771_0003_4365_5007_0700_0200_0000_0002; CROM[ 40] = 108'o0000_3770_0103_4365_5001_2700_0200_0014_0012; CROM[ 41] = 108'o0402_3771_0005_4365_5177_0521_3000_0041_2000; CROM[ 42] = 108'o0404_4443_0000_4174_4007_0040_0000_0000_0000; CROM[ 43] = 108'o0061_3447_1200_4174_4007_0700_0000_0000_0000; CROM[ 44] = 108'o1232_4552_0000_1275_5007_0701_0000_0000_1441; CROM[ 45] = 108'o3060_6551_1717_4374_4007_0700_0010_0000_0007; CROM[ 46] = 108'o3027_0001_1616_4174_4007_0700_0000_0000_0000; CROM[ 47] = 108'o3025_2225_0016_4174_4007_0700_4000_0000_0000; CROM[ 48] = 108'o3667_3443_0300_4174_4007_0700_0210_0003_0012; CROM[ 49] = 108'o0071_3771_0015_4374_4007_0700_0000_0000_0001; CROM[ 50] = 108'o3000_3446_0606_4174_4007_0700_0010_0000_0000; CROM[ 51] = 108'o1372_3333_0003_4174_4007_0520_0000_0000_0000; CROM[ 52] = 108'o3670_0111_0703_4170_4007_0700_0210_0003_0012; CROM[ 53] = 108'o2606_0111_0703_4174_4007_0700_0200_0004_0002; CROM[ 54] = 108'o3147_0661_0003_7274_4007_0701_0000_0000_0225; CROM[ 55] = 108'o2440_4571_1205_4374_4007_0700_0000_0024_1220; CROM[ 56] = 108'o3101_0553_0300_2274_4007_0700_0200_0004_0712; CROM[ 57] = 108'o0003_4751_1207_4374_4007_0700_0010_0000_0001; CROM[ 58] = 108'o3101_3443_0300_4174_4007_0700_0200_0004_0712; CROM[ 59] = 108'o1514_0111_0503_4174_4003_7700_0200_0003_0001; CROM[ 60] = 108'o3100_0553_0300_2274_4007_0700_0200_0004_0512; CROM[ 61] = 108'o0054_3447_0303_4174_4007_0700_0000_0000_0000; CROM[ 62] = 108'o3100_3443_0300_4174_4007_0700_0200_0004_0512; CROM[ 63] = 108'o2440_4571_1205_4374_4007_0700_0000_0024_1200; CROM[ 64] = 108'o0106_3333_0003_7174_4007_0700_0400_0000_0227; CROM[ 65] = 108'o3474_4751_1203_4374_4367_0700_0000_0000_0423; CROM[ 66] = 108'o3474_4751_1203_4374_4367_0700_0000_0000_0422; CROM[ 67] = 108'o3474_4751_1203_4374_4367_0700_0000_0000_0421; CROM[ 68] = 108'o3676_3333_0004_7174_4007_0700_0410_0000_0212; CROM[ 69] = 108'o0104_4751_1217_4374_4007_0700_0000_0000_0002; CROM[ 70] = 108'o0110_4221_0011_4364_4277_0700_0200_0000_0010; CROM[ 71] = 108'o0117_3443_0100_4174_4007_0700_0200_0014_0012; CROM[ 72] = 108'o0125_4221_0010_4174_4477_0700_0000_0000_0000; CROM[ 73] = 108'o3474_4751_1203_4374_4367_0700_0000_0000_0423; CROM[ 74] = 108'o3474_4751_1203_4374_4367_0700_0000_0000_0422; CROM[ 75] = 108'o3474_4751_1203_4374_4367_0700_0000_0000_0421; CROM[ 76] = 108'o3675_4223_0000_4364_4277_0700_0210_0000_0010; CROM[ 77] = 108'o0104_4751_1217_4374_4007_0700_0000_0000_0002; CROM[ 78] = 108'o3674_4221_0004_4174_4007_0700_0200_0021_1016; CROM[ 79] = 108'o0363_3771_0002_4365_5617_0700_0200_0000_0002; CROM[ 80] = 108'o2774_4557_0006_1274_4007_0701_0010_0000_1441; CROM[ 81] = 108'o2764_4557_0004_1274_4007_0701_0000_0000_1442; CROM[ 82] = 108'o0122_3336_0604_4174_4046_2630_2000_0060_0000; CROM[ 83] = 108'o0004_3334_0604_4174_4004_1700_0000_0000_0000; CROM[ 84] = 108'o0171_3223_0000_1174_4007_0700_0400_0000_1443; CROM[ 85] = 108'o0131_4221_0013_4174_4257_0700_0000_0000_0000; CROM[ 86] = 108'o0142_1116_0604_4174_4046_2630_6000_0060_0000; CROM[ 87] = 108'o0004_1114_0604_4174_4004_1700_4000_0000_0000; CROM[ 88] = 108'o3075_3771_0003_0276_6007_0700_0010_0000_0000; CROM[ 89] = 108'o0162_3333_0013_7174_4007_0700_0400_0000_0230; CROM[ 90] = 108'o2055_4221_0017_4174_4007_0700_0010_0000_0000; CROM[ 91] = 108'o2030_3441_0305_1174_4007_0421_0000_0000_1441; CROM[ 92] = 108'o3671_3441_0104_4170_4007_0700_0010_0000_0000; CROM[ 93] = 108'o1400_0551_0501_4370_4007_0701_0000_0000_0001; CROM[ 94] = 108'o1400_4113_0305_4174_4007_0330_0000_0000_0020; CROM[ 95] = 108'o3613_3771_0005_4374_0007_0700_0000_0003_0130; CROM[ 96] = 108'o0104_4751_1217_4374_4007_0700_0000_0000_1005; CROM[ 97] = 108'o3607_4221_0014_4174_4007_0700_0010_0000_0000; CROM[ 98] = 108'o0122_0116_0604_4174_4046_2630_2000_0060_0000; CROM[ 99] = 108'o0004_0114_0604_4174_4004_1700_0000_0000_0000; CROM[ 100] = 108'o3043_4222_0000_4174_4007_0700_2010_0071_0033; CROM[ 101] = 108'o0144_3447_0303_4174_4007_0700_1000_0041_0001; CROM[ 102] = 108'o0142_3336_0604_4174_4046_2630_2000_0060_0000; CROM[ 103] = 108'o0004_3334_0604_4174_4004_1700_0000_0000_0000; CROM[ 104] = 108'o2551_3771_0002_4365_5217_0700_0210_0000_0002; CROM[ 105] = 108'o0343_4751_1217_4374_4007_0700_0000_0000_0120; CROM[ 106] = 108'o0110_3441_0301_4170_4156_4700_0200_0014_0012; CROM[ 107] = 108'o2055_3444_1616_4174_4067_0700_0010_0000_0000; CROM[ 108] = 108'o3204_3227_0003_4174_4007_0700_0000_0000_0000; CROM[ 109] = 108'o2054_3333_0003_4174_4007_0621_0010_0000_0000; CROM[ 110] = 108'o2054_3333_0003_4174_4007_0621_0010_0000_0000; CROM[ 111] = 108'o3204_3227_0003_4174_4007_0700_0000_0000_0000; CROM[ 112] = 108'o1216_7443_0300_4174_4007_0621_0000_0000_0000; CROM[ 113] = 108'o0164_3333_0005_4174_4007_0621_0000_0000_0000; CROM[ 114] = 108'o0212_3333_0013_7174_4007_0700_0400_0000_0300; CROM[ 115] = 108'o3000_3446_0606_4174_4007_0700_0010_0000_0000; CROM[ 116] = 108'o0370_4443_0000_4174_4007_0700_2010_0071_0042; CROM[ 117] = 108'o0555_4443_0000_4174_4467_0700_0000_0051_1000; CROM[ 118] = 108'o1177_3441_0304_4174_4007_0700_0000_0000_0000; CROM[ 119] = 108'o3177_4662_0000_4370_4007_0700_0000_0077_7000; CROM[ 120] = 108'o0172_0551_0505_2270_4007_0700_0000_0000_0000; CROM[ 121] = 108'o0563_3442_0300_4174_4007_0700_2010_0071_0043; CROM[ 122] = 108'o0556_5741_0505_4174_4003_7700_0200_0000_0010; CROM[ 123] = 108'o3225_3444_1616_4174_4067_0700_0000_0000_0000; CROM[ 124] = 108'o3263_0551_0505_2270_4007_0700_0200_0004_0512; CROM[ 125] = 108'o2763_3441_0416_4174_4007_0700_0000_0000_0000; CROM[ 126] = 108'o3263_3443_0500_4174_4007_0700_0200_0004_0512; CROM[ 127] = 108'o3204_2227_0003_4174_4007_0700_4000_0000_0000; CROM[ 128] = 108'o0200_3444_0303_4174_4043_4701_1000_0041_1777; CROM[ 129] = 108'o0110_0551_0201_2270_4156_4700_0200_0014_0012; CROM[ 130] = 108'o0322_3333_0003_4174_4003_4701_0010_0000_0000; CROM[ 131] = 108'o0110_3441_0201_4170_4156_4700_0200_0014_0012; CROM[ 132] = 108'o0322_3446_0303_4174_4047_0700_1010_0041_0001; CROM[ 133] = 108'o0366_0551_0202_2270_4007_0700_0200_0004_0012; CROM[ 134] = 108'o0322_3446_0303_4174_4047_0700_1010_0041_0001; CROM[ 135] = 108'o0366_3443_0200_4174_4007_0700_0200_0004_0012; CROM[ 136] = 108'o3255_4002_0000_4174_0007_0700_0000_0000_0000; CROM[ 137] = 108'o0213_0551_0202_2270_4007_0700_0000_0000_0000; CROM[ 138] = 108'o0214_3333_0013_7174_4007_0700_0400_0000_0301; CROM[ 139] = 108'o0000_5741_0203_4174_4001_3700_0200_0000_0342; CROM[ 140] = 108'o0223_4223_0000_1174_4007_0700_0400_0000_1443; CROM[ 141] = 108'o0366_0551_0202_2270_4007_0700_0200_0004_0112; CROM[ 142] = 108'o0610_4111_1204_4174_4007_0700_0000_0000_0000; CROM[ 143] = 108'o0366_3443_0200_4174_4007_0700_0200_0004_0112; CROM[ 144] = 108'o0221_3441_0301_4174_4007_0700_0200_0014_0012; CROM[ 145] = 108'o0100_3440_0404_0174_4156_4700_0400_0000_0000; CROM[ 146] = 108'o1400_3440_0404_0174_4007_0700_0400_0000_0000; CROM[ 147] = 108'o0226_3333_0007_1174_4007_0700_0400_0000_1444; CROM[ 148] = 108'o0323_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 149] = 108'o0140_6553_0500_4374_4007_0321_0000_0033_0656; CROM[ 150] = 108'o0235_4221_0003_4174_4007_0700_2000_0071_0023; CROM[ 151] = 108'o2452_4553_0300_4374_4007_0331_0000_0000_0001; CROM[ 152] = 108'o3101_0553_0300_2274_4007_0701_0200_0004_0712; CROM[ 153] = 108'o3447_3441_0503_4174_4007_0700_0000_0000_0000; CROM[ 154] = 108'o3101_3443_0300_4174_4007_0700_0200_0004_0712; CROM[ 155] = 108'o3446_3770_0503_4334_4017_0700_0000_0032_6000; CROM[ 156] = 108'o3454_0553_0300_2274_4007_0701_0200_0004_0612; CROM[ 157] = 108'o0242_3333_0007_7174_4007_0700_0400_0000_0344; CROM[ 158] = 108'o3454_3443_0300_4174_4007_0700_0200_0004_0612; CROM[ 159] = 108'o3650_4571_1204_4374_4007_0700_0000_0021_1200; CROM[ 160] = 108'o3127_3333_0003_7174_4007_0700_0400_0000_0223; CROM[ 161] = 108'o0350_3770_0305_4334_4016_7351_0010_0033_6000; CROM[ 162] = 108'o0244_4223_0000_7174_4007_0700_0400_0000_0373; CROM[ 163] = 108'o2054_3333_0017_4174_4007_0621_0010_0000_0000; CROM[ 164] = 108'o0311_3771_0002_4374_4007_0700_0000_0000_0344; CROM[ 165] = 108'o0110_3443_0100_4174_4156_4700_0200_0014_0012; CROM[ 166] = 108'o3412_3333_0004_7174_4007_0700_0410_0000_0246; CROM[ 167] = 108'o3411_3771_0003_7274_4007_0701_0000_0000_0246; CROM[ 168] = 108'o0110_3443_0100_4174_4156_4700_0200_0014_0012; CROM[ 169] = 108'o1400_3333_0003_4174_4007_0520_0000_0000_0000; CROM[ 170] = 108'o1400_3333_0003_4174_4007_0621_0000_0000_0000; CROM[ 171] = 108'o1400_3333_0003_4174_4007_0421_0000_0000_0000; CROM[ 172] = 108'o0110_0111_0701_4170_4156_4700_0200_0014_0012; CROM[ 173] = 108'o0260_3333_0003_4174_4007_0520_0000_0000_0000; CROM[ 174] = 108'o0260_3333_0003_4174_4007_0621_0000_0000_0000; CROM[ 175] = 108'o0260_3333_0003_4174_4007_0421_0000_0000_0000; CROM[ 176] = 108'o0110_0111_0701_4170_4156_4700_0200_0014_0012; CROM[ 177] = 108'o0110_3443_0100_4174_4156_4700_0200_0014_0012; CROM[ 178] = 108'o0407_3447_0705_4174_4003_7700_0000_0000_0000; CROM[ 179] = 108'o3236_3444_0303_4174_4047_0700_0000_0000_0000; CROM[ 180] = 108'o3077_3333_0003_4174_4217_0700_0010_0000_0500; CROM[ 181] = 108'o0360_3333_0003_4174_4006_5701_0010_0000_0000; CROM[ 182] = 108'o0262_3447_0303_4174_4007_0700_1000_0041_0001; CROM[ 183] = 108'o1400_4443_0000_4174_4467_0700_0000_0005_0000; CROM[ 184] = 108'o0100_3440_0505_0174_4156_4700_0400_0000_0000; CROM[ 185] = 108'o0762_3770_0505_0174_4007_0520_0400_0000_0000; CROM[ 186] = 108'o0762_3770_0505_0174_4007_0621_0400_0000_0000; CROM[ 187] = 108'o0762_3770_0505_0174_4007_0421_0400_0000_0000; CROM[ 188] = 108'o0764_3440_0505_0174_4007_0700_0400_0000_0000; CROM[ 189] = 108'o0764_3770_0505_0174_4007_0520_0400_0000_0000; CROM[ 190] = 108'o0764_3770_0505_0174_4007_0621_0400_0000_0000; CROM[ 191] = 108'o0764_3770_0505_0174_4007_0421_0400_0000_0000; CROM[ 192] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 193] = 108'o2551_3771_0002_4365_5217_0700_0210_0000_0002; CROM[ 194] = 108'o0016_4443_0000_4174_4004_1700_0000_0000_0000; CROM[ 195] = 108'o2432_4553_1400_4374_4007_0331_0010_0007_7400; CROM[ 196] = 108'o0305_5111_0514_4170_4007_0700_0000_0000_0000; CROM[ 197] = 108'o3610_3770_1416_4344_4007_0700_0010_0000_0000; CROM[ 198] = 108'o0016_3447_0303_4174_4004_1700_1000_0041_0001; CROM[ 199] = 108'o3610_3770_1416_4344_4007_0700_0010_0000_0000; CROM[ 200] = 108'o2746_3333_0002_4175_5007_0701_0210_0000_0002; CROM[ 201] = 108'o0323_3771_0006_4374_4007_0700_0000_0000_0373; CROM[ 202] = 108'o2745_3741_0103_4074_4007_0700_0010_0000_0000; CROM[ 203] = 108'o0022_3333_0003_4175_5007_0701_0200_0000_0002; CROM[ 204] = 108'o2746_3333_0003_4175_5007_0701_0210_0000_0002; CROM[ 205] = 108'o0110_3443_0100_4174_4156_4700_0200_0014_0012; CROM[ 206] = 108'o0020_3333_0001_4175_5007_0701_0200_0000_0002; CROM[ 207] = 108'o0110_3441_0301_4170_4156_4700_0200_0014_0012; CROM[ 208] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 209] = 108'o2432_4553_1400_4374_4007_0331_0010_0007_7400; CROM[ 210] = 108'o0462_0007_0704_4174_4007_0511_0000_0000_0000; CROM[ 211] = 108'o0010_0111_0706_4174_4007_0700_0200_0000_0010; CROM[ 212] = 108'o0334_0111_0702_4174_4007_0700_0200_0000_0010; CROM[ 213] = 108'o0335_3333_0012_4174_4437_0700_0000_0000_0000; CROM[ 214] = 108'o0322_3446_0303_4174_4047_0700_1000_0041_0001; CROM[ 215] = 108'o2002_4553_1300_4374_4007_0321_0000_0000_2000; CROM[ 216] = 108'o1220_3333_0005_4174_4007_0520_0000_0000_0000; CROM[ 217] = 108'o3071_4551_0404_4374_0007_0700_0010_0037_7777; CROM[ 218] = 108'o3450_3771_0003_7274_4007_0700_0010_0000_0244; CROM[ 219] = 108'o1220_3333_0005_4174_4007_0520_0000_0000_0000; CROM[ 220] = 108'o0224_3333_0004_6174_4007_0630_2400_0060_0000; CROM[ 221] = 108'o1525_4223_0000_4364_4277_0700_0200_0000_0010; CROM[ 222] = 108'o3437_3771_0003_1276_6007_0701_0000_0000_1443; CROM[ 223] = 108'o2005_4111_1203_4174_4007_0700_0000_0000_0000; CROM[ 224] = 108'o0550_4443_0000_4174_4006_7701_0000_0031_0210; CROM[ 225] = 108'o3102_3770_0505_4334_4057_0700_0000_0073_0000; CROM[ 226] = 108'o3102_3770_0505_4334_4057_0700_0000_0074_0000; CROM[ 227] = 108'o0346_4221_0001_4174_4467_0700_0000_0000_0004; CROM[ 228] = 108'o3102_3770_0505_4334_4057_0700_0000_0075_0000; CROM[ 229] = 108'o3102_3770_0505_4334_4057_0700_0000_0076_0000; CROM[ 230] = 108'o0116_3771_0017_4374_4007_0700_0000_0000_0000; CROM[ 231] = 108'o3102_3770_0505_4334_4057_0700_0000_0077_0000; CROM[ 232] = 108'o3075_3441_0503_4174_4007_0700_0200_0003_0002; CROM[ 233] = 108'o0004_4443_0000_4174_4004_1700_0000_0000_0000; CROM[ 234] = 108'o3074_3770_0503_4334_4017_0700_0000_0032_6000; CROM[ 235] = 108'o0004_4443_0000_4174_4004_1700_0000_0000_0000; CROM[ 236] = 108'o1264_3446_1200_4174_4007_0700_2010_0071_0042; CROM[ 237] = 108'o3040_3444_0303_4174_4047_0700_0000_0000_0000; CROM[ 238] = 108'o3021_3224_0016_4174_4007_0700_0000_0000_0000; CROM[ 239] = 108'o3037_2222_0000_4174_4007_0700_4000_0000_0000; CROM[ 240] = 108'o3114_3333_0003_4174_4007_0700_1000_0031_7770; CROM[ 241] = 108'o3112_3770_0503_4334_4017_0700_0000_0041_0000; CROM[ 242] = 108'o3112_3770_0503_4334_4027_0700_0000_0041_0000; CROM[ 243] = 108'o0201_0111_0701_2170_4366_6700_0200_0010_0010; CROM[ 244] = 108'o3112_3770_0503_4334_4037_0700_0000_0041_0000; CROM[ 245] = 108'o3112_3770_0503_4334_4047_0700_0000_0041_0000; CROM[ 246] = 108'o0371_3771_0002_4361_5217_0700_0200_0000_0102; CROM[ 247] = 108'o3112_3770_0503_4334_4057_0700_0000_0041_0000; CROM[ 248] = 108'o3043_4662_0000_4374_0007_0700_0010_0037_7777; CROM[ 249] = 108'o0201_3443_0100_2174_4006_6700_0200_0010_0010; CROM[ 250] = 108'o0412_3333_0003_4174_4007_0520_3010_0041_2000; CROM[ 251] = 108'o0000_4221_0004_4174_4001_2700_0000_0000_0000; CROM[ 252] = 108'o0002_4443_0000_4174_4004_1700_0000_0000_0000; CROM[ 253] = 108'o0002_2222_0000_4174_4004_1700_4000_0000_0000; CROM[ 254] = 108'o0377_2222_0000_4174_4007_0700_4000_0000_0000; CROM[ 255] = 108'o0002_2441_0303_4174_4004_1700_4000_0000_0000; CROM[ 256] = 108'o2747_3333_0003_4174_4007_0700_0200_0003_0012; CROM[ 257] = 108'o0406_0111_0702_4170_4007_0700_0200_0004_0312; CROM[ 258] = 108'o0445_0111_0703_4174_4007_0700_0200_0004_0312; CROM[ 259] = 108'o0432_0111_0703_4174_4007_0700_0200_0004_0312; CROM[ 260] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 261] = 108'o0000_4443_0000_4174_4001_2700_0000_0000_0000; CROM[ 262] = 108'o0000_3771_0004_4365_5001_2700_0200_0000_0002; CROM[ 263] = 108'o0016_4443_0000_4174_4004_1700_0000_0000_0000; CROM[ 264] = 108'o2775_3777_0006_0274_4007_0701_0010_0000_0000; CROM[ 265] = 108'o2777_0113_1616_1174_4007_0701_0400_0000_1441; CROM[ 266] = 108'o0001_4551_0303_4374_0004_1700_0000_0000_0777; CROM[ 267] = 108'o0001_3551_0303_4374_0004_1700_0000_0077_7000; CROM[ 268] = 108'o2765_3223_0000_1174_4007_0700_0400_0000_1442; CROM[ 269] = 108'o0000_3771_0004_1276_6001_2701_0000_0000_1441; CROM[ 270] = 108'o0431_3776_0005_0274_4007_0701_0000_0000_0000; CROM[ 271] = 108'o0302_0111_0503_4174_4003_4701_0000_0000_0000; CROM[ 272] = 108'o0420_3444_0303_4174_4063_4701_1000_0041_1777; CROM[ 273] = 108'o2000_2222_0000_4174_4007_0311_4000_0000_0000; CROM[ 274] = 108'o0262_3333_0003_4174_4003_4701_0010_0000_0000; CROM[ 275] = 108'o2000_2222_0000_4174_4007_0311_4000_0000_0000; CROM[ 276] = 108'o0262_3447_0303_4174_4007_0700_1010_0041_0001; CROM[ 277] = 108'o2000_2222_0000_4174_4007_0311_4000_0000_0000; CROM[ 278] = 108'o0262_3447_0303_4174_4007_0700_1010_0041_0001; CROM[ 279] = 108'o2000_2222_0000_4174_4007_0311_4000_0000_0000; CROM[ 280] = 108'o1376_3223_0000_4174_4007_0621_0000_0000_0000; CROM[ 281] = 108'o0044_3446_0505_4174_4007_0700_0000_0000_0000; CROM[ 282] = 108'o0451_3551_0505_4374_0007_0700_0000_0077_7000; CROM[ 283] = 108'o3222_5111_1217_4174_4007_0700_0000_0000_0000; CROM[ 284] = 108'o1515_3333_0003_4175_5007_0701_0200_0000_0002; CROM[ 285] = 108'o1400_3333_0003_4175_5007_0701_0200_0000_0002; CROM[ 286] = 108'o1377_3770_0303_4324_0457_0700_0000_0041_0000; CROM[ 287] = 108'o0433_0222_0000_4174_4007_0700_4000_0000_0000; CROM[ 288] = 108'o0440_3444_0303_4174_4063_4701_1000_0041_1777; CROM[ 289] = 108'o2214_3771_0004_1276_6007_0701_0010_0000_1441; CROM[ 290] = 108'o0262_3333_0003_4174_4003_4701_0010_0000_0000; CROM[ 291] = 108'o2170_0111_0706_4174_4007_0630_2000_0060_0000; CROM[ 292] = 108'o0262_3447_0303_4174_4007_0700_1010_0041_0001; CROM[ 293] = 108'o0451_4551_0505_4374_0007_0700_0000_0000_0777; CROM[ 294] = 108'o0262_3447_0303_4174_4007_0700_1010_0041_0001; CROM[ 295] = 108'o2172_4553_0600_4374_4007_0331_0000_0077_7777; CROM[ 296] = 108'o0440_3444_0303_4174_4063_4701_1000_0041_1777; CROM[ 297] = 108'o0452_4557_0004_4365_5007_0701_0200_0000_0002; CROM[ 298] = 108'o0467_3447_0503_4174_4007_0700_0000_0000_0000; CROM[ 299] = 108'o3227_3446_1616_4174_4047_0700_0000_0000_0000; CROM[ 300] = 108'o0454_3444_0303_4174_4447_0630_2000_0060_0000; CROM[ 301] = 108'o1515_3445_0303_4174_4007_0700_0000_0000_0000; CROM[ 302] = 108'o0327_3770_0303_4324_0453_7700_0000_0041_0000; CROM[ 303] = 108'o0453_3551_1313_4374_0007_0700_0000_0000_2000; CROM[ 304] = 108'o1074_0551_0703_7274_4007_0701_0010_0000_0242; CROM[ 305] = 108'o2142_4553_0600_4374_4007_0321_0000_0010_0000; CROM[ 306] = 108'o0016_3770_0303_4324_0454_1700_0000_0041_0000; CROM[ 307] = 108'o0462_0441_0303_4174_4003_4701_4000_0000_0000; CROM[ 308] = 108'o3335_7771_0003_7274_4007_0701_0000_0000_0242; CROM[ 309] = 108'o2132_1553_0300_4374_4007_0532_4000_0000_0012; CROM[ 310] = 108'o0462_3447_0303_4174_4007_0700_1000_0041_0001; CROM[ 311] = 108'o0471_3447_0303_4174_4007_0700_2000_0011_0000; CROM[ 312] = 108'o3667_3741_0105_4074_4007_0700_0010_0000_0000; CROM[ 313] = 108'o0000_3443_0100_4174_4001_2700_0200_0014_0012; CROM[ 314] = 108'o0472_3446_1616_4174_4046_2630_2000_0060_0000; CROM[ 315] = 108'o0453_3221_0017_4174_4006_2700_0000_0000_0000; CROM[ 316] = 108'o3664_3771_0003_4374_0007_0700_0010_0000_0000; CROM[ 317] = 108'o2714_3441_0301_4174_4467_0700_0000_0000_0004; CROM[ 318] = 108'o2016_3551_1313_4374_0007_0700_0000_0000_2000; CROM[ 319] = 108'o2017_3551_1313_4374_0007_0700_0000_0000_2000; CROM[ 320] = 108'o1074_0551_0703_7274_4007_0701_0010_0000_0242; CROM[ 321] = 108'o0750_3441_0304_4174_4007_0520_0000_0000_0000; CROM[ 322] = 108'o0767_3441_0301_4174_4007_0700_0200_0014_0012; CROM[ 323] = 108'o1400_4223_0000_1174_4007_0700_0400_0000_1441; CROM[ 324] = 108'o3270_1771_0003_7274_4007_0701_4000_0000_0242; CROM[ 325] = 108'o3450_3771_0013_4370_4007_0700_0010_0000_0005; CROM[ 326] = 108'o1515_3333_0005_4175_5007_0701_0200_0000_0002; CROM[ 327] = 108'o0500_3771_0013_4370_4007_0700_0000_0000_0003; CROM[ 328] = 108'o3450_3771_0013_4370_4007_0700_0010_0000_0012; CROM[ 329] = 108'o1402_3771_0003_0270_6007_0700_0000_0000_0000; CROM[ 330] = 108'o1402_3771_0003_0276_0007_0700_0000_0000_0000; CROM[ 331] = 108'o2040_3333_0017_4174_4007_0520_1000_0031_0202; CROM[ 332] = 108'o0514_3445_0505_4174_4007_0520_1000_0041_0004; CROM[ 333] = 108'o1006_3777_0003_4334_4057_0700_0000_0041_0000; CROM[ 334] = 108'o3365_2551_0705_1274_4007_0701_4000_0000_1443; CROM[ 335] = 108'o0513_0222_0000_4174_4007_0700_4000_0000_0000; CROM[ 336] = 108'o0520_3444_0303_4174_4043_4701_1000_0041_1777; CROM[ 337] = 108'o2044_4553_1300_4374_4007_0321_0000_0000_2000; CROM[ 338] = 108'o0322_3333_0003_4174_4003_4701_0010_0000_0000; CROM[ 339] = 108'o2044_4553_1300_4374_4007_0321_0000_0000_2000; CROM[ 340] = 108'o0322_3446_0303_4174_4047_0700_1010_0041_0001; CROM[ 341] = 108'o2044_4553_1300_4374_4007_0321_0000_0000_2000; CROM[ 342] = 108'o0322_3446_0303_4174_4047_0700_1010_0041_0001; CROM[ 343] = 108'o2044_4553_1300_4374_4007_0321_0000_0000_2000; CROM[ 344] = 108'o3251_4002_0000_4174_0007_0700_0000_0000_0000; CROM[ 345] = 108'o0532_3333_0004_4175_5007_0701_0200_0000_0002; CROM[ 346] = 108'o0435_3443_0200_4174_4007_0700_0200_0003_0312; CROM[ 347] = 108'o3444_1111_0703_4174_4007_0700_4000_0000_0000; CROM[ 348] = 108'o0534_3446_0505_4174_4057_0630_2000_0060_0000; CROM[ 349] = 108'o1033_3444_0505_4174_4007_0700_0000_0000_0000; CROM[ 350] = 108'o3250_4221_0013_4174_4007_0700_0000_0000_0000; CROM[ 351] = 108'o1074_0551_0703_7274_4007_0701_0000_0000_0242; CROM[ 352] = 108'o2274_3333_0004_7174_4007_0520_0410_0000_0242; CROM[ 353] = 108'o0750_3441_0304_4174_4007_0520_0000_0000_0000; CROM[ 354] = 108'o3450_3771_0013_4370_4007_0700_0010_0000_0005; CROM[ 355] = 108'o0563_3442_0300_4174_4007_0700_2010_0071_0043; CROM[ 356] = 108'o0544_3444_0505_4174_4057_0630_2000_0060_0000; CROM[ 357] = 108'o1033_3444_0505_4174_4007_0700_0000_0000_0000; CROM[ 358] = 108'o3306_0551_0704_7274_4007_0701_0000_0000_0242; CROM[ 359] = 108'o2766_3445_0404_4174_4467_0700_0000_0005_0000; CROM[ 360] = 108'o3104_4443_0000_4174_4007_0700_1000_0031_0000; CROM[ 361] = 108'o1264_3446_0316_4174_4007_0520_2010_0071_0042; CROM[ 362] = 108'o3103_3770_0505_4344_4007_0700_0000_0000_0000; CROM[ 363] = 108'o3024_3224_0016_4174_4007_0700_0000_0000_0000; CROM[ 364] = 108'o1046_3772_0000_1275_5007_0701_0000_0000_1441; CROM[ 365] = 108'o0100_4443_0000_4174_4156_4700_0000_0000_0000; CROM[ 366] = 108'o3400_3333_0005_7174_4001_2700_0400_0000_0241; CROM[ 367] = 108'o2056_3333_0005_4174_4007_0530_0000_0000_0000; CROM[ 368] = 108'o0620_3771_0005_1276_6007_0701_0010_0000_1443; CROM[ 369] = 108'o2140_0551_0404_1274_4007_0562_0010_0000_1444; CROM[ 370] = 108'o2214_0111_0705_4174_4007_0700_0010_0000_0000; CROM[ 371] = 108'o3002_3446_1200_4174_4007_0700_0010_0000_0000; CROM[ 372] = 108'o1500_3111_0503_4174_4003_7700_0200_0003_0001; CROM[ 373] = 108'o0600_0551_0505_1274_4007_0701_0000_0000_1443; CROM[ 374] = 108'o3364_3333_0003_7174_4007_0700_0400_0000_0247; CROM[ 375] = 108'o0004_0113_0404_4174_4464_1701_0000_0001_0001; CROM[ 376] = 108'o0571_3771_0003_4374_4007_0700_0000_0000_0000; CROM[ 377] = 108'o0370_3333_0005_7174_4007_0700_0410_0000_0226; CROM[ 378] = 108'o1515_3445_0303_4174_4007_0700_1020_0041_0001; CROM[ 379] = 108'o3143_3772_0000_4374_0007_0700_0000_0000_0000; CROM[ 380] = 108'o0500_3771_0013_4370_4007_0700_0000_0000_0003; CROM[ 381] = 108'o3265_3771_0005_1276_6007_0701_0000_0000_1444; CROM[ 382] = 108'o3305_3441_0304_4174_4007_0700_0000_0000_0000; CROM[ 383] = 108'o0630_3771_0004_1276_6007_0522_0000_0000_1443; CROM[ 384] = 108'o0621_4443_0000_4174_4007_0700_0010_0000_0000; CROM[ 385] = 108'o2140_0111_0304_4174_4007_0561_0010_0000_0000; CROM[ 386] = 108'o0602_3445_0303_4174_4007_0630_2000_0060_0000; CROM[ 387] = 108'o3772_4443_0000_4174_4007_0700_0010_0000_0000; CROM[ 388] = 108'o0340_3333_0003_4174_4006_5701_1010_0051_0770; CROM[ 389] = 108'o3333_3440_0404_1174_4007_0700_0400_0000_1444; CROM[ 390] = 108'o0555_3440_0303_0174_4467_0700_0400_0005_0000; CROM[ 391] = 108'o1000_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 392] = 108'o3256_4111_0004_4174_4007_0700_0010_0000_0000; CROM[ 393] = 108'o1515_3447_0303_4174_4007_0700_1020_0041_0001; CROM[ 394] = 108'o3253_6111_0004_4174_4007_0700_0000_0000_0000; CROM[ 395] = 108'o2050_2441_0404_4174_4007_0561_4000_0000_0000; CROM[ 396] = 108'o0634_3447_0505_4174_4007_0700_2000_0041_1776; CROM[ 397] = 108'o0624_3447_0505_4174_4007_0700_2000_0031_1776; CROM[ 398] = 108'o3330_3771_0013_4370_4007_0700_0000_0000_0007; CROM[ 399] = 108'o0616_3551_0606_4374_0007_0700_0000_0040_0000; CROM[ 400] = 108'o0621_4443_0000_4174_4007_0700_0010_0000_0000; CROM[ 401] = 108'o0622_0111_0505_4174_4007_0700_0000_0000_0000; CROM[ 402] = 108'o2140_0111_0404_4174_4007_0561_0010_0000_0000; CROM[ 403] = 108'o3001_3447_0606_4174_4007_0700_2010_0071_0043; CROM[ 404] = 108'o0624_3446_0505_4174_4047_0630_2000_0060_0000; CROM[ 405] = 108'o1053_3444_0505_4174_4047_0700_0000_0000_0000; CROM[ 406] = 108'o0001_4443_0000_4174_4004_1700_0000_0000_0000; CROM[ 407] = 108'o0730_3442_0300_4174_4007_0700_2000_0071_0043; CROM[ 408] = 108'o3274_3771_0003_1276_6007_0701_0000_0000_1441; CROM[ 409] = 108'o2263_3771_0013_4370_4007_0700_0010_0000_0006; CROM[ 410] = 108'o0454_3777_0003_0274_4007_0631_2000_0060_0000; CROM[ 411] = 108'o3306_0551_0704_7274_4007_0701_0000_0000_0242; CROM[ 412] = 108'o0634_3444_0505_4174_4447_0630_2000_0060_0000; CROM[ 413] = 108'o1053_3444_0505_4174_4447_0700_0000_0000_0000; CROM[ 414] = 108'o2206_3333_0003_4174_4007_0700_0200_0004_0012; CROM[ 415] = 108'o0510_3333_0004_7174_4007_0700_0400_0000_0250; CROM[ 416] = 108'o2157_3440_0606_1174_4007_0700_0400_0000_1443; CROM[ 417] = 108'o3450_3333_0005_7174_4007_0700_0410_0000_0242; CROM[ 418] = 108'o1064_4662_0000_4374_0007_0700_0000_0037_7777; CROM[ 419] = 108'o1064_3662_0000_4374_0007_0700_0000_0040_0000; CROM[ 420] = 108'o0644_3446_0505_4174_4077_0630_2000_0060_0000; CROM[ 421] = 108'o1033_3444_0505_4174_4007_0700_0000_0000_0000; CROM[ 422] = 108'o0701_3447_0303_4174_4007_0700_0000_0000_0000; CROM[ 423] = 108'o3362_2551_0705_1274_4007_0701_4000_0000_1443; CROM[ 424] = 108'o3274_3441_0503_4174_4007_0700_0000_0000_0000; CROM[ 425] = 108'o3275_7771_0003_7274_4007_0701_0000_0000_0242; CROM[ 426] = 108'o3276_3770_0503_4334_4017_0700_0000_0032_6000; CROM[ 427] = 108'o3275_7771_0003_7274_4007_0701_0000_0000_0242; CROM[ 428] = 108'o2226_3770_0303_4344_4007_0700_2000_0071_0007; CROM[ 429] = 108'o2227_3770_0303_4344_4007_0700_0000_0000_0000; CROM[ 430] = 108'o2226_3447_0303_4174_4007_0700_2000_0071_0006; CROM[ 431] = 108'o3403_4551_0303_4374_4007_0700_0000_0000_0777; CROM[ 432] = 108'o0370_3771_0003_4374_4007_0700_0010_0000_0000; CROM[ 433] = 108'o2232_1553_0300_4374_4007_0532_4000_0000_0005; CROM[ 434] = 108'o3135_3223_0000_7174_4007_0700_0400_0000_0224; CROM[ 435] = 108'o2250_3333_0006_4174_4007_0520_0000_0000_0000; CROM[ 436] = 108'o0370_3771_0003_4374_4007_0700_0010_0000_0000; CROM[ 437] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 438] = 108'o3141_3333_0003_7174_4007_0700_0400_0000_0225; CROM[ 439] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 440] = 108'o1334_3333_0005_4174_4007_0520_0000_0000_0000; CROM[ 441] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 442] = 108'o3172_3441_0304_4174_4007_0700_0000_0000_0000; CROM[ 443] = 108'o2254_4553_0600_4374_4007_0321_0000_0010_0000; CROM[ 444] = 108'o0555_4443_0000_4174_4467_0700_0000_0041_1000; CROM[ 445] = 108'o2254_4553_0600_4374_4007_0321_0000_0020_0000; CROM[ 446] = 108'o0720_4443_0000_4174_4006_7701_2000_0041_1544; CROM[ 447] = 108'o2254_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 448] = 108'o3443_0551_0303_7274_4007_0700_0010_0000_0241; CROM[ 449] = 108'o0706_3447_0303_4174_4037_0700_1020_0041_0001; CROM[ 450] = 108'o2244_3333_0003_4174_4007_0621_0000_0000_0000; CROM[ 451] = 108'o0246_3771_0013_4370_4007_0700_0000_0000_0011; CROM[ 452] = 108'o3404_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 453] = 108'o3450_3771_0013_4370_4007_0700_0010_0000_0013; CROM[ 454] = 108'o0455_3445_0303_4174_4007_0700_0000_0000_0000; CROM[ 455] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 456] = 108'o3404_0111_0701_4174_4007_0700_0000_0000_0000; CROM[ 457] = 108'o2240_3771_0013_4370_4007_0700_0000_0000_0011; CROM[ 458] = 108'o0006_3333_0006_4174_4007_0520_0000_0000_0000; CROM[ 459] = 108'o3423_4551_0606_4374_0007_0700_0000_0007_7777; CROM[ 460] = 108'o0715_3771_0005_1276_6007_0701_0000_0000_1443; CROM[ 461] = 108'o2236_3443_0500_4174_4007_0700_0200_0004_0012; CROM[ 462] = 108'o3442_3447_0303_4174_4007_0700_0000_0000_0000; CROM[ 463] = 108'o3440_3770_0303_7174_0007_0700_0000_0000_0241; CROM[ 464] = 108'o1370_4443_0000_4174_4007_0630_2000_0060_0000; CROM[ 465] = 108'o2270_3333_0006_4174_4007_0520_0000_0000_0000; CROM[ 466] = 108'o3210_4443_0000_4174_4007_0700_2000_0031_0232; CROM[ 467] = 108'o0004_4443_0000_4174_4004_1700_0000_0000_0000; CROM[ 468] = 108'o1264_4222_0000_4174_4007_0700_2010_0071_0032; CROM[ 469] = 108'o0721_5551_0606_4374_0007_0700_0000_0010_0000; CROM[ 470] = 108'o1054_3221_0016_4174_4007_0700_2000_0071_0043; CROM[ 471] = 108'o0721_3551_0606_4374_0007_0700_0000_0010_0000; CROM[ 472] = 108'o3002_4443_0000_4174_4007_0700_0010_0000_0000; CROM[ 473] = 108'o0721_3551_0606_4374_0007_0700_0000_0020_0000; CROM[ 474] = 108'o3002_3442_0500_4174_4007_0700_2010_0071_0043; CROM[ 475] = 108'o0004_3551_0606_4374_0004_1700_0000_0020_0000; CROM[ 476] = 108'o3233_3441_0416_4174_4007_0700_0000_0000_0000; CROM[ 477] = 108'o0731_5551_0606_4374_0007_0700_0000_0010_0000; CROM[ 478] = 108'o3235_3221_0017_4174_4007_0700_0000_0000_0000; CROM[ 479] = 108'o0721_3551_0606_4374_0007_0700_0000_0030_0000; CROM[ 480] = 108'o3450_3551_1313_4370_4007_0700_0010_0000_0012; CROM[ 481] = 108'o3416_3551_0606_4374_0007_0700_0000_0040_0000; CROM[ 482] = 108'o0742_3444_0505_4174_4077_0630_2000_0060_0000; CROM[ 483] = 108'o1033_3444_0505_4174_4007_0700_0000_0000_0000; CROM[ 484] = 108'o0250_3440_0303_0174_4003_7700_0400_0000_0000; CROM[ 485] = 108'o0250_4443_0000_4174_4003_7700_0000_0000_0000; CROM[ 486] = 108'o3416_3551_0606_4374_0007_0700_0000_0040_0000; CROM[ 487] = 108'o0752_3447_0303_4174_4007_0700_0000_0000_0000; CROM[ 488] = 108'o3307_4223_0000_1174_4007_0700_0400_0000_1443; CROM[ 489] = 108'o2263_3771_0013_4370_4007_0700_0010_0000_0004; CROM[ 490] = 108'o0706_3445_0303_4174_4037_0700_1020_0041_0001; CROM[ 491] = 108'o2147_3440_0606_0174_4007_0700_0400_0000_0000; CROM[ 492] = 108'o0533_3771_0003_1276_6003_7701_0000_0000_1443; CROM[ 493] = 108'o2271_3551_0606_4374_0007_0700_0000_0040_0000; CROM[ 494] = 108'o0002_3771_0003_7274_4004_1701_0000_0000_0244; CROM[ 495] = 108'o0003_3771_0003_1276_6004_1701_0000_0000_1444; CROM[ 496] = 108'o3450_3771_0013_4370_4007_0700_0010_0000_0012; CROM[ 497] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 498] = 108'o0110_3443_0100_4174_4156_4700_0200_0014_0012; CROM[ 499] = 108'o0110_3441_0301_4170_4156_4700_0200_0014_0012; CROM[ 500] = 108'o0110_3441_0301_4170_4156_4700_0200_0014_0012; CROM[ 501] = 108'o0110_3443_0100_4174_4156_4700_0200_0014_0012; CROM[ 502] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 503] = 108'o0514_4443_0000_4174_4007_0700_1000_0071_1764; CROM[ 504] = 108'o0770_3773_0000_4074_4003_1701_0000_0000_0000; CROM[ 505] = 108'o3622_3551_1414_4370_4007_0700_0000_0004_0000; CROM[ 506] = 108'o3623_3551_1414_4370_4007_0700_0000_0002_0000; CROM[ 507] = 108'o3624_3551_1414_4370_4007_0700_0000_0001_0000; CROM[ 508] = 108'o3625_3551_1414_4370_4007_0700_0000_0000_4000; CROM[ 509] = 108'o3626_3551_1414_4370_4007_0700_0000_0000_2000; CROM[ 510] = 108'o3627_3551_1414_4370_4007_0700_0000_0000_1000; CROM[ 511] = 108'o3630_3551_1414_4370_4007_0700_0000_0000_0400; CROM[ 512] = 108'o3767_4443_0000_4174_4007_0700_2010_0071_0007; CROM[ 513] = 108'o2552_4553_0300_4374_4007_0321_0000_0000_0077; CROM[ 514] = 108'o2550_0551_0303_7274_4007_0701_0000_0000_0215; CROM[ 515] = 108'o3772_0551_0303_7274_4007_0701_0010_0000_0215; CROM[ 516] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 517] = 108'o2601_3441_0301_4174_4007_0700_0000_0000_0000; CROM[ 518] = 108'o1023_4251_0303_4374_4007_0700_0000_0000_0077; CROM[ 519] = 108'o2546_4553_0300_4374_4007_0321_0000_0000_0077; CROM[ 520] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 521] = 108'o0303_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 522] = 108'o3002_3442_0300_4174_4007_0700_2010_0071_0043; CROM[ 523] = 108'o3647_3551_0505_0274_4007_0700_0000_0000_0000; CROM[ 524] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 525] = 108'o0060_4521_1205_4074_4007_0700_0000_0000_0000; CROM[ 526] = 108'o0243_3446_0403_4174_4007_0700_1000_0041_1576; CROM[ 527] = 108'o3647_5551_0505_0274_4007_0700_0000_0000_0000; CROM[ 528] = 108'o2275_3771_0013_4370_4007_0700_0010_0000_0011; CROM[ 529] = 108'o2120_3333_0004_4174_4007_0520_0000_0000_0000; CROM[ 530] = 108'o3312_3333_0003_7174_4007_0700_0400_0000_0245; CROM[ 531] = 108'o0100_3440_0303_1174_4156_4700_0400_0000_1441; CROM[ 532] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 533] = 108'o2715_3443_0300_4174_4007_0700_0200_0003_0012; CROM[ 534] = 108'o0534_4443_0000_4174_4007_0630_2000_0060_0000; CROM[ 535] = 108'o2442_4553_0300_4374_4007_0331_0000_0000_0001; CROM[ 536] = 108'o2122_4443_0000_4174_4007_0700_0010_0000_0000; CROM[ 537] = 108'o3315_3771_0003_7274_4007_0701_0000_0000_0244; CROM[ 538] = 108'o3315_3440_0404_1174_4007_0700_0400_0000_1443; CROM[ 539] = 108'o1036_3444_0505_4174_4007_0700_0000_0000_0000; CROM[ 540] = 108'o2716_3441_0302_4174_4617_0700_0000_0000_0100; CROM[ 541] = 108'o1034_3333_0002_4174_4167_0700_0000_0000_0000; CROM[ 542] = 108'o1064_3440_0505_0174_4007_0700_0400_0000_0000; CROM[ 543] = 108'o0003_3441_0503_4174_4004_1700_0000_0000_0000; CROM[ 544] = 108'o2642_3771_0003_7274_4007_0622_0010_0000_0423; CROM[ 545] = 108'o2642_3771_0003_7274_4007_0622_0010_0000_0424; CROM[ 546] = 108'o1047_3333_0004_7174_4007_0700_0400_0000_0423; CROM[ 547] = 108'o1047_3333_0004_7174_4007_0700_0400_0000_0424; CROM[ 548] = 108'o0220_3333_0005_4175_5003_7701_0200_0000_0002; CROM[ 549] = 108'o2720_3333_0005_4175_5007_0701_0200_0000_0002; CROM[ 550] = 108'o0614_3776_0005_0274_4007_0631_0000_0000_0000; CROM[ 551] = 108'o1130_0113_0405_4174_4007_0700_0200_0024_1016; CROM[ 552] = 108'o0560_3771_0004_1276_6007_0701_0010_0000_1444; CROM[ 553] = 108'o3331_3771_0005_1276_6007_0701_0000_0000_1444; CROM[ 554] = 108'o0460_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 555] = 108'o0642_0113_0505_0174_4007_0521_0400_0000_0000; CROM[ 556] = 108'o1264_5002_0000_4174_4007_0621_0010_0000_0000; CROM[ 557] = 108'o2466_3771_0004_2274_4007_0120_0000_0000_0000; CROM[ 558] = 108'o3247_3446_1200_4174_4007_0700_0000_0000_0000; CROM[ 559] = 108'o0001_3771_0003_7274_4124_1701_0000_0000_0422; CROM[ 560] = 108'o1060_3773_0000_4304_4003_1702_0000_0000_0000; CROM[ 561] = 108'o1503_3333_0005_7174_4007_0700_0400_0000_0213; CROM[ 562] = 108'o3556_4553_0500_4374_4007_0321_0010_0076_0740; CROM[ 563] = 108'o3724_3771_0006_4374_4007_0700_0000_0000_0000; CROM[ 564] = 108'o0100_3223_0000_1174_4156_4700_0400_0000_1441; CROM[ 565] = 108'o1501_4571_1206_4374_4007_0700_0000_0037_0000; CROM[ 566] = 108'o3257_4521_0206_4374_4007_0700_0000_0000_0740; CROM[ 567] = 108'o1501_4571_1206_4374_4007_0700_0000_0037_0000; CROM[ 568] = 108'o3727_3333_0005_7174_4007_0700_0400_0000_0213; CROM[ 569] = 108'o1503_3333_0005_7174_4007_0700_0400_0000_0213; CROM[ 570] = 108'o3727_3333_0005_7174_4007_0700_0400_0000_0213; CROM[ 571] = 108'o3727_3333_0005_7174_4007_0700_0400_0000_0213; CROM[ 572] = 108'o2274_3333_0003_7174_4007_0520_0410_0000_0242; CROM[ 573] = 108'o0001_4221_0013_4170_4004_1700_0000_0000_0000; CROM[ 574] = 108'o0716_4443_0000_7174_4003_7700_0000_0000_0241; CROM[ 575] = 108'o0644_4443_0000_4174_4007_0630_2000_0060_0000; CROM[ 576] = 108'o2702_4221_0013_4170_4007_0370_0000_0000_0000; CROM[ 577] = 108'o3167_3771_0003_7274_4007_0701_0000_0000_0212; CROM[ 578] = 108'o1562_0111_0701_4174_4007_0700_0000_0000_0000; CROM[ 579] = 108'o3463_3771_0013_4370_4007_0700_0000_0000_0011; CROM[ 580] = 108'o3463_3771_0013_4370_4007_0700_0000_0000_0012; CROM[ 581] = 108'o2310_3771_0013_4370_4007_0700_0000_0000_0003; CROM[ 582] = 108'o3472_3771_0013_4370_4007_0700_0000_0000_0012; CROM[ 583] = 108'o3467_3771_0013_4370_4007_0700_0000_0000_0011; CROM[ 584] = 108'o3461_3771_0013_4370_4007_0700_0000_0000_0011; CROM[ 585] = 108'o2302_4221_0013_4170_4007_0700_0000_0000_0000; CROM[ 586] = 108'o2310_4221_0013_4170_4007_0700_0000_0000_0000; CROM[ 587] = 108'o2310_3771_0013_4370_4007_0700_0000_0000_0011; CROM[ 588] = 108'o3661_0111_0702_4170_4007_0700_0210_0004_0012; CROM[ 589] = 108'o3572_4551_0404_4370_4007_0700_0010_0077_0000; CROM[ 590] = 108'o1123_4551_0303_0274_4007_0700_0000_0000_0000; CROM[ 591] = 108'o1400_3333_0004_7174_4007_0700_0400_0000_0301; CROM[ 592] = 108'o3561_3771_0003_7274_4117_0700_0010_0000_0301; CROM[ 593] = 108'o3577_3333_0002_4174_4007_0700_0200_0003_0012; CROM[ 594] = 108'o1764_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 595] = 108'o0014_3440_0303_0174_4007_0700_0400_0000_0000; CROM[ 596] = 108'o3657_3333_0016_7174_4127_0700_0400_0000_0210; CROM[ 597] = 108'o1124_4443_0000_4174_4006_7653_2000_0060_0000; CROM[ 598] = 108'o3657_3333_0016_7174_4127_0700_0400_0000_0210; CROM[ 599] = 108'o2473_3333_0016_7174_4007_0700_0400_0000_0210; CROM[ 600] = 108'o3767_3771_0003_4365_5007_0700_0210_0000_0002; CROM[ 601] = 108'o1134_4553_0300_4374_4007_0321_0000_0000_0077; CROM[ 602] = 108'o2561_0551_0303_7274_4007_0701_0000_0000_0215; CROM[ 603] = 108'o2566_3770_0305_4344_4007_0670_0000_0000_0000; CROM[ 604] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[ 605] = 108'o2622_4251_0304_4374_4007_0700_0010_0000_3777; CROM[ 606] = 108'o1143_4443_0000_4174_4007_0700_0200_0003_0002; CROM[ 607] = 108'o3737_3551_0606_4374_0007_0700_0000_0010_0000; CROM[ 608] = 108'o3561_3771_0003_7274_4117_0701_0010_0000_0301; CROM[ 609] = 108'o2673_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 610] = 108'o1507_4223_0000_4364_4277_0700_0200_0000_0010; CROM[ 611] = 108'o1477_3333_0003_4175_5007_0701_0200_0000_0002; CROM[ 612] = 108'o2724_3443_0300_4174_4007_0700_0200_0003_0312; CROM[ 613] = 108'o2723_3443_0300_4174_4007_0700_0200_0003_0312; CROM[ 614] = 108'o1147_4443_0000_4174_4467_0700_0000_0001_2000; CROM[ 615] = 108'o0221_3771_0001_4361_5007_0700_0200_0000_0002; CROM[ 616] = 108'o1152_0113_0503_0174_4407_0521_0400_0000_0000; CROM[ 617] = 108'o1154_0113_0503_0174_4407_0521_0400_0000_0000; CROM[ 618] = 108'o0100_4443_0000_4174_4156_4700_0000_0000_0000; CROM[ 619] = 108'o0555_4443_0000_4174_4467_0700_0000_0001_2000; CROM[ 620] = 108'o0555_4443_0000_4174_4467_0700_0000_0001_2000; CROM[ 621] = 108'o0100_4443_0000_4174_4156_4700_0000_0000_0000; CROM[ 622] = 108'o1510_0111_1104_4174_4007_0700_0010_0000_0000; CROM[ 623] = 108'o1160_3333_0010_4174_4007_0520_0000_0000_0000; CROM[ 624] = 108'o0310_3333_0004_4174_4007_0700_0200_0021_1016; CROM[ 625] = 108'o1162_3770_0203_4344_4007_0700_0000_0000_0000; CROM[ 626] = 108'o2745_4521_1203_4074_0007_0700_0010_0000_0000; CROM[ 627] = 108'o0314_3333_0004_4174_4007_0700_0200_0021_1016; CROM[ 628] = 108'o1165_3551_0505_4370_4007_0700_0000_0000_0001; CROM[ 629] = 108'o1166_4553_0300_4374_4007_0321_0000_0001_0000; CROM[ 630] = 108'o1167_3551_0505_4370_4007_0700_0000_0000_0004; CROM[ 631] = 108'o2743_3333_0005_4174_4007_0700_0200_0024_1016; CROM[ 632] = 108'o2753_0551_0303_0274_4467_0702_4000_0001_0001; CROM[ 633] = 108'o2752_7441_1205_4174_4007_0700_0000_0000_0000; CROM[ 634] = 108'o2753_2551_0303_0274_4467_0702_0000_0001_0001; CROM[ 635] = 108'o2753_2551_0303_0274_4467_0702_4000_0001_0001; CROM[ 636] = 108'o1404_4551_0404_4374_0007_0700_0000_0037_7777; CROM[ 637] = 108'o1404_3551_0404_4374_0007_0700_0000_0040_0000; CROM[ 638] = 108'o2755_3445_0404_4174_4007_0700_0000_0000_0000; CROM[ 639] = 108'o1500_3221_0003_4174_4003_7700_0200_0003_0001; CROM[ 640] = 108'o1202_3770_0404_4174_0007_0520_0000_0000_0000; CROM[ 641] = 108'o1500_7001_0003_4174_4003_7700_0200_0003_0001; CROM[ 642] = 108'o1404_3221_0003_4174_4467_0700_0000_0041_1000; CROM[ 643] = 108'o1404_7001_0003_4174_4467_0700_0000_0041_1000; CROM[ 644] = 108'o1500_4001_0004_4174_4003_7700_0200_0003_0001; CROM[ 645] = 108'o1206_4113_0616_4174_4007_0520_0000_0000_0000; CROM[ 646] = 108'o1500_7001_0004_4174_4003_7700_0200_0003_0001; CROM[ 647] = 108'o1404_7001_0004_4174_4467_0700_0000_0041_1000; CROM[ 648] = 108'o2773_3223_0000_1174_4007_0700_0400_0000_1441; CROM[ 649] = 108'o2767_7003_0000_1174_4007_0700_0400_0000_1441; CROM[ 650] = 108'o0110_3443_0100_4174_4156_4700_0200_0014_0012; CROM[ 651] = 108'o1400_4443_0000_4174_4467_0700_0000_0041_1000; CROM[ 652] = 108'o0161_4221_0003_4174_4007_0700_0000_0000_0000; CROM[ 653] = 108'o0161_2441_0703_4174_4007_0700_4000_0000_0000; CROM[ 654] = 108'o3007_3441_0306_4174_4007_0700_0000_0000_0000; CROM[ 655] = 108'o0164_3333_0005_4174_4007_0621_0000_0000_0000; CROM[ 656] = 108'o1222_2113_0305_4174_4007_0521_4000_0000_0000; CROM[ 657] = 108'o1222_0113_0305_4174_4007_0521_0000_0000_0000; CROM[ 658] = 108'o0555_4443_0000_4174_4467_0700_0000_0051_1000; CROM[ 659] = 108'o0161_3441_0603_4174_4007_0700_0000_0000_0000; CROM[ 660] = 108'o1230_3446_0505_4174_4007_0700_0000_0000_0000; CROM[ 661] = 108'o1226_3446_0505_4174_4007_0520_0000_0000_0000; CROM[ 662] = 108'o1230_4003_0000_4174_4007_0621_0000_0000_0000; CROM[ 663] = 108'o3012_4751_1217_4374_4007_0700_0000_0000_0005; CROM[ 664] = 108'o3015_3446_0505_4174_4047_0700_0000_0000_0000; CROM[ 665] = 108'o0555_4443_0000_4174_4467_0700_0000_0051_1000; CROM[ 666] = 108'o3042_3446_0303_4174_4007_0700_0010_0000_0000; CROM[ 667] = 108'o1234_2113_0305_4174_4007_0521_4000_0000_0000; CROM[ 668] = 108'o1236_2113_0305_4174_4007_0620_4000_0000_0000; CROM[ 669] = 108'o3020_3221_0004_4174_4007_0700_0000_0000_0000; CROM[ 670] = 108'o0033_3333_0017_4174_4003_5701_0000_0000_0000; CROM[ 671] = 108'o1240_1003_0600_4174_4007_0521_4000_0000_0000; CROM[ 672] = 108'o0033_3333_0017_4174_4003_5701_0000_0000_0000; CROM[ 673] = 108'o3020_3221_0004_4174_4007_0700_0000_0000_0000; CROM[ 674] = 108'o3042_3442_0400_4174_4007_0700_0010_0000_0000; CROM[ 675] = 108'o3023_3221_0004_4174_4007_0700_0000_0000_0000; CROM[ 676] = 108'o3030_3440_1616_1174_4007_0700_0400_0000_1441; CROM[ 677] = 108'o3032_4223_0000_1174_4007_0700_0400_0000_1441; CROM[ 678] = 108'o3036_3442_0400_4174_4007_0700_0000_0000_0000; CROM[ 679] = 108'o3033_0112_0406_4174_4007_0700_0000_0000_0000; CROM[ 680] = 108'o0100_4003_0000_1174_4156_4700_0400_0000_1443; CROM[ 681] = 108'o3041_4002_0000_1174_4007_0700_0000_0000_1443; CROM[ 682] = 108'o3045_4221_0004_4174_4007_0700_0000_0000_0000; CROM[ 683] = 108'o1254_2222_0000_4174_4007_0621_4000_0000_0000; CROM[ 684] = 108'o3044_7441_0303_4174_4007_0700_0000_0000_0000; CROM[ 685] = 108'o3044_2441_0303_4174_4007_0700_4000_0000_0000; CROM[ 686] = 108'o3047_3446_0303_4174_4007_0700_0000_0000_0000; CROM[ 687] = 108'o3046_2441_0505_4174_4007_0700_4000_0000_0000; CROM[ 688] = 108'o1260_0114_0503_4174_4067_0630_2100_0060_0000; CROM[ 689] = 108'o3053_3444_1717_4174_4067_0700_0100_0000_0000; CROM[ 690] = 108'o3054_3444_0303_4174_4007_0700_0000_0000_0000; CROM[ 691] = 108'o1262_0111_0503_4174_4007_0700_0000_0000_0000; CROM[ 692] = 108'o3057_1114_0604_4174_4057_0700_4000_0000_0000; CROM[ 693] = 108'o3057_0114_0604_4174_4057_0700_0000_0000_0000; CROM[ 694] = 108'o3057_0114_0604_4174_4067_0700_0100_0000_0000; CROM[ 695] = 108'o0002_4444_0002_4174_4064_1700_0100_0000_0000; CROM[ 696] = 108'o3064_7772_0000_1274_4007_0701_0000_0000_1442; CROM[ 697] = 108'o3062_1772_0000_1274_4007_0701_4000_0000_1442; CROM[ 698] = 108'o3065_7772_0000_1274_4007_0701_0000_0000_1441; CROM[ 699] = 108'o3063_1772_0000_1274_4007_0701_4000_0000_1441; CROM[ 700] = 108'o3066_7771_0003_0274_4007_0700_0000_0000_0000; CROM[ 701] = 108'o3066_1771_0003_0274_4007_0701_4000_0000_0000; CROM[ 702] = 108'o2220_7441_0303_4174_4467_0700_0000_0001_0001; CROM[ 703] = 108'o2220_2441_0303_4174_4467_0701_4000_0001_0001; CROM[ 704] = 108'o2220_7441_0303_4174_4007_0700_0000_0000_0000; CROM[ 705] = 108'o2220_2441_0303_4174_4007_0700_4000_0000_0000; CROM[ 706] = 108'o1302_3447_0404_4174_4007_0630_2000_0060_0000; CROM[ 707] = 108'o3130_4557_0404_4374_4007_0701_0000_0000_0176; CROM[ 708] = 108'o1304_3447_0505_4174_4007_0630_2000_0060_0000; CROM[ 709] = 108'o1306_3333_0005_7174_4007_0621_0400_0000_0222; CROM[ 710] = 108'o0660_3442_0400_4174_4007_0700_2000_0071_0042; CROM[ 711] = 108'o1404_3771_0003_7274_4007_0701_0000_0000_0223; CROM[ 712] = 108'o0570_0662_0000_0274_4007_0522_2000_0071_0042; CROM[ 713] = 108'o0555_4443_0000_4174_4467_0700_0000_0051_1000; CROM[ 714] = 108'o3145_0661_0005_7274_4407_0701_0000_0000_0223; CROM[ 715] = 108'o3144_1002_0700_4170_4007_0700_4000_0000_0000; CROM[ 716] = 108'o1314_3445_0303_4174_4007_0630_2000_0060_0000; CROM[ 717] = 108'o3152_4551_0505_4374_0007_0700_0000_0000_7777; CROM[ 718] = 108'o3663_3443_0400_4174_4007_0700_0210_0004_0712; CROM[ 719] = 108'o3154_4221_0006_4174_0007_0700_0000_0000_0000; CROM[ 720] = 108'o3164_3443_0600_4174_4007_0700_0200_0003_0312; CROM[ 721] = 108'o3162_3443_0600_4174_4007_0700_0200_0003_0312; CROM[ 722] = 108'o3165_4443_0000_4174_4007_0700_0000_0000_0000; CROM[ 723] = 108'o1324_2113_0603_4174_4007_0521_4000_0000_0000; CROM[ 724] = 108'o1400_4221_0013_4170_4007_0700_0000_0000_0000; CROM[ 725] = 108'o1326_0111_0704_4174_4007_0370_0000_0000_0000; CROM[ 726] = 108'o3162_0111_0706_4170_4007_0700_0200_0003_0312; CROM[ 727] = 108'o3164_0111_0706_4170_4007_0700_0200_0003_0312; CROM[ 728] = 108'o1400_4221_0013_4170_4007_0700_0000_0000_0000; CROM[ 729] = 108'o3166_0111_0706_4174_4007_0700_0000_0000_0000; CROM[ 730] = 108'o3175_4551_0303_4374_0007_0700_0000_0000_0777; CROM[ 731] = 108'o3175_3551_0303_4374_0007_0700_0000_0077_7000; CROM[ 732] = 108'o3175_4551_0505_4374_0007_0700_0000_0000_0777; CROM[ 733] = 108'o3175_3551_0505_4374_0007_0700_0000_0077_7000; CROM[ 734] = 108'o1336_3446_0505_4174_4047_0630_2000_0060_0000; CROM[ 735] = 108'o0420_0111_0503_4174_4003_4701_0000_0000_0000; CROM[ 736] = 108'o3176_4551_0606_4374_0007_0700_0000_0000_0777; CROM[ 737] = 108'o3176_3551_0606_4374_0007_0700_0000_0077_7000; CROM[ 738] = 108'o1344_3771_0003_0276_6007_0520_1000_0030_2000; CROM[ 739] = 108'o0555_4443_0000_4174_4467_0700_0000_0071_1000; CROM[ 740] = 108'o3201_4551_0303_4374_0007_0700_0000_0000_0777; CROM[ 741] = 108'o3202_3551_0303_4374_0007_0700_0000_0077_7000; CROM[ 742] = 108'o1350_2113_0406_4174_4007_0311_4000_0000_0000; CROM[ 743] = 108'o1346_2445_0506_4174_4007_0700_4000_0000_0000; CROM[ 744] = 108'o1352_3447_0606_4174_4007_0700_0000_0000_0000; CROM[ 745] = 108'o0555_4443_0000_4174_4467_0700_0000_0071_1000; CROM[ 746] = 108'o3665_3445_0303_4174_4007_0700_0010_0000_0000; CROM[ 747] = 108'o0144_2113_0604_4174_4007_0421_4000_0000_0000; CROM[ 748] = 108'o1356_2441_0305_4174_4007_0521_4000_0000_0000; CROM[ 749] = 108'o1363_4222_0000_4174_4007_0700_1000_0071_0233; CROM[ 750] = 108'o1360_4553_0500_4374_4007_0321_0000_0077_7000; CROM[ 751] = 108'o3205_4222_0000_4174_4007_0700_1000_0071_0244; CROM[ 752] = 108'o3205_4222_0000_4174_4007_0700_1000_0071_0244; CROM[ 753] = 108'o1363_4222_0000_4174_4007_0700_1000_0071_0233; CROM[ 754] = 108'o1362_3446_0303_4174_4047_0630_2000_0060_0000; CROM[ 755] = 108'o0420_3333_0003_4174_4003_4701_0000_0000_0000; CROM[ 756] = 108'o1363_4551_0303_4374_0007_0700_0000_0000_0777; CROM[ 757] = 108'o1363_3551_0303_4374_0007_0700_0000_0077_7000; CROM[ 758] = 108'o1366_3446_0303_4174_4047_0630_2000_0060_0000; CROM[ 759] = 108'o0063_3447_0705_4174_4003_7700_0000_0000_0000; CROM[ 760] = 108'o1370_3445_0303_4174_4007_0630_2000_0060_0000; CROM[ 761] = 108'o0100_3440_0303_0174_4156_4700_0400_0000_0000; CROM[ 762] = 108'o0100_3440_0303_0174_4156_4700_0400_0000_0000; CROM[ 763] = 108'o1374_3223_0000_4174_4007_0621_0000_0000_0000; CROM[ 764] = 108'o1514_0111_0703_4174_4003_7700_0200_0003_0001; CROM[ 765] = 108'o0073_7441_1205_4174_4007_0700_0000_0000_0000; CROM[ 766] = 108'o0420_3444_0303_4174_4063_4701_1000_0041_1777; CROM[ 767] = 108'o1514_4443_0000_4174_4003_7700_0200_0003_0001; CROM[ 768] = 108'o0110_3443_0100_4174_4156_4700_0200_0014_0012; CROM[ 769] = 108'o0110_0111_0701_4170_4156_4700_0200_0014_0012; CROM[ 770] = 108'o1500_3770_0303_4344_4003_7700_0200_0003_0001; CROM[ 771] = 108'o1404_3333_0003_4174_4007_0520_0000_0000_0000; CROM[ 772] = 108'o1500_4443_0000_4174_4003_7700_0200_0003_0001; CROM[ 773] = 108'o1404_2441_0303_4174_4467_0701_4000_0001_0001; CROM[ 774] = 108'o0506_3771_0005_0276_6007_0700_0200_0003_0002; CROM[ 775] = 108'o1500_3771_0003_0276_0003_7700_0200_0003_0001; CROM[ 776] = 108'o1500_3771_0003_0270_6003_7700_0200_0003_0001; CROM[ 777] = 108'o1410_3770_0303_4344_4007_0700_0000_0000_0000; CROM[ 778] = 108'o1407_3770_0303_4344_4007_0700_0000_0000_0000; CROM[ 779] = 108'o0511_3770_0303_4344_4007_0700_0000_0000_0000; CROM[ 780] = 108'o1500_3770_0303_4344_0003_7700_0200_0003_0001; CROM[ 781] = 108'o0512_3770_0303_4344_4007_0700_0000_0000_0000; CROM[ 782] = 108'o1500_3770_0303_4340_4003_7700_0200_0003_0001; CROM[ 783] = 108'o1420_3333_0003_4174_4007_0530_0000_0000_0000; CROM[ 784] = 108'o1500_5731_0003_4174_4003_7700_0200_0003_0001; CROM[ 785] = 108'o1500_5431_1203_4174_4003_7700_0200_0003_0001; CROM[ 786] = 108'o1424_3333_0003_4174_4007_0530_0000_0000_0000; CROM[ 787] = 108'o1426_3333_0003_4174_4007_0520_0000_0000_0000; CROM[ 788] = 108'o1402_3771_0003_4374_0007_0700_0000_0000_0000; CROM[ 789] = 108'o1402_3771_0003_4374_0007_0700_0000_0077_7777; CROM[ 790] = 108'o1402_3771_0003_4370_4007_0700_0000_0000_0000; CROM[ 791] = 108'o1402_3771_0003_4370_4007_0700_0000_0077_7777; CROM[ 792] = 108'o1432_3333_0003_4174_4007_0520_0000_0000_0000; CROM[ 793] = 108'o1136_0111_0703_4174_4467_0701_0000_0001_0001; CROM[ 794] = 108'o1500_5371_0003_4174_4003_7700_0200_0003_0001; CROM[ 795] = 108'o1500_5341_1203_4174_4003_7700_0200_0003_0001; CROM[ 796] = 108'o3070_4551_0404_4374_0007_0700_0010_0037_7777; CROM[ 797] = 108'o2660_4553_0400_4374_4007_0331_0000_0002_0000; CROM[ 798] = 108'o1515_3440_0404_1174_4007_0700_0400_0000_1441; CROM[ 799] = 108'o1136_1111_0703_4174_4467_0701_4000_0001_0001; CROM[ 800] = 108'o0270_3771_0005_0276_6003_7700_0000_0000_0000; CROM[ 801] = 108'o1500_4221_0003_4174_4003_7700_0200_0003_0001; CROM[ 802] = 108'o1500_4551_0303_0274_4003_7700_0200_0003_0001; CROM[ 803] = 108'o1500_5551_0303_0274_4003_7700_0200_0003_0001; CROM[ 804] = 108'o1442_7441_0303_4174_4007_0700_0000_0000_0000; CROM[ 805] = 108'o1500_6551_0303_0274_4003_7700_0200_0003_0001; CROM[ 806] = 108'o1500_3551_0303_0274_4003_7700_0200_0003_0001; CROM[ 807] = 108'o1443_7441_0303_4174_4007_0700_0000_0000_0000; CROM[ 808] = 108'o1500_7551_0303_0274_4003_7700_0200_0003_0001; CROM[ 809] = 108'o1500_7771_0003_0274_4003_7700_0200_0003_0001; CROM[ 810] = 108'o0564_7771_0005_0274_4007_0700_0000_0000_0000; CROM[ 811] = 108'o1500_7441_0303_4174_4003_7700_0200_0003_0001; CROM[ 812] = 108'o1446_7441_0303_4174_4007_0700_0000_0000_0000; CROM[ 813] = 108'o1453_4551_0303_0274_4007_0700_0000_0000_0000; CROM[ 814] = 108'o1500_2441_0703_4174_4003_7700_4200_0003_0001; CROM[ 815] = 108'o1170_0551_0404_1274_4007_0562_0000_0000_1441; CROM[ 816] = 108'o2436_4443_0000_4174_4007_0700_0010_0000_0000; CROM[ 817] = 108'o2446_3771_0005_0276_6007_0700_0000_0000_0000; CROM[ 818] = 108'o0502_4551_1205_0276_6007_0622_0000_0000_0000; CROM[ 819] = 108'o1400_3440_0303_0174_4007_0700_0400_0000_0000; CROM[ 820] = 108'o0544_4443_0000_4174_4007_0630_2000_0060_0000; CROM[ 821] = 108'o1026_3333_0003_4174_4007_0700_2000_0031_5777; CROM[ 822] = 108'o0554_3333_0003_4174_4007_0330_3000_0041_4000; CROM[ 823] = 108'o1062_3771_0005_4365_5007_0700_0200_0000_0002; CROM[ 824] = 108'o0742_4443_0000_4174_4007_0630_2000_0060_0000; CROM[ 825] = 108'o1077_3333_0003_4174_4007_0700_2000_0031_5777; CROM[ 826] = 108'o1473_3770_0303_4344_4007_0700_0000_0000_0000; CROM[ 827] = 108'o0014_4221_0005_4174_4003_7700_0000_0000_0000; CROM[ 828] = 108'o1475_3770_0303_4344_4007_0700_0000_0000_0000; CROM[ 829] = 108'o0014_4551_0305_0274_4003_7700_0000_0000_0000; CROM[ 830] = 108'o0250_2551_0303_0274_4003_7701_4000_0000_0000; CROM[ 831] = 108'o0744_3770_0303_4174_0007_0360_0000_0000_0000; CROM[ 832] = 108'o2607_3551_0606_4374_4007_0700_0000_0004_0000; CROM[ 833] = 108'o2670_3333_0005_7174_4007_0700_0400_0000_0213; CROM[ 834] = 108'o2656_3111_0506_4174_4007_0700_0000_0000_0000; CROM[ 835] = 108'o1140_4443_0000_4174_4007_0370_0000_0000_0000; CROM[ 836] = 108'o0434_4443_0000_4174_4007_0360_0000_0000_0000; CROM[ 837] = 108'o1515_3440_0404_1174_4007_0700_0400_0000_1441; CROM[ 838] = 108'o1505_3333_0003_4175_5007_0701_0200_0000_0002; CROM[ 839] = 108'o3762_3771_0003_7274_4007_0701_0000_0000_0210; CROM[ 840] = 108'o0001_4223_0000_4364_4274_1700_0200_0000_0010; CROM[ 841] = 108'o2700_3333_0003_4174_4467_0700_0000_0000_0004; CROM[ 842] = 108'o2704_3443_0300_4174_4007_0700_0200_0021_1016; CROM[ 843] = 108'o1563_3333_0005_4175_5007_0701_0200_0000_0002; CROM[ 844] = 108'o0104_4751_1217_4374_4007_0700_0000_0000_1000; CROM[ 845] = 108'o0100_3440_0303_0174_4156_4700_0400_0000_0000; CROM[ 846] = 108'o1400_3333_0003_4175_5007_0701_0200_0000_0002; CROM[ 847] = 108'o1515_3333_0003_4175_5007_0701_0200_0000_0002; CROM[ 848] = 108'o0110_3441_0301_4170_4156_4700_0200_0014_0012; CROM[ 849] = 108'o0110_3441_0301_4170_4156_4700_0200_0014_0012; CROM[ 850] = 108'o0150_1113_0701_4170_4007_0700_4200_0004_0012; CROM[ 851] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 852] = 108'o1004_4443_0000_4174_4007_0340_0000_0000_0000; CROM[ 853] = 108'o2606_3443_0300_4174_4007_0700_0200_0004_0012; CROM[ 854] = 108'o0320_4443_0000_4174_4007_0340_0000_0000_0000; CROM[ 855] = 108'o1014_4443_0000_4174_4007_0340_0000_0000_0000; CROM[ 856] = 108'o1010_1113_0701_4170_4007_0040_4200_0004_0012; CROM[ 857] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 858] = 108'o0300_1113_0701_4170_4007_0040_4200_0004_0012; CROM[ 859] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 860] = 108'o1024_4443_0000_4174_4007_0340_0000_0000_0000; CROM[ 861] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 862] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 863] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 864] = 108'o0762_4443_0000_4174_4467_0551_0000_0001_0010; CROM[ 865] = 108'o1034_4443_0000_4174_4007_0340_0000_0000_0000; CROM[ 866] = 108'o0270_2551_0705_0274_4463_7702_4000_0001_0001; CROM[ 867] = 108'o2717_3771_0005_4365_5007_0700_0200_0000_0002; CROM[ 868] = 108'o2717_3741_0105_4074_4467_0700_0000_0005_0000; CROM[ 869] = 108'o2721_3771_0004_0276_6007_0701_0200_0004_0712; CROM[ 870] = 108'o2725_3771_0004_0276_6007_0701_0200_0004_0712; CROM[ 871] = 108'o0270_0551_1505_0274_4403_7701_0000_0000_0000; CROM[ 872] = 108'o2727_3741_0105_4074_4007_0700_0000_0000_0000; CROM[ 873] = 108'o2726_3770_0303_4344_0007_0700_0000_0000_0000; CROM[ 874] = 108'o2730_3741_0105_4074_4467_0700_0000_0005_0000; CROM[ 875] = 108'o3713_3551_0303_4374_0007_0700_0000_0016_0000; CROM[ 876] = 108'o2733_3441_0305_4174_4007_0700_0200_0003_0002; CROM[ 877] = 108'o2734_3771_0005_0276_6007_0700_0000_0000_0000; CROM[ 878] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 879] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[ 880] = 108'o1500_0551_0303_0274_4463_7701_0200_0001_0001; CROM[ 881] = 108'o1500_2551_0303_0274_4463_7701_4200_0001_0001; CROM[ 882] = 108'o2710_4221_0013_4170_4007_0370_0000_0000_0000; CROM[ 883] = 108'o2743_0111_0703_4174_4007_0700_0200_0024_1016; CROM[ 884] = 108'o0001_0111_0703_4170_4004_1700_0200_0023_1016; CROM[ 885] = 108'o3067_3771_0004_1276_6007_0701_0010_0000_1441; CROM[ 886] = 108'o2761_3447_0303_4174_4007_0700_0000_0000_0000; CROM[ 887] = 108'o0531_0113_0207_4174_4007_0700_0200_0003_0312; CROM[ 888] = 108'o1340_3771_0006_0276_6007_0521_1000_0040_2000; CROM[ 889] = 108'o2756_3442_0300_0174_4007_0700_0000_0000_0000; CROM[ 890] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 891] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 892] = 108'o1342_3441_0305_0174_4007_0621_0000_0000_0000; CROM[ 893] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 894] = 108'o1577_2441_0303_4174_4007_0700_4000_0000_0000; CROM[ 895] = 108'o0670_3771_0005_0276_6006_7701_2000_0020_2000; CROM[ 896] = 108'o3003_3441_0305_0174_4007_0700_0000_0000_0000; CROM[ 897] = 108'o3004_3441_0305_4174_4007_0700_0000_0000_0000; CROM[ 898] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 899] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 900] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 901] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 902] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 903] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 904] = 108'o0240_4443_0000_4174_4007_0360_0000_0000_0000; CROM[ 905] = 108'o0270_0551_0705_0274_4463_7702_0000_0001_0001; CROM[ 906] = 108'o0572_3771_0003_0276_6007_0700_1000_0031_1777; CROM[ 907] = 108'o0611_4551_1203_0276_6007_0700_1000_0041_0001; CROM[ 908] = 108'o2436_4443_0000_4174_4007_0700_0010_0000_0000; CROM[ 909] = 108'o1172_2551_0404_1274_4007_0562_4000_0000_1441; CROM[ 910] = 108'o1354_4553_0300_4374_4007_0321_0000_0077_7000; CROM[ 911] = 108'o0014_4551_0305_0274_4003_7700_0000_0000_0000; CROM[ 912] = 108'o0350_3770_0305_4334_4016_7351_0010_0033_6000; CROM[ 913] = 108'o3206_3333_0003_4174_4007_0700_2000_0041_4000; CROM[ 914] = 108'o0632_4222_0000_4174_4007_0700_0000_0000_0000; CROM[ 915] = 108'o0611_3771_0003_0276_6007_0700_1000_0041_0001; CROM[ 916] = 108'o3077_3333_0003_4174_4217_0701_1010_0073_0500; CROM[ 917] = 108'o0604_3443_0100_4174_4007_0700_0200_0014_0012; CROM[ 918] = 108'o0674_4222_0000_4174_4006_7701_0000_0041_1534; CROM[ 919] = 108'o3011_4112_0400_4174_4007_0700_0000_0000_0000; CROM[ 920] = 108'o0350_3770_0305_4334_4016_7351_0010_0033_6000; CROM[ 921] = 108'o2020_3442_0400_4174_4007_0700_2000_0071_0006; CROM[ 922] = 108'o0747_3777_0003_0274_4007_0701_1000_0031_1777; CROM[ 923] = 108'o0646_3777_0003_0274_4007_0701_1000_0041_0001; CROM[ 924] = 108'o3072_3775_0004_0274_4007_0701_0000_0000_0000; CROM[ 925] = 108'o3212_2441_0404_4174_4007_0700_4000_0000_0000; CROM[ 926] = 108'o0132_3441_0406_4174_4007_0700_0000_0000_0000; CROM[ 927] = 108'o3213_4557_0006_1274_4007_0701_0000_0000_1441; CROM[ 928] = 108'o3153_3771_0006_0276_6007_0700_0010_0000_0000; CROM[ 929] = 108'o2754_3441_0306_0174_4007_0700_0000_0000_0000; CROM[ 930] = 108'o3662_3440_0505_0174_4007_0700_0410_0000_0000; CROM[ 931] = 108'o3161_0551_0405_4370_4007_0701_0000_0000_0001; CROM[ 932] = 108'o2436_3441_0306_4174_4007_0700_0010_0000_0000; CROM[ 933] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 934] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 935] = 108'o1013_3441_0305_4174_4003_7700_0000_0000_0000; CROM[ 936] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 937] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 938] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 939] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 940] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 941] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 942] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 943] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 944] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 945] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 946] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 947] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 948] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 949] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 950] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 951] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 952] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 953] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 954] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 955] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 956] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 957] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 958] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 959] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 960] = 108'o0137_3771_0005_4374_4007_0700_0000_0001_0001; CROM[ 961] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 962] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 963] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 964] = 108'o3503_3771_0005_7274_4007_0701_0000_0000_0230; CROM[ 965] = 108'o3516_3771_0005_7274_4007_0701_0000_0000_0230; CROM[ 966] = 108'o3502_3771_0005_4304_4007_0701_0000_0000_0000; CROM[ 967] = 108'o3500_3771_0005_4304_4007_0701_0000_0000_0000; CROM[ 968] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 969] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 970] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 971] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 972] = 108'o2364_4553_0300_4374_4007_0331_0000_0001_0000; CROM[ 973] = 108'o3613_3441_1405_4174_4007_0700_0000_0000_0000; CROM[ 974] = 108'o0136_3441_1405_4174_4007_0700_0000_0000_0000; CROM[ 975] = 108'o3501_3441_1405_4174_4007_0700_0000_0000_0000; CROM[ 976] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 977] = 108'o2352_4551_1105_4374_0007_0700_0000_0050_7700; CROM[ 978] = 108'o3615_3443_0300_4174_4147_0700_0200_0000_0010; CROM[ 979] = 108'o3524_3443_0300_4174_4007_0700_0200_0004_0012; CROM[ 980] = 108'o2342_3445_0303_4174_4007_0700_2000_0071_0006; CROM[ 981] = 108'o2350_3447_1005_4174_4007_0700_2000_0071_0006; CROM[ 982] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 983] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 984] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 985] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 986] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 987] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 988] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 989] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 990] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 991] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[ 992] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[ 993] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[ 994] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[ 995] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[ 996] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[ 997] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[ 998] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[ 999] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[1000] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[1001] = 108'o0400_4751_1203_4374_4007_0700_0000_0000_0040; CROM[1002] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[1003] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[1004] = 108'o3672_3443_0300_4174_4207_0700_0200_0004_0012; CROM[1005] = 108'o3673_3443_0300_4174_4207_0700_0200_0003_0012; CROM[1006] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[1007] = 108'o0000_0000_0000_0000_0000_0000_0000_0000_0000; // Unused CROM[1008] = 108'o3613_3771_0005_7274_4007_0701_0000_0000_0215; CROM[1009] = 108'o3613_3771_0005_7274_4007_0701_0000_0000_0216; CROM[1010] = 108'o3613_3771_0005_7274_4007_0701_0000_0000_0220; CROM[1011] = 108'o3613_3771_0005_7274_4007_0701_0000_0000_0217; CROM[1012] = 108'o3573_4451_1205_4324_4007_0700_0000_0000_0000; CROM[1013] = 108'o3613_3771_0005_7274_4007_0701_0000_0000_0302; CROM[1014] = 108'o3613_3771_0005_7274_4007_0701_0000_0000_0227; CROM[1015] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[1016] = 108'o3544_4443_0000_4174_4007_0703_0200_0006_0002; CROM[1017] = 108'o3546_4443_0000_4174_4007_0703_0200_0006_0002; CROM[1018] = 108'o3550_4443_0000_4174_4007_0703_0200_0006_0002; CROM[1019] = 108'o3552_4443_0000_4174_4007_0703_0200_0006_0002; CROM[1020] = 108'o3571_4443_0000_4174_4007_0700_0200_0004_0002; CROM[1021] = 108'o3602_4443_0000_4174_4007_0700_0200_0004_0002; CROM[1022] = 108'o3554_4443_0000_4174_4007_0703_0200_0006_0002; CROM[1023] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[1024] = 108'o0440_7441_0303_4174_4003_4701_0000_0000_0000; CROM[1025] = 108'o0440_2441_0303_4174_4003_4701_4000_0000_0000; CROM[1026] = 108'o3211_7441_0303_4174_4007_0700_0000_0000_0000; CROM[1027] = 108'o2004_3223_0000_4174_4007_0621_0000_0000_0000; CROM[1028] = 108'o3211_7441_0303_4174_4007_0700_0000_0000_0000; CROM[1029] = 108'o3211_2441_0303_4174_4007_0700_4000_0000_0000; CROM[1030] = 108'o2010_5547_0505_0374_4007_0631_0000_0077_7400; CROM[1031] = 108'o2010_3547_0505_0374_4007_0631_0000_0077_7400; CROM[1032] = 108'o2012_3442_0600_4174_4007_0700_0000_0000_0000; CROM[1033] = 108'o3215_3771_0016_0276_6007_0700_2000_0041_2000; CROM[1034] = 108'o0153_3441_0516_4174_4007_0700_0010_0000_0000; CROM[1035] = 108'o3214_3441_1605_4174_4007_0700_0000_0000_0000; CROM[1036] = 108'o0153_3441_0316_4174_4007_0700_0010_0000_0000; CROM[1037] = 108'o3217_3441_1603_4174_4007_0700_0000_0000_0000; CROM[1038] = 108'o2016_3446_1616_4174_4047_0630_2000_0060_0000; CROM[1039] = 108'o0453_3221_0017_4174_4007_0700_0000_0000_0000; CROM[1040] = 108'o2020_3444_0303_4174_4047_0630_2000_0060_0000; CROM[1041] = 108'o3230_3446_1200_4174_4007_0700_0000_0000_0000; CROM[1042] = 108'o0732_5547_0606_4374_4007_0701_0000_0077_7400; CROM[1043] = 108'o0732_3547_0606_4374_4007_0701_0000_0077_7400; CROM[1044] = 108'o2025_0002_0500_4174_4007_0700_0000_0000_0000; CROM[1045] = 108'o3240_3444_0303_4174_4047_0700_0000_0000_0000; CROM[1046] = 108'o2027_0002_0500_4174_4007_0700_0000_0000_0000; CROM[1047] = 108'o0520_3333_0003_4174_4003_4701_1000_0041_0002; CROM[1048] = 108'o3243_4557_0004_1274_4007_0700_0000_0000_1441; CROM[1049] = 108'o3241_7441_1717_4174_4007_0700_0000_0000_0000; CROM[1050] = 108'o2034_5547_0303_4374_4007_0701_0000_0077_7400; CROM[1051] = 108'o3244_7441_1717_4174_4007_0700_0000_0000_0000; CROM[1052] = 108'o3042_3442_0400_4174_4007_0700_0010_0000_0000; CROM[1053] = 108'o2036_2113_0305_4174_4007_0521_4000_0000_0000; CROM[1054] = 108'o0555_4443_0000_4174_4467_0700_0000_0071_1000; CROM[1055] = 108'o0724_3221_0004_4174_4007_0700_0000_0000_0000; CROM[1056] = 108'o0520_3441_1603_4174_4003_4701_0000_0000_0000; CROM[1057] = 108'o0200_3441_1603_4174_4003_4701_0000_0000_0000; CROM[1058] = 108'o0520_3444_0303_4174_4043_4701_1000_0041_1777; CROM[1059] = 108'o1515_3440_0303_1174_4007_0700_0400_0000_1441; CROM[1060] = 108'o3252_7222_0000_4174_4007_0700_0000_0000_0000; CROM[1061] = 108'o2046_2222_0000_4174_4007_0511_4000_0000_0000; CROM[1062] = 108'o0200_7441_0303_4174_4003_4701_0000_0000_0000; CROM[1063] = 108'o0200_2441_0303_4174_4003_4701_4000_0000_0000; CROM[1064] = 108'o3254_7333_0003_0174_4007_0700_0400_0000_0000; CROM[1065] = 108'o3254_2443_0300_0174_4007_0701_4400_0000_0000; CROM[1066] = 108'o0200_3444_0303_4174_4043_4701_1000_0041_1777; CROM[1067] = 108'o1515_3440_0303_1174_4007_0700_0400_0000_1441; CROM[1068] = 108'o0023_3551_1313_4374_0004_1700_0000_0000_2000; CROM[1069] = 108'o0023_5551_1313_4374_0004_1700_0000_0000_2000; CROM[1070] = 108'o3400_3333_0005_7174_4001_2700_0400_0000_0241; CROM[1071] = 108'o0556_3771_0005_4374_0007_0700_0000_0077_7777; CROM[1072] = 108'o3556_4553_0500_4374_4007_0321_0010_0077_7000; CROM[1073] = 108'o3556_4553_0400_4374_4007_0321_0010_0077_7000; CROM[1074] = 108'o3460_4521_0306_4374_4007_0700_0010_0077_7000; CROM[1075] = 108'o2066_2113_0305_1174_4007_0521_4400_0000_1443; CROM[1076] = 108'o2062_3771_0003_0276_6007_0700_0000_0000_0000; CROM[1077] = 108'o2110_3771_0006_0276_6007_0700_0000_0000_0000; CROM[1078] = 108'o3264_7441_0503_4174_4007_0700_0000_0000_0000; CROM[1079] = 108'o3264_7441_0303_4174_4007_0700_0000_0000_0000; CROM[1080] = 108'o2070_4224_0003_4174_4026_7701_1000_0041_1770; CROM[1081] = 108'o3560_4443_0000_4174_4007_0700_0010_0000_0000; CROM[1082] = 108'o3267_7221_0003_4174_4007_0700_0000_0000_0000; CROM[1083] = 108'o3302_3771_0003_7274_4007_0701_0000_0000_0211; CROM[1084] = 108'o3271_3440_0303_1174_4007_0700_0400_0000_1443; CROM[1085] = 108'o2074_1111_0503_4174_4007_0700_4000_0000_0000; CROM[1086] = 108'o2077_0111_0503_4174_4007_0700_0000_0000_0000; CROM[1087] = 108'o3273_3111_0603_4174_4007_0700_0000_0000_0000; CROM[1088] = 108'o3277_3333_0003_7174_4007_0700_0400_0000_0211; CROM[1089] = 108'o2102_1111_0704_4174_4007_0521_4000_0000_0000; CROM[1090] = 108'o0650_3770_0305_4334_4016_7371_0000_0033_6000; CROM[1091] = 108'o0546_4223_0000_1174_4007_0700_0400_0000_1443; CROM[1092] = 108'o3664_0111_0403_4174_4007_0700_0010_0000_0000; CROM[1093] = 108'o3720_3113_0306_0174_4007_0700_0400_0000_0000; CROM[1094] = 108'o2107_0111_0703_4174_4007_0700_0000_0000_0000; CROM[1095] = 108'o2112_0111_0703_4170_4007_0700_0200_0004_0012; CROM[1096] = 108'o3556_4553_0600_4374_4007_0321_0010_0077_7000; CROM[1097] = 108'o3556_4553_0600_4374_4007_0321_0010_0004_7777; CROM[1098] = 108'o3662_4221_0003_4174_4007_0700_0010_0000_0000; CROM[1099] = 108'o3320_3223_0000_7174_4007_0700_0400_0000_0244; CROM[1100] = 108'o2106_2113_0604_4174_4007_0521_4000_0000_0000; CROM[1101] = 108'o3401_3443_0600_4174_4007_0700_0200_0004_0012; CROM[1102] = 108'o0250_4221_0013_4170_4003_7700_0000_0000_0000; CROM[1103] = 108'o3311_3771_0003_1276_6007_0701_0000_0000_1441; CROM[1104] = 108'o3323_3772_0000_7274_4007_0701_0000_0000_0244; CROM[1105] = 108'o2116_4221_0003_4174_4007_0700_0000_0000_0000; CROM[1106] = 108'o3451_3771_0003_1276_6007_0701_0010_0000_1444; CROM[1107] = 108'o0340_3333_0003_4174_4006_5701_1000_0051_0770; CROM[1108] = 108'o2220_3771_0004_1276_6007_0701_0010_0000_1444; CROM[1109] = 108'o2220_3333_0004_7174_4007_0700_0410_0000_0250; CROM[1110] = 108'o2130_3440_0404_1174_4007_0700_0400_0000_1444; CROM[1111] = 108'o2160_3333_0003_7174_4007_0520_0400_0000_0247; CROM[1112] = 108'o2154_3333_0006_4174_4007_0520_0010_0000_0000; CROM[1113] = 108'o0616_4551_0303_4374_0003_7700_0000_0000_0777; CROM[1114] = 108'o3335_7771_0003_7274_4007_0701_0000_0000_0242; CROM[1115] = 108'o1050_3771_0005_1276_6007_0622_0000_0000_1443; CROM[1116] = 108'o1050_4443_0000_4174_4007_0700_0000_0000_0000; CROM[1117] = 108'o3332_3775_0005_1276_6007_0701_0000_0000_1444; CROM[1118] = 108'o3665_0551_0505_1274_4007_0700_0010_0000_1444; CROM[1119] = 108'o0460_0113_0305_1174_4007_0701_0400_0000_1444; CROM[1120] = 108'o0004_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1121] = 108'o3334_4551_0404_4374_0007_0700_0000_0037_7777; CROM[1122] = 108'o3341_3771_0004_1276_6007_0701_0000_0000_1444; CROM[1123] = 108'o3337_3771_0003_1276_6007_0701_0000_0000_1444; CROM[1124] = 108'o3340_4551_0303_4374_0007_0700_0000_0037_7777; CROM[1125] = 108'o3340_3551_0303_4374_0007_0700_0000_0040_0000; CROM[1126] = 108'o2154_3770_0606_0174_4007_0520_0410_0000_0000; CROM[1127] = 108'o0260_4221_0013_4170_4007_0700_0000_0000_0000; CROM[1128] = 108'o2153_7771_0003_1274_4007_0700_0000_0000_1443; CROM[1129] = 108'o2152_1771_0003_1274_4007_0621_4000_0000_1443; CROM[1130] = 108'o2153_4571_1204_4374_4007_0700_0000_0040_0000; CROM[1131] = 108'o3343_3440_0303_1174_4007_0700_0400_0000_1443; CROM[1132] = 108'o3344_4223_0000_1174_4007_0700_0400_0000_1443; CROM[1133] = 108'o0001_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1134] = 108'o3345_4551_0606_4374_4007_0700_0000_0077_7000; CROM[1135] = 108'o3363_3771_0003_0276_6007_0700_0000_0000_0000; CROM[1136] = 108'o2170_4221_0006_4170_4007_0700_0000_0000_0000; CROM[1137] = 108'o2164_3551_0606_4374_0007_0700_0000_0010_0000; CROM[1138] = 108'o2160_3440_0404_1174_4007_0700_0400_0000_1441; CROM[1139] = 108'o3347_0111_0704_4174_4007_0700_0000_0000_0000; CROM[1140] = 108'o3071_4551_0404_4374_0007_0700_0010_0037_7777; CROM[1141] = 108'o2220_3441_1617_4174_4007_0700_0210_0000_0010; CROM[1142] = 108'o2162_3770_0303_0174_4007_0520_0400_0000_0000; CROM[1143] = 108'o2216_1551_0404_6274_4007_0561_4000_0000_0000; CROM[1144] = 108'o0441_3771_0003_0276_6007_0700_0000_0000_0000; CROM[1145] = 108'o2174_3551_0606_4374_0007_0700_0000_0020_0000; CROM[1146] = 108'o2174_3551_0606_4374_0007_0700_0000_0020_0000; CROM[1147] = 108'o2174_0111_0706_4174_4007_0700_0000_0000_0000; CROM[1148] = 108'o3460_3771_0003_1276_6007_0701_0010_0000_1443; CROM[1149] = 108'o3350_4221_0005_4174_4007_0700_0000_0000_0000; CROM[1150] = 108'o3373_3771_0004_7274_4007_0701_0000_0000_0250; CROM[1151] = 108'o2200_3333_0006_4174_4007_0520_0000_0000_0000; CROM[1152] = 108'o2157_3440_0606_1174_4007_0700_0400_0000_1443; CROM[1153] = 108'o3352_3441_0603_4174_0007_0700_0000_0000_0000; CROM[1154] = 108'o3374_0111_0704_4174_4007_0700_0000_0000_0000; CROM[1155] = 108'o3370_3440_0303_0174_4007_0700_0400_0000_0000; CROM[1156] = 108'o0562_2441_0705_4174_4467_0701_4000_0003_0000; CROM[1157] = 108'o0260_4221_0013_4170_4467_0700_0000_0005_0000; CROM[1158] = 108'o3660_4221_0013_4170_4007_0700_0010_0000_0000; CROM[1159] = 108'o2210_4553_0600_4374_4007_0331_0000_0077_7777; CROM[1160] = 108'o0637_4221_0003_4174_0007_0700_0000_0000_0000; CROM[1161] = 108'o2212_4553_0600_4374_4007_0321_0000_0010_0000; CROM[1162] = 108'o2213_3770_0303_4344_4007_0700_0000_0000_0000; CROM[1163] = 108'o0637_4221_0003_4174_0007_0700_0000_0000_0000; CROM[1164] = 108'o2165_0551_0616_4374_4007_0701_0000_0000_0344; CROM[1165] = 108'o2677_4443_0000_4174_4007_0700_0000_0000_0000; CROM[1166] = 108'o2217_1111_0703_4174_4007_0700_4000_0000_0000; CROM[1167] = 108'o3375_0551_0616_4374_4007_0701_0000_0000_0373; CROM[1168] = 108'o0002_4551_0404_4374_0004_1700_0000_0037_7777; CROM[1169] = 108'o3377_0551_0303_6274_4007_0700_0000_0000_0000; CROM[1170] = 108'o0006_4551_0404_4374_0004_1700_0000_0037_7777; CROM[1171] = 108'o2222_0111_0703_4174_4007_0700_0000_0000_0000; CROM[1172] = 108'o3660_0115_0505_4174_4007_0700_0010_0000_0000; CROM[1173] = 108'o0654_3333_0005_4174_4003_1701_0000_0000_0000; CROM[1174] = 108'o2226_3447_0303_4174_4007_0630_2000_0060_0000; CROM[1175] = 108'o3403_4551_0303_4374_4007_0700_0000_0000_0777; CROM[1176] = 108'o2230_3447_0505_4174_4007_0630_2000_0060_0000; CROM[1177] = 108'o0661_3333_0005_4174_4003_5701_0000_0000_0000; CROM[1178] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[1179] = 108'o0710_3333_0003_4174_4003_5701_0000_0000_0000; CROM[1180] = 108'o1515_3770_0303_4334_4017_0700_0000_0041_0000; CROM[1181] = 108'o2234_0111_0703_4174_4007_0700_1000_0051_0700; CROM[1182] = 108'o3660_3772_0000_1275_5007_0701_0010_0000_1444; CROM[1183] = 108'o3407_4443_0000_4174_4007_0700_0200_0003_0002; CROM[1184] = 108'o2275_3771_0003_1276_6007_0701_0010_0000_1441; CROM[1185] = 108'o0360_3333_0003_4174_4006_5701_0010_0000_0000; CROM[1186] = 108'o0700_3447_0303_7174_4007_0700_0000_0000_0241; CROM[1187] = 108'o0006_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1188] = 108'o0705_4443_0000_4174_4007_0700_0000_0000_0000; CROM[1189] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[1190] = 108'o3417_4751_1203_4374_4007_0700_0010_0000_0002; CROM[1191] = 108'o0740_3771_0003_4365_5007_0621_0200_0000_0002; CROM[1192] = 108'o0760_3771_0003_7274_4007_0622_0000_0000_0244; CROM[1193] = 108'o2252_4251_0303_4374_4007_0700_0000_0000_0077; CROM[1194] = 108'o3417_0111_0703_7174_4007_0700_0010_0000_0240; CROM[1195] = 108'o0760_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1196] = 108'o3421_4551_0303_4374_4007_0700_0000_0000_0077; CROM[1197] = 108'o3423_4443_0000_4174_4007_0700_0000_0000_0000; CROM[1198] = 108'o2260_3447_0303_4174_4007_0700_2000_0071_0000; CROM[1199] = 108'o2256_3551_0303_4370_4007_0700_0000_0000_0200; CROM[1200] = 108'o2260_3447_0303_4174_4007_0630_2000_0060_0000; CROM[1201] = 108'o3432_0111_0306_4170_4007_0700_0000_0000_0000; CROM[1202] = 108'o0002_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1203] = 108'o0332_4443_0000_7174_4007_0700_0000_0000_0244; CROM[1204] = 108'o3661_3445_0303_4174_4007_0700_0010_0000_0000; CROM[1205] = 108'o2266_4553_0300_4374_4007_0331_0000_0000_0001; CROM[1206] = 108'o0721_3441_0403_4174_4003_1701_0000_0000_0000; CROM[1207] = 108'o2266_3770_0404_4344_4007_0700_0000_0000_0000; CROM[1208] = 108'o0754_3333_0004_4174_4003_7530_0000_0000_0000; CROM[1209] = 108'o0005_4251_0403_4374_4004_1700_0000_0007_7777; CROM[1210] = 108'o1074_3771_0003_7274_4007_0701_0000_0000_0242; CROM[1211] = 108'o1074_0551_0703_7274_4007_0701_0000_0000_0242; CROM[1212] = 108'o0001_3771_0003_1276_6004_1701_0000_0000_1443; CROM[1213] = 108'o3445_3771_0003_1276_6007_0701_0000_0000_1441; CROM[1214] = 108'o3076_3333_0003_4174_4217_0701_1010_0073_0500; CROM[1215] = 108'o0340_3333_0003_4174_4006_5701_1000_0051_0770; CROM[1216] = 108'o3451_3771_0003_1276_6007_0701_0010_0000_1444; CROM[1217] = 108'o2241_0113_0404_4174_4007_0701_1000_0077_0000; CROM[1218] = 108'o3473_3771_0003_1276_6007_0701_0010_0000_1441; CROM[1219] = 108'o2700_3440_0505_1174_4007_0700_0400_0000_1441; CROM[1220] = 108'o3453_3441_0503_4174_4217_0700_0000_0000_0600; CROM[1221] = 108'o3572_0111_0703_4174_4007_0700_0010_0000_0000; CROM[1222] = 108'o3452_3770_0503_4334_4017_0700_0000_0032_6000; CROM[1223] = 108'o2356_4221_0003_4174_4007_0700_0000_0000_0000; CROM[1224] = 108'o3473_3771_0003_1276_6007_0701_0010_0000_1444; CROM[1225] = 108'o2700_3440_0505_1174_4007_0700_0400_0000_1444; CROM[1226] = 108'o3466_3440_0303_1174_4007_0700_0400_0000_1443; CROM[1227] = 108'o2314_3441_0304_4174_4007_0700_0000_0000_0000; CROM[1228] = 108'o3671_3551_0404_7274_4007_0701_0010_0000_0214; CROM[1229] = 108'o3465_1111_0503_4174_4007_0700_4000_0000_0000; CROM[1230] = 108'o3476_0111_1103_4364_4007_0700_0200_0024_1016; CROM[1231] = 108'o3476_0111_1003_4364_4007_0700_0200_0024_1016; CROM[1232] = 108'o2716_4443_0000_4174_4467_0700_0000_0001_0000; CROM[1233] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[1234] = 108'o2323_3111_0405_4174_4007_0700_0000_0000_0000; CROM[1235] = 108'o2324_4553_0300_4374_4007_0331_0000_0004_0000; CROM[1236] = 108'o2325_5111_0405_4174_4007_0700_0000_0000_0000; CROM[1237] = 108'o3510_3771_0006_4304_4007_0701_0000_0000_0000; CROM[1238] = 108'o2327_5111_0406_4174_4007_0700_0000_0000_0000; CROM[1239] = 108'o2330_4553_0300_4374_4007_0331_0000_0001_0000; CROM[1240] = 108'o2331_3111_0406_4174_4007_0700_0000_0000_0000; CROM[1241] = 108'o2332_4553_0300_4374_4007_0331_0000_0003_0000; CROM[1242] = 108'o3513_3333_0006_4174_4007_0700_0000_0000_0000; CROM[1243] = 108'o3511_3333_0005_4174_4007_0700_0000_0000_0000; CROM[1244] = 108'o2336_4551_0303_4374_0007_0321_0000_0010_0000; CROM[1245] = 108'o3525_4551_1111_4374_0007_0700_0000_0077_0077; CROM[1246] = 108'o3527_4551_0305_4374_4007_0700_0000_0000_3777; CROM[1247] = 108'o1400_3111_0311_4174_0477_0700_0000_0000_0000; CROM[1248] = 108'o2340_3445_0505_4174_4007_0630_2000_0060_0000; CROM[1249] = 108'o3530_4551_1111_4374_0007_0700_0000_0077_7774; CROM[1250] = 108'o2342_3445_0303_4174_4007_0630_2000_0060_0000; CROM[1251] = 108'o3533_3771_0005_7274_4007_0701_0000_0000_0230; CROM[1252] = 108'o2345_3551_0505_4370_4007_0700_0000_0003_0000; CROM[1253] = 108'o3535_3333_0005_4174_4257_0700_0000_0000_0000; CROM[1254] = 108'o2406_3551_1010_4374_0007_0700_0000_0040_0000; CROM[1255] = 108'o2406_5551_1010_4374_0007_0700_0000_0040_0000; CROM[1256] = 108'o2350_3447_0505_4174_4007_0630_2000_0060_0000; CROM[1257] = 108'o3540_4551_0505_4374_4007_0700_0000_0006_3777; CROM[1258] = 108'o2354_3447_1106_4174_4007_0700_2010_0071_0006; CROM[1259] = 108'o3614_3443_0300_4174_4007_0700_0200_0003_0012; CROM[1260] = 108'o2354_3447_0606_4174_4007_0630_2000_0060_0000; CROM[1261] = 108'o3543_4551_0606_4374_4007_0700_0000_0000_3777; CROM[1262] = 108'o3564_3333_0003_7174_4007_0700_0400_0000_0301; CROM[1263] = 108'o2305_3771_0003_7274_4007_0701_0000_0000_0300; CROM[1264] = 108'o0002_3333_0003_7174_4004_1700_0400_0000_0303; CROM[1265] = 108'o3566_3771_0003_7274_4007_0701_0000_0000_0302; CROM[1266] = 108'o2363_3441_0604_4174_4007_0700_0000_0000_0000; CROM[1267] = 108'o3576_3771_0005_7274_4007_0701_0000_0000_0300; CROM[1268] = 108'o2365_4221_0014_4174_4007_0700_0000_0000_0000; CROM[1269] = 108'o2366_4553_0300_4374_4007_0331_0000_0074_0000; CROM[1270] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[1271] = 108'o3605_4551_0305_4374_4007_0700_0000_0000_0177; CROM[1272] = 108'o2371_5111_0514_4174_0007_0700_0000_0000_0000; CROM[1273] = 108'o2372_4553_0300_4374_4007_0331_0000_0000_4000; CROM[1274] = 108'o2373_3111_0514_4174_0007_0700_0000_0000_0000; CROM[1275] = 108'o2374_4553_0300_4374_4007_0331_0000_0000_0200; CROM[1276] = 108'o2375_3551_1414_4370_4007_0700_0000_0000_0200; CROM[1277] = 108'o2376_4553_0300_4374_4007_0331_0000_0000_0400; CROM[1278] = 108'o2377_5551_1414_4370_4007_0700_0000_0000_0200; CROM[1279] = 108'o2400_4553_0300_4374_4007_0331_0000_0000_2000; CROM[1280] = 108'o2401_3111_0514_4170_4007_0700_0000_0000_0000; CROM[1281] = 108'o0304_4553_0300_4374_4007_0331_0000_0000_1000; CROM[1282] = 108'o3621_3771_0003_4374_4007_0700_0010_0037_7377; CROM[1283] = 108'o3616_3771_0005_4374_4247_0700_0000_0000_1001; CROM[1284] = 108'o2404_1111_0503_4174_4247_0630_6000_0060_1000; CROM[1285] = 108'o2411_3333_0003_4174_4007_0700_0000_0000_0000; CROM[1286] = 108'o3621_3771_0003_4374_4007_0700_0010_0037_7377; CROM[1287] = 108'o3617_3771_0005_4374_4347_0700_0000_0000_1001; CROM[1288] = 108'o2410_1111_0503_4174_4347_0630_6000_0060_1000; CROM[1289] = 108'o3620_4223_0000_7174_4007_0700_0400_0000_0424; CROM[1290] = 108'o3666_4571_1203_4374_4007_0700_0010_0024_1300; CROM[1291] = 108'o2414_3771_0003_4364_4007_0331_0200_0000_0002; CROM[1292] = 108'o3642_4221_0004_4174_4007_0700_0000_0000_0000; CROM[1293] = 108'o3634_3445_0603_4174_4007_0700_0000_0000_0000; CROM[1294] = 108'o2420_6553_0300_4374_4007_0321_0000_0026_4000; CROM[1295] = 108'o3641_4521_1205_4074_4007_0700_0000_0000_0000; CROM[1296] = 108'o0104_4751_1217_4374_4007_0700_0000_0000_0101; CROM[1297] = 108'o0470_4443_0000_4174_4007_0700_0200_0023_0002; CROM[1298] = 108'o3642_0111_1504_4174_4007_0700_0000_0000_0000; CROM[1299] = 108'o2424_4571_1203_4374_4007_0700_0000_0024_1240; CROM[1300] = 108'o3666_3111_0403_4174_4007_0700_0010_0000_0000; CROM[1301] = 108'o2426_3771_0016_4364_4007_0700_0200_0000_0002; CROM[1302] = 108'o3663_0551_1005_4374_4007_0701_0010_0000_0100; CROM[1303] = 108'o3643_0111_0504_4174_4007_0700_0200_0024_1016; CROM[1304] = 108'o3644_4557_1606_4374_4007_0701_0000_0000_0774; CROM[1305] = 108'o0104_4751_1217_4374_4007_0700_0000_0000_0102; CROM[1306] = 108'o3646_3771_0005_4374_4007_0700_0000_0004_0000; CROM[1307] = 108'o0004_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1308] = 108'o0004_5111_0514_4170_4004_1700_0000_0000_0000; CROM[1309] = 108'o3646_3447_0505_4174_4007_0700_0000_0000_0000; CROM[1310] = 108'o2456_4443_0000_4174_4137_0700_0010_0000_0000; CROM[1311] = 108'o0067_4443_0000_4174_4003_7700_0000_0000_0000; CROM[1312] = 108'o3656_3113_0305_4174_4007_0701_0210_0000_0036; CROM[1313] = 108'o1027_3771_0005_4364_4003_7700_0200_0000_0002; CROM[1314] = 108'o2444_3447_0505_4174_4007_0700_2000_0071_0005; CROM[1315] = 108'o0003_4551_0503_4374_4004_1700_0000_0000_0377; CROM[1316] = 108'o2444_3447_0505_4174_4007_0630_2000_0060_0000; CROM[1317] = 108'o0003_4551_0503_4374_4004_1700_0000_0000_0377; CROM[1318] = 108'o2456_4443_0000_4174_4137_0700_0010_0000_0000; CROM[1319] = 108'o0227_4443_0000_4174_4003_7700_0000_0000_0000; CROM[1320] = 108'o3656_3333_0005_4175_5007_0701_0210_0000_0002; CROM[1321] = 108'o0110_3443_0100_4174_4156_4700_0200_0014_0012; CROM[1322] = 108'o2454_3445_0505_4174_4007_0700_2000_0071_0005; CROM[1323] = 108'o3650_4571_1204_4374_4007_0700_0000_0021_1220; CROM[1324] = 108'o2454_3445_0505_4174_4007_0630_2000_0060_0000; CROM[1325] = 108'o3650_4571_1204_4374_4007_0700_0000_0021_1220; CROM[1326] = 108'o3660_1113_0701_4170_4007_0700_4210_0004_0012; CROM[1327] = 108'o3651_7441_0306_4174_4007_0700_0000_0000_0000; CROM[1328] = 108'o2462_4553_0200_4374_4007_0321_0000_0000_0020; CROM[1329] = 108'o2460_4713_1203_7174_4007_0700_0400_0000_0422; CROM[1330] = 108'o3652_3771_0003_7274_4007_0701_0000_0000_0422; CROM[1331] = 108'o1055_4443_0000_2174_4006_6700_0000_0000_0000; CROM[1332] = 108'o2465_0551_0303_2270_4007_0701_0000_0000_0000; CROM[1333] = 108'o3654_3443_0300_4174_4007_0700_0200_0004_0012; CROM[1334] = 108'o0001_0551_0403_7274_4124_1701_0000_0000_0422; CROM[1335] = 108'o3655_0551_0403_7274_4007_0701_0000_0000_0422; CROM[1336] = 108'o2472_4443_0000_4174_4127_0630_2000_0060_0000; CROM[1337] = 108'o0001_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1338] = 108'o2470_4443_0000_4174_4127_0653_0000_0000_0000; CROM[1339] = 108'o1501_4571_1206_4374_4007_0700_0000_0020_0000; CROM[1340] = 108'o3670_0111_0704_4170_4007_0700_0210_0023_1016; CROM[1341] = 108'o0005_4443_0000_4174_4107_0700_0000_0000_0074; CROM[1342] = 108'o0117_3443_0100_4174_4007_0700_0200_0014_0012; CROM[1343] = 108'o2500_4571_1203_4374_4007_0700_0000_0024_1200; CROM[1344] = 108'o3666_3551_0303_4370_4007_0700_0010_0020_0000; CROM[1345] = 108'o2716_3771_0002_4365_5617_0700_0200_0000_0002; CROM[1346] = 108'o3700_3333_0012_4174_4437_0700_0000_0000_0000; CROM[1347] = 108'o0002_3771_0004_7274_4004_1701_0000_0000_0212; CROM[1348] = 108'o2746_3333_0000_4175_5007_0701_0210_0000_0002; CROM[1349] = 108'o2746_3333_0002_4175_5007_0701_0210_0000_0002; CROM[1350] = 108'o3701_3333_0001_4175_5007_0701_0200_0000_0002; CROM[1351] = 108'o2510_3333_0003_4175_5007_0701_0200_0000_0002; CROM[1352] = 108'o2746_3333_0003_7174_4007_0700_0410_0000_0211; CROM[1353] = 108'o2746_3333_0003_4175_5007_0701_0210_0000_0002; CROM[1354] = 108'o2511_3771_0003_7274_4007_0701_0000_0000_0212; CROM[1355] = 108'o3702_3333_0005_4175_5007_0701_0200_0000_0002; CROM[1356] = 108'o2746_3333_0006_4175_5007_0701_0210_0000_0002; CROM[1357] = 108'o2746_3333_0010_4175_5007_0701_0210_0000_0002; CROM[1358] = 108'o3703_3333_0007_4175_5007_0701_0200_0000_0002; CROM[1359] = 108'o3704_3333_0011_4175_5007_0701_0200_0000_0002; CROM[1360] = 108'o2746_3333_0012_4175_5007_0701_0210_0000_0002; CROM[1361] = 108'o2746_3333_0014_4175_5007_0701_0210_0000_0002; CROM[1362] = 108'o3705_3333_0013_4175_5007_0701_0200_0000_0002; CROM[1363] = 108'o3706_3333_0015_4175_5007_0701_0200_0000_0002; CROM[1364] = 108'o2746_3333_0016_4175_5007_0701_0210_0000_0002; CROM[1365] = 108'o2746_3771_0003_7274_4007_0701_0010_0000_0210; CROM[1366] = 108'o2525_3333_0017_4175_5007_0701_0200_0000_0002; CROM[1367] = 108'o3707_3333_0003_4175_5007_0701_0200_0000_0002; CROM[1368] = 108'o3727_3771_0013_4370_4007_0700_0000_0040_0002; CROM[1369] = 108'o0100_3440_0303_0174_4156_4700_0400_0000_0000; CROM[1370] = 108'o2533_3551_0606_4374_0007_0700_0000_0001_0000; CROM[1371] = 108'o3732_4551_0606_4374_0007_0700_0000_0041_1000; CROM[1372] = 108'o2534_3447_0505_4174_4007_0630_2000_0060_0000; CROM[1373] = 108'o3734_4251_0505_4374_4007_0700_0000_0000_0777; CROM[1374] = 108'o2540_3333_0006_4174_4007_0520_0000_0000_0000; CROM[1375] = 108'o3774_3447_0504_4174_4007_0700_0000_0000_0000; CROM[1376] = 108'o2544_3771_0004_7274_4007_0622_0000_0000_0423; CROM[1377] = 108'o2542_3771_0004_7274_4007_0622_0000_0000_0424; CROM[1378] = 108'o1130_0113_0405_4174_4007_0700_0200_0024_1016; CROM[1379] = 108'o3735_0551_1103_4374_4007_0701_0000_0000_0540; CROM[1380] = 108'o1130_0113_0405_4174_4007_0700_0200_0024_1016; CROM[1381] = 108'o3735_0551_1003_4374_4007_0701_0000_0000_0540; CROM[1382] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[1383] = 108'o0602_3445_0303_4174_4007_0630_2000_0060_0000; CROM[1384] = 108'o3772_4443_0000_4174_4007_0700_0010_0000_0000; CROM[1385] = 108'o0030_4443_0000_2174_4006_6700_0000_0000_0000; CROM[1386] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[1387] = 108'o2555_4251_0304_4374_4007_0700_0000_0000_3777; CROM[1388] = 108'o2552_4553_0300_4374_4007_0321_0000_0000_0077; CROM[1389] = 108'o2622_3441_0403_4174_4007_0700_0010_0000_0000; CROM[1390] = 108'o2551_3771_0002_4365_5217_0700_0200_0000_0002; CROM[1391] = 108'o2560_3551_0303_7274_4007_0701_0000_0000_0220; CROM[1392] = 108'o3075_4443_0000_4174_4007_0700_0210_0001_0002; CROM[1393] = 108'o3772_4443_0000_4174_4007_0700_0010_0000_0000; CROM[1394] = 108'o2562_3445_0404_4174_4007_0630_2000_0060_0000; CROM[1395] = 108'o1040_3333_0006_4174_4007_0520_0000_0000_0000; CROM[1396] = 108'o2562_4443_0000_4174_4007_0700_2000_0071_0007; CROM[1397] = 108'o1134_4553_0300_4374_4007_0321_0000_0000_0077; CROM[1398] = 108'o2600_3333_0003_7174_4007_0700_0400_0000_0426; CROM[1399] = 108'o2570_4251_0505_4374_4007_0370_0000_0000_0777; CROM[1400] = 108'o1000_4551_0303_4374_0007_0700_0000_0027_7000; CROM[1401] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[1402] = 108'o3745_3551_0606_4374_4007_0700_0000_0002_0000; CROM[1403] = 108'o2574_4553_0600_4374_4007_0321_0000_0003_0000; CROM[1404] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[1405] = 108'o2603_3551_0303_7274_4007_0701_0000_0000_0220; CROM[1406] = 108'o2604_3551_0303_4370_4007_0700_0000_0000_0001; CROM[1407] = 108'o2604_4553_0300_4374_4007_0331_0000_0000_0001; CROM[1408] = 108'o3561_3771_0003_7274_4117_0701_0010_0000_0301; CROM[1409] = 108'o0104_4751_1217_4374_4007_0700_0000_0000_0001; CROM[1410] = 108'o1133_3771_0003_7274_4007_0701_0000_0000_0426; CROM[1411] = 108'o3075_4443_0000_4174_4007_0700_0210_0001_0002; CROM[1412] = 108'o2575_3551_0606_4374_0007_0700_0000_0004_0000; CROM[1413] = 108'o2575_5551_1313_4374_0007_0700_0000_0002_0000; CROM[1414] = 108'o2623_3771_0005_4365_5007_0700_0200_0000_0002; CROM[1415] = 108'o2610_4553_1300_4374_4007_0331_0000_0040_0000; CROM[1416] = 108'o2612_3441_0403_4174_4007_0700_2000_0071_0007; CROM[1417] = 108'o3753_3771_0003_7274_4007_0701_0000_0000_0210; CROM[1418] = 108'o2612_3445_0303_4174_4007_0630_2000_0060_0000; CROM[1419] = 108'o3746_4551_0303_4374_0007_0700_0000_0000_0003; CROM[1420] = 108'o2615_3551_0606_4374_0007_0700_0000_0000_2000; CROM[1421] = 108'o3752_4551_0606_4370_4007_0700_0000_0000_0777; CROM[1422] = 108'o2617_3551_0606_4374_4007_0700_0000_0004_0000; CROM[1423] = 108'o2620_4553_1300_4374_4147_0321_0000_0000_4000; CROM[1424] = 108'o3762_3551_0606_4374_4007_0700_0000_0002_0000; CROM[1425] = 108'o3762_3333_0006_4174_4007_0700_0000_0000_0000; CROM[1426] = 108'o3772_0551_0303_7274_4007_0701_0010_0000_0216; CROM[1427] = 108'o2627_0111_0703_4174_4007_0700_0200_0004_0012; CROM[1428] = 108'o0002_4551_0303_7274_4004_1701_0000_0000_0217; CROM[1429] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[1430] = 108'o2624_4553_0300_4374_4007_0321_0000_0077_0000; CROM[1431] = 108'o2701_3771_0001_4361_5007_0700_0200_0000_0002; CROM[1432] = 108'o2632_4553_0300_4374_4007_0321_0000_0030_0000; CROM[1433] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[1434] = 108'o2634_4553_0300_4374_4007_0321_0000_0010_0000; CROM[1435] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[1436] = 108'o2636_4553_0300_4374_4007_0321_0000_0020_0000; CROM[1437] = 108'o0002_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1438] = 108'o0003_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1439] = 108'o0001_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1440] = 108'o0004_3771_0003_4365_5004_1700_0200_0000_0002; CROM[1441] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[1442] = 108'o0007_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1443] = 108'o3773_7441_1303_4174_4007_0700_0000_0000_0000; CROM[1444] = 108'o0007_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1445] = 108'o0002_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1446] = 108'o2650_1553_0500_4374_4007_0532_4000_0000_0340; CROM[1447] = 108'o3775_0111_1104_4174_4007_0700_0200_0024_1016; CROM[1448] = 108'o2652_1553_0500_4374_4007_0532_4000_0000_0400; CROM[1449] = 108'o2652_0551_0404_4374_4007_0701_0000_0000_0600; CROM[1450] = 108'o3775_0111_1004_4174_4007_0700_0200_0024_1016; CROM[1451] = 108'o2647_0551_0404_4374_4007_0701_0000_0000_0220; CROM[1452] = 108'o2656_3333_0004_4174_4007_0530_0000_0000_0000; CROM[1453] = 108'o2654_3770_0404_4344_4007_0700_0000_0000_0000; CROM[1454] = 108'o2672_4553_1300_4374_4007_0321_0000_0001_0000; CROM[1455] = 108'o1435_5551_1313_4374_4007_0700_0000_0002_4000; CROM[1456] = 108'o2661_3551_1313_4374_0007_0700_0000_0000_4000; CROM[1457] = 108'o2662_4553_0400_4374_4007_0331_0000_0004_0000; CROM[1458] = 108'o2663_3551_0606_4374_0007_0700_0000_0002_0000; CROM[1459] = 108'o2664_4553_0400_4374_4007_0331_0000_0010_0000; CROM[1460] = 108'o1500_3551_1313_4374_0007_0700_0000_0002_0000; CROM[1461] = 108'o2666_4553_0600_4374_4007_0321_0000_0001_0000; CROM[1462] = 108'o2656_3551_0606_4374_0007_0700_0000_0010_0000; CROM[1463] = 108'o2607_4443_0000_4174_4007_0700_0000_0000_0000; CROM[1464] = 108'o1510_3771_0005_4354_4007_0700_0010_0000_0000; CROM[1465] = 108'o1502_4551_0505_4374_0007_0700_0000_0040_1237; CROM[1466] = 108'o0104_4751_1217_4374_4007_0700_0000_0000_0100; CROM[1467] = 108'o2674_3771_0003_7274_4007_0611_0000_0000_0210; CROM[1468] = 108'o2676_4553_0300_4374_4007_0321_0000_0010_0000; CROM[1469] = 108'o1511_3771_0003_7274_4007_0701_0000_0000_0425; CROM[1470] = 108'o1100_4443_0000_4174_4007_0700_0000_0000_0000; CROM[1471] = 108'o2700_1111_0701_4170_4007_0700_4000_0000_0000; CROM[1472] = 108'o1100_3333_0013_4174_4003_5701_0000_0000_0000; CROM[1473] = 108'o2714_3333_0005_4174_4467_0700_0000_0001_0004; CROM[1474] = 108'o1512_0551_1103_4374_4007_0701_0000_0000_0500; CROM[1475] = 108'o0770_3551_1313_4374_0007_0700_0000_0001_0000; CROM[1476] = 108'o1564_3333_0006_4175_5007_0701_0210_0000_0002; CROM[1477] = 108'o2706_4553_1000_4374_4007_0321_0000_0040_0000; CROM[1478] = 108'o2712_4521_1205_4074_4007_0700_0000_0000_0000; CROM[1479] = 108'o1513_3741_0105_4074_4007_0700_0000_0000_0000; CROM[1480] = 108'o1500_3441_0603_4174_4003_7700_0200_0003_0001; CROM[1481] = 108'o2703_1111_0701_4174_4007_0700_4000_0000_0000; CROM[1482] = 108'o1564_3333_0005_4175_5007_0701_0210_0000_0002; CROM[1483] = 108'o1563_3333_0001_4175_5007_0701_0200_0000_0002; CROM[1484] = 108'o0305_5551_1313_4374_4007_0700_0000_0001_0000; CROM[1485] = 108'o0435_4521_1203_4074_4007_0700_0000_0000_0000; CROM[1486] = 108'o0371_4713_1202_7174_4007_0700_0400_0000_0422; CROM[1487] = 108'o1044_0551_1504_0274_4407_0311_0200_0003_0712; CROM[1488] = 108'o0220_4443_0000_4174_4463_7700_0000_0001_2000; CROM[1489] = 108'o2722_3771_0005_4365_5007_0700_0200_0000_0002; CROM[1490] = 108'o1144_0551_0404_4374_4407_0311_0000_0077_7777; CROM[1491] = 108'o0220_3333_0005_4175_5003_7701_0200_0000_0002; CROM[1492] = 108'o2720_3333_0005_4175_5007_0701_0200_0000_0002; CROM[1493] = 108'o1146_0551_0404_4374_4407_0311_0000_0077_7777; CROM[1494] = 108'o1150_3771_0005_0276_6007_0521_0000_0000_0000; CROM[1495] = 108'o0764_3440_0505_0174_4467_0700_0400_0005_0000; CROM[1496] = 108'o2731_3443_0300_4174_4007_0700_0200_0003_0012; CROM[1497] = 108'o2732_3333_0005_4175_5007_0701_0200_0000_0002; CROM[1498] = 108'o1400_0551_0301_4370_4007_0701_0000_0000_0001; CROM[1499] = 108'o0130_3770_0304_4344_4007_0700_0000_0000_0000; CROM[1500] = 108'o2735_3770_0505_4344_4007_0700_0000_0000_0000; CROM[1501] = 108'o2736_3443_0500_4174_4007_0700_0200_0004_0012; CROM[1502] = 108'o0274_3771_0005_4365_5007_0700_0200_0000_0002; CROM[1503] = 108'o1156_4751_1204_4374_4007_0700_0000_0000_0424; CROM[1504] = 108'o2741_0111_1105_4174_4007_0700_0000_0000_0000; CROM[1505] = 108'o2742_4521_1203_4074_4007_0700_0000_0000_0000; CROM[1506] = 108'o1164_4553_0300_4374_4007_0321_0000_0000_0600; CROM[1507] = 108'o2744_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1508] = 108'o0764_3333_0003_4174_4467_0700_0000_0000_0404; CROM[1509] = 108'o0001_5551_0303_4374_0004_1700_0000_0000_0600; CROM[1510] = 108'o0002_0111_0704_4170_4004_1700_0200_0023_1016; CROM[1511] = 108'o2750_4551_0202_4374_0007_0700_0000_0077_7740; CROM[1512] = 108'o2751_3333_0002_4175_5007_0701_0200_0000_0002; CROM[1513] = 108'o2501_0111_0703_4170_4007_0700_0200_0004_0012; CROM[1514] = 108'o1170_3111_0503_4170_4007_0700_0000_0000_0000; CROM[1515] = 108'o1174_3770_0303_4174_0007_0520_0000_0000_0000; CROM[1516] = 108'o0021_3772_0000_0275_5007_0700_2000_0071_0043; CROM[1517] = 108'o1200_5113_0412_4174_4007_0621_0000_0000_0000; CROM[1518] = 108'o2757_3441_0316_4174_4007_0700_0000_0000_0000; CROM[1519] = 108'o0031_3771_0006_0276_6007_0700_2000_0071_0043; CROM[1520] = 108'o1204_3770_0303_4174_0007_0520_0000_0000_0000; CROM[1521] = 108'o2762_4117_0004_4174_4007_0700_0000_0000_0000; CROM[1522] = 108'o0120_3441_0405_4174_4007_0350_0000_0000_0000; CROM[1523] = 108'o0410_3227_0004_1174_4007_0700_0400_0000_1442; CROM[1524] = 108'o0410_3777_0016_1276_6007_0701_0000_0000_1441; CROM[1525] = 108'o0543_0111_1604_4174_4007_0700_0000_0000_0000; CROM[1526] = 108'o1210_3770_0404_0174_4007_0520_0400_0000_0000; CROM[1527] = 108'o2770_3772_0000_1275_5007_0701_0000_0000_1442; CROM[1528] = 108'o2771_7003_0000_1174_4007_0700_0400_0000_1442; CROM[1529] = 108'o2772_3772_0000_1275_5007_0701_0000_0000_1443; CROM[1530] = 108'o2773_7003_0000_1174_4007_0700_0400_0000_1443; CROM[1531] = 108'o1212_3741_0103_4074_4007_0520_0000_0000_0000; CROM[1532] = 108'o2775_4221_0004_4174_4007_0700_0000_0000_0000; CROM[1533] = 108'o2776_3442_0500_4174_4007_0700_2000_0071_0043; CROM[1534] = 108'o0563_3447_0606_4174_4007_0700_0000_0000_0000; CROM[1535] = 108'o2677_4443_0000_4174_4467_0700_0000_0003_0000; CROM[1536] = 108'o3001_3446_0606_4174_4007_0700_0000_0000_0000; CROM[1537] = 108'o0122_4226_0004_4174_4007_0630_2000_0060_0000; CROM[1538] = 108'o0122_3446_1200_4174_4007_0630_2000_0060_0000; CROM[1539] = 108'o1214_3772_0000_0275_5007_0520_0000_0000_0000; CROM[1540] = 108'o3005_3771_0003_0276_6007_0700_0000_0000_0000; CROM[1541] = 108'o3006_3772_0000_1275_5007_0701_0000_0000_1441; CROM[1542] = 108'o0160_3333_0003_4174_4007_0621_0000_0000_0000; CROM[1543] = 108'o3010_3221_0004_4174_4007_0700_0000_0000_0000; CROM[1544] = 108'o0330_3333_0003_4174_4007_0520_0000_0000_0000; CROM[1545] = 108'o1224_3447_0305_4174_4007_0421_0000_0000_0000; CROM[1546] = 108'o3013_3662_0000_4374_0007_0700_0000_0060_0000; CROM[1547] = 108'o3014_2222_0000_4174_4007_0700_4000_0000_0000; CROM[1548] = 108'o3016_2446_0505_4174_4047_0700_0040_0000_0000; CROM[1549] = 108'o3016_4751_1217_4374_4007_0700_0000_0000_0004; CROM[1550] = 108'o3017_3221_0006_0174_4007_0700_0000_0000_0000; CROM[1551] = 108'o0054_3777_0003_0274_4007_0520_0000_0000_0000; CROM[1552] = 108'o0354_4552_0000_1275_5007_0701_0000_0000_1442; CROM[1553] = 108'o3022_0002_1600_4174_4007_0700_0000_0000_0000; CROM[1554] = 108'o1242_4003_0000_1174_4007_0700_0400_0000_1440; CROM[1555] = 108'o0551_4552_0000_1275_5007_0701_0000_0000_1443; CROM[1556] = 108'o0056_3333_0017_4174_4003_5701_0000_0000_0000; CROM[1557] = 108'o3026_1772_0000_0274_4007_0701_0040_0000_0000; CROM[1558] = 108'o1244_3223_0000_0174_4007_0621_0400_0000_0000; CROM[1559] = 108'o3032_4113_1600_1174_4007_0700_0400_0000_1441; CROM[1560] = 108'o3031_3551_1616_4374_0007_0700_0000_0040_0000; CROM[1561] = 108'o3032_3440_1616_1174_4007_0700_0400_0000_1441; CROM[1562] = 108'o1246_3333_0003_4174_4007_0520_0000_0000_0000; CROM[1563] = 108'o3034_0111_0503_4174_4007_0700_0040_0000_0000; CROM[1564] = 108'o3035_0002_0600_4174_4007_0700_0000_0000_0000; CROM[1565] = 108'o3036_0111_0503_4174_4007_0700_0040_0000_0000; CROM[1566] = 108'o0355_3333_0017_4174_4003_5701_0000_0000_0000; CROM[1567] = 108'o3040_2444_0303_4174_4047_0700_0040_0000_0000; CROM[1568] = 108'o1250_0113_0303_1174_4007_0521_0400_0000_1442; CROM[1569] = 108'o0100_7003_0000_1174_4156_4700_0400_0000_1443; CROM[1570] = 108'o0001_3446_0303_4174_4044_1700_0000_0000_0000; CROM[1571] = 108'o1252_3333_0003_4174_4007_0520_0000_0000_0000; CROM[1572] = 108'o3045_3771_0004_4374_4007_0700_0000_0010_0000; CROM[1573] = 108'o1256_3333_0005_4174_4007_0520_0000_0000_0000; CROM[1574] = 108'o1256_3551_0404_4374_4007_0700_0000_0004_0000; CROM[1575] = 108'o3050_3447_0303_4174_4007_0700_0000_0000_0000; CROM[1576] = 108'o3051_3447_0505_4174_4007_0700_0000_0000_0000; CROM[1577] = 108'o3052_3447_0505_4174_4007_0700_0000_0000_0000; CROM[1578] = 108'o1260_1114_0503_4174_4067_0630_6000_0060_0000; CROM[1579] = 108'o1262_3447_0303_4174_4007_0520_0000_0000_0000; CROM[1580] = 108'o3055_3444_0303_4174_4007_0700_0000_0000_0000; CROM[1581] = 108'o3056_4002_1200_4174_4007_0700_0000_0000_0000; CROM[1582] = 108'o0014_3333_0004_4174_4000_1701_0000_0000_0000; CROM[1583] = 108'o1266_0115_0503_4174_4007_0630_2040_0060_0000; CROM[1584] = 108'o3061_1772_0000_1274_4007_0701_4000_0000_1443; CROM[1585] = 108'o1270_4003_0000_1174_4007_0621_0400_0000_1443; CROM[1586] = 108'o1272_4003_0000_1174_4007_0621_0400_0000_1442; CROM[1587] = 108'o1274_4003_0000_1174_4007_0621_0400_0000_1441; CROM[1588] = 108'o1272_4003_0000_1174_4007_0700_0400_0000_1442; CROM[1589] = 108'o1274_4003_0000_1174_4007_0700_0400_0000_1441; CROM[1590] = 108'o0024_3440_0303_0174_4004_1700_0400_0000_0000; CROM[1591] = 108'o3070_4551_0404_4374_0007_0700_0000_0037_7777; CROM[1592] = 108'o1276_2441_0404_4174_4007_0621_4000_0000_0000; CROM[1593] = 108'o1300_2441_0404_4174_4007_0621_4000_0000_0000; CROM[1594] = 108'o3073_3443_0400_4174_4007_0701_1000_0077_0000; CROM[1595] = 108'o0264_3771_0004_0276_6007_0700_0000_0000_0000; CROM[1596] = 108'o3075_0111_0703_4170_4007_0700_0200_0003_0002; CROM[1597] = 108'o0004_3333_0003_4175_5004_1701_0200_0000_0002; CROM[1598] = 108'o0070_4443_0000_2174_4006_6700_0000_0000_0000; CROM[1599] = 108'o0070_4443_0000_2174_4466_6700_0000_0003_0000; CROM[1600] = 108'o3076_3771_0003_4361_5217_0700_0200_0000_0502; CROM[1601] = 108'o0001_4551_1205_4365_5004_1700_0200_0000_0002; CROM[1602] = 108'o0002_4257_0503_4374_4004_1701_0000_0000_0376; CROM[1603] = 108'o3104_4221_0005_4174_0007_0700_1000_0031_0220; CROM[1604] = 108'o3105_3447_0505_4174_4007_0700_1020_0041_0010; CROM[1605] = 108'o3106_3333_0003_4174_4007_0700_1000_0031_7770; CROM[1606] = 108'o3107_4222_0000_4174_4007_0700_0000_0000_0000; CROM[1607] = 108'o3110_4224_0003_4174_4027_0700_1020_0041_0010; CROM[1608] = 108'o3111_4224_0003_4174_4027_0700_0000_0000_0000; CROM[1609] = 108'o0002_4001_0503_4174_4004_1700_0000_0000_0000; CROM[1610] = 108'o3113_3447_1200_4174_4007_0700_0200_0003_0002; CROM[1611] = 108'o0002_3333_0003_4175_5004_1701_0200_0000_0002; CROM[1612] = 108'o3115_4222_0000_4174_4007_0700_0000_0000_0000; CROM[1613] = 108'o3116_4224_0000_4174_4027_0700_1020_0041_0010; CROM[1614] = 108'o3117_4224_0000_4174_4027_0700_0000_0000_0000; CROM[1615] = 108'o3120_3333_0003_4174_4007_0701_1000_0073_0000; CROM[1616] = 108'o3121_4443_0000_4174_4007_0700_1000_0051_0770; CROM[1617] = 108'o3122_4002_1200_4174_4007_0700_1000_0031_0000; CROM[1618] = 108'o3123_3444_0404_4174_4007_0700_1020_0041_0010; CROM[1619] = 108'o3124_7221_0003_4174_4007_0700_0000_0000_0000; CROM[1620] = 108'o3125_4111_0503_4174_4007_0700_0000_0000_0000; CROM[1621] = 108'o3126_4001_0404_4174_4007_0700_0000_0000_0000; CROM[1622] = 108'o3112_3111_0403_4174_4007_0700_0000_0000_0000; CROM[1623] = 108'o1302_3770_0304_4344_4007_0700_2000_0071_0011; CROM[1624] = 108'o3131_3771_0004_4374_0007_0700_0000_0000_0000; CROM[1625] = 108'o3132_3333_0004_7174_4007_0700_0400_0000_0221; CROM[1626] = 108'o3133_4557_0305_4374_4007_0701_0000_0000_7700; CROM[1627] = 108'o3134_3770_0505_4344_4007_0700_2000_0071_0003; CROM[1628] = 108'o1304_4221_0005_4174_0007_0700_0000_0000_0000; CROM[1629] = 108'o3136_3772_0000_4370_4007_0700_0000_0000_0044; CROM[1630] = 108'o3137_1662_0000_7274_4007_0701_4000_0000_0221; CROM[1631] = 108'o3140_3771_0005_7274_4007_0701_0000_0000_0222; CROM[1632] = 108'o0664_4443_0000_4174_4007_0700_2000_0071_0042; CROM[1633] = 108'o3142_3771_0003_4374_4007_0700_0000_0077_7777; CROM[1634] = 108'o1310_0661_0005_7274_4007_0622_0000_0000_0224; CROM[1635] = 108'o1312_3333_0003_4174_4007_0421_0000_0000_0000; CROM[1636] = 108'o1312_0551_0303_7274_4007_0701_0000_0000_0226; CROM[1637] = 108'o3146_3441_0306_4174_4007_0700_2000_0071_0043; CROM[1638] = 108'o0062_3772_0000_7274_4007_0701_0000_0000_0222; CROM[1639] = 108'o3150_2555_0303_4374_4007_0701_4000_0000_0044; CROM[1640] = 108'o3151_3770_0303_4344_4007_0700_2000_0071_0011; CROM[1641] = 108'o1314_3771_0003_4370_4007_0700_0000_0000_0000; CROM[1642] = 108'o1400_3113_0305_0174_4007_0700_0400_0000_0000; CROM[1643] = 108'o1316_3770_0604_4344_4007_0700_0000_0000_0000; CROM[1644] = 108'o3155_2112_0306_4174_4007_0700_4000_0000_0000; CROM[1645] = 108'o3156_0001_0705_4174_4007_0700_0000_0000_0000; CROM[1646] = 108'o3157_3770_0505_4344_0007_0700_0000_0000_0000; CROM[1647] = 108'o3160_0551_0505_0274_4407_0701_0000_0000_0000; CROM[1648] = 108'o0002_3771_0013_4370_4004_1700_0000_0000_0001; CROM[1649] = 108'o1320_2113_0506_4174_4007_0331_4000_0000_0000; CROM[1650] = 108'o1322_3223_0000_4174_4007_0671_0200_0000_0002; CROM[1651] = 108'o1320_3772_0000_4365_5007_0700_0200_0000_0002; CROM[1652] = 108'o3165_3223_0000_4174_4007_0701_0200_0000_0002; CROM[1653] = 108'o1330_2113_0603_4174_4007_0521_4000_0000_0000; CROM[1654] = 108'o3163_0111_0704_4170_4007_0700_0200_0004_0712; CROM[1655] = 108'o3170_3770_0303_4344_4007_0700_0000_0000_0000; CROM[1656] = 108'o3171_3771_0003_7270_4007_0701_0000_0000_0214; CROM[1657] = 108'o1100_3440_0303_0174_4007_0700_0400_0000_0000; CROM[1658] = 108'o3173_3441_0503_4174_4007_0700_2000_0041_2000; CROM[1659] = 108'o3174_3441_0405_4174_4007_0700_2000_0020_0000; CROM[1660] = 108'o1332_3333_0003_4174_4007_0520_1000_0041_2000; CROM[1661] = 108'o1336_4222_0000_4174_4007_0630_2000_0060_0000; CROM[1662] = 108'o0163_3442_0300_4174_4007_0700_2000_0071_0033; CROM[1663] = 108'o3200_3441_0403_4174_4007_0700_1000_0041_0002; CROM[1664] = 108'o0420_3446_0303_4174_4003_4701_1000_0041_1600; CROM[1665] = 108'o3203_3441_0304_4174_4007_0700_1000_0031_0200; CROM[1666] = 108'o3203_2441_0304_4174_4007_0700_5000_0031_0200; CROM[1667] = 108'o1346_3445_0506_4174_4007_0520_0000_0000_0000; CROM[1668] = 108'o1363_4222_0000_4174_4007_0700_0000_0000_0000; CROM[1669] = 108'o1362_3446_0303_4174_4047_0700_2000_0071_0006; CROM[1670] = 108'o3207_4222_0000_0174_4007_0700_0000_0000_0000; CROM[1671] = 108'o1364_3771_0003_0276_6007_0520_1000_0040_2000; CROM[1672] = 108'o1366_4443_0000_4174_4007_0630_2000_0060_0000; CROM[1673] = 108'o1514_4221_0013_4174_4003_7700_0200_0003_0001; CROM[1674] = 108'o1637_2441_0303_4174_4007_0700_0040_0000_0000; CROM[1675] = 108'o2006_3777_0005_0274_4007_0521_2000_0020_2000; CROM[1676] = 108'o3220_0002_0400_4174_4007_0700_0000_0000_0000; CROM[1677] = 108'o3216_3442_0400_4174_4007_0700_2000_0020_0000; CROM[1678] = 108'o2014_3333_0016_4174_4007_0700_1000_0041_2000; CROM[1679] = 108'o3220_0002_0600_4174_4007_0700_0000_0000_0000; CROM[1680] = 108'o3221_0116_0503_4174_4047_0700_0040_0000_0000; CROM[1681] = 108'o0433_3444_0303_4174_4046_2700_0000_0000_0000; CROM[1682] = 108'o3223_3444_0303_4174_4047_0700_1000_0041_1777; CROM[1683] = 108'o3224_3444_0303_4174_4047_0700_1000_0041_1777; CROM[1684] = 108'o2027_3002_1700_4170_4007_0700_0000_0000_0000; CROM[1685] = 108'o3226_3444_1616_4174_4067_0700_0000_0000_0000; CROM[1686] = 108'o0472_3446_1616_4174_4047_0630_2000_0060_0000; CROM[1687] = 108'o0001_3446_1616_4174_4044_1700_0000_0000_0000; CROM[1688] = 108'o3231_4662_0000_4374_0007_0700_0000_0007_7777; CROM[1689] = 108'o3232_3221_0005_4174_4007_0700_0000_0000_0000; CROM[1690] = 108'o0623_4557_0006_1274_4007_0700_0000_0000_1441; CROM[1691] = 108'o3234_3227_0004_4174_4007_0700_2000_0011_0000; CROM[1692] = 108'o2022_3777_0006_0274_4007_0521_1000_0040_2000; CROM[1693] = 108'o1012_0111_1604_4174_4007_0700_0000_0000_0000; CROM[1694] = 108'o3237_3447_0705_4174_4007_0700_0000_0000_0000; CROM[1695] = 108'o2024_4553_1700_4374_4007_0321_0000_0020_0000; CROM[1696] = 108'o2026_4553_1700_4374_4007_0321_0000_0010_0000; CROM[1697] = 108'o3242_2441_0606_4174_4007_0700_4000_0000_0000; CROM[1698] = 108'o2030_2331_0005_1174_4007_0521_0040_0000_1441; CROM[1699] = 108'o2032_3777_0003_0274_4007_0521_1000_0030_2000; CROM[1700] = 108'o3245_3547_0303_4374_4007_0701_0000_0077_7400; CROM[1701] = 108'o3246_2442_0400_4174_4007_0700_4000_0000_0000; CROM[1702] = 108'o2035_2446_0303_4174_4047_0700_0040_0000_0000; CROM[1703] = 108'o0513_3444_1616_4174_4046_2700_0000_0000_0000; CROM[1704] = 108'o1515_4113_0400_1174_4007_0700_0400_0000_1441; CROM[1705] = 108'o2042_3223_0000_4174_4007_0621_0000_0000_0000; CROM[1706] = 108'o2046_4221_0013_4174_4007_0700_0000_0000_0000; CROM[1707] = 108'o2050_4221_0013_4174_4007_0700_0000_0000_0000; CROM[1708] = 108'o0100_4113_0400_1174_4156_4700_0400_0000_1441; CROM[1709] = 108'o2052_3223_0000_4174_4007_0621_0000_0000_0000; CROM[1710] = 108'o0002_4553_1300_4374_4004_1321_0000_0000_2000; CROM[1711] = 108'o3260_3111_0605_4174_0417_0700_0000_0000_0000; CROM[1712] = 108'o3261_3333_0005_4174_4217_0700_0000_0000_0500; CROM[1713] = 108'o3262_3333_0003_7174_4007_0700_0400_0000_0240; CROM[1714] = 108'o0170_4443_0000_2174_4006_6700_0000_0000_0000; CROM[1715] = 108'o3262_3771_0005_4361_5217_0700_0200_0000_0502; CROM[1716] = 108'o0574_3333_0003_7174_4003_7700_0400_0000_0242; CROM[1717] = 108'o3266_3333_0005_4174_4007_0700_1000_0041_6020; CROM[1718] = 108'o2070_4222_0000_4174_4006_7701_1000_0041_1770; CROM[1719] = 108'o0507_4113_0312_7174_4007_0700_0400_0000_0243; CROM[1720] = 108'o2074_3771_0005_1276_6007_0522_0000_0000_1443; CROM[1721] = 108'o3272_7771_0003_7274_4007_0701_0000_0000_0242; CROM[1722] = 108'o2076_3333_0005_4174_4007_0520_0000_0000_0000; CROM[1723] = 108'o1515_4221_0013_4170_4007_0700_0000_0000_0000; CROM[1724] = 108'o2100_3440_0303_1174_4007_0670_0400_0000_1441; CROM[1725] = 108'o2104_3440_0303_1174_4007_0700_0400_0000_1443; CROM[1726] = 108'o3274_0111_0703_4170_4007_0700_0000_0000_0000; CROM[1727] = 108'o3300_3333_0005_7174_4007_0700_0400_0000_0213; CROM[1728] = 108'o3301_3333_0004_7174_4007_0700_0400_0000_0212; CROM[1729] = 108'o2071_3333_0006_7174_4007_0700_0400_0000_0214; CROM[1730] = 108'o3303_3771_0005_7274_4007_0701_0000_0000_0213; CROM[1731] = 108'o3304_3771_0004_7274_4007_0701_0000_0000_0212; CROM[1732] = 108'o3274_3771_0006_7274_4007_0701_0000_0000_0214; CROM[1733] = 108'o3306_0111_0704_4174_4007_0700_0000_0000_0000; CROM[1734] = 108'o0540_3771_0013_4370_4007_0700_0000_0000_0003; CROM[1735] = 108'o3310_3113_0406_0174_4007_0700_0400_0000_0000; CROM[1736] = 108'o0252_4221_0013_4170_4007_0700_0000_0000_0000; CROM[1737] = 108'o1020_3333_0006_4174_4007_0520_0000_0000_0000; CROM[1738] = 108'o3313_3440_0606_0174_4007_0700_0400_0000_0000; CROM[1739] = 108'o3314_3771_0013_4370_4007_0700_0000_0000_0010; CROM[1740] = 108'o1030_3333_0004_4174_4007_0520_0000_0000_0000; CROM[1741] = 108'o3316_4111_1203_7174_4007_0700_0000_0000_0245; CROM[1742] = 108'o3317_4551_1205_7274_4007_0700_0000_0000_0245; CROM[1743] = 108'o3320_2111_0503_4174_4007_0700_4000_0000_0000; CROM[1744] = 108'o3321_1111_0704_4174_4007_0700_4000_0000_0000; CROM[1745] = 108'o3322_1111_0706_4174_4007_0700_4000_0000_0000; CROM[1746] = 108'o2116_3333_0003_4174_4007_0621_0000_0000_0000; CROM[1747] = 108'o3324_3771_0013_4370_4007_0700_0000_0000_0012; CROM[1748] = 108'o1030_3223_0000_7174_4007_0700_0400_0000_0245; CROM[1749] = 108'o3326_3333_0003_7174_4007_0700_0400_0000_0243; CROM[1750] = 108'o3327_3771_0003_0276_6007_0700_0000_0000_0000; CROM[1751] = 108'o2124_4521_0306_4374_4007_0700_0000_0077_7000; CROM[1752] = 108'o0460_7333_0003_7174_4007_0700_0400_0000_0242; CROM[1753] = 108'o2134_4553_0500_4374_4007_0321_0000_0076_0000; CROM[1754] = 108'o2136_3445_0505_1174_4007_0700_0000_0000_1444; CROM[1755] = 108'o0002_3440_0505_1174_4004_1700_0400_0000_1443; CROM[1756] = 108'o0004_0111_0705_4174_4004_1700_0000_0000_0000; CROM[1757] = 108'o3336_3111_0306_4174_4007_0700_0000_0000_0000; CROM[1758] = 108'o2143_1111_0701_4170_4007_0700_4000_0000_0000; CROM[1759] = 108'o2144_3771_0005_1276_6007_0522_0000_0000_1443; CROM[1760] = 108'o2146_3440_0303_1174_4007_0700_0400_0000_1444; CROM[1761] = 108'o3342_4551_0404_4374_0007_0700_0000_0037_7777; CROM[1762] = 108'o2150_2441_0404_1174_4007_0621_4000_0000_1443; CROM[1763] = 108'o2143_3440_0404_1174_4007_0700_0400_0000_1444; CROM[1764] = 108'o0001_4223_0000_1174_4004_1700_0400_0000_1444; CROM[1765] = 108'o3346_3771_0004_1276_6007_0701_0000_0000_1441; CROM[1766] = 108'o2125_3771_0003_0276_6007_0700_2000_0071_0024; CROM[1767] = 108'o2164_3551_0606_4374_0007_0700_0000_0004_0000; CROM[1768] = 108'o3351_3441_0605_4170_4007_0700_0000_0000_0000; CROM[1769] = 108'o2176_1111_0305_4174_4007_0421_4000_0000_0000; CROM[1770] = 108'o3353_3440_0303_1174_4007_0700_0400_0000_1443; CROM[1771] = 108'o3354_3771_0003_7274_4007_0701_0000_0000_0240; CROM[1772] = 108'o3355_0111_0703_4174_4007_0700_0200_0004_0012; CROM[1773] = 108'o3356_3771_0016_4365_5007_0700_0200_0000_0002; CROM[1774] = 108'o3357_3771_0013_4370_4007_0700_0000_0000_0012; CROM[1775] = 108'o3360_2113_0507_7174_4007_0701_4400_0000_0242; CROM[1776] = 108'o3361_3441_1603_7174_4007_0700_0000_0000_0242; CROM[1777] = 108'o0640_0551_0705_7274_4007_0521_0000_0000_0242; CROM[1778] = 108'o3360_3440_0505_1174_4007_0700_0400_0000_1443; CROM[1779] = 108'o3372_3771_0004_1276_6007_0701_0000_0000_1441; CROM[1780] = 108'o0636_0551_0503_7274_4003_7701_0000_0000_0241; CROM[1781] = 108'o3366_3771_0003_7274_4007_0701_0000_0000_0247; CROM[1782] = 108'o3367_3771_0004_7274_4007_0701_0000_0000_0250; CROM[1783] = 108'o2202_4553_0500_4374_4007_0321_0000_0004_0000; CROM[1784] = 108'o3371_3440_0404_1174_4007_0700_0400_0000_1441; CROM[1785] = 108'o3372_3440_0505_1174_4007_0700_0400_0000_1443; CROM[1786] = 108'o2204_1111_0706_4174_4007_0531_4000_0000_0000; CROM[1787] = 108'o1505_3771_0003_7274_4007_0701_0000_0000_0247; CROM[1788] = 108'o2203_5551_0505_4374_0007_0700_0000_0004_0000; CROM[1789] = 108'o3376_3333_0016_4174_4007_0700_0200_0000_0010; CROM[1790] = 108'o2220_1551_0303_6274_4007_0522_4000_0000_0000; CROM[1791] = 108'o3400_3333_0017_4174_4007_0700_0200_0000_0010; CROM[1792] = 108'o2222_0551_0404_6274_4007_0561_0000_0000_0000; CROM[1793] = 108'o3402_4221_0013_4170_4007_0700_0000_0000_0000; CROM[1794] = 108'o2224_3770_0605_4344_4007_0700_0000_0000_0000; CROM[1795] = 108'o2230_3447_0305_4174_4007_0700_2000_0071_0002; CROM[1796] = 108'o3405_7441_0605_4174_4007_0700_1000_0071_0010; CROM[1797] = 108'o3406_3441_0603_4174_4007_0701_1000_0043_0000; CROM[1798] = 108'o2234_4553_0500_4374_4007_0321_0000_0003_0000; CROM[1799] = 108'o3410_3223_0000_4174_4007_0701_0200_0000_0002; CROM[1800] = 108'o3423_3440_0303_1174_4007_0700_0400_0000_1444; CROM[1801] = 108'o0705_4251_0303_4374_4007_0700_0000_0007_7777; CROM[1802] = 108'o3413_3771_0005_1276_6007_0701_0000_0000_1443; CROM[1803] = 108'o3414_3443_0500_4174_4007_0700_0200_0003_0012; CROM[1804] = 108'o3415_3771_0005_1276_6007_0701_0000_0000_1444; CROM[1805] = 108'o2246_3333_0005_4175_5007_0701_0200_0000_0002; CROM[1806] = 108'o0007_3440_0606_0174_4004_1700_0400_0000_0000; CROM[1807] = 108'o3420_0551_0303_7274_4007_0701_0000_0000_0240; CROM[1808] = 108'o0001_3443_0300_4174_4004_1700_0200_0004_0012; CROM[1809] = 108'o3422_0115_0703_4174_4007_0700_0000_0000_0000; CROM[1810] = 108'o3424_3333_0003_4174_4007_0701_2000_0007_0000; CROM[1811] = 108'o3424_4443_0000_4174_4007_0700_2000_0071_0000; CROM[1812] = 108'o3425_3333_0006_4174_4007_0701_1000_0073_0000; CROM[1813] = 108'o3426_4443_0000_4174_4007_0700_1000_0051_0030; CROM[1814] = 108'o3427_4443_0000_4174_4007_0700_1000_0040_0000; CROM[1815] = 108'o3430_4443_0000_4174_4007_0700_1000_0041_0010; CROM[1816] = 108'o3431_3777_0003_4334_4057_0700_2000_0041_0000; CROM[1817] = 108'o2256_4251_0303_4374_4007_0630_0000_0000_0170; CROM[1818] = 108'o3433_3770_0303_4334_4017_0700_0000_0041_0000; CROM[1819] = 108'o3434_4551_0606_4374_0007_0700_0000_0070_0000; CROM[1820] = 108'o3435_4551_0303_4374_4007_0700_0000_0003_0000; CROM[1821] = 108'o3436_3111_0306_4174_0007_0700_0000_0000_0000; CROM[1822] = 108'o2115_3440_0606_0174_4007_0700_0400_0000_0000; CROM[1823] = 108'o2262_0113_0703_1174_4007_0521_0400_0000_1443; CROM[1824] = 108'o3441_0551_0303_7274_4007_0700_0000_0000_0241; CROM[1825] = 108'o0004_4553_0300_7274_4004_1622_0000_0000_0243; CROM[1826] = 108'o3443_0551_0303_7274_4007_0701_0000_0000_0241; CROM[1827] = 108'o2264_3333_0003_4174_4007_0700_0200_0004_0012; CROM[1828] = 108'o2272_3770_0303_1174_4007_0520_0400_0000_1443; CROM[1829] = 108'o0231_3770_0305_4334_4016_7701_0000_0033_6000; CROM[1830] = 108'o3447_0111_0703_4170_4007_0700_0000_0000_0000; CROM[1831] = 108'o2276_3440_0303_1174_4007_0700_0400_0000_1441; CROM[1832] = 108'o2300_3441_0304_4174_4007_0700_0000_0000_0000; CROM[1833] = 108'o2304_3770_0305_4334_4016_7701_0000_0033_6000; CROM[1834] = 108'o3453_0111_0703_4170_4217_0700_0000_0000_0600; CROM[1835] = 108'o0230_3440_0303_1174_4006_6701_1400_0073_1444; CROM[1836] = 108'o3455_3771_0003_4361_5217_0700_0200_0000_0602; CROM[1837] = 108'o0230_4443_0000_2174_4006_6700_0000_0000_0000; CROM[1838] = 108'o3457_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1839] = 108'o0010_3333_0003_7174_4004_1700_0400_0000_0244; CROM[1840] = 108'o0001_4551_0303_4374_0004_1700_0000_0000_0777; CROM[1841] = 108'o3462_3771_0003_7274_4007_0701_0000_0000_0214; CROM[1842] = 108'o2310_0113_0703_0174_4007_0701_0400_0000_0000; CROM[1843] = 108'o3464_1771_0003_7274_4007_0701_4000_0000_0242; CROM[1844] = 108'o2312_3771_0005_1276_6007_0522_0000_0000_1443; CROM[1845] = 108'o2700_3440_0303_1174_4007_0700_0400_0000_1443; CROM[1846] = 108'o3470_0111_0503_4174_4007_0700_0000_0000_0000; CROM[1847] = 108'o3470_1771_0003_7274_4007_0701_4000_0000_0242; CROM[1848] = 108'o3471_3551_0303_7274_4007_0701_0000_0000_0214; CROM[1849] = 108'o2700_3440_0303_0174_4007_0700_0400_0000_0000; CROM[1850] = 108'o3464_7771_0003_7274_4007_0701_0000_0000_0242; CROM[1851] = 108'o0001_3770_0305_4334_4014_1700_0000_0043_6000; CROM[1852] = 108'o3475_3741_0104_4074_4007_0700_0000_0000_0000; CROM[1853] = 108'o2316_3333_0004_7174_4007_0340_0400_0000_0425; CROM[1854] = 108'o3477_3771_0002_4365_5617_0700_0200_0000_0002; CROM[1855] = 108'o2320_4553_0200_4374_4007_0321_0000_0070_0000; CROM[1856] = 108'o3501_4251_0505_4374_4007_0700_0000_0000_7770; CROM[1857] = 108'o0260_4113_0305_4174_4007_0330_0000_0000_0000; CROM[1858] = 108'o0136_4251_0505_4374_4007_0700_0000_0000_7770; CROM[1859] = 108'o3504_5551_0505_4370_4007_0700_0000_0000_0007; CROM[1860] = 108'o3505_4551_0304_4374_4007_0700_0000_0000_0007; CROM[1861] = 108'o3506_3111_0405_4174_4007_0700_0000_0000_0000; CROM[1862] = 108'o3507_4551_0304_4374_4007_0700_0000_0000_7760; CROM[1863] = 108'o2322_4553_0300_4374_4007_0331_0000_0010_0000; CROM[1864] = 108'o2326_4553_0300_4374_4007_0331_0000_0002_0000; CROM[1865] = 108'o3512_3333_0005_4174_4257_0700_0000_0000_0000; CROM[1866] = 108'o1400_3333_0005_7174_4007_0700_0400_0000_0230; CROM[1867] = 108'o3514_3333_0006_4174_4237_0700_0000_0000_0000; CROM[1868] = 108'o3515_5551_0606_4370_4007_0700_0000_0000_2000; CROM[1869] = 108'o2333_3333_0006_4174_4237_0700_0000_0000_0000; CROM[1870] = 108'o3517_3770_0505_4344_0007_0700_0000_0000_0000; CROM[1871] = 108'o3520_4551_0505_4374_0007_0700_0000_0000_7760; CROM[1872] = 108'o3521_4551_0505_4370_4007_0700_0000_0000_0007; CROM[1873] = 108'o3522_3771_0004_4304_4007_0701_0000_0000_0000; CROM[1874] = 108'o3523_4251_0404_4374_4007_0700_0000_0000_7770; CROM[1875] = 108'o3613_3111_0405_4174_4007_0700_0000_0000_0000; CROM[1876] = 108'o2334_3771_0003_4365_5007_0521_0200_0000_0002; CROM[1877] = 108'o3526_4551_0303_4374_0007_0700_0000_0050_7700; CROM[1878] = 108'o2336_4553_0300_4374_4007_0321_0000_0010_0000; CROM[1879] = 108'o2340_4221_0005_4174_0007_0700_2000_0071_0007; CROM[1880] = 108'o3531_4221_0011_4170_4007_0700_0000_0000_0000; CROM[1881] = 108'o3532_3111_0511_4174_4007_0700_0000_0000_0000; CROM[1882] = 108'o2406_3111_0311_4174_0477_0700_0000_0000_0000; CROM[1883] = 108'o3534_4551_0505_4370_4007_0700_0000_0074_7777; CROM[1884] = 108'o2344_4553_0300_4374_4007_0321_0000_0000_0020; CROM[1885] = 108'o3536_3333_0005_7174_4007_0700_0400_0000_0230; CROM[1886] = 108'o3537_3441_0310_4174_4007_0700_0000_0000_0000; CROM[1887] = 108'o2346_4553_1000_4374_4007_0321_0000_0000_0040; CROM[1888] = 108'o3613_4221_0005_4174_0007_0700_0000_0000_0000; CROM[1889] = 108'o3542_4551_1105_4374_0007_0700_0000_0050_7700; CROM[1890] = 108'o2354_3447_1106_4174_4007_0700_2000_0071_0006; CROM[1891] = 108'o0001_3441_0605_4170_4004_1700_0000_0000_0000; CROM[1892] = 108'o3545_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1893] = 108'o1400_3333_0003_7174_4007_0700_0400_0000_0215; CROM[1894] = 108'o3547_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1895] = 108'o1400_3333_0003_7174_4007_0700_0400_0000_0216; CROM[1896] = 108'o3551_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1897] = 108'o1400_3333_0003_7174_4007_0700_0400_0000_0220; CROM[1898] = 108'o3553_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1899] = 108'o1400_3333_0003_7174_4007_0700_0400_0000_0217; CROM[1900] = 108'o3555_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1901] = 108'o1400_3333_0003_7174_4007_0700_0400_0000_0227; CROM[1902] = 108'o2737_4551_0202_4374_0007_0700_0000_0077_7740; CROM[1903] = 108'o0004_4443_0000_4174_4004_1700_0000_0000_0000; CROM[1904] = 108'o3561_3771_0003_7274_4117_0701_0000_0000_0301; CROM[1905] = 108'o3562_4751_1205_4374_4007_0700_0000_0001_0000; CROM[1906] = 108'o3563_0111_0503_4174_4007_0700_0000_0000_0000; CROM[1907] = 108'o2356_3770_0303_4174_0007_0520_0000_0000_0000; CROM[1908] = 108'o3565_3771_0003_7274_4007_0701_0000_0000_0303; CROM[1909] = 108'o2360_1111_0503_4174_4007_0421_4000_0000_0000; CROM[1910] = 108'o3567_3771_0005_4304_4007_0701_0000_0000_0000; CROM[1911] = 108'o3570_3551_0505_4374_4007_0700_0000_0000_0040; CROM[1912] = 108'o2360_3333_0005_4174_4237_0700_0000_0000_0000; CROM[1913] = 108'o1114_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1914] = 108'o0002_3333_0003_7174_4004_1700_0400_0000_0300; CROM[1915] = 108'o3574_4451_1204_4324_4007_0700_0000_0000_0000; CROM[1916] = 108'o3575_4451_1206_4324_4007_0700_0000_0000_0000; CROM[1917] = 108'o2362_6113_0405_4174_4007_0621_0000_0000_0000; CROM[1918] = 108'o1120_0551_0404_7274_4007_0671_0000_0000_0301; CROM[1919] = 108'o3600_3333_0005_4175_5007_0701_0200_0000_0002; CROM[1920] = 108'o3601_0111_0702_4170_4007_0700_0200_0003_0012; CROM[1921] = 108'o1400_3333_0004_4175_5007_0701_0200_0000_0002; CROM[1922] = 108'o3603_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1923] = 108'o3604_3333_0003_7174_4007_0700_0400_0000_0302; CROM[1924] = 108'o1400_3333_0003_7174_4007_0700_0400_0000_0303; CROM[1925] = 108'o3606_3770_0505_4344_0007_0700_0000_0000_0000; CROM[1926] = 108'o2370_4553_0300_4374_4007_0331_0000_0002_0000; CROM[1927] = 108'o3610_3770_1416_4344_4007_0700_0000_0000_0000; CROM[1928] = 108'o3611_2441_0716_4170_4007_0700_4000_0000_0000; CROM[1929] = 108'o3612_4111_1416_4174_4007_0700_0000_0000_0000; CROM[1930] = 108'o0010_7443_1600_4174_4434_1700_0000_0000_0000; CROM[1931] = 108'o3614_3443_0300_4174_4007_0700_0200_0003_0012; CROM[1932] = 108'o1400_3333_0005_4175_5007_0701_0200_0000_0002; CROM[1933] = 108'o2402_4221_0003_4174_4007_0700_0000_0000_0000; CROM[1934] = 108'o2404_3333_0003_4174_4247_0700_0000_0000_1000; CROM[1935] = 108'o2410_3333_0003_4174_4347_0700_0000_0000_1000; CROM[1936] = 108'o1400_4223_0000_7174_4007_0700_0400_0000_0423; CROM[1937] = 108'o0001_4443_0000_4174_4004_1700_2000_0071_0375; CROM[1938] = 108'o3631_4751_1206_4374_4007_0700_0000_0000_0001; CROM[1939] = 108'o3631_4751_1206_4374_4007_0700_0000_0000_0002; CROM[1940] = 108'o3631_4751_1206_4374_4007_0700_0000_0000_0003; CROM[1941] = 108'o3631_4751_1206_4374_4007_0700_0000_0000_0004; CROM[1942] = 108'o3631_4751_1206_4374_4007_0700_0000_0000_0005; CROM[1943] = 108'o3631_4751_1206_4374_4007_0700_0000_0000_0006; CROM[1944] = 108'o3631_4751_1206_4374_4007_0700_0000_0000_0007; CROM[1945] = 108'o3632_4251_1403_4374_4007_0700_0000_0007_7577; CROM[1946] = 108'o3633_7443_0300_4174_4437_0700_0000_0000_0000; CROM[1947] = 108'o2412_4223_0000_4364_4277_0700_0200_0000_0010; CROM[1948] = 108'o3635_0551_0303_4370_4007_0701_0000_0000_0040; CROM[1949] = 108'o3636_0111_1003_4174_4007_0700_0000_0000_0000; CROM[1950] = 108'o3637_3443_0300_4174_4007_0700_0200_0024_1016; CROM[1951] = 108'o3640_3771_0003_4365_5007_0701_0200_0020_0012; CROM[1952] = 108'o2416_6553_0300_4374_4007_0321_0000_0025_4340; CROM[1953] = 108'o0060_4223_0000_4174_4467_0700_0000_0000_0004; CROM[1954] = 108'o2422_3445_0303_4174_4007_0530_0000_0000_0000; CROM[1955] = 108'o2430_3771_0005_4365_5007_0331_0200_0000_0002; CROM[1956] = 108'o3645_3447_0606_4174_4007_0700_0000_0000_0000; CROM[1957] = 108'o3637_0111_0605_4174_4007_0700_0200_0024_0012; CROM[1958] = 108'o2434_4113_0514_4174_4007_0330_0000_0000_0000; CROM[1959] = 108'o2446_3441_0603_4174_4007_0700_0000_0000_0000; CROM[1960] = 108'o2450_3113_0304_4174_4007_0701_0200_0000_0036; CROM[1961] = 108'o2460_4553_0600_4374_4007_0321_0000_0070_0000; CROM[1962] = 108'o3653_3333_0002_4174_4217_0700_0000_0000_0000; CROM[1963] = 108'o2464_4553_0200_4374_4007_0321_0000_0000_0017; CROM[1964] = 108'o0001_3771_0003_4365_5124_1700_0200_0000_0002; CROM[1965] = 108'o0001_4221_0003_4174_0124_1700_0000_0000_0000; CROM[1966] = 108'o1124_3771_0016_4354_4007_0650_2000_0071_0200; CROM[1967] = 108'o2470_4443_0000_4174_4007_0650_2000_0071_0777; CROM[1968] = 108'o0001_3771_0003_4365_5004_1700_0200_0000_0002; CROM[1969] = 108'o0001_3771_0004_4365_5004_1700_0200_0000_0002; CROM[1970] = 108'o0001_3772_0000_4365_5004_1700_0200_0000_0002; CROM[1971] = 108'o0001_4221_0004_4174_0004_1700_0000_0000_0000; CROM[1972] = 108'o0001_0111_0703_4174_4004_1700_0000_0000_0000; CROM[1973] = 108'o0001_3445_0505_4174_4004_1700_0000_0000_0000; CROM[1974] = 108'o0001_3443_0300_4174_4004_1701_0200_0000_0036; CROM[1975] = 108'o0004_3333_0005_4175_5004_1701_0200_0000_0002; CROM[1976] = 108'o0001_3333_0001_4175_5004_1701_0200_0000_0002; CROM[1977] = 108'o0001_3440_0404_0174_4004_1700_0400_0000_0000; CROM[1978] = 108'o1515_3771_0003_4365_5007_0700_0200_0000_0002; CROM[1979] = 108'o1516_3771_0003_0276_6007_0700_0000_0000_0000; CROM[1980] = 108'o2474_3333_0017_4175_5007_0701_0200_0000_0002; CROM[1981] = 108'o2502_3771_0004_7274_4007_0422_0000_0000_0227; CROM[1982] = 108'o3677_3771_0004_4354_4007_0700_0000_0000_0000; CROM[1983] = 108'o0010_3333_0004_7174_4004_1700_0400_0000_0210; CROM[1984] = 108'o2504_3333_0004_4174_4007_0700_0200_0021_1016; CROM[1985] = 108'o2505_0111_0704_4170_4007_0700_0200_0023_1016; CROM[1986] = 108'o2514_0111_0704_4170_4007_0700_0200_0023_1016; CROM[1987] = 108'o2515_0111_0704_4170_4007_0700_0200_0023_1016; CROM[1988] = 108'o2520_0111_0704_4170_4007_0700_0200_0023_1016; CROM[1989] = 108'o2521_0111_0704_4170_4007_0700_0200_0023_1016; CROM[1990] = 108'o2524_0111_0704_4170_4007_0700_0200_0023_1016; CROM[1991] = 108'o3710_3771_0003_7274_4007_0701_0000_0000_0211; CROM[1992] = 108'o3711_3771_0004_7274_4007_0701_0000_0000_0210; CROM[1993] = 108'o3712_3443_0400_4174_4007_0700_0200_0000_0010; CROM[1994] = 108'o0006_3771_0004_7274_4004_1701_0000_0000_0212; CROM[1995] = 108'o3714_3771_0006_4354_4007_0700_0000_0000_0000; CROM[1996] = 108'o3715_4551_0606_4374_0007_0700_0000_0040_0000; CROM[1997] = 108'o3716_3333_0006_7174_4007_0700_0400_0000_0210; CROM[1998] = 108'o3717_3771_0005_7274_4007_0701_0000_0000_0230; CROM[1999] = 108'o2530_4553_0500_4374_4007_0331_0000_0003_0000; CROM[2000] = 108'o3721_3333_0006_7174_4007_0700_0400_0000_0214; CROM[2001] = 108'o3722_3771_0006_4354_4007_0700_0000_0000_0000; CROM[2002] = 108'o3723_3333_0006_7174_4007_0700_0400_0000_0210; CROM[2003] = 108'o1060_3333_0004_7174_4007_0370_0400_0000_0212; CROM[2004] = 108'o3725_3333_0006_7174_4007_0700_0400_0000_0160; CROM[2005] = 108'o3726_3333_0006_7174_4007_0700_0400_0000_0161; CROM[2006] = 108'o1501_4571_1206_4374_4007_0700_0000_0036_0000; CROM[2007] = 108'o3730_4223_0000_4364_4277_0700_0200_0000_0010; CROM[2008] = 108'o3731_3551_1313_4374_0007_0700_0000_0002_4000; CROM[2009] = 108'o2532_4553_0600_4374_4007_0321_0000_0002_0000; CROM[2010] = 108'o3733_6551_0606_4374_0007_0700_0000_0000_1000; CROM[2011] = 108'o2534_3441_0605_4174_4007_0700_2000_0071_0007; CROM[2012] = 108'o2536_4553_1000_4374_4007_0321_0000_0000_0040; CROM[2013] = 108'o3736_3443_0300_4174_4007_0700_0200_0024_1016; CROM[2014] = 108'o1000_3771_0003_4365_5007_0700_0200_0000_0002; CROM[2015] = 108'o2572_4553_1300_4374_4007_0321_0000_0002_0000; CROM[2016] = 108'o2061_3771_0004_1276_6007_0701_0000_0000_1443; CROM[2017] = 108'o3456_0111_0703_4170_4007_0700_0210_0004_0012; CROM[2018] = 108'o3325_4571_1203_4374_4007_0700_0000_0077_7777; CROM[2019] = 108'o2156_3771_0006_1276_6007_0351_0000_0000_1443; CROM[2020] = 108'o3456_0111_0703_4174_4007_0700_0210_0004_0012; CROM[2021] = 108'o2576_4553_0600_4374_4007_0321_0000_0001_0000; CROM[2022] = 108'o3747_4221_0013_4170_4007_0700_0000_0000_0000; CROM[2023] = 108'o3750_3551_0606_4374_0007_0700_0000_0010_0000; CROM[2024] = 108'o2614_4553_1300_4374_4007_0321_0000_0000_4000; CROM[2025] = 108'o2111_3771_0006_0276_6007_0700_0000_0000_0000; CROM[2026] = 108'o1500_3111_0603_4174_4003_7700_0200_0003_0001; CROM[2027] = 108'o3755_3441_0305_4174_4007_0700_0000_0000_0000; CROM[2028] = 108'o2060_3771_0005_1276_6007_0701_0000_0000_1443; CROM[2029] = 108'o3756_5551_0305_4374_0007_0700_0000_0007_0000; CROM[2030] = 108'o3757_3443_0500_4174_4007_0701_0200_0000_0030; CROM[2031] = 108'o3760_4251_0404_4374_4007_0700_0000_0000_3777; CROM[2032] = 108'o3761_3551_0406_4374_4007_0700_0000_0040_0000; CROM[2033] = 108'o2616_4553_1300_4374_4007_0321_0000_0002_0000; CROM[2034] = 108'o3763_3771_0004_7274_4007_0701_0000_0000_0212; CROM[2035] = 108'o3764_3771_0005_7274_4007_0701_0000_0000_0213; CROM[2036] = 108'o3765_3771_0006_7274_4007_0701_0000_0000_0214; CROM[2037] = 108'o3766_3443_0300_4174_4007_0701_0200_0000_0032; CROM[2038] = 108'o0000_3771_0003_7274_4004_1701_0000_0000_0211; CROM[2039] = 108'o3770_3551_0304_4374_4007_0700_0000_0075_3777; CROM[2040] = 108'o3771_4111_0413_4174_0007_0700_0000_0000_0000; CROM[2041] = 108'o2630_3333_0003_4174_4007_0520_0000_0000_0000; CROM[2042] = 108'o2640_3443_0300_4174_4007_0370_0200_0024_1016; CROM[2043] = 108'o2644_4553_0300_4374_4007_0321_0000_0002_4000; CROM[2044] = 108'o2646_3333_0006_4174_4007_0520_0000_0000_0000; CROM[2045] = 108'o3776_3771_0004_4365_5007_0700_0200_0000_0002; CROM[2046] = 108'o2654_4553_0500_4374_4007_0331_0000_0000_0001; CROM[2047] = 108'o3720_3333_0003_7174_4007_0700_0400_0000_0211; Dist/rtl/ks10/cpu/useq/crom.v0000700000175100010010000001334012151540224014412 0ustar RobNone//////////////////////////////////////////////////////////////////// //! //! KS-10 Processor //! //! \brief //! Microcontroller Control ROM (CROM) //! //! \details //! The Control ROM contains the executable microcode of the //! the microcontroller. //! //! \note //! Although all of the microcontroller addressing supports //! 12-bit addresses (4096 words of ROM) the Control ROM only //! implements 2048 words of ROM. //! //! The current microcode uses all of the ROM except for //! about 25 words. //! //! Implementing 4096 words of ROM would all double the amount //! of microcode and allow for feature growth. //! //! \note //! The contents of this file was extracted from the microcode //! listing file by a simple AWK script. Go see the makefile. //! //! \file //! crom.v //! //! \author //! Rob Doyle - doyle (at) cox (dot) net //! //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "crom.vh" module CROM(clk, rst, clken, addr, crom); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [0:11] addr; // Address output reg [0:cromWidth-1] crom; // Output Data // // Control ROM initialization // // Note: // The KS10 microcode is extracted from the listing file by // a 'simple' AWK script and is included below. // reg [0:cromWidth-1] CROM[0:2047]; initial begin `include "crom.dat" end // // Control ROM // // Details: // The Control ROM stores the microcode. // // Note: // The KS10 only implemented half of the microcode. Therefore // the MSB of the address is ignored. If you need more than // 2048 words of microcode, you can simply add more ROM. See // notes at top-of-file. // // The KS10 used asynchronous ROM followed by a 108-bit wide // register. This register has been absorbed into this // synchronous ROM implementation. // // Trace: // Registers // CRA6/E2, CRA6/E46, CRA6/E67, CRA6/E86, CRA6/E87, CRA6/E104 // Address buffers: // CRA7/E5, CRA7/E6, CRA7/E10, CRA7/E11, CRA7/E19, CRA7/E20 // CRA7/E68, CRA7/E80, CRA7/E93, CRA7/E94, CRA7/E100, CRA7/E106 // ROMS: // CRA8/E8, CRA8/E13, CRA8/E14, CRA8/E22, CRA8/E23, CRA8/E28, // CRA8/E29, CRA8/E37, CRA8/E38, CRA8/E40, CRA8/E41, CRA8/E49, // CRA8/E50, CRA8/E52, CRA8/E53, CRA8/E60, CRA8/E61, CRA8/E63, // CRA8/E64, CRA8/E71, CRA8/E72, CRA8/E74, CRA8/E75, CRA8/E83, // CRA8/E109, CRA8/E117, CRA8/E120, CRA8/E126, CRA8/E134, CRA8/E142, // CRA8/E146, CRA8/E154, CRA8/E157, CRA8/E166, CRA8/E169, CRA8/E178, // // CRA9/E7, CRA9/E12, CRA9/E21, CRA9/E27, CRA9/E36, CRA9/E39, // CRA9/E48, CRA9/E51, CRA9/E59, CRA9/E62, CRA9/E70, CRA9/E73, // CRA9/E102, CRA9/E108, CRA9/E116, CRA9/E119, CRA9/E125, CRA9/E133, // CRA9/E141, CRA9/E145, CRA9/E153, CRA9/E156, CRA9/E165, CRA9/E168, // CRA9/E101, CRA9/E107, CRA9/E115, CRA9/E118, CRA9/E124, CRA9/E132, // CRA9/E140, CRA9/E144, CRA9/E152, CRA9/E155, CRA9/E164, CRA9/E167, // // CRM4/E7, CRM4/E14, CRM4/E19, CRM4/E33, CRM4/E40, CRM4/E45, // CRM4/E52, CRM4/E56, CRM4/E82, CRM4/E89, CRM4/E94, CRM4/E101, // CRM4/E105, CRM4/E117, CRM4/E127, CRM4/E132, CRM4/E133, CRM4/E140, // CRM4/E147, CRM4/E152, CRM4/E159, CRM4/E184, CRM4/E191, CRM4/E198, // // CRM5/E6, CRM5/E13, CRM5/E18, CRM5/E39, CRM5/E44, CRM5/E51, // CRM5/E70, CRM5/E74, CRM5/E81, CRM5/E88, CRM5/E100, CRM5/E104, // CRM5/E112, CRM5/E116, CRM5/E126, CRM5/E139, CRM5/E146, CRM5/E151, // CRM5/E158, CRM5/E165, CRM5/E178, CRM5/E183, CRM5/E190, CRM5/E197, // // CRM6/E5, CRM6/E12, CRM6/E17, CRM6/E31, CRM6/E38, CRM6/E43, // CRM6/E50, CRM6/E54, CRM6/E60, CRM6/E73, CRM6/E80, CRM6/E87, // CRM6/E103, CRM6/E107, CRM6/E125, CRM6/E138, CRM6/E145, CRM6/E150, // CRM6/E157, CRM6/E164, CRM6/E170, CRM6/E182, CRM6/E189, CRM6/E196, // // CRM7/E4, CRM7/E11, CRM7/E16, CRM7/E23, CRM7/E42, CRM7/E49, // CRM7/E59, CRM7/E62, CRM7/E68, CRM7/E72, CRM7/E79, CRM7/E93, // CRM7/E98, CRM7/E102, CRM7/E110, CRM7/E114, CRM7/E137, CRM7/E144, // CRM7/E156, CRM7/E163, CRM7/E176, CRM7/E181, CRM7/E188, CRM7/E195, // always @(posedge clk) begin if (clken) crom <= CROM[addr[1:11]]; end endmodule Dist/rtl/ks10/cpu/useq/crom.vh0000700000175100010010000004635312151540222014572 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Control ROM (CROM) Definitions // // Details // This file contains the Control ROM microcode field // definitions. // // Include it everywhere you need to access the Control ROM. // // File // crom.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __CROM_VH `define __CROM_VH `define CROM_WIDTH 108 // CROM Width // // Control ROM Fields // `define cromJ crom[0:11] // Jump address // // ALU Functions // See LSRC and RSRC (below) for definition of R and S // `define cromFUN crom[12:14] // ALU Function `define cromFUN_ADD 3'b000 // F <- R + S `define cromFUN_SUBR 3'b001 // F <- R - S `define cromFUN_SUBS 3'b010 // F <- S - R `define cromFUN_ORRS 3'b011 // F <- R | S `define cromFUN_ANDRS 3'b100 // F <- R & S `define cromFUN_NOTRS 3'b101 // F <- ~R & S `define cromFUN_EXOR 3'b110 // F <- R ^ S `define cromFUN_EXNOR 3'b111 // F <- ~(R ^ S) // // ALU Sources (Left and Right) // `define cromLSRC crom[15:17] // ALU Left Source `define cromRSRC crom[18:20] // ALU Right Source `define cromSRC_AQ 3'b000 // R <- A, S <- Q `define cromSRC_AB 3'b001 // R <- A, S <- B `define cromSRC_ZQ 3'b010 // R <- 0, S <- Q `define cromSRC_ZB 3'b011 // R <- 0, S <- B `define cromSRC_ZA 3'b100 // R <- 0, S <- A `define cromSRC_DA 3'b101 // R <- D, S <- A `define cromSRC_DQ 3'b110 // R <- D, S <- Q `define cromSRC_DZ 3'b111 // R <- D, S <- 0 // // ALU Destinations // The shift operation are controlled by the cromSPEC_SHSTYLE field // `define cromDST crom[21:23] // ALU Destinations `define cromDST_QREG 3'b000 // RAM <- RAM, Q <- F `define cromDST_NOP 3'b001 // RAM <- RAM, Q <- Q `define cromDST_RAMA 3'b010 // RAM <- A, Q <- Q `define cromDST_RAMF 3'b011 // RAM <- F, Q <- Q `define cromDST_RAMQD 3'b100 // RAM <- F shifted right, Q <- Q shifted right `define cromDST_RAMD 3'b101 // RAM <- F shifted right, Q <- Q `define cromDST_RAMQU 3'b110 // RAM <- F shifted left, Q <- Q shifted left `define cromDST_RAMU 3'b111 // RAM <- F shifted left, Q <- Q // // ALU Register Selection // `define cromALU_A crom[26:29] // ALU A Address `define cromALU_B crom[32:35] // ALU B Address // // RAMFILE Address // `define cromRAMADDR_SEL crom[36:38] // RAMFILE address mux `define cromRAMADDR_SEL_AC 3'b000 // AC `define cromRAMADDR_SEL_ACOPNUM 3'b001 // AC OP # `define cromRAMADDR_SEL_XR 3'b010 // XR `define cromRAMADDR_SEL_SPARE3 3'b011 // Not used `define cromRAMADDR_SEL_VMA 3'b100 // `define cromRAMADDR_SEL_SPARE5 3'b101 // Not used `define cromRAMADDR_SEL_RAM 3'b110 // `define cromRAMADDR_SEL_NUM 3'b111 // Number Field // // DBUS // `define cromDBUS_SEL crom[40:41] // DBUS MUX Select `define cromDBUS_SEL_FLAGS 2'b00 // PC Flags `define cromDBUS_SEL_DP 2'b01 // Datapath `define cromDBUS_SEL_RAMFILE 2'b10 // RAM file `define cromDBUS_SEL_DBM 2'b11 // DBM Mux // // DBM // `define cromDBM_SEL crom[42:44] // DBM Select `define cromDBM_SEL_SCADPFAPR 3'b000 // SCAD,PF DISP, APR `define cromDBM_SEL_BYTES 3'b001 // BYTES `define cromDBM_SEL_EXPTIME 3'b010 // EXP, TIMER `define cromDBM_SEL_DP 3'b011 // DP `define cromDBM_SEL_DPSWAP 3'b100 // DP swapped `define cromDBM_SEL_VMA 3'b101 // VMA flags, VMA `define cromDBM_SEL_MEM 3'b110 // Memory bus `define cromDBM_SEL_NUM 3'b111 // CROM Number field // // Clock enables // `define cromLCLKEN crom[45] // ALU Left Clock Enable `define cromRCLKEN crom[48] // ALU Right Clock Enable // // SPEC Field // `define cromSPEC crom[51:56] // SPEC Fields `define cromSPEC_EN_40 crom[51] // SPEC Select 40 `define cromSPEC_EN_20 crom[52] // SPEC Select 20 `define cromSPEC_EN_10 crom[53] // SPEC Select 10 `define cromSPEC_SEL crom[54:56] // SPEC Select `define cromSPEC_SEL_CONS 3'b000 // 10: Console `define cromSPEC_SEL_PREVIOUS 3'b000 // 20: Force Previous Context `define cromSPEC_SEL_CRY18INH 3'b000 // 40: Inhibit Carry into Left Half `define cromSPEC_SEL_CLR1MSEC 3'b001 // 10: CLR Interval Timer `define cromSPEC_SEL_LOADXR 3'b001 // 20: Load XR `define cromSPEC_SEL_LOADIR 3'b001 // 40: Load IR `define cromSPEC_SEL_CLRIOLAT 3'b010 // 10: Clear IO Latch `define cromSPEC_SEL_SPARE20_2 3'b010 // 20: Spare `define cromSPEC_SEL_SPARE10_2 3'b010 // 40: Spare `define cromSPEC_SEL_CLRIOBUSY 3'b011 // 10: Clear IO Busy `define cromSPEC_SEL_APRFLAGS 3'b011 // 20: Load APR Flags `define cromSPEC_SEL_LOADPI 3'b011 // 40: Load PI `define cromSPEC_SEL_PAGEWRITE 3'b100 // 10: PAGE WRITE `define cromSPEC_SEL_CLRCACHE 3'b100 // 20: Clear/Sweep cache `define cromSPEC_SEL_ASHTEST 3'b100 // 40: ASH Test `define cromSPEC_SEL_LOADNICOND 3'b101 // 10: Load NICOND `define cromSPEC_SEL_LOADAPR 3'b101 // 20: Load APR `define cromSPEC_SEL_EXPTEST 3'b101 // 40: EXP Test `define cromSPEC_SEL_PXCTEN 3'b110 // 10: Enable PXCT `define cromSPEC_SEL_PXCTOFF 3'b110 // 20: Turn off PXCT `define cromSPEC_SEL_PCFLAGS 3'b110 // 40: Load PC FLAGS `define cromSPEC_SEL_MEMWAIT 3'b111 // 10: Mem Wait `define cromSPEC_SEL_MEMCLR 3'b111 // 20: Mem Clear `define cromSPEC_SEL_LOADACBLK 3'b111 // 40: Load AC Block `define cromSPEC_SHSTYLE crom[54:56] // Shift Style `define cromSPEC_SHSTYLE_NORM 3'b000 // NORMAL `define cromSPEC_SHSTYLE_ZERO 3'b001 // ZERO `define cromSPEC_SHSTYLE_ONES 3'b010 // ONES `define cromSPEC_SHSTYLE_ROT 3'b011 // ROT `define cromSPEC_SHSTYLE_ASHC 3'b100 // ASHC `define cromSPEC_SHSTYLE_LSHC 3'b101 // LSHC `define cromSPEC_SHSTYLE_DIV 3'b110 // DIV `define cromSPEC_SHSTYLE_ROTC 3'b111 // ROTC `define cromSPEC_SELBYTE crom[54:56] // Byte Select `define cromSPEC_SELBYTE_1 3'b001 // Byte Select Byte 1 `define cromSPEC_SELBYTE_2 3'b010 // Byte Select Byte 2 `define cromSPEC_SELBYTE_3 3'b011 // Byte Select Byte 3 `define cromSPEC_SELBYTE_4 3'b100 // Byte Select Byte 4 `define cromSPEC_SELBYTE_5 3'b101 // Byte Select Byte 5 // // Displacement Select // `define cromDISP crom[57:62] // DISP Fields `define cromDISP_EN_40 (~crom[57]) // DISP Select 40 (active low in microcode) `define cromDISP_EN_20 (~crom[58]) // DISP Select 20 (active low in microcode) `define cromDISP_EN_10 (~crom[59]) // DISP Select 10 (active low in microcode) `define cromDISP_SELH crom[61:62] // DISP Select (high 4 bits) `define cromDISP_SELH_DIAG 2'b00 // Diagnostic Dispatch `define cromDISP_SELH_RET 2'b01 // Return Dispatch `define cromDISP_SELH_J 2'b10 // DROM J Dispatch `define cromDISP_SELH_AREAD 2'b11 // DROM AREAD Dispatch `define cromDISP_SEL crom[60:62] // DISP Select (low 8 bits) `define cromDISP_SEL_DIAG 3'b000 // Diagnostic Dispatch `define cromDISP_SEL_RET 3'b001 // Return Dispatch `define cromDISP_SEL_MULTIPLY 3'b010 // Multiply Dispatch `define cromDISP_SEL_PAGEFAIL 3'b011 // Page Fail Dispatch `define cromDISP_SEL_NICOND 3'b100 // Next Instruction Dispatch `define cromDISP_SEL_BYTE 3'b101 // Byte Dispatch `define cromDISP_SEL_EAMODE 3'b110 // EA Mode Dispatch `define cromDISP_SEL_SCAD 3'b111 // SCAD Dispatch `define cromDISP_SEL_ZERO 3'b000 // No Dispatch (NOP) `define cromDISP_SEL_DP18TO21 3'b001 // DP[18:21] Dispatch `define cromDISP_SEL_J 3'b010 // DROM J Dispatch `define cromDISP_SEL_AREAD 3'b011 // DROM AREAD Dispatch `define cromDISP_SEL_NORM 3'b100 // Normailze Dispatch `define cromDISP_SEL_DP32TO35 3'b101 // DP[32:35] Dispatch `define cromDISP_SEL_DROMA 3'b110 // DROM A Dispatch `define cromDISP_SEL_DROMB 3'b111 // DROM B Dispatch // // Skip Select // `define cromSKIP crom[63:68] // SKIP Fields `define cromSKIP_EN_40 (~crom[63]) // SKIP Select 40 (active low in microcode) `define cromSKIP_EN_20 (~crom[64]) // SKIP Select 20 (active low in microcode) `define cromSKIP_EN_10 (~crom[65]) // SKIP Select 10 (active low in microcode) `define cromSKIP_SEL crom[66:68] // SKIP Select // // Misc Bits // `define cromT crom[69:71] // Microinstruction cycle length `define cromCRY38 crom[72] // Insert a carry into the LSB of the ALU `define cromLOADSC crom[73] // Load Step Counter from SCAD `define cromLOADFE crom[74] // Load FE Register from SCAD `define cromFMWRITE crom[75] // Write to RAMFILE `define cromMEM_CYCLE crom[76] // Start/complete a memory or IO cycle using # field `define cromDIVIDE crom[77] // Microinstruction is doing a divide `define cromMULTIPREC crom[78] // Multiprecision step (Divide, DFAD, DFSB) `define cromMULTISHIFT crom[79] // Fast Shift (repeat until FE overflows) `define cromCALL crom[80] // Save current micro sequencer address on stack // // SCAD // Note: Only the ALU OPs that are actually used are implemented. // `define cromSCAD_FUN crom[90:92] // SCAD ALU OP `define cromSCAD_A_PLUS_A 3'b000 // A + A `define cromSCAD_A_OR_B 3'b001 // A | B `define cromSCAD_A_MINUS_B_1 3'b010 // A - B - 1 `define cromSCAD_A_MINUS_B 3'b011 // A - B `define cromSCAD_A_PLUS_B 3'b100 // A + B `define cromSCAD_A_AND_B 3'b101 // A & B `define cromSCAD_A_MINUS_1 3'b110 // A - 1 `define cromSCAD_A 3'b111 // A `define cromSCAD_ASEL crom[93:95] // SCAD A MUX Select `define cromSCAD_ASEL_SC 3'b000 // Step Counter `define cromSCAD_ASEL_SNUM 3'b001 // Small Number field `define cromSCAD_ASEL_PTR44 3'b010 // 044 `define cromSCAD_ASEL_BYTE1 3'b011 // DP[ 0: 6] `define cromSCAD_ASEL_BYTE2 3'b100 // DP[ 7:13] `define cromSCAD_ASEL_BYTE3 3'b101 // DP[14:20] `define cromSCAD_ASEL_BYTE4 3'b110 // DP[21:28] `define cromSCAD_ASEL_BYTE5 3'b111 // DP[28:34] `define cromSCAD_BSEL crom[96:97] // SCAD B MUX Select `define cromSCAD_BSEL_FE 2'b00 // FE `define cromSCAD_BSEL_EXP 2'b01 // EXP `define cromSCAD_BSEL_SHIFT 2'b10 // Shift `define cromSCAD_BSEL_SIZE 2'b11 // DP[6:11] `define cromSNUM crom[98:107] // Small Number field (10-bit) for SCAD // // Number Field // `define cromNUM crom[90:107] // Immediate Data // // State Field // Overloaded with Number Field // `define cromSTATE crom[90:107] // State Definition // // Memory Cycle Control // Overloaded with Number Field // `define cromMEM_FORCEUSER crom[90] // Force user mode reference `define cromMEM_FORCEEXEC crom[91] // Force exec mode reference `define cromMEM_FETCHCYCLE crom[92] // This is an instruction fetch cycle `define cromMEM_READCYCLE crom[93] // This is a read cycle `define cromMEM_WRTESTCYCLE crom[94] // Page Fail if not written `define cromMEM_WRITECYCLE crom[95] // This is a write cycle `define cromMEM_CACHEINH crom[97] // Don't lock in cache `define cromMEM_PHYSICAL crom[98] // Don't invoke paging hardare `define cromMEM_PXCTSEL crom[99:101] // Which PXCT bits to look at `define cromMEM_AREAD crom[102] // Let DROM select cycle type and VMA load `define cromMEM_DPFUNC crom[103] // Use dp[0:13] instead of cromNUM[0:13] `define cromMEM_CYCLE_SEL crom[102:103] // See above. Select Cycle type as a group. `define cromMEM_LOADVMA crom[104] // Load the VMA `define cromMEM_EXTADDR crom[105] // Put VMA[14:17] Bits onto Bus `define cromMEM_WAIT crom[106] // Start memory or IO cycle `define cromMEM_BWRITE crom[107] // Start memory cycle if DROM asks for it // These are only defined when cromMEM_DPFUNC (bit 103) is asserted `define cromMEM_IOCYCLE crom[100] // This is an IO cycle `define cromMEM_WRUCYCLE crom[101] // This is a WRU cycle `define cromMEM_VECTORCYCLE crom[102] // This is a read vector interrupt cycle `define cromMEM_IOBYTECYCLE crom[103] // This is a byte cycle // // Flag Manipulation // Overloaded with Number Field // `define cromSETOV crom[90] // Set arithmetic overflow `define cromSETFOV crom[91] // Set floating point overflow `define cromSETNODIV crom[92] // Set no divide `define cromCLRFPD crom[93] // Clear first part done `define cromSETFPD crom[94] // Set first part done `define cromHOLDUSER crom[95] // Do not update USER `define cromSPARE1 crom[96] // Spare `define cromSETTRAP2 crom[97] // Set trap 2 `define cromSETTRAP1 crom[98] // Set trap 1 `define cromSETPCU crom[99] // Set PCU `define cromSPARE2 crom[100] // Spare `define cromSPARE3 crom[101] // Spare `define cromSPARE4 crom[102] // Spare `define cromSPARE5 crom[103] // Spare `define cromJFCLFLAGS crom[104] // JFCL instruction `define cromLDFLAGS crom[105] // Load flags from DP bus `define cromSPARE6 crom[106] // Spare `define cromADFLAGS crom[107] // Update Carry Flags // // AC Math // // // MICROCODE // BIT -> 98 99 100 101 102 103 104 105 105 106 // +-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ // |CARRY| S8 | S4 | S2 | S1 | MODE| B8 | B4 | B2 | B1 | // | IN | FUNCTION | | DATA INPUTS | // +-----+-----------------------+-----+-----------------------+ // `define cromACALU_FUN crom[98:103] // AC ALU Function `define cromACALU_NUM crom[104:107] // AC ALU Number `define cromACALU_FUN_NUM 6'o25; // NUM `define cromACALU_FUN_ADDAC 6'o62; // AC + NUM // // Priority Interrupt (PI) bits // Overloaded with Number Field // `define cromPI_ZER crom[90:92] // (Not used) `define cromPI_IP1 crom[93] // PI 1 in progress `define cromPI_IP2 crom[94] // PI 2 in progress (Not used) `define cromPI_IP3 crom[95] // PI 3 in progress (Not used) `define cromPI_IP4 crom[96] // PI 4 in progress (Not used) `define cromPI_IP5 crom[97] // PI 5 in progress (Not used) `define cromPI_IP6 crom[98] // PI 6 in progress (Not used) `define cromPI_IP7 crom[99] // PI 7 in progress (Not used) `define cromPI_ON crom[100] // PI is on `define cromPI_CO11 crom[101] // Chan 1 is on (Not used) `define cromPI_CO12 crom[102] // Chan 2 is on (Not used) `define cromI_CO3 crom[103] // (Not used) `define cromI_CO4 crom[104] // (Not used) `define cromI_CO5 crom[105] // (Not used) `define cromI_CO6 crom[106] // (Not used) `define cromI_CO7 crom[107] // (Not used) // // Console Interface // Overloaded with Number Field // This usage is not very well documented in the microcode listing. // See "SET HALT", "CLEAR CONTINUE", "CLEAR EXECUTE", "CLEAR RUN" // and "UNHALT" macros in the microcode listing. // `define cromCONS_CLR_CONT crom[102] // Clear Continue `define cromCONS_CLR_EXEC crom[103] // Clear Execute `define cromCONS_CLR_RUN crom[104] // Clear Run `define cromCONS_SET_HALT crom[105] // Set Halt `define cromCONS_CLR_HALT crom[106] // Clear Halt `define cromCONS_UNUSED107 crom[107] // Not used // // Workspace Address Field // Overloaded with Number Field // `define cromWORK crom[98:107] // Workspace Address // // DT Field // `define cromDT crom[109:111] // Not used `endif Dist/rtl/ks10/cpu/useq/dispatch.v0000700000175100010010000001450312151540224015253 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Microcontroller Dispatch Logic // // Details // // File // disp.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "crom.vh" module DISPATCH(crom, dp, dispDIAG, dispRET, dispJ, dispAREAD, dispMUL, dispPF, dispNI, dispBYTE, dispEA, dispSCAD, dispNORM, dispDROM_A, dispDROM_B, dispADDR); parameter cromWidth = `CROM_WIDTH; input [0:cromWidth-1] crom; // Control ROM Data input [0:35] dp; // Datapath Dispatch input [0:11] dispDIAG; // Diagnostic dispatch input [0:11] dispRET; // Microcode return dispatch input [0:11] dispJ; // Jump dispatch input [0:11] dispAREAD; // Address Read dispatch input [8:11] dispMUL; // Multiply Dispatch input [8:11] dispPF; // Page Fail Dispatch input [8:11] dispNI; // Next Instruction Dispatch input [8:11] dispBYTE; // Byte Size/Position Dispatch input [8:11] dispEA; // Effective Address Mode Dispatch input [8:11] dispSCAD; // SCAD Dispatch input [8:11] dispNORM; // Normalize Dispatch input [8:11] dispDROM_A; // DROM A Dispatch input [8:11] dispDROM_B; // DROM B Dispatch output reg [0:11] dispADDR; // Dispatch Addr // // Microcode aliases // wire dispEN10 = `cromDISP_EN_10; wire dispEN20 = `cromDISP_EN_20; wire dispEN40 = `cromDISP_EN_40; wire [0:1] dispSELH = `cromDISP_SELH; wire [0:2] dispSEL = `cromDISP_SEL; // // Control ROM Dispatch Address // // Details // The micro-machine provides many mechanisms to perform an // N-way dispatch based on conditions. // // This supplies the dispatch address when a dispatch is // required. // // Note: // Like the skip function, the dispatch function can only // set bits in the microcode address. It cannot clear // bits. // always @(dispDIAG or dispRET or dispJ or dispAREAD or dispMUL or dispPF or dispNI or dispBYTE or dispEA or dispSCAD or dispNORM or dispDROM_A or dispDROM_B or dispEN40 or dispEN20 or dispEN10 or dispSEL or dispSELH or dp) begin // // Default dispatch if none of the data selectors // are activated. // dispADDR[0:11] = 12'b000_000_000_000; // // Dispatch Address Select MSBs // CRA1/E69 // CRA1/E68 // CRA1/E151 // CRA1/E138 // if (dispEN20) begin case (dispSELH) `cromDISP_SELH_DIAG: dispADDR[0:7] = dispDIAG[0:7]; `cromDISP_SELH_RET: dispADDR[0:7] = dispRET[0:7]; `cromDISP_SELH_J: dispADDR[0:7] = dispJ[0:7]; `cromDISP_SELH_AREAD: dispADDR[0:7] = dispAREAD[0:7]; endcase end // // Dispatch Address Select LSBs // CRA1/E158 // CRA1/E170 // CRA1/E171 // CRA1/E182 // if (dispEN10) begin case (dispSEL) `cromDISP_SEL_DIAG: dispADDR[8:11] = dispDIAG[8:11]; `cromDISP_SEL_RET: dispADDR[8:11] = dispRET[8:11]; `cromDISP_SEL_MULTIPLY: dispADDR[8:11] = dispMUL[8:11]; `cromDISP_SEL_PAGEFAIL: dispADDR[8:11] = dispPF[8:11]; `cromDISP_SEL_NICOND: dispADDR[8:11] = dispNI[8:11]; `cromDISP_SEL_BYTE: dispADDR[8:11] = dispBYTE[8:11]; `cromDISP_SEL_EAMODE: dispADDR[8:11] = dispEA[8:11]; `cromDISP_SEL_SCAD: dispADDR[8:11] = dispSCAD[8:11]; endcase end // // Dispatch Address Select LSBs // DPEA/E132 // DPEA/E138 // DPEA/E146 // DPEA/E160 // if (dispEN40) begin case (dispSEL) `cromDISP_SEL_ZERO: dispADDR[8:11] = 4'b0; `cromDISP_SEL_DP18TO21: dispADDR[8:11] = dp[18:21]; `cromDISP_SEL_J: dispADDR[8:11] = dispJ[8:11]; `cromDISP_SEL_AREAD: dispADDR[8:11] = dispAREAD[8:11]; `cromDISP_SEL_NORM: dispADDR[8:11] = dispNORM[8:11]; `cromDISP_SEL_DP32TO35: dispADDR[8:11] = dp[32:35]; `cromDISP_SEL_DROMA: dispADDR[8:11] = dispDROM_A; `cromDISP_SEL_DROMB: dispADDR[8:11] = dispDROM_B; endcase end end endmodule Dist/rtl/ks10/cpu/useq/drom.awk0000700000175100010010000000142612151540234014733 0ustar RobNoneBEGIN { FS="[, ; ]"; printf "//\n"; printf "//\n"; printf "// DROM.DAT\n"; printf "// This code is extracted from the KS10 microcode listing by an\n"; printf "// AWK script. DO NOT EDIT THIS FILE!\n"; printf "//\n"; printf "//\n"; printf "\n"; } /D [0-7][0-7][0-7][0-7], / { #print $2 " " $4 " " $5 " " $6 i = strtonum("0" $2) MAP2[i] = $2; MAP[4,i] = $4; MAP[5,i] = $5; MAP[6,i] = $6; } END { for (i = 0; i < 512; i++) { if (strtonum("0" MAP2[i]) == i) { printf " DROM[%3d] = 36'o%s_%s_%s;\n", i, MAP[ 4,i], MAP[ 5,i], MAP[ 6,i] } else { printf " DROM[%3d] <= 36'o%s_%s_%s; // Unused\n", i, "0000", "0000", "0000" } } } Dist/rtl/ks10/cpu/useq/drom.dat0000700000175100010010000005020112151540234014714 0ustar RobNone// // // DROM.DAT // This code is extracted from the KS10 microcode listing by an // AWK script. DO NOT EDIT THIS FILE! // // DROM[ 0] = 36'o0000_1556_2100; DROM[ 1] = 36'o0001_1740_2100; DROM[ 2] = 36'o0002_1740_2100; DROM[ 3] = 36'o0003_1740_2100; DROM[ 4] = 36'o0002_1741_2100; DROM[ 5] = 36'o0005_1740_2100; DROM[ 6] = 36'o0006_1740_2100; DROM[ 7] = 36'o0007_1740_2100; DROM[ 8] = 36'o0001_1742_2100; DROM[ 9] = 36'o0004_1742_2100; DROM[ 10] = 36'o0001_1743_2100; DROM[ 11] = 36'o0000_1743_2100; DROM[ 12] = 36'o0001_1744_2100; DROM[ 13] = 36'o0000_1744_2100; DROM[ 14] = 36'o0002_1744_2100; DROM[ 15] = 36'o0003_1744_2100; DROM[ 16] = 36'o0000_1746_2100; DROM[ 17] = 36'o0000_1747_2100; DROM[ 18] = 36'o0000_1750_2100; DROM[ 19] = 36'o0000_1751_2100; DROM[ 20] = 36'o0001_1751_2100; DROM[ 21] = 36'o0002_1751_2100; DROM[ 22] = 36'o0004_1751_2100; DROM[ 23] = 36'o0010_1751_2100; DROM[ 24] = 36'o0000_1557_2100; DROM[ 25] = 36'o0001_1557_2100; DROM[ 26] = 36'o0002_1557_2100; DROM[ 27] = 36'o0003_1557_2100; DROM[ 28] = 36'o0004_1557_2100; DROM[ 29] = 36'o0005_1557_2100; DROM[ 30] = 36'o0006_1557_2100; DROM[ 31] = 36'o0007_1557_2100; DROM[ 32] = 36'o0000_1556_2100; DROM[ 33] = 36'o0000_1556_2100; DROM[ 34] = 36'o0000_1556_2100; DROM[ 35] = 36'o0000_1556_2100; DROM[ 36] = 36'o0000_1556_2100; DROM[ 37] = 36'o0000_1556_2100; DROM[ 38] = 36'o0000_1556_2100; DROM[ 39] = 36'o0000_1556_2100; DROM[ 40] = 36'o0000_1556_2100; DROM[ 41] = 36'o0000_1556_2100; DROM[ 42] = 36'o0000_1556_2100; DROM[ 43] = 36'o0000_1556_2100; DROM[ 44] = 36'o0000_1556_2100; DROM[ 45] = 36'o0000_1556_2100; DROM[ 46] = 36'o0000_1556_2100; DROM[ 47] = 36'o0000_1556_2100; DROM[ 48] = 36'o0000_1556_2100; DROM[ 49] = 36'o0000_1556_2100; DROM[ 50] = 36'o0000_1556_2100; DROM[ 51] = 36'o0000_1556_2100; DROM[ 52] = 36'o0000_1556_2100; DROM[ 53] = 36'o0000_1556_2100; DROM[ 54] = 36'o0000_1556_2100; DROM[ 55] = 36'o0000_1556_2100; DROM[ 56] = 36'o0000_1556_2100; DROM[ 57] = 36'o0000_1556_2100; DROM[ 58] = 36'o0000_1556_2100; DROM[ 59] = 36'o0000_1556_2100; DROM[ 60] = 36'o0000_1556_2100; DROM[ 61] = 36'o0000_1556_2100; DROM[ 62] = 36'o0000_1556_2100; DROM[ 63] = 36'o0000_1556_2100; DROM[ 64] = 36'o0000_1556_2100; DROM[ 65] = 36'o0000_1661_2100; DROM[ 66] = 36'o0000_1662_2100; DROM[ 67] = 36'o0000_1663_2100; DROM[ 68] = 36'o0000_1664_2100; DROM[ 69] = 36'o0000_1551_3000; DROM[ 70] = 36'o0000_1666_2100; DROM[ 71] = 36'o0000_1667_2100; DROM[ 72] = 36'o1100_1637_1100; DROM[ 73] = 36'o1100_1635_1100; DROM[ 74] = 36'o1105_1631_1100; DROM[ 75] = 36'o1105_1636_1100; DROM[ 76] = 36'o0205_1457_1100; DROM[ 77] = 36'o0205_1615_1100; DROM[ 78] = 36'o0205_1566_1100; DROM[ 79] = 36'o0205_1627_1100; DROM[ 80] = 36'o0205_1505_1100; DROM[ 81] = 36'o0215_1434_1100; DROM[ 82] = 36'o0701_1626_1100; DROM[ 83] = 36'o0000_1467_3100; DROM[ 84] = 36'o0300_1567_0100; DROM[ 85] = 36'o0100_1565_0500; DROM[ 86] = 36'o0711_1626_1100; DROM[ 87] = 36'o0011_1616_1100; DROM[ 88] = 36'o0000_1660_2100; DROM[ 89] = 36'o0001_1660_2100; DROM[ 90] = 36'o0001_1621_2100; DROM[ 91] = 36'o0015_1610_1100; DROM[ 92] = 36'o0000_1620_1500; DROM[ 93] = 36'o0000_1624_1100; DROM[ 94] = 36'o0000_1630_1500; DROM[ 95] = 36'o0000_1634_1100; DROM[ 96] = 36'o0701_1577_1100; DROM[ 97] = 36'o0002_1660_2100; DROM[ 98] = 36'o0702_1577_1700; DROM[ 99] = 36'o0703_1577_1700; DROM[100] = 36'o0711_1577_1100; DROM[101] = 36'o0611_1577_0100; DROM[102] = 36'o0712_1577_1700; DROM[103] = 36'o0713_1577_1700; DROM[104] = 36'o0701_1576_1100; DROM[105] = 36'o0003_1660_2100; DROM[106] = 36'o0702_1576_1700; DROM[107] = 36'o0703_1576_1700; DROM[108] = 36'o0711_1576_1100; DROM[109] = 36'o0611_1576_0100; DROM[110] = 36'o0712_1576_1700; DROM[111] = 36'o0713_1576_1700; DROM[112] = 36'o0701_1570_1100; DROM[113] = 36'o0004_1660_2100; DROM[114] = 36'o0702_1570_1700; DROM[115] = 36'o0703_1570_1700; DROM[116] = 36'o0711_1570_1100; DROM[117] = 36'o0611_1570_0100; DROM[118] = 36'o0712_1570_1700; DROM[119] = 36'o0713_1570_1700; DROM[120] = 36'o0701_1574_1100; DROM[121] = 36'o0005_1660_2100; DROM[122] = 36'o0702_1574_1700; DROM[123] = 36'o0703_1574_1700; DROM[124] = 36'o0711_1574_1100; DROM[125] = 36'o0611_1574_0100; DROM[126] = 36'o0712_1574_1700; DROM[127] = 36'o0713_1574_1700; DROM[128] = 36'o1015_1515_1100; DROM[129] = 36'o0015_1515_3000; DROM[130] = 36'o0116_1404_0700; DROM[131] = 36'o0004_1504_1700; DROM[132] = 36'o1015_1402_1100; DROM[133] = 36'o0015_1402_3000; DROM[134] = 36'o0116_1402_0700; DROM[135] = 36'o0004_1402_1700; DROM[136] = 36'o1015_1405_1100; DROM[137] = 36'o0015_1405_3000; DROM[138] = 36'o0116_1405_0700; DROM[139] = 36'o0004_1405_1700; DROM[140] = 36'o1015_1403_1100; DROM[141] = 36'o0015_1515_3000; DROM[142] = 36'o0116_1403_0700; DROM[143] = 36'o0004_1403_1700; DROM[144] = 36'o1015_1641_1100; DROM[145] = 36'o0015_1641_3000; DROM[146] = 36'o0016_1641_1700; DROM[147] = 36'o0017_1641_1700; DROM[148] = 36'o1005_1571_1100; DROM[149] = 36'o0005_1571_3000; DROM[150] = 36'o0016_1571_1700; DROM[151] = 36'o0006_1571_1700; DROM[152] = 36'o1005_1600_1100; DROM[153] = 36'o0005_1600_3000; DROM[154] = 36'o0016_1600_1700; DROM[155] = 36'o0006_1600_1700; DROM[156] = 36'o1005_1601_1100; DROM[157] = 36'o0005_1601_3000; DROM[158] = 36'o0016_1601_1700; DROM[159] = 36'o0006_1601_1700; DROM[160] = 36'o0400_1622_1000; DROM[161] = 36'o0400_1632_1000; DROM[162] = 36'o0400_1612_1000; DROM[163] = 36'o0000_1462_2100; DROM[164] = 36'o0000_1466_3000; DROM[165] = 36'o0500_1470_1000; DROM[166] = 36'o0500_1464_1000; DROM[167] = 36'o0000_1665_2100; DROM[168] = 36'o0015_1406_1500; DROM[169] = 36'o0000_1640_2100; DROM[170] = 36'o0005_1547_2100; DROM[171] = 36'o0001_1547_2100; DROM[172] = 36'o0000_1520_6000; DROM[173] = 36'o0000_1540_2100; DROM[174] = 36'o0000_1541_1100; DROM[175] = 36'o1215_1553_0100; DROM[176] = 36'o0000_1544_2100; DROM[177] = 36'o0002_1543_3100; DROM[178] = 36'o0002_1545_2100; DROM[179] = 36'o0000_1546_2100; DROM[180] = 36'o0000_1552_2100; DROM[181] = 36'o0000_1550_2100; DROM[182] = 36'o0000_1554_2100; DROM[183] = 36'o0000_1555_2100; DROM[184] = 36'o1015_1560_1100; DROM[185] = 36'o0015_1560_3000; DROM[186] = 36'o0016_1560_1700; DROM[187] = 36'o0017_1560_1700; DROM[188] = 36'o1015_1561_1100; DROM[189] = 36'o0015_1561_3000; DROM[190] = 36'o0016_1561_1700; DROM[191] = 36'o0017_1561_1700; DROM[192] = 36'o0000_1400_2100; DROM[193] = 36'o0001_1476_2100; DROM[194] = 36'o0002_1476_2100; DROM[195] = 36'o0003_1476_2100; DROM[196] = 36'o0004_1476_2100; DROM[197] = 36'o0005_1476_2100; DROM[198] = 36'o0006_1476_2100; DROM[199] = 36'o0007_1476_2100; DROM[200] = 36'o0000_1476_1100; DROM[201] = 36'o0001_1476_1100; DROM[202] = 36'o0002_1476_1100; DROM[203] = 36'o0003_1476_1100; DROM[204] = 36'o0004_1476_1100; DROM[205] = 36'o0005_1476_1100; DROM[206] = 36'o0006_1476_1100; DROM[207] = 36'o0007_1476_1100; DROM[208] = 36'o0000_1400_2100; DROM[209] = 36'o0001_1440_2100; DROM[210] = 36'o0002_1440_2100; DROM[211] = 36'o0003_1440_2100; DROM[212] = 36'o0004_1520_2100; DROM[213] = 36'o0005_1440_2100; DROM[214] = 36'o0006_1440_2100; DROM[215] = 36'o0007_1440_2100; DROM[216] = 36'o0000_1477_1100; DROM[217] = 36'o0001_1477_1100; DROM[218] = 36'o0002_1477_1100; DROM[219] = 36'o0003_1477_1100; DROM[220] = 36'o0004_1477_1100; DROM[221] = 36'o0005_1477_1100; DROM[222] = 36'o0006_1477_1100; DROM[223] = 36'o0007_1477_1100; DROM[224] = 36'o0000_1611_3000; DROM[225] = 36'o0001_1611_2100; DROM[226] = 36'o0002_1611_2100; DROM[227] = 36'o0003_1611_2100; DROM[228] = 36'o0004_1611_2100; DROM[229] = 36'o0005_1611_2100; DROM[230] = 36'o0006_1611_2100; DROM[231] = 36'o0007_1611_2100; DROM[232] = 36'o0000_1431_1500; DROM[233] = 36'o0001_1431_1500; DROM[234] = 36'o0002_1431_1500; DROM[235] = 36'o0003_1431_1500; DROM[236] = 36'o0004_1431_1500; DROM[237] = 36'o0005_1431_1500; DROM[238] = 36'o0006_1431_1500; DROM[239] = 36'o0007_1431_1500; DROM[240] = 36'o0000_1542_3000; DROM[241] = 36'o0001_1542_2100; DROM[242] = 36'o0002_1542_2100; DROM[243] = 36'o0003_1542_2100; DROM[244] = 36'o0004_1542_2100; DROM[245] = 36'o0005_1542_2100; DROM[246] = 36'o0006_1542_2100; DROM[247] = 36'o0007_1542_2100; DROM[248] = 36'o0000_1437_1500; DROM[249] = 36'o0001_1437_1500; DROM[250] = 36'o0002_1437_1500; DROM[251] = 36'o0003_1437_1500; DROM[252] = 36'o0004_1437_1500; DROM[253] = 36'o0005_1437_1500; DROM[254] = 36'o0006_1437_1500; DROM[255] = 36'o0007_1437_1500; DROM[256] = 36'o0015_1441_3000; DROM[257] = 36'o0015_1441_3000; DROM[258] = 36'o0016_1441_2700; DROM[259] = 36'o0017_1441_2700; DROM[260] = 36'o1015_1442_1100; DROM[261] = 36'o0015_1442_3000; DROM[262] = 36'o0016_1442_1700; DROM[263] = 36'o0017_1442_1700; DROM[264] = 36'o1015_1443_1100; DROM[265] = 36'o0015_1443_3000; DROM[266] = 36'o0016_1443_1700; DROM[267] = 36'o0017_1443_1700; DROM[268] = 36'o1015_1404_1100; DROM[269] = 36'o0015_1404_3000; DROM[270] = 36'o0016_1404_1700; DROM[271] = 36'o0017_1404_1700; DROM[272] = 36'o1015_1444_1100; DROM[273] = 36'o0015_1444_3000; DROM[274] = 36'o0016_1444_1700; DROM[275] = 36'o0017_1444_1700; DROM[276] = 36'o0000_1400_1100; DROM[277] = 36'o0000_1400_2100; DROM[278] = 36'o0116_1404_0700; DROM[279] = 36'o0116_1404_0700; DROM[280] = 36'o1015_1445_1100; DROM[281] = 36'o0015_1445_3000; DROM[282] = 36'o0016_1445_1700; DROM[283] = 36'o0017_1445_1700; DROM[284] = 36'o1015_1446_1100; DROM[285] = 36'o0015_1446_3000; DROM[286] = 36'o0016_1446_1700; DROM[287] = 36'o0017_1446_1700; DROM[288] = 36'o1015_1447_1100; DROM[289] = 36'o0015_1447_3000; DROM[290] = 36'o0016_1447_1700; DROM[291] = 36'o0017_1447_1700; DROM[292] = 36'o1015_1450_1100; DROM[293] = 36'o0015_1450_3000; DROM[294] = 36'o0016_1450_1700; DROM[295] = 36'o0017_1450_1700; DROM[296] = 36'o0015_1451_3000; DROM[297] = 36'o0015_1451_3000; DROM[298] = 36'o0016_1451_2700; DROM[299] = 36'o0017_1451_2700; DROM[300] = 36'o1015_1452_1100; DROM[301] = 36'o0015_1452_3000; DROM[302] = 36'o0016_1452_1700; DROM[303] = 36'o0017_1452_1700; DROM[304] = 36'o1015_1453_1100; DROM[305] = 36'o0015_1453_3000; DROM[306] = 36'o0016_1453_1700; DROM[307] = 36'o0017_1453_1700; DROM[308] = 36'o1015_1454_1100; DROM[309] = 36'o0015_1454_3000; DROM[310] = 36'o0016_1454_1700; DROM[311] = 36'o0017_1454_1700; DROM[312] = 36'o1015_1455_1100; DROM[313] = 36'o0015_1455_3000; DROM[314] = 36'o0016_1455_1700; DROM[315] = 36'o0017_1455_1700; DROM[316] = 36'o0015_1456_3000; DROM[317] = 36'o0015_1456_3000; DROM[318] = 36'o0016_1456_2700; DROM[319] = 36'o0017_1456_2700; DROM[320] = 36'o1015_1410_1100; DROM[321] = 36'o0015_1410_3000; DROM[322] = 36'o0016_1407_1700; DROM[323] = 36'o0004_1404_1700; DROM[324] = 36'o1015_1411_1100; DROM[325] = 36'o0015_1411_3000; DROM[326] = 36'o0016_1413_1700; DROM[327] = 36'o0004_1414_1700; DROM[328] = 36'o1015_1432_1100; DROM[329] = 36'o0015_1432_3000; DROM[330] = 36'o0116_1432_0700; DROM[331] = 36'o0004_1432_1700; DROM[332] = 36'o1015_1424_1100; DROM[333] = 36'o0015_1424_3000; DROM[334] = 36'o0116_1424_0700; DROM[335] = 36'o0004_1424_1700; DROM[336] = 36'o1015_1433_1100; DROM[337] = 36'o0015_1433_3000; DROM[338] = 36'o0116_1433_0700; DROM[339] = 36'o0004_1433_1700; DROM[340] = 36'o1015_1425_1100; DROM[341] = 36'o0015_1425_3000; DROM[342] = 36'o0116_1425_0700; DROM[343] = 36'o0004_1425_1700; DROM[344] = 36'o1015_1430_1100; DROM[345] = 36'o0015_1430_3000; DROM[346] = 36'o0116_1430_0700; DROM[347] = 36'o0004_1430_1700; DROM[348] = 36'o1015_1422_1100; DROM[349] = 36'o0015_1422_3000; DROM[350] = 36'o0116_1422_0700; DROM[351] = 36'o0004_1422_1700; DROM[352] = 36'o1015_1407_1100; DROM[353] = 36'o0015_1407_3000; DROM[354] = 36'o0016_1410_1700; DROM[355] = 36'o0004_1404_1700; DROM[356] = 36'o1015_1412_1100; DROM[357] = 36'o0015_1412_3000; DROM[358] = 36'o0016_1415_1700; DROM[359] = 36'o0004_1416_1700; DROM[360] = 36'o1015_1420_1100; DROM[361] = 36'o0015_1420_3000; DROM[362] = 36'o0116_1420_0700; DROM[363] = 36'o0004_1420_1700; DROM[364] = 36'o1015_1426_1100; DROM[365] = 36'o0015_1426_3000; DROM[366] = 36'o0116_1426_0700; DROM[367] = 36'o0004_1426_1700; DROM[368] = 36'o1015_1421_1100; DROM[369] = 36'o0015_1421_3000; DROM[370] = 36'o0116_1421_0700; DROM[371] = 36'o0004_1421_1700; DROM[372] = 36'o1015_1427_1100; DROM[373] = 36'o0015_1427_3000; DROM[374] = 36'o0116_1427_0700; DROM[375] = 36'o0004_1427_1700; DROM[376] = 36'o1015_1417_1100; DROM[377] = 36'o0015_1417_3000; DROM[378] = 36'o0116_1417_0700; DROM[379] = 36'o0004_1417_1700; DROM[380] = 36'o1015_1423_1100; DROM[381] = 36'o0015_1423_3000; DROM[382] = 36'o0116_1423_0700; DROM[383] = 36'o0004_1423_1700; DROM[384] = 36'o0000_1400_2100; DROM[385] = 36'o0000_1400_2100; DROM[386] = 36'o0000_1475_2100; DROM[387] = 36'o0000_1474_2100; DROM[388] = 36'o0000_1473_2100; DROM[389] = 36'o0000_1472_2100; DROM[390] = 36'o0004_1475_2100; DROM[391] = 36'o0004_1474_2100; DROM[392] = 36'o0000_1400_2100; DROM[393] = 36'o0000_1400_2100; DROM[394] = 36'o0000_1475_1100; DROM[395] = 36'o0000_1474_1100; DROM[396] = 36'o0000_1473_1100; DROM[397] = 36'o0000_1472_1100; DROM[398] = 36'o0004_1475_1100; DROM[399] = 36'o0004_1474_1100; DROM[400] = 36'o0005_1473_2100; DROM[401] = 36'o0005_1472_2100; DROM[402] = 36'o0001_1475_2100; DROM[403] = 36'o0001_1474_2100; DROM[404] = 36'o0001_1473_2100; DROM[405] = 36'o0001_1472_2100; DROM[406] = 36'o0005_1475_2100; DROM[407] = 36'o0005_1474_2100; DROM[408] = 36'o0005_1473_1100; DROM[409] = 36'o0005_1472_1100; DROM[410] = 36'o0001_1475_1100; DROM[411] = 36'o0001_1474_1100; DROM[412] = 36'o0001_1473_1100; DROM[413] = 36'o0001_1472_1100; DROM[414] = 36'o0005_1475_1100; DROM[415] = 36'o0005_1474_1100; DROM[416] = 36'o0006_1473_2100; DROM[417] = 36'o0006_1472_2100; DROM[418] = 36'o0002_1475_2100; DROM[419] = 36'o0002_1474_2100; DROM[420] = 36'o0002_1473_2100; DROM[421] = 36'o0002_1472_2100; DROM[422] = 36'o0006_1475_2100; DROM[423] = 36'o0006_1474_2100; DROM[424] = 36'o0006_1473_1100; DROM[425] = 36'o0006_1472_1100; DROM[426] = 36'o0002_1475_1100; DROM[427] = 36'o0002_1474_1100; DROM[428] = 36'o0002_1473_1100; DROM[429] = 36'o0002_1472_1100; DROM[430] = 36'o0006_1475_1100; DROM[431] = 36'o0006_1474_1100; DROM[432] = 36'o0007_1473_2100; DROM[433] = 36'o0007_1472_2100; DROM[434] = 36'o0003_1475_2100; DROM[435] = 36'o0003_1474_2100; DROM[436] = 36'o0003_1473_2100; DROM[437] = 36'o0003_1472_2100; DROM[438] = 36'o0007_1475_2100; DROM[439] = 36'o0007_1474_2100; DROM[440] = 36'o0007_1473_1100; DROM[441] = 36'o0007_1472_1100; DROM[442] = 36'o0003_1475_1100; DROM[443] = 36'o0003_1474_1100; DROM[444] = 36'o0003_1473_1100; DROM[445] = 36'o0003_1472_1100; DROM[446] = 36'o0007_1475_1100; DROM[447] = 36'o0007_1474_1100; DROM[448] = 36'o1200_1700_4100; DROM[449] = 36'o1200_1720_4100; DROM[450] = 36'o1216_1760_4700; DROM[451] = 36'o0003_1650_2100; DROM[452] = 36'o1200_1754_0100; DROM[453] = 36'o1200_1755_0100; DROM[454] = 36'o0006_1650_2100; DROM[455] = 36'o0007_1650_2100; DROM[456] = 36'o1210_1614_0100; DROM[457] = 36'o1214_1614_0100; DROM[458] = 36'o1210_1460_0100; DROM[459] = 36'o1210_1461_0100; DROM[460] = 36'o1210_1644_0100; DROM[461] = 36'o1214_1644_0100; DROM[462] = 36'o0006_1651_2100; DROM[463] = 36'o0007_1651_2100; DROM[464] = 36'o1200_1614_0100; DROM[465] = 36'o1204_1614_0100; DROM[466] = 36'o1200_1460_0100; DROM[467] = 36'o1200_1461_0100; DROM[468] = 36'o1200_1644_0100; DROM[469] = 36'o1204_1644_0100; DROM[470] = 36'o0006_1652_2100; DROM[471] = 36'o0007_1652_2100; DROM[472] = 36'o0000_1653_2100; DROM[473] = 36'o0001_1653_2100; DROM[474] = 36'o0002_1653_2100; DROM[475] = 36'o0003_1653_2100; DROM[476] = 36'o0004_1653_2100; DROM[477] = 36'o0005_1653_2100; DROM[478] = 36'o0006_1653_2100; DROM[479] = 36'o0007_1653_2100; DROM[480] = 36'o0000_1654_2100; DROM[481] = 36'o0001_1654_2100; DROM[482] = 36'o0002_1654_2100; DROM[483] = 36'o0003_1654_2100; DROM[484] = 36'o0004_1654_2100; DROM[485] = 36'o0005_1654_2100; DROM[486] = 36'o0006_1654_2100; DROM[487] = 36'o0007_1654_2100; DROM[488] = 36'o0000_1655_2100; DROM[489] = 36'o0001_1655_2100; DROM[490] = 36'o0002_1655_2100; DROM[491] = 36'o0003_1655_2100; DROM[492] = 36'o0004_1655_2100; DROM[493] = 36'o0005_1655_2100; DROM[494] = 36'o0006_1655_2100; DROM[495] = 36'o0007_1655_2100; DROM[496] = 36'o0000_1656_2100; DROM[497] = 36'o0001_1656_2100; DROM[498] = 36'o0002_1656_2100; DROM[499] = 36'o0003_1656_2100; DROM[500] = 36'o0004_1656_2100; DROM[501] = 36'o0005_1656_2100; DROM[502] = 36'o0006_1656_2100; DROM[503] = 36'o0007_1656_2100; DROM[504] = 36'o0000_1657_2100; DROM[505] = 36'o0001_1657_2100; DROM[506] = 36'o0002_1657_2100; DROM[507] = 36'o0003_1657_2100; DROM[508] = 36'o0004_1657_2100; DROM[509] = 36'o0005_1657_2100; DROM[510] = 36'o0006_1657_2100; DROM[511] = 36'o0007_1657_2100; Dist/rtl/ks10/cpu/useq/drom.v0000700000175100010010000000633612151540224014422 0ustar RobNone//////////////////////////////////////////////////////////////////// //! //! KS-10 Processor //! //! \brief //! Dispatch ROM (DROM) //! //! \details //! The Dispatch ROM maps the instruction (from the Instruction //! Register) to the address of code that executes that //! instruction in the Control ROM. //! //! \note //! The contents of this file was extracted from the microcode //! listing file by a simple AWK script. Go see the makefile. //! //! \file //! drom.v //! //! \author //! Rob Doyle - doyle (at) cox (dot) net //! //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "crom.vh" `include "drom.vh" module DROM(clk, rst, clken, dbus, crom, drom); parameter cromWidth = `CROM_WIDTH; parameter dromWidth = `DROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [0:35] dbus; // DBUS input [0:cromWidth-1] crom; // Control ROM output reg [0:dromWidth-1] drom; // Dispatch ROM Output // // Microcode decode // wire loadIR = `cromSPEC_EN_40 & (`cromSPEC_SEL == `cromSPEC_SEL_LOADIR); wire [0:8] addr = dbus[0:8]; // // Dispatch ROM initialization // // Note: // The KS10 microcode is extracted from the listing file by // a 'simple' AWK script and is included below. // reg [0:dromWidth-1] DROM[0:511]; initial begin `include "drom.dat" end // // Dispatch ROM // // Details: // The DROM in the KS10 is asynchronous. That won't work in an FPGA // implementation. Fortunately the DROM is addressed by the Instruction // Register (IR) which is loaded synchronously. Therefore we can // absorb a copy of the OPCODE portion of IR directly into Dispatch ROM // addressing. // // Simply put: when we load the IR, we also synchronously lookup the // contents of the Dispatch ROM. // // Trace: // DPEA/E98 // DPEA/E117 // DPEA/E110 // always @(posedge clk) begin if (clken & loadIR) drom <= DROM[addr]; end endmodule Dist/rtl/ks10/cpu/useq/drom.vh0000700000175100010010000001000612151540222014555 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Dispatch ROM (DROM) Definitions // // Details // The Dispatch ROM is addressed by the instruction OPCODE and // provides a microcode dispatch address to handle the // instruction as well as some other instruction specific // information. // // File // drom.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __DROM_VH `define __DROM_VH `define DROM_WIDTH 36 // DROM Width // // Dispatch ROM Fields // // Details: // The Dispatch ROM is addressed by the instruction OPCODE and // provides a microcode dispatch address to handle the instruction // as well as some other instruction specific information. // // Notes // See page 5-39 of EK-0KS10-TM-002 for info about dromTXXXEN. // The bit is not replicated into DROM DPEA/E114[2]. // // The microcode constrains the jump address ("cromJ") to be // between o1400 and o1777. With this constraint, the four upper // address bits of the "cromJ" field are always b"0001". This // allows these four bits of data to be elided from the DISPATCH // ROM. The KS10 then hard-wires these bits into the dispatch // logic. // // This works nicely but creates a design that is somewhat difficult // to understand. This specialization has been removed from the // verilog design - with no ill effects. // // The verilog synthesis tool is smart and discovers that the // contents of these DISPATCH ROM bits are constant and replaces // these ROM bit with hard-wired logic anyway. // // dromI and dromAEQJ are aliases of each other. // // The dromTXXXEN usage is used in the schematic but it's definition // is buried deeply in the microcode. The microcode states that // for the purposes of the "Test Group" dispatch that "... bit 1 of // the B field is used to determine the sense" // `define dromA drom[ 2: 5] // Operand Fetch Mode `define dromB drom[ 8:11] // Store result as: `define dromROUND drom[ 8] // Round the result `define dromMODE drom[ 9] // Seperate Add/Sub & Mul/Div `define dromTXXXEN drom[ 9] // Test Instruction sense `define dromFL_B drom[10:11] // Store Floating-point results as `define dromJ drom[12:23] // Dispatch "Jump" address `define dromACDISP drom[24] // Dispatch on AC Field `define dromI drom[25] // Immediate dispatch on J field. `define dromAEQJ drom[25] // Immediate dispatch on J field. `define dromREADCYCLE drom[26] // Start a read at AREAD `define dromWRTESTCYCLE drom[27] // Start a write test at AREAD `define dromCOND_FUNC drom[28] // Start a memory cycle on BWRITE `define dromVMA drom[29] // Load the VMA on AREAD `define dromWRITECYCLE drom[30] // Start a write on AREAD `endif Dist/rtl/ks10/cpu/useq/ks10.mcr0000700000175100010010000247344212151540232014562 0ustar RobNone; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 1 ; Table of Contents ; 1 KS10.MIC[7,3] 14:54 7-JAN-1986 ; 57 REVISION HISTORY ; 184 HOW TO READ THE MICROCODE ; 389 CONDITIONAL ASSEMBLY DEFINITIONS ; 435 2901 REGISTER USAGE ; 471 MICROCODE FIELDS -- LISTING FORMAT ; 519 MICROCODE FIELDS -- DATAPATH CHIP ; 671 MICROCODE FIELDS -- RAM FILE ADDRESS AND D-BUS ; 705 MICROCODE FIELDS -- PARITY GENERATION & HALF WORD CONTROL ; 728 MICROCODE FIELDS -- SPEC ; 831 MICROCODE FIELDS -- DISPATCH ; 875 MICROCODE FIELDS -- SKIP ; 926 MICROCODE FIELDS -- TIME CONTROL ; 946 MICROCODE FIELDS -- RANDOM CONTROL BITS ; 968 MICROCODE FIELDS -- NUMBER FIELD ; 1312 DISPATCH ROM DEFINITIONS ; 1358 HOW TO READ MACROS ; 1517 MACROS -- DATA PATH CHIP -- GENERAL ; 1667 MACROS -- DATA PATH CHIP -- Q ; 1702 MACROS -- DATA PATH CHIP -- MISC. ; 1723 MACROS -- STORE IN AC ; 1755 MACROS -- MICROCODE WORK SPACE ; 1782 MACROS -- MEMORY CONTROL ; 1832 MACROS -- VMA ; 1849 MACROS -- TIME CONTROL ; 1862 MACROS -- SCAD, SC, FE LOGIC ; 1945 MACROS -- DATA PATH FIELD CONTROL ; 1961 MACROS -- SHIFT PATH CONTROL ; 1974 MACROS -- SPECIAL FUNCTIONS ; 2005 MACROS -- PC FLAGS ; 2034 MACROS -- PAGE FAIL FLAGS ; 2042 MACROS -- SINGLE SKIPS ; 2067 MACROS -- SPECIAL DISPATCH MACROS ; 2101 DISPATCH ROM MACROS ; 2142 SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ; 2144 POWER UP SEQUENCE ; 2226 THE INSTRUCTION LOOP -- START NEXT INSTRUCTION ; 2350 THE INSTRUCTION LOOP -- FETCH ARGUMENTS ; 2462 THE INSTRUCTION LOOP -- STORE ANSWERS ; 2546 MOVE GROUP ; 2583 EXCH ; 2598 HALFWORD GROUP ; 2765 DMOVE, DMOVN, DMOVEM, DMOVNM ; 2796 BOOLEAN GROUP ; 2951 ROTATES AND LOGICAL SHIFTS -- ROT, LSH, JFFO ; 3047 ROTATES AND LOGICAL SHIFTS -- LSHC ; 3082 ROTATES AND LOGICAL SHIFTS -- ASHC ; 3121 ROTATES AND LOGICAL SHIFTS -- ROTC ; 3153 TEST GROUP ; 3305 COMPARE -- CAI, CAM ; 3374 ARITHMETIC SKIPS -- AOS, SOS, SKIP ; 3424 CONDITIONAL JUMPS -- JUMP, AOJ, SOJ, AOBJ ; 3515 AC DECODE JUMPS -- JRST, JFCL ; 3605 EXTENDED ADDRESSING INSTRUCTIONS ; 3646 XCT ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 2 ; Table of Contents ; 3668 STACK INSTRUCTIONS -- PUSHJ, PUSH, POP, POPJ ; 3765 STACK INSTRUCTIONS -- ADJSP ; 3798 SUBROUTINE CALL/RETURN -- JSR, JSP, JSA, JRA ; 3853 ILLEGAL INSTRUCTIONS AND UUO'S ; 4052 ARITHMETIC -- ADD, SUB ; 4081 ARITHMETIC -- DADD, DSUB ; 4114 ARITHMETIC -- MUL, IMUL ; 4165 ARITHMETIC -- DMUL ; 4306 ARITHMETIC -- DIV, IDIV ; 4383 ARITHMETIC -- DDIV ; 4504 ARITHMETIC -- DIVIDE SUBROUTINE ; 4569 ARITHMETIC -- DOUBLE DIVIDE SUBROUTINE ; 4609 ARITHMETIC -- SUBROUTINES FOR ARITHMETIC ; 4655 BYTE GROUP -- IBP, ILDB, LDB, IDPB, DPB ; 4732 BYTE GROUP -- INCREMENT BYTE POINTER SUBROUTINE ; 4745 BYTE GROUP -- BYTE EFFECTIVE ADDRESS EVALUATOR ; 4779 BYTE GROUP -- LOAD BYTE SUBROUTINE ; 4832 BYTE GROUP -- DEPOSIT BYTE IN MEMORY ; 4920 BYTE GROUP -- ADJUST BYTE POINTER ; 5079 BLT ; 5261 FLT.MIC[7,3] 01:46 20-MAR-1981 ; 5262 FLOATING POINT -- FAD, FSB ; 5307 FLAOTING POINT -- FMP ; 5336 FLOATING POINT -- FDV ; 5386 FLOATING POINT -- FLTR, FSC ; 5421 FLOATING POINT -- FIX AND FIXR ; 5458 FLOATING POINT -- SINGLE PRECISION NORMALIZE ; 5525 FLOATING POINT -- ROUND ANSWER ; 5536 FLOATING POINT -- DFAD, DFSB ; 5625 FLOATING POINT -- DFMP ; 5686 FLOATING POINT -- DFDV ; 5740 FLOATING POINT -- DOUBLE PRECISION NORMALIZE ; 5850 EXTEND.MIC[7,3] 11:35 26-JULY-1984 ; 5851 EXTEND -- DISPATCH ROM ENTRIES ; 5906 EXTEND -- INSTRUCTION SET DECODING ; 5948 EXTEND -- MOVE STRING -- SETUP ; 5993 EXTEND -- MOVE STRING -- OFFSET/TRANSLATE ; 6024 EXTEND -- MOVE STRING -- MOVSRJ ; 6072 EXTEND -- MOVE STRING -- SIMPLE MOVE LOOP ; 6096 EXTEND -- COMPARE STRING ; 6157 EXTEND -- DECIMAL TO BINARY CONVERSION ; 6289 EXTEND -- BINARY TO DECIMAL CONVERSION ; 6447 EXTEND -- EDIT -- MAIN LOOP ; 6501 EXTEND -- EDIT -- DECODE OPERATE GROUP ; 6520 EXTEND -- EDIT -- STOP EDIT ; 6535 EXTEND -- EDIT -- START SIGNIFICANCE ; 6542 EXTEND -- EDIT -- EXCHANGE MARK AND DESTINATION ; 6553 EXTEND -- EDIT -- PROCESS SOURCE BYTE ; 6616 EXTEND -- EDIT -- MESSAGE BYTE ; 6639 EXTEND -- EDIT -- SKIP ; 6653 EXTEND -- EDIT -- ADVANCE PATTERN POINTER ; 6686 EXTEND SUBROUTINES -- FILL OUT DESTINATION ; 6710 EXTEND SUBROUTINES -- GET MODIFIED SOURCE BYTE ; 6747 EXTEND SUBROUTINES -- TRANSLATE ; 6833 EXTEND SUBROUTINES -- GET UNMODIFIED SOURCE BYTE ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 3 ; Table of Contents ; 6862 EXTEND SUBROUTINES -- STORE BYTE IN DESTINATION STRING ; 6883 EXTEND SUBROUTINES -- UPDATE DEST STRING POINTERS ; 6927 EXTEND -- PAGE FAIL CLEANUP ; 6966 INOUT.MIC[7,3] 13:32 7-JAN-1986 ; 6967 TRAPS ; 6998 IO -- INTERNAL DEVICES ; 7109 IO -- INTERNAL DEVICES -- EBR & UBR ; 7235 IO -- INTERNAL DEVICES -- KL PAGING REGISTERS ; 7277 IO -- INTERNAL DEVICES -- TIMER CONTROL ; 7308 IO -- INTERNAL DEVICES -- WRTIME & RDTIME ; 7347 IO -- INTERNAL DEVICES -- WRINT & RDINT ; 7361 IO -- INTERNAL DEVICES -- RDPI & WRPI ; 7401 IO -- INTERNAL DEVICES -- SUBROUTINES ; 7542 PRIORITY INTERRUPTS -- DISMISS SUBROUTINE ; 7557 EXTERNAL IO INSTRUCTIONS ; 7745 SMALL SUBROUTINES ; 7769 UNDEFINED IO INSTRUCTIONS ; 7850 UMOVE AND UMOVEM ; 7905 WRITE HALT STATUS BLOCK ; 7997 PAGEF.MIC[7,3] 12:15 10-APR-1985 ; 7999 PAGE FAIL REFIL LOGIC ; Cross Reference Index ; DCODE Location / Line Number Index ; UCODE Location / Line Number Index ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 4 ; KS10.MIC[7,3] 14:54 7-JAN-1986 KS10.MIC[7,3] 14:54 7-JAN-1986 ; 1 .NOBIN ; 2 .TITLE "KS10 MICROCODE V130, 7-JAN-86" ; 3 ; 4 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; 5 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; 6 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; 7 ;;; ;;; ; 8 ;;; ;;; ; 9 ;;; COPYRIGHT (C) 1976,1977,1978,1979,1980,1981,1982, ;;; ; 10 ;;; 1984,1985,1986 ;;; ; 11 ;;; DIGITAL EQUIPMENT CORP., MAYNARD, MASS. ;;; ; 12 ;;; ;;; ; 13 ;;; THIS SOFTWARE IS FURNISHED UNDER A LICENSE FOR USE ;;; ; 14 ;;; ONLY ON A SINGLE COMPUTER SYSTEM AND MAY BE COPIED ;;; ; 15 ;;; ONLY WITH THE INCLUSION OF THE ABOVE COPYRIGHT ;;; ; 16 ;;; NOTICE. THIS SOFTWARE, OR ANY OTHER COPIES THEREOF, ;;; ; 17 ;;; MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ;;; ; 18 ;;; ANY OTHER PERSON EXCEPT FOR USE ON SUCH SYSTEM AND ;;; ; 19 ;;; TO ONE WHO AGREES TO THESE LICENSE TERMS. TITLE TO ;;; ; 20 ;;; AND OWNERSHIP OF THE SOFTWARE SHALL AT ALL TIMES ;;; ; 21 ;;; REMAIN IN DEC. ;;; ; 22 ;;; ;;; ; 23 ;;; THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO ;;; ; 24 ;;; CHANGE WITHOUT NOTICE AND SHOULD NOT BE CONSTRUED AS ;;; ; 25 ;;; A COMMITMENT BY DIGITAL EQUIPMENT CORPORATION. ;;; ; 26 ;;; ;;; ; 27 ;;; DEC ASSUMES NO RESPONSIBILITY FOR THE USE OR ;;; ; 28 ;;; RELIABILITY OF ITS SOFTWARE IN EQUIPMENT WHICH IS ;;; ; 29 ;;; NOT SUPPLIED BY DEC. ;;; ; 30 ;;; ;;; ; 31 ;;; DESIGNED AND WRITTEN BY: ;;; ; 32 ;;; DONALD A. LEWINE ;;; ; 33 ;;; DIGITAL EQUIPMENT CORP. ;;; ; 34 ;;; MARLBORO, MASS. ;;; ; 35 ;;; MR1-2/E47 X6430 ;;; ; 36 ;;; ;;; ; 37 ;;; MAINTAINED AND ENHANCED BY: ;;; ; 38 ;;; DONALD D. DOSSA ;;; ; 39 ;;; DIGITAL EQUIPMENT CORP. ;;; ; 40 ;;; MARLBORO, MASS. ;;; ; 41 ;;; MR1-2/E18 DTN 231-4138 ;;; ; 42 ;;; ;;; ; 43 ;;; SEAN KEENAN ;;; ; 44 ;;; DIGITAL EQUIPMENT CORP. ;;; ; 45 ;;; MARLBORO, MASS. ;;; ; 46 ;;; MR1-2/E18 DTN 231-4463 ;;; ; 47 ;;; ;;; ; 48 ;;; TIMOTHE LITT ;;; ; 49 ;;; DIGITAL EQUIPMENT CORP. ;;; ; 50 ;;; MARLBORO, MASS. ;;; ; 51 ;;; IND-3/C9 262-8374 ;;; ; 52 ;;; ;;; ; 53 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; 54 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; 55 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; 56 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 5 ; KS10.MIC[7,3] 14:54 7-JAN-1986 REVISION HISTORY ; 57 .TOC "REVISION HISTORY" ; 58 ; 59 ;REV WHY ; 60 ;1 START KS10 MICROCODE BASED ON SM10 MICROCODE VERSION 510 ; 61 ;2 UPDATE TO KS10 VERSION 512 ; 62 ;3 FIX SOME DEFAULTS ; 63 ;4 CHANGE HARDWARE TO MATCH ECO #215 ; 64 ;5 START TO UPDATE IO MICROCODE ; 65 ;6 MORE WORK ON IO ; 66 ;7 MAKE INTERRUPT THE 8080 BE A PULSE. ; 67 ;10 ADD NEW RDIO AND WRIO ; 68 ;11 FIX PROBLEMS IN MUUO CODE & CORRECT T-FIELDS ; 69 ;12 FIX PROBLEMS IN DDIV ; 70 ;13 FIX UP PROBLEMS IN PI ; 71 ;14 TURN ON WRITE FOR FL-EXIT ; 72 ;15 FIX UP MAP INSTRUCTION ; 73 ;16 MORE WORK ON KI-STYLE MAP ; 74 ;17 INVERT HOLD RIGHT AND HOLD LEFT BITS ; 75 ;20 FIXUP WRIO & RDIO EFFECTIVE ADDRESS CALC. ; 76 ;21 FIX EDIT 15 ; 77 ;22 HAVE LSH USE FAST SHIFT HARDWARE ; 78 ;23 FIX T-FIELD VALUES FOR PRODUCTION HARDWARE ; 79 ;24 REMOVE WRITE TEST FROM IO READS & WRITES ; 80 ;25 REWRITE MUL & MULI TO BE FASTER AND SMALLER. ALSO MAKE ADJBP ; 81 ; USE NEW MULSUB ; 82 ;26 MAKE BYTES USE FAST SHIFT ECO. ; 83 ;27 MAKE SURE VMA FETCH IS CORRECT ; 84 ;30 MORE OF 25 (FORGOT FMP) ; 85 ;31 FIX SOME PROBLEMS WITH TRAPS ; 86 ;32 SPEED UP EFFECTIVE ADDRESS CALCULATION ; 87 ;33 MORE OF 32 ; 88 ;34 SPEED UP ASH & ROT ; 89 ;35 FIX UP RDTIM SO THAT TIME DOES NOT GO BACKWARDS ; 90 ;36 MORE OF 35 ; 91 ;37 FIX UP PROBLEMS WITH INTERRUPTS AND DOUBLE F.P. ; 92 ;40 IMPROVE LISTING FORMAT ; 93 ;41 SPEEDUP KL-MODE PAGE REFILL ; 94 ;42 FIX UP DDIV ; 95 ;43 STILL MORE DDIV STUFF ; 96 ;44 CORRECT PROBLEMS IN D.P. PARITY STUFF ; 97 ;45 CORRECT THE BLT CLEAR-CORE CASE TO INTERRUPT CORRECTLY ; 98 ;46 MORE OF 45 ; 99 ;47 DO NOT ALLOW SOFTWARE INTERRUPTS IF THE PI LEVEL IS NOT ; 100 ; ACTIVE. ; 101 ;50 MAKE FDV WORK THE SAME AS THE KL10 ; 102 ;51 FIX INTERRUPT IN CVTBDX. MAKE ABORT WORK LIKE SPEC. ; 103 ;52 FIX BUG IN HALT LOOP ; 104 ;53 FIX IOEA TO WORK IF NO @ OR INDEXING ; 105 ;54 EDIT 47 BROKE JEN ; 106 ;55 FIX FLAGS IN MULTIPLY. ALSO CODE BUMS ; 107 ;56 MORE CODE BUMS ; 108 ;57 CORRECT OVERFLOW TRAPS WHICH DO MUUOS TO NOT STORE ; 109 ; THE TRAP FLAGS. ; 110 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 6 ; KS10.MIC[7,3] 14:54 7-JAN-1986 REVISION HISTORY ; 111 ;60 CORRECT TRAPS SO THAT DSKEA RUNS RIGHT ; 112 ;61 MORE OF 60. NOTE: MICROCODE REQUIRES ECO #299!! ; 113 ;62 ONE MORE TRY AT EDIT 60. ; 114 ;63 CORRECT TOPS-10 STYLE PAGING SO THAT A WRITE VIOLATION SETS ; 115 ; BIT 2 IN THE PAGE FAIL WORD (ACCESS ALLOWED). ; 116 ;64 EDIT 63 BROKE HARD PAGE FAILS. (NXM, BAD DATA, AND IO NXM) ; 117 ;65 INTERRUPTS OUT OF MOVSRJ INSTRUCTIONS DO STRANGE THINGS. ; 118 ;66 IO NXM PAGE FAIL FOR MISSING UBA GIVES PC+1 IN PAGE FAIL BLOCK. ; 119 ;67 ON A BAD DATA ERROR, STORE THE BAD WORD IN AC BLOCK 7 WORD 0 AND ; 120 ; 1 ; 121 ;70 FIX A BUG WHICH CAUSED INTERRUPTS OUT OF CVTBDT TO GENERATE A BAD ; 122 ; ANSWER. ; 123 ;71 CLEANUP SOME THINGS TO MAKE LIFE EASIER FOR FIELD SERVICE ; 124 ;72 LOOK FOR 1-MS TRAP ON @ PAGE POINTERS AND ABORT REFILL IF ; 125 ; SET. ; 126 ;73 CORRECT EDIT 72. ; 127 ;74 EDIT 67 GENERATES A DATA PATH PARITY ERROR BECAUSE OF THE BAD ; 128 ; DATA. CORRECT TO NOT CHECK PARITY. ; 129 ; ALSO CHANGE POP TO TIE UP BUS LESS. ; 130 ;75 EDIT 60 BROKE TRAPS. MISSING =0 AT TRAP:. ; 131 ;76 CORRECT BUG IN DFAD AND DFSB ; 132 ;77 FIX PROBLEM SEEN IN SOME (ALL BUT ENGINEERING?) MACHINES CAUSED ; 133 ; BY EDIT 76 ; 134 ;100 CHANGE DFAD/DFSB TO HAVE 2 MORE GUARD BITS. THIS SHOULD PRODUCE ; 135 ; KL10 ANSWERS FOR ALL NORMALIZED INPUTS ; 136 ; ALSO FIX A BUG IN CVTBDX PAGE FAIL LOGIC. ; 137 ;101 DFDV OF 0.0 / -0.5 HANGS THE MACHINE ; 138 ;102 FIX CHOPPED FLOATING POINT INSTRUCTIONS ; 139 ;103 CORRECT DFDV ROUNDING BUG. ; 140 ;104 CORRECT PROBLEMS IN DFMP ; 141 ;105 RDTIME SOMETIMES GIVES WRONG ANSWER. CARRY BETWEEN ; 142 ; WORDS GETS LOST SOMETIME. ; 143 ;106 MOVEM (ALSO, SETZM, SETOM, ETC.) SOMETIMES DOES NOT GENERATE ; 144 ; A WRITE-TRAP IN 100% OF THE CASES THAT IT SHOULD. ; 145 ;107 PXCT 14, DOES NOT GET THE INDEX REGISTER IN THE PREVIOUS ; 146 ; CONTEXT ALL THE TIME. ; 147 ;110 FIX TYPO IN EDIT 103 ; 148 ;111 63. BIT BYTES DO NOT WORK CORRECTLY. DSKDA FAILS BECAUSE OF THIS ; 149 ; PROBLEM. ; 150 ;******* VERSION 111 WENT OUT WITH SYSTEM REV 2 ******* ; 151 ; 152 ;112 FIX COMMENT IN TEST INSTRUCTIONS ; 153 ;113 CORRECT IOEA TO COMPUTE CORRECT ADDRESS IF JUST LOCAL INDEXING ; 154 ; IS USED. ; 155 ;114 CORRECT INTERRUPT BUG IN DMUL ; 156 ;115 CORRECT COMMENTS HALT STATUS BLOCK ; 157 ;116 CORRECT PROBLEM WHERE CST MODIFIED BIT GETS SET BY MISTAKE. ; 158 ;117 RDINT INSTRUCTION DOES NOT WORK AT ALL. IT STORES RANDOM TRASH ; 159 ; IN THE WRONG PLACE. NEED TO LOAD BR NOT AR. ; 160 ;120 FLOATING POINT OPERATIONS SOMETIMES GET THE WRONG RESULT WITH ; 161 ; INPUTS OF UNNORMALIZED ZEROS. THIS SHOULD NEVER HAPPEN WITH ; 1623 ; FORTRAN OR ANY OTHER DEC LANGUAGE. ; 163 ;121 PREVENT KEEP-ALIVE CRASHES FROM OCCURRING BECAUSE THE MOVSRJ ; 164 ; INSTRUCTION CAN LOCK OUT THE 1MS TIMER INTERRUPTS FROM BEING ; 165 ; HANDLED. THIS CAUSES THE OPERATING SYSTEM TO LOSE TRACK OF THE ; 166 ; PASSAGE OF TIME. ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 6-1 ; KS10.MIC[7,3] 14:54 7-JAN-1986 REVISION HISTORY ; 167 ;122 DFAD FOLLOWED BY A FSC OF -5 CAUSES THE FSC TO GET WRONG ; 168 ; ANSWER. HAD TO CLEAR FLAG WORD AT EXIT OF DFAD TO FIX PROBLEM ; 169 ;123 MORE CODE FOR EDIT 121. ADDED ANOTHER DISPATCH ADDRESS FOR ; 170 ; PAGE FAIL CODE AT PFD:. ; 171 ;124 ADD ASSEMBLY OPTIONS FOR NOCST AND INHIBIT CST UPDATE. ; 172 ; ADD BLTUB/BLTBU TO GET UBA STYLE BYTES SWAPPED TO/FROM ILDB FORM. ; 173 ; ADD ASSEMBLY OPTIONS FOR KI/KL PAGE. NEED THE SPACE FOR BLTUB/BU. ; 174 ;125 SUPPORT THE "MAJOR/MINOR VERSION IN 136" UCODE STANDARD. ; 175 ; FIX BAD CONSTRAINT FOR INHCST ASSEMBLIES (NOT CURRENTLY USED) ; 176 ;126 FIX NON-TRIVIAL CASES OF RDUBR,WRUBR, AND PROCESS CONTEXT WORD. ; 177 ;127 JSR IN A TRAP CYCLE STORES E+1 SOMETIMES. TRAP CYCLE WAS NOT BEING ; 178 ; CLEARED (BY NICOND) BEFORE STARTING THE NEXT MEMORY READ. ; 179 ;130 FIX UCODE HANG WITH STOPPPED CLOCKS ON WR (KL-PAGING REGISTER) IF ; 180 ; PAGING IS ON. IDEALLY, WE WOULD REMOVE WRITE TEST FROM THE DROM ; 181 ; FIELD, BUT IT'S TOO LATE TO ECO THE ROMS. ; 182 ; RESTRICTION: WRITE KLPAGE REGISTER LOCATION MUST BE WRITABLE. ; 183 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 7 ; KS10.MIC[7,3] 14:54 7-JAN-1986 HOW TO READ THE MICROCODE ; 184 .TOC "HOW TO READ THE MICROCODE" ; 185 ; 186 ; ; 187 ; ; 188 ; 1.0 FIELD DEFINITIONS ; 189 ; ; 190 ; THESE OCCUR AT THE BEGINNING OF THE LISTING, IN THE SOURCE FILE KS10.MIC ; 191 ; (CONTROL AND DISPATCH RAM DEFINITIONS). THEY HAVE THE FORM: ; 192 ; ; 193 ; SYMBOL/=M,J ; 194 ; ; 195 ; THE PARAMETER (J) IS MEANINGFUL WHEN "D" IS SPECIFIED AS THE DEFAULT MECHANISM, ; 196 ; AND IN THAT CASE, GIVES THE DEFAULT VALUE OF THE FIELD IN OCTAL. WHEN "F" IS ; 197 ; SPECIFIED AS THE DEFAULT MECHANISM, (J) IS THE NAME OF A FIELD WHICH CONTAINS ; 198 ; THE DEFAULT VALUE FOR THIS FIELD. ; 199 ; ; 200 ; THE PARAMETER (L) GIVES THE BIT POSITION OF THE LEFTMOST BIT IN THE FIELD. THE ; 201 ; SAME METHOD IS USED AS FOR (R) BELOW. ; 202 ; ; 203 ; THE PARAMETER (R) GIVES THE FIELD POSITION IN DECIMAL AS THE BIT NUMBER OF THE ; 204 ; RIGHTMOST BIT OF THE FIELD. BITS ARE NUMBERED FROM 0 ON THE LEFT. NOTE THAT ; 205 ; THE POSITION OF BITS IN THE MICROWORD SHOWN IN THE LISTING BEARS NO RELATION TO ; 206 ; THE ORDERING OF BITS IN THE HARDWARE MICROWORD, WHERE FIELDS ARE OFTEN BROKEN UP ; 207 ; AND SCATTERED. ; 208 ; ; 209 ; THE PARAMETER (M) IS OPTIONAL, AND SELECTS A DEFAULT MECHANISM FOR THE FIELD. ; 210 ; THE LEGAL VALUES OF THIS PARAMETER ARE THE CHARACTERS "D", "F", "T", "P", OR ; 211 ; "+". ; 212 ; ; 213 ; "D" MEANS (J) IS THE DEFAULT VALUE OF THE FIELD IF NO EXPLICIT VALUE IS ; 214 ; SPECIFIED. ; 215 ; ; 216 ; "F" IS USED TO CAUSE THIS FIELD TO DEFAULT TO SOME OTHER FIELD. ; 217 ; ; 218 ; "T" IS USED ON THE TIME FIELD TO SPECIFY THAT THE VALUE OF THE FIELD ; 219 ; DEPENDS ON THE TIME PARAMETERS SELECTED FOR OTHER FIELDS. "T" IS NOT ; 220 ; USED IN THE KS10. ; 221 ; ; 222 ; "P" IS USED ON THE PARITY FIELD TO SPECIFY THAT THE VALUE OF THE FIELD ; 223 ; SHOULD DEFAULT SUCH THAT PARITY OF THE ENTIRE WORD IS ODD. "P" IS NOT ; 224 ; USED ON THE KS10. ; 225 ; ; 226 ; "+" IS USED ON THE JUMP ADDRESS FIELD TO SPECIFY THAT THE DEFAULT JUMP ; 227 ; ADDRESS IS THE ADDRESS OF THE NEXT INSTRUCTION ASSEMBLED (NOT, IN ; 228 ; GENERAL, THE CURRENT LOCATION +1). ; 229 ; ; 230 ; IN GENERAL, A FIELD CORRESPONDS TO THE SET OF BITS WHICH PROVIDE SELECT INPUTS ; 231 ; FOR MIXERS OR DECODERS, OR CONTROLS FOR ALU'S. ; 232 ; ; 233 ; ; 234 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 8 ; KS10.MIC[7,3] 14:54 7-JAN-1986 HOW TO READ THE MICROCODE ; 235 ; 2.0 VALUE DEFINITIONS ; 236 ; ; 237 ; FOLLOWING A FIELD DEFINITION, SYMBOLS MAY BE CREATED IN THAT FIELD TO CORRESPOND ; 238 ; TO VALUES OF THE FIELD. THE FORM IS: ; 239 ; ; 240 ; SYMBOL=N ; 241 ; ; 242 ; "N" IS, IN OCTAL, THE VALUE OF SYMBOL WHEN USED IN THE FIELD. ; 243 ; ; 244 ; ; 245 ; ; 246 ; 3.0 LABEL DEFINITIONS ; 247 ; ; 248 ; A MICRO INSTRUCTION MAY BE LABELLED BY A SYMBOL FOLLOWED BY COLON PRECEDING THE ; 249 ; MICROINSTRUCTION DEFINITION. THE ADDRESS OF THE MICROINSTRUCTION BECOMES THE ; 250 ; VALUE OF THE SYMBOL IN THE FIELD NAMED "J". EXAMPLE: ; 251 ; ; 252 ; FOO: J/FOO ; 253 ; ; 254 ; THIS IS A MICROINSTRUCTION WHOSE "J" FIELD (JUMP ADDRESS) CONTAINS THE VALUE ; 255 ; "FOO". IT ALSO DEFINES THE SYMBOL "FOO" TO BE THE ADDRESS OF ITSELF. ; 256 ; THEREFORE, IF EXECUTED BY THE MICROPROCESSOR, IT WOULD LOOP ON ITSELF. ; 257 ; ; 258 ; ; 259 ; ; 260 ; 4.0 COMMENTS ; 261 ; ; 262 ; A SEMICOLON ANYWHERE ON A LINE CAUSES THE REST OF THE LINE TO BE IGNORED BY THE ; 263 ; ASSEMBLER. THIS TEXT IS AN EXAMPLE OF COMMENTS. ; 264 ; ; 265 ; ; 266 ; ; 267 ; 5.0 MICROINSTRUCTION DEFINITION ; 268 ; ; 269 ; A WORD OF MICROCODE IS DEFINED BY SPECIFYING A FIELD NAME, FOLLOWED BY SLASH ; 270 ; (/), FOLLOWED BY A VALUE. THE VALUE MAY BE A SYMBOL DEFINED FOR THAT FIELD, AN ; 271 ; OCTAL DIGIT STRING, OR A DECIMAL DIGIT STRING (DISTINGUISHED BY THE FACT THAT IT ; 272 ; CONTAINS "8" AND/OR "9" AND/OR IS TERMINATED BY A PERIOD). SEVERAL FIELDS MAY ; 273 ; BE SPECIFIED IN ONE MICROINSTRUCTION BY SEPARATING FIELD/VALUE SPECIFICATIONS ; 274 ; WITH COMMAS. EXAMPLE: ; 275 ; ; 276 ; AD/ZERO,RAMADR/AC*#,ACALU/AC+N,ACN/1,DBUS/DP ; 277 ; ; 278 ; ; 279 ; 6.0 CONTINUATION ; 280 ; ; 281 ; THE DEFINITION OF A MICROINSTRUCTION MAY CONTINUED ONTO TWO OR MORE LINES BY ; 282 ; BREAKING IT AFTER ANY COMMA. IN OTHER WORDS, IF THE LAST NON-BLANK, NON-COMMENT ; 283 ; CHARACTER ON A LINE IS A COMMA, THE INSTRUCTION SPECIFICATION IS CONTINUED ON ; 284 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 9 ; KS10.MIC[7,3] 14:54 7-JAN-1986 HOW TO READ THE MICROCODE ; 285 ; THE FOLLOWING LINE. EXAMPLE: ; 286 ; READ [AR], ;LOOK AT EFFECTIVE ADDRESS ; 287 ; SKIP DP18, ;SEE IF RIGHT OR LEFT SHIFT ; 288 ; SC_SHIFT-1, ;PUT NUMBER OF PLACE TO ; 289 ; ;SHIFT IN SC ; 290 ; LOAD FE, ; AND IN FE ; 291 ; INST DISP ;GO DO THE SHIFT ; 292 ; ; 293 ; ; 294 ; ; 295 ; 7.0 MACROS ; 296 ; ; 297 ; A MACRO IS A SYMBOL WHOSE VALUE IS ONE OR MORE FIELD/VALUE SPECIFICATIONS AND/OR ; 298 ; MACROS. A MACRO DEFINITION IS A LINE CONTAINING THE MACRO NAME FOLLOWED BY A ; 299 ; QUOTED STRING WHICH IS THE VALUE OF THE MACRO. EXAMPLE: ; 300 ; ; 301 ; LOAD VMA "MEM/1, LDVMA/1 ; 302 ; ; 303 ; THE APPEARANCE OF A MACRO IN A MICROINSTRUCTION DEFINITION IS EQUIVALENT TO THE ; 304 ; APPEARANCE OF ITS VALUE. ; 305 ; ; 306 ; MACRO MAY HAVE PARAMETERS ENCLOSED IN []. FOR EXAMPLE, ; 307 ; ; 308 ; []_[] "AD/A,A/@2,DEST/AD,B/@1" ; 309 ; ; 310 ; THE @1 GETS REPLACED BY WHAT IS WRITTEN IN THE FIRST SET OF [] AND @2 IS ; 311 ; REPLACED BY WHAT IS WRITTEN IN THE SECOND SET OF []. THUS ; 312 ; ; 313 ; [AR]_[ARX] ; 314 ; ; 315 ; HAS THE SAME EFFECT AS SAYING ; 316 ; ; 317 ; AD/A,A/ARX,DEST/AD,B/AR ; 318 ; ; 319 ; ; 320 ; SEE DESCRIPTION OF RULES FOR MACRO NAMES. ; 321 ; ; 322 ; 8.0 PSEUDO OPS ; 323 ; ; 324 ; THE MICRO ASSEMBLER HAS 13 PSEUDO-OPERATORS: ; 325 ; ; 326 ; .DCODE AND .UCODE SELECT THE RAM INTO WHICH SUBSEQUENT MICROCODE WILL BE ; 327 ; LOADED, AND THEREFORE THE FIELD DEFINITIONS AND MACROS WHICH ARE ; 328 ; MEANINGFUL IN SUBSEQUENT MICROCODE ; 329 ; .TITLE DEFINES A STRING OF TEXT TO APPEAR IN THE PAGE HEADER, AND ; 330 ; .TOC DEFINES AN ENTRY FOR THE TABLE OF CONTENTS AT THE BEGINNING. ; 331 ; .SET DEFINES THE VALUE OF A CONDITIONAL ASSEMBLY PARAMETER, ; 332 ; .CHANGE REDEFINES A CONDITIONAL ASSEMBLY PARAMETER, ; 333 ; .DEFAULT ASSIGNS A VALUE TO AN UNDEFINED PARAMETER. ; 334 ; .IF ENABLES ASSEMBLY IF THE VALUE OF THE PARAMETER IS NOT ZERO, ; 335 ; .IFNOT ENABLES ASSEMBLY IF THE PARAMETER VALUE IS ZERO, AND ; 336 ; .ENDIF RE-ENABLES ASSEMBLY IF SUPPRESSED BY THE PARAMETER NAMED. ; 337 ; .NOBIN TURNS OFF THE BINARY A GETS RID OF THE SPACE USED TO LIST IT, ; 338 ; .BIN TURN BINARY BACK ON AGAIN. ; 339 ; .WIDTH CONTROLS THE NUMBER OF BITS IN THE CRAM ; 340 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 10 ; KS10.MIC[7,3] 14:54 7-JAN-1986 HOW TO READ THE MICROCODE ; 341 ; 9.0 LOCATION CONTROL ; 342 ; ; 343 ; A MICROINSTRUCTION "LABELLED" WITH A NUMBER IS ASSIGNED TO THAT ADDRESS. ; 344 ; ; 345 ; THE CHARACTER "=" AT THE BEGINNING OF A LINE, FOLLOWED BY A STRING OF 0'S, 1'S, ; 346 ; AND/OR *'S, SPECIFIES A CONSTRAINT ON THE ADDRESS OF FOLLOWING ; 347 ; MICROINSTRUCTIONS. THE NUMBER OF CHARACTERS IN THE CONSTRAINT STRING (EXCLUDING ; 348 ; THE "=") IS THE NUMBER OF LOW-ORDER BITS CONSTRAINED IN THE ADDRESS. THE ; 349 ; MICROASSEMBLER ATTEMPTS TO FIND AN UNUSED LOCATION WHOSE ADDRESS HAS 0 BITS IN ; 350 ; THE POSITIONS CORRESPONDING TO 0'S IN THE CONSTRAINT STRING AND 1 BITS WHERE THE ; 351 ; CONSTRAINT HAS 1'S. ASTERISKS DENOTE "DON'T CARE" BIT POSITIONS. ; 352 ; ; 353 ; IF THERE ARE ANY 0'S IN THE CONSTRAINT STRING, THE CONSTRAINT IMPLIES A BLOCK OF ; 354 ; <2**N> MICROWORDS, WHERE N IS THE NUMBER OF 0'S IN THE STRING. ALL LOCATIONS IN ; 355 ; THE BLOCK WILL HAVE 1'S IN THE ADDRESS BITS CORRESPONDING TO 1'S IN THE STRING, ; 356 ; AND BIT POSITIONS DENOTED BY *'S WILL BE THE SAME IN ALL LOCATIONS OF THE BLOCK. ; 357 ; ; 358 ; IN SUCH A CONSTRAINT BLOCK, THE DEFAULT ADDRESS PROGRESSION IS COUNTING IN THE ; 359 ; "0" POSITIONS OF THE CONSTRAINT STRING, BUT A NEW CONSTRAINT STRING OCCURING ; 360 ; WITHIN A BLOCK MAY FORCE SKIPPING OVER SOME LOCATIONS OF THE BLOCK. WITHIN A ; 361 ; BLOCK, A NEW CONSTRAINT STRING DOES NOT CHANGE THE PATTERN OF DEFAULT ADDRESS ; 362 ; PROGRESSION, IT MERELY ADVANCES THE LOCATION COUNTER OVER THOSE LOCATIONS. THE ; 363 ; MICROASSEMBLER WILL LATER FILL THEM IN. ; 364 ; ; 365 ; A NULL CONSTRAINT STRING ("=" FOLLOWED BY ANYTHING BUT "0", "1", OR "*") SERVES ; 366 ; TO TERMINATE A CONSTRAINT BLOCK. EXAMPLES: ; 367 ; ; 368 ; =0 ; 369 ; ; 370 ; THIS SPECIFIES THAT THE LOW-ORDER ADDRESS BIT MUST BE ZERO-- THE MICROASSEMBLER ; 371 ; FINDS AN EVEN-ODD PAIR OF LOCATIONS, AND PUTS THE NEXT TWO MICROINSTRUCTIONS ; 372 ; INTO THEM. ; 373 ; ; 374 ; =11 ; 375 ; THIS SPECIFIES THAT THE TWO LOW-ORDER BITS OF THE ADDRESS MUST BOTH BE ONES. ; 376 ; SINCE THERE ARE NO 0'S IN THIS CONSTRAINT, THE ASSEMBLER FINDS ONLY ONE LOCATION ; 377 ; MEETING THE CONSTRAINT. ; 378 ; ; 379 ; =0***** ; 380 ; ; 381 ; THIS SPECIFIES AN ADDRESS IN WHICH THE "40" BIT IS ZERO. DUE TO THE ; 382 ; IMPLEMENTATION OF THIS FEATURE IN THE ASSEMBLER, THE DEFAULT ADDRESS PROGRESSION ; 383 ; APPLIES ONLY TO THE LOW-ORDER 5 BITS, SO THIS CONSTRAINT FINDS ONE WORD IN WHICH ; 384 ; THE "40" BIT IS ZERO, AND DOES NOT ATTEMPT TO FIND ONE IN WHICH THAT BIT IS A ; 385 ; ONE. THIS LIMITATION HAS BEEN CHANGED WITH NEWER ASSEMBLER VERSIONS. HOWEVER ; 386 ; NONE OF THE LOCATIONS IN THE MICROCODE REQUIRE ANYTHING BUT THE CONSTRAINT ; 387 ; MENTIONED ABOVE. ; 388 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 11 ; KS10.MIC[7,3] 14:54 7-JAN-1986 CONDITIONAL ASSEMBLY DEFINITIONS ; 389 .TOC "CONDITIONAL ASSEMBLY DEFINITIONS" ; 390 ; 391 .DEFAULT/SIM=0 ;0=RUN ON REAL HARDWARE ; 392 ;1=RUN UNDER SIMULATOR ; 393 ; 394 .DEFAULT/FULL=1 ;0=INCLUDE ONLY BASIC INSTRUCTIONS ; 395 ;1=INCLUDE FULL INSTRUCTION SET ; 396 ; 397 .DEFAULT/INHCST=0 ;0=NO CODE TO INHIBIT CST UPDATE IF CSB=0 ; 398 ;1=DON'T UPDATE CST IF CSB=0 ; 399 ; 400 .DEFAULT/NOCST=0 ;0=INCLUDE SUPPORT FOR WRITING THE CST ; 401 ;1=COMPLETELY DESUPPORT CST (FOR TOPS-10) ; 402 ; 403 .DEFAULT/UBABLT=0 ;0=NO UBABLT SUPPORT ; 404 ;1=SUPPORT UBA STYLE BLT INSTRUCTIONS. ; 405 ; 406 .DEFAULT/KIPAGE=1 ;0=DON'T SUPPORT KI PAGING ; 407 ;1=DO ; 408 ; 409 .DEFAULT/KLPAGE=1 ;0=DON'T SUPPORT KL PAGING ; 410 ;1=DO ; 411 ;;412 .IF/UBABLT ;THESE INSTRUCTIONS ;;413 .IF/KLPAGE ;;414 .CHANGE/KIPAGE=0 ;;415 .ENDIF/KLPAGE ;;416 .IF/KIPAGE ;ALLOW ONLY ONE PAGING MODE ;;417 .CHANGE/KLPAGE=0 ;;418 .ENDIF/KIPAGE ; 419 .ENDIF/UBABLT ;OTHERWISE, MAY HAVE EITHER OR BOTH ; 420 ;;421 .IF/NOCST ;;422 .CHANGE/INHCST=0 ; 423 .ENDIF/NOCST ; 424 ; 425 .DEFAULT/NONSTD=0 ;0=STANDARD MICROCODE ; 426 ;1=NON-STANDARD MICROCODE ; 427 ; 428 .WIDTH/108 ;ONLY FIELDS BETWEEN BITS 0 AND 107 EVER ; 429 ; GET LOADED INTO THE CRAM. OTHER FIELDS ; 430 ; ARE USED FOR DEFAULTING PROCESS. ; 431 ; 432 .REGION/0,1377/2000,3777/1400,1777 ; 433 ;TRY AND KEEP STUFF OUT OF DROM SPACE ; 434 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 12 ; KS10.MIC[7,3] 14:54 7-JAN-1986 2901 REGISTER USAGE ; 435 .TOC "2901 REGISTER USAGE" ; 436 ; 437 ; !=========================================================================! ; 438 ;0: ! MAG (ONES IN BITS 1-36, REST ZERO) ! ; 439 ; !-------------------------------------------------------------------------! ; 440 ;1: ! PC (ADDRESS OF CURRENT INSTRUCTION + 1) ! ; 441 ; !-------------------------------------------------------------------------! ; 442 ;2: ! HR (CURRENT INSTRUCTION) ! ; 443 ; !-------------------------------------------------------------------------! ; 444 ;3: ! AR (TEMP -- MEM OP AT INST START) ! ; 445 ; !-------------------------------------------------------------------------! ; 446 ;4: ! ARX (TEMP -- LOW ORDER HALF OF DOUBLE PREC) ! ; 447 ; !-------------------------------------------------------------------------! ; 448 ;5: ! BR (TEMP) ! ; 449 ; !-------------------------------------------------------------------------! ; 450 ;6: ! BRX (TEMP -- LOW ORDER HALF OF DOUBLE PREC BR!BRX) ! ; 451 ; !-------------------------------------------------------------------------! ; 452 ;7: ! ONE (THE CONSTANT 1) ! ; 453 ; !-------------------------------------------------------------------------! ; 454 ;10: ! EBR (EXEC BASE REGISTER) ! ; 455 ; !-------------------------------------------------------------------------! ; 456 ;11: ! UBR (USER BASE REGISTER) ! ; 457 ; !-------------------------------------------------------------------------! ; 458 ;12: ! MASK (ONES IN BITS 0-35, ZERO IN -1, -2, 36 AND 37) ! ; 459 ; !-------------------------------------------------------------------------! ; 460 ;13: ! FLG (FLAG BITS) ! PAGE FAIL CODE ! ; 461 ; !-------------------------------------------------------------------------! ; 462 ;14: ! PI (PI SYSTEM STATUS REGISTER [RDPI]) ! ; 463 ; !-------------------------------------------------------------------------! ; 464 ;15: ! XWD1 (1 IN EACH HALF WORD) ! ; 465 ; !-------------------------------------------------------------------------! ; 466 ;16: ! T0 (TEMP) ! ; 467 ; !-------------------------------------------------------------------------! ; 468 ;17: ! T1 (TEMP) ! ; 469 ; !=========================================================================! ; 470 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 13 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- LISTING FORMAT ; 471 .TOC "MICROCODE FIELDS -- LISTING FORMAT" ; 472 ; 473 ; ; 3633 1561: ; 474 ; ; 3634 SUB: [AR]_AC-[AR], ; 475 ; ; 3635 AD FLAGS, 3T, ; 476 ; U 1561, 1500,2551,0303,0274,4463,7701,4200,0001,0001 ; 3636 EXIT ; 477 ; [--] [--] !!!! [][] !!![-][][-][]! !!! [----] ; 478 ; ! ! !!!! ! ! !!!! ! ! ! ! !!! ! ; 479 ; ! ! !!!! ! ! !!!! ! ! ! ! !!! +---- # (MAGIC NUMBER) ; 480 ; ! ! !!!! ! ! !!!! ! ! ! ! !!! ; 481 ; ! ! !!!! ! ! !!!! ! ! ! ! !!+------------- MULTI PREC, MULTI SHIFT, CALL (4S, 2S, 1S) ; 482 ; ! ! !!!! ! ! !!!! ! ! ! ! !! ; 483 ; ! ! !!!! ! ! !!!! ! ! ! ! !+-------------- FM WRITE, MEM, DIVIDE (4S, 2S, 1S) ; 484 ; ! ! !!!! ! ! !!!! ! ! ! ! ! ; 485 ; ! ! !!!! ! ! !!!! ! ! ! ! +--------------- CRY38, LOAD SC, LOAD FE (4S, 2S, 1S) ; 486 ; ! ! !!!! ! ! !!!! ! ! ! ! ; 487 ; ! ! !!!! ! ! !!!! ! ! ! +----------------- T ; 488 ; ! ! !!!! ! ! !!!! ! ! ! ; 489 ; ! ! !!!! ! ! !!!! ! ! +------------------- SKIP ; 490 ; ! ! !!!! ! ! !!!! ! ! ; 491 ; ! ! !!!! ! ! !!!! ! +---------------------- DISP ; 492 ; ! ! !!!! ! ! !!!! ! ; 493 ; ! ! !!!! ! ! !!!! +------------------------ SPEC ; 494 ; ! ! !!!! ! ! !!!! ; 495 ; ! ! !!!! ! ! !!!+--------------------------- CLOCKS & PARITY (CLKR, GENR, CHKR, CLKL, GENL, CHKL) ; 496 ; ! ! !!!! ! ! !!! ; 497 ; ! ! !!!! ! ! !!+---------------------------- DBM ; 498 ; ! ! !!!! ! ! !! ; 499 ; ! ! !!!! ! ! !+----------------------------- DBUS ; 500 ; ! ! !!!! ! ! ! ; 501 ; ! ! !!!! ! ! +------------------------------ RAM ADDRESS ; 502 ; ! ! !!!! ! ! ; 503 ; ! ! !!!! ! +--------------------------------- B ; 504 ; ! ! !!!! ! ; 505 ; ! ! !!!! +----------------------------------- A ; 506 ; ! ! !!!! ; 507 ; ! ! !!!+------------------------------------- DEST ; 508 ; ! ! !!! ; 509 ; ! ! !!+-------------------------------------- RSRC ; 510 ; ! ! !! ; 511 ; ! ! !+--------------------------------------- LSRC ] ; 512 ; ! ! ! ] - AD ; 513 ; ! ! +---------------------------------------- ALU ] ; 514 ; ! ! ; 515 ; ! +--------------------------------------------- J ; 516 ; ! ; 517 ; LOCATION OF THIS MICRO WORD ; 518 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 14 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- DATAPATH CHIP ; 519 .TOC "MICROCODE FIELDS -- DATAPATH CHIP" ; 520 ; 521 J/=<0:11>+ ;CRA1 ; 522 ;NEXT MICROCODE ADDRESS ; 523 ; 524 ;ALU FUNCTIONS ; 525 ; 526 ;NOTE: THE AD FIELD IS A 2 DIGIT FIELD. THE LEFT DIGIT IS THE ; 527 ; 2901 ALU FUNCTION. THE RIGHT DIGIT IS THE 2901 SRC CODE FOR ; 528 ; THE LEFT HALF. NORMALY THE RIGHT HALF SRC CODE IS THE SAME AS ; 529 ; THE LEFT HALF. ; 530 AD/=<12:17>D,44 ;DPE1 & DPE2 ; 531 A+Q=00 ; 532 A+B=01 ; 533 0+Q=02 ; 534 0+B=03 ; 535 0+A=04 ; 536 D+A=05 ; 537 D+Q=06 ; 538 0+D=07 ; 539 Q-A-.25=10 ; 540 B-A-.25=11 ; 541 Q-.25=12 ; 542 B-.25=13 ; 543 A-.25=14 ; 544 A-D-.25=15 ; 545 Q-D-.25=16 ; 546 -D-.25=17 ; 547 A-Q-.25=20 ; 548 A-B-.25=21 ; 549 -Q-.25=22 ; 550 -B-.25=23 ; 551 -A-.25=24 ; 552 D-A-.25=25 ; 553 D-Q-.25=26 ; 554 D-.25=27 ; 555 A.OR.Q=30 ; 556 A.OR.B=31 ; 557 Q=32 ; 558 B=33 ; 559 A=34 ; 560 D.OR.A=35 ; 561 D.OR.Q=36 ; 562 D=37 ; 563 A.AND.Q=40 ; 564 A.AND.B=41 ; 565 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 15 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- DATAPATH CHIP ; 566 ;MORE ALU FUNCTIONS ; 567 ; 568 ZERO=42 ; 569 ; ZERO=43 ; 570 ; ZERO=44 ; 571 D.AND.A=45 ; 572 D.AND.Q=46 ; 573 ; ZERO=47 ; 574 .NOT.A.AND.Q=50 ; 575 .NOT.A.AND.B=51 ; 576 ; Q=52 ; 577 ; B=53 ; 578 ; A=54 ; 579 .NOT.D.AND.A=55 ; 580 .NOT.D.AND.Q=56 ; 581 ; ZERO=57 ; 582 A.XOR.Q=60 ; 583 A.XOR.B=61 ; 584 ; Q=62 ; 585 ; B=63 ; 586 ; A=64 ; 587 D.XOR.A=65 ; 588 D.XOR.Q=66 ; 589 ; D=67 ; 590 A.EQV.Q=70 ; 591 A.EQV.B=71 ; 592 .NOT.Q=72 ; 593 .NOT.B=73 ; 594 .NOT.A=74 ; 595 D.EQV.A=75 ; 596 D.EQV.Q=76 ; 597 .NOT.D=77 ; 598 ; 599 ;THIS FIELD IS THE RIGHTMOST 3 BITS OF THE ; 600 ; AD FIELD. IT IS USED ONLY TO DEFAULT THE RSRC ; 601 ; FIELD. ; 602 LSRC/=<15:17> ;DPE1 ; 603 ; 604 ;THIS IS THE SOURCE FOR THE RIGHT HALF OF THE ; 605 ; DATA PATH. IT LETS US MAKE THE RIGHT AND LEFT ; 606 ; HALF WORDS DO SLIGHTLY DIFFERENT THINGS. ; 607 RSRC/=<18:20>F,LSRC ;DPE2 ; 608 AQ=0 ;A Q ; 609 AB=1 ;A B ; 610 0Q=2 ;0 Q ; 611 0B=3 ;0 B ; 612 0A=4 ;0 A ; 613 DA=5 ;D A ; 614 DQ=6 ;D Q ; 615 D0=7 ;D 0 ; 616 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 16 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- DATAPATH CHIP ; 617 ;DESTINATION CONTROL ; 618 ;SEE DPE1 AND DPE2 (2'S WEIGHT IS INVERTED ON DPE5) ; 619 DEST/=<21:23>D,3 ;DPE1 & DPE2 ; 620 A=0 ;A REG IS CHIP OUTPUT, AD IS WRITTEN ; 621 ; INTO REG FILE ; 622 AD=1 ;REG FILE GETS AD ; 623 Q_AD=2 ;REG FILE IS NOT LOADED ; 624 PASS=3 ;AD OUTPUT IS CHIP OUTPUT ; 625 ; Q AND REG FILE LEFT ALONE ; 626 Q_Q*2=4 ;ALSO REG FILE GETS AD*2 ; 627 AD*2=5 ;AND Q IS LEFT ALONE ; 628 Q_Q*.5=6 ;ALSO REG FILE GETS AD*.5 ; 629 AD*.5=7 ;AND Q IS LEFT ALONE ; 630 ; 631 ; <24:25> ;UNUSED ; 632 ; 633 A/=<26:29> ;DPE1 & DPE2 ; 634 MAG=0 ; 635 PC=1 ; 636 HR=2 ; 637 AR=3 ; 638 ARX=4 ; 639 BR=5 ; 640 BRX=6 ; 641 ONE=7 ; 642 EBR=10 ; 643 UBR=11 ; 644 MASK=12 ; 645 FLG=13 ; 646 PI=14 ; 647 XWD1=15 ; 648 T0=16 ; 649 T1=17 ; 650 ; 651 ; <30:31> ;UNUSED ; 652 ; 653 B/=<32:35>D,0 ;DPE1 & DPE2 ; 654 MAG=0 ; 655 PC=1 ; 656 HR=2 ; 657 AR=3 ; 658 ARX=4 ; 659 BR=5 ; 660 BRX=6 ; 661 ONE=7 ; 662 EBR=10 ; 663 UBR=11 ; 664 MASK=12 ; 665 FLG=13 ; 666 PI=14 ; 667 XWD1=15 ; 668 T0=16 ; 669 T1=17 ; 670 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 17 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- RAM FILE ADDRESS AND D-BUS ; 671 .TOC "MICROCODE FIELDS -- RAM FILE ADDRESS AND D-BUS" ; 672 ; 673 RAMADR/=<36:38>D,4 ;DPE6 ; 674 AC#=0 ;AC NUMBER ; 675 AC*#=1 ;AC .FN. # ; 676 XR#=2 ;INDEX REGISTER ; 677 VMA=4 ;VIRTUAL MEMORY REFERENCE ; 678 RAM=6 ;VMA SUPPLIES 10-BIT RAM ADDRESS ; 679 #=7 ;ABSOLUTE RAM FILE REFERENCE ; 680 ; 681 ; <39:39> ; 682 ; 683 ;LEFT HALF ON DPE3 AND RIGHT HALF ON DPE4 ; 684 DBUS/=<40:41>D,1 ;DPE3 & DPE4 ; 685 PC FLAGS=0 ;PC FLAGS IN LEFT HALF ; 686 PI NEW=0 ;NEW PI LEVEL IN BITS 19-21 ; 687 ; VMA=0 ;VMA IN BITS 27-35 ; 688 DP=1 ;DATA PATH ; 689 RAM=2 ;CACHE, AC'S AND WORKSPACE ; 690 DBM=3 ;DBM MIXER ; 691 ; 692 ;LEFT HALF ON DPM1 AND RIGHT HALF ON DPM2 ; 693 DBM/=<42:44>D,7 ;DPM1 & DPM2 ; 694 SCAD DIAG=0 ;(LH) SCAD DIAGNOSTIC ; 695 PF DISP=0 ;PAGE FAIL DISP IN BITS 18-21 ; 696 APR FLAGS=0 ;APR FLAGS IN BITS 22-35 ; 697 BYTES=1 ;5 COPIES OF SCAD 1-7 ; 698 EXP=2 ;LH=EXPONENT, RH=TIME FRACTION ; 699 DP=3 ;DATA PATH ; 700 DP SWAP=4 ;DATA PATH SWAPPED ; 701 VMA=5 ;VMA FLAGS,,VMA ; 702 MEM=6 ;MEMORY BUFFER ; 703 #=7 ;NUMBER FIELD IN BOTH HALVES ; 704 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 18 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- PARITY GENERATION & HALF WORD CONTROL ; 705 .TOC "MICROCODE FIELDS -- PARITY GENERATION & HALF WORD CONTROL" ; 706 ; 707 AD PARITY OK/=<108>D,0 ;**NOT STORED IN CRAM** ; 708 ;THIS BIT IS A 1 IF THE ALU IS DOING ; 709 ; SOMETHING WHICH DOES NOT INVALIDATE ; 710 ; PARITY. IT DOES NOT APPEAR IN THE ; 711 ; REAL MACHINE. WE JUST USE IT TO SET ; 712 ; THE DEFAULT FOR GENR & GENL ; 713 ; 714 CLKL/=<45:45>D,1 ;DPE5 ; 715 ;CLOCK THE LEFT HALF OF THE MACHINE ; 716 GENL/=<46:46>F,AD PARITY OK ;DPE4 FROM CRM2 PARITY EN LEFT H ; 717 ;STORE PARITY FOR 2901 LEFT ; 718 CHKL/=<47:47> ;DPE4 FROM CRM2 PARITY CHK LEFT H ; 719 ;CHECK LEFT HALF DBUS PARITY ; 720 ; 721 CLKR/=<48:48>D,1 ;DPE5 ; 722 ;CLOCK THE RIGHT HALF OF THE MACHINE ; 723 GENR/=<49:49>F,AD PARITY OK ;DPE4 FROM CRM2 PARITY EN RIGHT H ; 724 ;STORE PARITY FOR 2901 RIGHT ; 725 CHKR/=<50:50> ;DPE4 FROM CRM2 PARITY CHK RIGHT H ; 726 ;CHECK RIGHT HALF DBUS PARITY ; 727 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 19 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- SPEC ; 728 .TOC "MICROCODE FIELDS -- SPEC" ; 729 ; 730 ; 731 ; ; 732 ;THE FOLLOWING SPECIAL FUNCTION ARE DECODED ON DPE1, DPE5, AND DPMA: ; 733 ; !=========================================================================! ; 734 ; !S! EFFECT ! CRA6 SPEC ! CRA6 SPEC ! CRA6 SPEC ! ; 735 ; !P! ON SHIFT ! EN 40 ! EN 20 ! EN 10 ! ; 736 ; !E! PATHS ! E102 ON DPE5 ! E101 ON DPE5 ! E410 ON DPMA ! ; 737 ; !C! (SEE DPE1) ! ! E411 ON DPMA ! E113 ON CRA2 ! ; 738 ; !=========================================================================! ; 739 ; !0! NORMAL ! CRY 18 INH ! PREVIOUS ! # ! ; 740 ; !-------------------------------------------------------------------------! ; 741 ; !1! ZERO ! IR LOAD ! XR LOAD ! CLR 1 MSEC ! ; 742 ; !-------------------------------------------------------------------------! ; 743 ; !2! ONES ! ! ! CLR IO LATCH ! ; 744 ; !-------------------------------------------------------------------------! ; 745 ; !3! ROT ! PI LOAD ! APR FLAGS ! CLR IO BUSY ! ; 746 ; !-------------------------------------------------------------------------! ; 747 ; !4! ASHC ! ASH TEST ! SET SWEEP ! PAGE WRITE ! ; 748 ; !-------------------------------------------------------------------------! ; 749 ; !5! LSHC ! EXP TEST ! APR EN ! NICOND ! ; 750 ; !-------------------------------------------------------------------------! ; 751 ; !6! DIV ! PC FLAGS ! PXCT OFF ! PXCT EN ! ; 752 ; !-------------------------------------------------------------------------! ; 753 ; !7! ROTC ! AC BLOCKS EN ! MEM CLR ! MEM WAIT ! ; 754 ; !=========================================================================! ; 755 ; THE DPM BOARD USES THE SPEC FIELD TO CONTROL THE ; 756 ; DBM MIXER, AS FOLLOWS: ; 757 ; ; 758 ; !=====================================! ; 759 ; ! S ! ! ; 760 ; ! P ! ACTION WHEN DBM ! ; 761 ; ! E ! SELECTS DP ! ; 762 ; ! C ! GET DP BITS ! GET SCAD 1-7 ! ; 763 ; !=====================================! ; 764 ; ! 0 ! ALL ! NONE ! ; 765 ; !-------------------------------------! ; 766 ; ! 1 ! 7-35 ! 0-6 ! ; 767 ; !-------------------------------------! ; 768 ; ! 2 !0-6 AND 14-35 ! 7-13 ! ; 769 ; !-------------------------------------! ; 770 ; ! 3 !0-13 AND 21-35! 14-20 ! ; 771 ; !-------------------------------------! ; 772 ; ! 4 !0-20 AND 28-35! 21-27 ! ; 773 ; !-------------------------------------! ; 774 ; ! 5 ! 0-27 AND 35 ! 28-34 ! ; 775 ; !-------------------------------------! ; 776 ; ! 6 ! SAME AS ZERO ! ; 777 ; !-------------------------------------! ; 778 ; ! 7 ! SAME AS ZERO ! ; 779 ; !=====================================! ; 780 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 20 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- SPEC ; 781 ;THE SPEC FIELD IS DEFINED AS A 6-BIT FIELD. THE TOP 3 BITS ; 782 ; ARE SPEC SEL A, SPEC SEL B, AND SPEC SEL C. THE LOW 3 BITS ARE ; 783 ; THE SELECT CODE. ; 784 ; 785 SPEC/=<51:56>D,0 ;DPE1 & DPE5 & DPM1 & DPMA ; 786 #=10 ;DECODE # BITS ; 787 CLRCLK=11 ;CLEAR 1MS NICOND FLAG ; 788 CLR IO LATCH=12 ;CLEAR IO LATCH ; 789 CLR IO BUSY=13 ;CLEAR IO BUSY ; 790 LDPAGE=14 ;WRITE PAGE TABLE ; 791 NICOND=15 ;DOING NICOND DISPATCH ; 792 LDPXCT=16 ;LOAD PXCT FLAGS ; 793 WAIT=17 ;MEM WAIT ; 794 PREV=20 ;FORCE PREVIOUS CONTEXT ; 795 LOADXR=21 ;LOAD XR #, USES PXCT FIELD TO SELECT ; 796 ; CORRECT AC BLOCK ; 797 APR FLAGS=23 ;LOAD APR FLAGS ; 798 CLRCSH=24 ;CLEAR CACHE ; 799 APR EN=25 ;SET APR ENABLES ; 800 MEMCLR=27 ;CLEAR PAGE FAULT CONDITION ; 801 SWEEP=34 ;SET SWEEP ; 802 PXCT OFF=36 ;TURN OFF THE EFFECT OF PXCT ; 803 INHCRY18=40 ;INHIBIT CARRY INTO LEFT HALF ; 804 LOADIR=41 ;LOAD THE IR ; 805 LDPI=43 ;LOAD PI SYSTEM ; 806 ASHOV=44 ;TEST RESULT OF ASH ; 807 EXPTST=45 ;TEST RESULT OF FLOATING POINT ; 808 FLAGS=46 ;CHANGE PC FLAGS ; 809 LDACBLK=47 ;LOAD AC BLOCK NUMBERS ; 810 LDINST=61 ;LOAD INSTRUCTION ; 811 ; 812 ;THE SPEC FIELD IS REDEFINED WHEN USED FOR BYTE MODE STUFF ; 813 BYTE/=<54:56> ;DPM1 (SPEC SEL) ; 814 BYTE1=1 ; 815 BYTE2=2 ; 816 BYTE3=3 ; 817 BYTE4=4 ; 818 BYTE5=5 ; 819 ; 820 ;THE SPEC FIELD IS REDEFINED WHEN USED TO CONTROL SHIFT PATHS ; 821 SHSTYLE/=<54:56> ;DPE1 (SPEC SEL) ; 822 NORM=0 ;2 40-BIT REGISTERS ; 823 ZERO=1 ;SHIFT ZERO INTO 36 BITS (ASH TOP 2901) ; 824 ONES=2 ;SHIFT IN ONES ; 825 ROT=3 ;ROTATE ; 826 ASHC=4 ;ASHC ; 827 LSHC=5 ;LSHC ; 828 DIV=6 ;SPECIAL DIVIDE ; 829 ROTC=7 ;ROTATE DOUBLE ; 830 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 21 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- DISPATCH ; 831 .TOC "MICROCODE FIELDS -- DISPATCH" ; 832 ; !=======================================================! ; 833 ; ! D ! CRA1 ! CRA1 ! DPEA ! ; 834 ; ! I ! DISP ! DISP ! DISP ! ; 835 ; ! S ! 10 ! 20 ! 40 ! ; 836 ; ! P ! ! ! ! ; 837 ; !=======================================================! ; 838 ; ! 0 ! DIAG ADR ! DIAG ADR ! 0 ! ; 839 ; !-------------------------------------------------------! ; 840 ; ! 1 ! RETURN ! RETURN ! DP 18-21 ! ; 841 ; !-------------------------------------------------------! ; 842 ; ! 2 ! MULTIPLY ! J ! J ! ; 843 ; !-------------------------------------------------------! ; 844 ; ! 3 ! PAGE FAIL ! AREAD ! AREAD ! ; 845 ; !-------------------------------------------------------! ; 846 ; ! 4 ! NICOND ! NOT USABLE ! NORM ! ; 847 ; !-------------------------------------------------------! ; 848 ; ! 5 ! BYTE ! NOT USABLE ! DP 32-35 ! ; 849 ; !-------------------------------------------------------! ; 850 ; ! 6 ! EA MODE ! NOT USABLE ! DROM A ! ; 851 ; !-------------------------------------------------------! ; 852 ; ! 7 ! SCAD ! NOT USABLE ! DROM B ! ; 853 ; !=======================================================! ; 854 ;NOTE: DISP EN 40 & DISP EN 10 ONLY CONTROL THE LOW 4 BITS OF THE ; 855 ; JUMP ADDRESS. DISP EN 20 ONLY CONTROLS THE HI 7 BITS. TO DO ; 856 ; SOMETHING TO ALL 11 BITS BOTH 20 & 40 OR 20 & 10 MUST BE ENABLED. ; 857 ; 858 DISP/=<57:62>D,70 ;CRA1 & DPEA ; 859 CONSOLE=00 ;CONSOLE DISPATCH ; 860 DROM=12 ;DROM ; 861 AREAD=13 ;AREAD ; 862 DP LEFT=31 ;DP 18-21 ; 863 NORM=34 ;NORMALIZE ; 864 DP=35 ;DP 32-35 ; 865 ADISP=36 ;DROM A FIELD ; 866 BDISP=37 ;DROM B FIELD ; 867 RETURN=41 ;RETURN ; 868 MUL=62 ;MULTIPLY ; 869 PAGE FAIL=63 ;PAGE FAIL ; 870 NICOND=64 ;NEXT INSTRUCTION DISPATCH ; 871 BYTE=65 ;BYTE SIZE AND POSITION ; 872 EAMODE=66 ;EFFECTIVE ADDRESS MODE ; 873 SCAD0=67 ;J!2 IF SCAD BIT 0 = 1 ; 874 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 22 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- SKIP ; 875 .TOC "MICROCODE FIELDS -- SKIP" ; 876 ; !=======================================================! ; 877 ; ! S ! CRA2 ! DPEA ! DPEA ! ; 878 ; ! K ! SKIP ! SKIP ! SKIP ! ; 879 ; ! I ! 10 ! 20 ! 40 ! ; 880 ; ! P ! ! ! ! ; 881 ; !=======================================================! ; 882 ; ! 0 ! 0 ! 0 ! 0 ! ; 883 ; !-------------------------------------------------------! ; 884 ; ! 1 ! TRAP CYCLE ! CRY 02 ! CARRY OUT ! ; 885 ; !-------------------------------------------------------! ; 886 ; ! 2 ! AD=0 ! ADL SIGN ! ADL=0 ! ; 887 ; !-------------------------------------------------------! ; 888 ; ! 3 ! SC SIGN ! ADR SIGN ! ADR=0 ! ; 889 ; !-------------------------------------------------------! ; 890 ; ! 4 ! EXECUTE ! USER IOT ! -USER ! ; 891 ; !-------------------------------------------------------! ; 892 ; ! 5 ! -BUS IO BUSY ! JFCL SKIP ! FPD FLAG ! ; 893 ; !-------------------------------------------------------! ; 894 ; ! 6 ! -CONTINUE ! CRY 01 ! AC # IS ZERO ! ; 895 ; !-------------------------------------------------------! ; 896 ; ! 7 ! -1 MSEC ! TXXX ! INTERRUPT REQ ! ; 897 ; !=======================================================! ; 898 ; 899 SKIP/=<63:68>D,70 ;CRA2 & DPEA ; 900 IOLGL=04 ;(.NOT.USER)!(USER IOT)!(CONSOLE EXECUTE MODE) ; 901 LLE=12 ;AD LEFT .LE. 0 ; 902 CRY0=31 ;AD CRY -2 ; 903 ADLEQ0=32 ;ADDER LEFT = 0 ; 904 ADREQ0=33 ;ADDER RIGHT = 0 ; 905 KERNEL=34 ;.NOT. USER ; 906 FPD=35 ;FIRST PART DONE ; 907 AC0=36 ;AC NUMBER IS ZERO ; 908 INT=37 ;INTERRUPT REQUEST ; 909 LE=42 ;(AD SIGN)!(AD.EQ.0) ; 910 CRY2=51 ;AD CRY 02 ; 911 DP0=52 ;AD SIGN ; 912 DP18=53 ;AD BIT 18 ; 913 IOT=54 ;USER IOT ; 914 JFCL=55 ;JFCL SKIP ; 915 CRY1=56 ;AD CRY 1 ; 916 TXXX=57 ;TEST INSTRUCTION SHOULD SKIP ; 917 TRAP CYCLE=61 ;THIS INSTRUCTION IS THE RESULT OF A ; 918 ; TRAP 1, 2, OR 3 ; 919 ADEQ0=62 ;AD.EQ.0 ; 920 SC=63 ;SC SIGN BIT ; 921 EXECUTE=64 ;CONSOLE EXECUTE MODE ; 922 -IO BUSY=65 ;.NOT. I/O LATCH ; 923 -CONTINUE=66 ;.NOT. CONTINUE ; 924 -1 MS=67 ;.NOT. 1 MS. TIMER ; 925 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 23 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- TIME CONTROL ; 926 .TOC "MICROCODE FIELDS -- TIME CONTROL" ; 927 ; 928 DT/=<109:111>D,0 ;**NOT STORED IN CRAM** ; 929 ;DEFAULT TIME FIELD (USED IN MACROS) ; 930 ; CAN BE OVERRIDDEN IN MACRO CALL ; 931 2T=0 ; 932 3T=1 ; 933 4T=2 ; 934 5T=3 ; 935 ; 936 ; 937 T/=<69:71>F,DT ;CSL5 (E601) ; 938 ;CLOCK TICKS MINUS TWO REQUIRED TO ; 939 ; DO A MICRO INSTRUCTION ; 940 2T=0 ;TWO TICKS ; 941 3T=1 ;THREE TICKS ; 942 4T=2 ;FOUR TICKS ; 943 5T=3 ;FIVE TICKS ; 944 ; 945 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 24 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- RANDOM CONTROL BITS ; 946 .TOC "MICROCODE FIELDS -- RANDOM CONTROL BITS" ; 947 ; 948 CRY38/=<72> ;DPE5 ; 949 ;INJECT A CARRY INTO THE 2901 ADDER ; 950 LOADSC/=<73> ;DPM4 ; 951 ;LOAD THE STEP COUNTER FROM THE SCAD ; 952 LOADFE/=<74> ;DPM4 ; 953 ;LOAD THE FE REGISTER FROM THE SCAD ; 954 FMWRITE/=<75> ;DPE5 (E302) ; 955 ;WRITE THE RAM FILE. ; 956 MEM/=<76> ;DPM5 (E612) & DPE5 (E205) ; 957 ;START (OR COMPLETE) A MEMORY OR I/O CYCLE UNDER ; 958 ; CONTROL OF THE NUMBER FIELD. ; 959 DIVIDE/=<77> ;DPE5 ; 960 ;THIS MICROINSTRUCTION IS DOING A DIVIDE ; 961 MULTI PREC/=<78> ;DPE5 ; 962 ;MULTIPRECISION STEP IN DIVIDE, DFAD, DFSB ; 963 MULTI SHIFT/=<79> ;CSL5 (HAS NOTHING TO DO WITH DPE5 MULTI SHIFT) ; 964 ;FAST SHIFT ; 965 CALL/=<80> ;CRA2 (STACK IS ON CRA3) ; 966 ;THIS IS A CALL ; 967 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 25 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 968 .TOC "MICROCODE FIELDS -- NUMBER FIELD" ; 969 ; 970 ;HERE IS THE GENERAL FIELD ; 971 #/=<90:107> ;MANY PLACES ; 972 ; 973 ;# REDEFINED WHEN USED AS SCAD CONTROL: ; 974 SCAD/=<90:92> ;DPM3 ; 975 A*2=0 ; 976 A.OR.B=1 ; 977 A-B-1=2 ; 978 A-B=3 ; 979 A+B=4 ; 980 A.AND.B=5 ; 981 A-1=6 ; 982 A=7 ; 983 SCADA/=<93:95> ;DPM3 ; 984 SC=0 ; 985 S#=1 ; 986 PTR44=2 ;44 AND BIT 6 (SEE DPM3) ; 987 BYTE1=3 ; 988 BYTE2=4 ; 989 BYTE3=5 ; 990 BYTE4=6 ; 991 BYTE5=7 ; 992 SCADB/=<96:97> ;DPM3 ; 993 FE=0 ; 994 EXP=1 ; 995 SHIFT=2 ; 996 SIZE=3 ; 997 S#/=<98:107> ;DPM3 ; 998 ; 999 ;# REDEFINED WHEN USED AS STATE REGISTER CONTROL: ; 1000 STATE/=<90:107> ;NOT USED BY HARDWARE ; 1001 SIMPLE=0 ;SIMPLE INSTRUCTIONS ; 1002 BLT=1 ;BLT IN PROGRESS ; 1003 MAP=400002 ;MAP IN PROGRESS ; 1004 SRC=3 ;MOVE STRING SOURCE IN PROGRESS ; 1005 DST=4 ;MOVE STRING FILL IN PROGRESS ; 1006 SRC+DST=5 ;MOVE STRING DEST IN PROGRESS ; 1007 DSTF=6 ;FILLING DEST ; 1008 CVTDB=7 ;CONVERT DEC TO BIN ; 1009 COMP-DST=10 ;COMPARE DEST ; 1010 EDIT-SRC=11 ;EDIT SOURCE ; 1011 EDIT-DST=12 ;EDIT DEST ; 1012 EDIT-S+D=13 ;BOTH SRC AND DST POINTERS ; 1013 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 26 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 1014 ;# REDEFINED WHEN USED AS WORSPACE ADDRESS ; 1015 ; 1016 WORK/=<98:107> ;DPE6 ; 1017 BADW0=160 ;AC BLK 7 WORD 0 (BAD DATA FROM MEMORY) ; 1018 BADW1=161 ;AC BLK 7 WORD 1 (BAD DATA FROM MEMORY) ; 1019 MUL=200 ;TEMP FOR MULTIPLY ; 1020 DIV=201 ;TEMP FOR DIVIDE ; 1021 SV.VMA=210 ;SAVE VMA ; 1022 SV.AR=211 ;SAVE AR ; 1023 SV.ARX=212 ;SAVE ARX ; 1024 SV.BR=213 ;SAVE BR ; 1025 SV.BRX=214 ;SAVE BRX ; 1026 SBR=215 ;SPT BASE REGISTER ; 1027 CBR=216 ;CST BASE ADDRESS ; 1028 CSTM=217 ;CST MASK ; 1029 PUR=220 ;PROCESS USE REGISTER ; 1030 ADJP=221 ;"P" FOR ADJBP ; 1031 ADJS=222 ;"S" FOR ADJBP ; 1032 ADJPTR=223 ;BYTE POINTER FOR ADJBP ; 1033 ADJQ1=224 ;TEMP FOR ADJBP ; 1034 ADJR2=225 ;TEMP FOR ADJBP ; 1035 ADJBPW=226 ;(BYTES/WORD) FOR ADJBP ; 1036 HSBADR=227 ;ADDRESS OF HALT STATUS BLOCK ; 1037 APR=230 ;APR ENABLES ; 1038 ;THE FOLLOWING WORDS ARE USED BY EXTEND INSTRUCTION ; 1039 E0=240 ;ORIGINAL EFFECTIVE ADDRESS ; 1040 E1=241 ;EFFECTIVE ADDRESS OF WORD AT E0 ; 1041 SLEN=242 ;SOURCE LENGTH ; 1042 MSK=243 ;BYTE MASK ; 1043 FILL=244 ;FILL BYTE ; 1044 CMS=245 ;SRC BYTE IN STRING COMPARE ; 1045 FSIG=246 ;PLACE TO SAVE ARX WHILE STORING ; 1046 ; THE FLOAT CHAR ; 1047 BDH=247 ;BINARY BEING CONVERTED TO ; 1048 BDL=250 ; DECIMAL ; 1049 ; 1050 ;TIMER STUFF ; 1051 TIME0=300 ;HIGH ORDER 36 BITS OF TIME ; 1052 TIME1=301 ;LOW ORDER 36 BITS OF TIME ; 1053 PERIOD=302 ;INTERRUPT PERIOD ; 1054 TTG=303 ;TIME TO GO TO NEXT INTERRUPT ; 1055 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 27 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 1056 ;DDIV STUFF ; 1057 AC0=314 ; 1058 AC1=315 ; 1059 AC2=316 ; 1060 AC3=317 ; 1061 DDIV SGN=320 ; 1062 DVSOR H=321 ; 1063 DVSOR L=322 ; 1064 ;POWERS OF TEN ; 1065 DECLO=344 ;LOW WORD ; 1066 DECHI=373 ;HIGH WORD ; 1067 ; 1068 YSAVE=422 ;Y OF LAST INDIRECT POINTER ; 1069 PTA.E=423 ;ADDRESS OF EXEC PAGE MAP (NOT PROCESS TABLE) ; 1070 PTA.U=424 ;ADDRESS OF USER PAGE MAP ; 1071 TRAPPC=425 ;SAVED PC FROM TRAP CYCLE ; 1072 SV.AR1=426 ;ANOTHER PLACE TO SAVE AR ; 1073 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 28 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 1074 ;# REDEFINED WHEN USED AS PC FLAG CONTROL (ALL ON DPE9) ; 1075 ; 1076 SETOV/=<90> ;DPE9 ; 1077 ;SET ARITHMETIC OVERFLOW ; 1078 SETFOV/=<91> ;SET FLOATING OVERFLOW ; 1079 SETNDV/=<92> ;SET NO DIVIDE ; 1080 ; 1081 ;--------------------------------------------------------------------- ; 1082 ; 1083 CLRFPD/=<93> ;CLEAR FIRST PART DONE ; 1084 SETFPD/=<94> ;SET FIRST PART DONE ; 1085 HOLD USER/=<95> ;WHEN THIS BIT IS SET IT: ; 1086 ; 1. PREVENTS SETTING USER IOT IN USER MODE ; 1087 ; 2. PREVENTS CLEARING USER IN USER MODE ; 1088 ; 1089 ;--------------------------------------------------------------------- ; 1090 ; 1091 ; <96> ;SPARE ; 1092 TRAP2/=<97> ;SET TRAP 2 ; 1093 TRAP1/=<98> ;SET TRAP 1 ; 1094 ; 1095 ;--------------------------------------------------------------------- ; 1096 ; 1097 LD PCU/=<99> ;LOAD PCU FROM USER ; 1098 ; <100> ;SPARE ; 1099 ; <101> ;SPARE ; 1100 ; 1101 ;--------------------------------------------------------------------- ; 1102 ; 1103 ; <102> ;SPARE ; 1104 ; <103> ;SPARE ; 1105 JFCLFLG/=<104> ;DO A JFCL INSTRUCTION ; 1106 ; 1107 ;--------------------------------------------------------------------- ; 1108 ; 1109 LD FLAGS/=<105> ;LOAD FLAGS FROM DP ; 1110 ; <106> ; 1111 ADFLGS/=<107> ;UPDATE CARRY FLAGS ; 1112 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 29 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 1113 ;# REDEFINED WHEN USED AS MEMORY CYCLE CONTROL ; 1114 ; 1115 FORCE USER/=<90> ;FORCE USER MODE REFERENCE ; 1116 FORCE EXEC/=<91> ;FORCE EXEC MODE REFERENCE ; 1117 ; (DOES NOT WORK UNDER PXCT) ; 1118 FETCH/=<92> ;THIS IS AN INSTRUCTION FETCH ; 1119 ; 1120 ;--------------------------------------------------------------------- ; 1121 ; 1122 READ CYCLE/=<93> ;SELECT A READ CYCLE ; 1123 WRITE TEST/=<94> ;PAGE FAILE IF NOT WRITTEN ; 1124 WRITE CYCLE/=<95> ;SELECT A MEMORY WRITE CYCLE ; 1125 ; 1126 ;--------------------------------------------------------------------- ; 1127 ; 1128 ; <96> ;SPARE BIT ; 1129 DONT CACHE/=<97> ;DO NOT LOOK IN CACHE ; 1130 PHYSICAL/=<98> ;DO NOT INVOKE PAGING HARDWARE ; 1131 ; 1132 ;--------------------------------------------------------------------- ; 1133 ; 1134 PXCT/=<99:101> ;WHICH PXCT BITS TO LOOK AT ; 1135 CURRENT=0 ; 1136 E1=1 ; 1137 D1=3 ; 1138 BIS-SRC-EA=4 ; 1139 E2=5 ; 1140 BIS-DST-EA=6 ; 1141 D2=7 ; 1142 ; 1143 ;--------------------------------------------------------------------- ; 1144 ; 1145 AREAD/=<102> ;LET DROM SELECT SYSLE TYPE AND VMA LOAD ; 1146 DP FUNC/=<103> ;IGNORE # BITS 0-11 AND USE DP 0-13 INSTEAD ; 1147 ; DP9 MEANS "FORCE PREVIOUS" ; 1148 LDVMA/=<104> ;LOAD THE VMA ; 1149 ; 1150 ;--------------------------------------------------------------------- ; 1151 ; 1152 EXT ADR/=<105> ;PUT VMA BITS 14-17 ONTO BUS ; 1153 WAIT/=<106> ;START A MEMORY OR I/O CYCLE ; 1154 BWRITE/=<107> ;START A MEMORY CYCLE IF DROM ASKS FOR IT ; 1155 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 30 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 1156 ;THESE BITS ARE USED ONLY TO SETUP DP FOR A DP FUNCTION ; 1157 ; 1158 ; <99> ;PREVIOUS ; 1159 IO CYCLE/=<100> ;THIS IS AN I/O CYCLE ; 1160 WRU CYCLE/=<101> ;WHO ARE YOU CYCLE ; 1161 ; 1162 ;--------------------------------------------------------------------- ; 1163 ; 1164 VECTOR CYCLE/=<102> ;READ INTERRUPT VECTOR ; 1165 IO BYTE/=<103> ;BYTE CYCLE ; 1166 ; <104> ; 1167 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 31 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 1168 ;# REDEFINED WHEN USED AS PI RIGHT BITS ; 1169 PI.ZER/=<90:92> ;ZEROS ; 1170 PI.IP1/=<93> ;PI 1 IN PROG ; 1171 PI.IP2/=<94> ; 1172 PI.IP3/=<95> ; 1173 PI.IP4/=<96> ; 1174 PI.IP5/=<97> ; 1175 PI.IP6/=<98> ; 1176 PI.IP7/=<99> ; 1177 PI.ON/=<100> ;SYSTEM IS ON; ; 1178 PI.CO1/=<101> ;CHAN 1 IS ON ; 1179 PI.CO2/=<102> ; 1180 I.CO3/=<103> ; 1181 I.CO4/=<104> ; 1182 I.CO5/=<105> ; 1183 I.CO6/=<106> ; 1184 I.CO7/=<107> ; 1185 ; 1186 ;# REDEFINED WHEN USED AS WRPI DATA ; 1187 PI.MBZ/=<90:93> ;MUST BE ZERO ; 1188 PI.DIR/=<94> ;DROP INTERRUPT REQUESTS ; 1189 PI.CLR/=<95> ;CLEAR SYSTEM ; 1190 PI.REQ/=<96> ;REQUEST INTERRUPT ; 1191 PI.TCN/=<97> ;TURN CHANNEL ON ; 1192 PI.TCF/=<98> ;TURN CHANNEL OFF ; 1193 PI.TSF/=<99> ;TURN SYSTEM OFF ; 1194 PI.TSN/=<100> ;TURN SYSTEM ON ; 1195 PI.SC1/=<101> ;SELECT CHANNEL 1 ; 1196 PI.SC2/=<102> ; 1197 PI.SC3/=<103> ; 1198 PI.SC4/=<104> ; 1199 PI.SC5/=<105> ; 1200 PI.SC6/=<106> ; 1201 PI.SC7/=<107> ; 1202 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 32 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 1203 ;# REDEFINED WHEN USED AS AC CONTROL ; 1204 ; 1205 ; 1206 ;THIS FIELD CONTROLS THE INPUT TO A 74LS181 ON DPE6. THE NUMBER ; 1207 ; FIELD HAS THIS FORMAT IN <98:107>: ; 1208 ; ; 1209 ; !-----!-----!-----!-----!-----!-----!-----!-----!-----!-----! ; 1210 ; !CARRY! S8 ! S4 ! S2 ! S1 ! MODE! B8 ! B4 ! B2 ! B1 ! ; 1211 ; ! IN ! FUNCTION ! ! DATA INPUTS ! ; 1212 ; !-----!-----------------------!-----!-----------------------! ; 1213 ; ; 1214 ; 1215 ACALU/=<98:103> ; 1216 B=25 ; 1217 AC+N=62 ; 1218 ACN/=<104:107> ; 1219 ;AC NAMES FOR STRING INSTRUCTIONS ; 1220 SRCLEN=0 ;SOURCE LENGTH ; 1221 SRCP=1 ;SOURCE POINTER ; 1222 DLEN=3 ;DEST LENGTH ; 1223 DSTP=4 ;DEST POINTER ; 1224 MARK=3 ;POINTER TO MARK ; 1225 BIN0=3 ;HIGH WORD OF BINARY ; 1226 BIN1=4 ;LOW WORD OF BINARY ; 1227 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 33 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 1228 ;# FIELD REDEFINED WHEN USE AS APRID DATA ; 1229 MICROCODE OPTIONS/=<90:98> ; 1230 ;100 - NON-STANDARD MICROCODE ; 1231 ;200 - NO CST AT ALL ; 1232 ;400 - INHIBIT CST UPDATE IS AVAILABLE ; 1233 ;040 - UBABLT INSTRUCTIONS ARE PRESENT ; 1234 ;020 - KI PAGING IS PRESENT ; 1235 ;010 - KL PAGING IS PRESENT ; 1236 MICROCODE OPTION(INHCST)/=<90> ;;1237 .IF/INHCST ;;1238 OPT=1 ; 1239 .IFNOT/INHCST ; 1240 OPT=0 ; 1241 .ENDIF/INHCST ; 1242 MICROCODE OPTION(NOCST)/=<91> ;;1243 .IF/NOCST ;;1244 OPT=1 ; 1245 .IFNOT/NOCST ; 1246 OPT=0 ; 1247 .ENDIF/NOCST ; 1248 MICROCODE OPTION(NONSTD)/=<92> ;;1249 .IF/NONSTD ;;1250 OPT=1 ; 1251 .IFNOT/NONSTD ; 1252 OPT=0 ; 1253 .ENDIF/NONSTD ; 1254 MICROCODE OPTION(UBABLT)/=<93> ;;1255 .IF/UBABLT ;;1256 OPT=1 ; 1257 .IFNOT/UBABLT ; 1258 OPT=0 ; 1259 .ENDIF/UBABLT ; 1260 MICROCODE OPTION(KIPAGE)/=<94> ; 1261 .IF/KIPAGE ; 1262 OPT=1 ;;1263 .IFNOT/KIPAGE ;;1264 OPT=0 ; 1265 .ENDIF/KIPAGE ; 1266 MICROCODE OPTION(KLPAGE)/=<95> ; 1267 .IF/KLPAGE ; 1268 OPT=1 ;;1269 .IFNOT/KLPAGE ;;1270 OPT=0 ; 1271 .ENDIF/KLPAGE ; 1272 ; 1273 MICROCODE VERSION/=<99:107> ; 1274 UCV=130 ; 1275 ; 1276 MICROCODE RELEASE(MAJOR)/=<99:104> ; 1277 UCR=2 ;MAJOR VERSION NUMBER (1,2,3,....) ; 1278 ; 1279 MICROCODE RELEASE(MINOR)/=<105:107> ; 1280 UCR=0 ;MINOR VERSION NUMBER (.1,.2,.3,...) ; 1281 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 34 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MICROCODE FIELDS -- NUMBER FIELD ; 1282 ;# FIELD REDEFINED WHEN USED AS A HALT CODE ; 1283 ; 1284 HALT/=<90:107> ; 1285 ;CODES 0 TO 77 ARE "NORMAL" HALTS ; 1286 POWER=0 ;POWER UP ; 1287 HALT=1 ;HALT INSTRUCTION ; 1288 CSL=2 ;CONSOLE HALT ; 1289 ;CODES 100 TO 777 ARE SOFTWARE ERRORS ; 1290 IOPF=100 ;I/O PAGE FAIL ; 1291 ILLII=101 ;ILLEGAL INTERRUPT INSTRUCTION ; 1292 ILLINT=102 ;BAD POINTER TO UNIBUS INTERRUPT VECTOR ; 1293 ;CODES 1000 TO 1777 ARE HARDWARE ERRORS ; 1294 BW14=1000 ;ILLEGAL BWRITE FUNCTION (BAD DROM) ; 1295 NICOND 5=1004 ;ILLEGAL NICOND DISPATCH ; 1296 MULERR=1005 ;VALUE COMPUTED FOR 10**21 WAS WRONG ;;1297 .IFNOT/FULL ;;1298 PAGEF=1777 ;PAGE FAIL IN SMALL MICROCODE ; 1299 .ENDIF/FULL ; 1300 ; 1301 ; 1302 ; 1303 ;# FIELD REDEFINED WHEN USED AS FLG BITS ; 1304 ; 1305 FLG.W/=<94> ;W BIT FROM PAGE MAP ; 1306 FLG.PI/=<95> ;PI CYCLE ; 1307 FLG.C/=<96> ;CACHE BIT FROM PAGE MAP ; 1308 FLG.SN/=<97> ;SPECIAL NEGATE IN FDV & DFDV ; 1309 ; 1310 ;RIGHT HALF OF FLG USED TO RECOVER FROM PAGE FAILS ; 1311 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 35 ; KS10.MIC[7,3] 14:54 7-JAN-1986 DISPATCH ROM DEFINITIONS ; 1312 .TOC "DISPATCH ROM DEFINITIONS" ; 1313 ; 1314 ;ALL ON DPEA ; 1315 ; 1316 .DCODE ; 1317 A/=<2:5> ;OPERAND FETCH MODE ; 1318 READ=0 ;READ ; 1319 WRITE=1 ;WRITE ; 1320 DREAD=2 ;DOUBLE READ ; 1321 DBLAC=3 ;DOUBLE AC ; 1322 SHIFT=4 ;SIMPLE SHIFT ; 1323 DSHIFT=5 ;DOUBLE SHIFT ; 1324 FPI=6 ;FLOATING POINT IMMEDIATE ; 1325 FP=7 ;FLOATING POINT ; 1326 RD-PF=10 ;READ, THEN START PREFETCH ; 1327 DFP=11 ;DOUBLE FLOATING POINT ; 1328 IOT=12 ;CHECK FOR IO LEGAL THEN SAME AS I ; 1329 ; 1330 B/=<8:11> ;STORE RESULTS AS ; 1331 SELF=4 ;SELF ; 1332 DBLAC=5 ;DOUBLE AC ; 1333 DBLB=6 ;DOUBLE BOTH ; 1334 AC=15 ;AC ; 1335 MEM=16 ;MEMORY ; 1336 BOTH=17 ;BOTH ; 1337 ; 1338 ;B-FIELD WHEN USED IN FLOATING POINT OPERATIONS ; 1339 ROUND/=<8> ;ROUND THE RESULT ; 1340 MODE/=<9> ;SEPARATE ADD/SUB & MUL/DIV ETC. ; 1341 FL-B/=<10:11> ;STORE RESULTS AS ; 1342 AC=1 ;AC ; 1343 MEM=2 ;MEMORY ; 1344 BOTH=3 ;BOTH ; 1345 ; 1346 J/=<12:23> ;DISPATCH ADDRESS (MUST BE 1400 TO 1777) ; 1347 ; 1348 ACDISP/=<24> ;DISPATCH ON AC FIELD ; 1349 I/=<25> ;IMMEDIATE DISPATCH. DISP/AREAD DOES A DISP/DROM ; 1350 ; IF THIS BIT IS SET. ; 1351 READ/=<26> ;START A READ AT AREAD ; 1352 TEST/=<27> ;START A WRITE TEST AT AREAD ; 1353 COND FUNC/=<28> ;START A MEMORY CYCLE ON BWRITE ; 1354 VMA/=<29>D,1 ;LOAD THE VMA ON AREAD ; 1355 WRITE/=<30> ;START A WRITE ON AREAD ; 1356 .UCODE ; 1357 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 36 ; KS10.MIC[7,3] 14:54 7-JAN-1986 HOW TO READ MACROS ; 1358 .TOC "HOW TO READ MACROS" ; 1359 ; ; 1360 ; 1.0 REGISTER TRANSFER MACROS ; 1361 ; ; 1362 ; MOST MACROS USED IN THE KS10 ARE USED TO OPERATE ON DATA IN (OR FROM/TO) 2901 ; 1363 ; REGISTERS. THE NAMES OF THE 2901 REGISTERS ARE MACRO PARAMETERS AND ARE ; 1364 ; ENCLOSED IN []. A TYPICAL MACRO IS: ; 1365 ; ; 1366 ; [AR]_[AR]+[BR] ; 1367 ; ; 1368 ; THE SYMBOL _ IS PRONOUNCED "GETS". THE ABOVE MACRO WOULD BE READ "THE AR GETS ; 1369 ; THE AR PLUS THE BR". ; 1370 ; ; 1371 ; IF A MACRO DOES NOT HAVE A _ IN IT, THERE IS NO RESULT STORED. THUS, [AR]-[BR] ; 1372 ; JUST COMPARES THE AR AND THE BR AND ALLOWS FOR SKIPS ON THE VARIOUS ALU BITS. ; 1373 ; ; 1374 ; ; 1375 ; ; 1376 ; 1.1 SPECIAL SYMBOLS ; 1377 ; ; 1378 ; THERE ARE A BUNCH OF SYMBOLS USED IN THE MACROS WHICH ARE NOT 2901 REGISTERS. ; 1379 ; THEY ARE DEFINED HERE: ; 1380 ; ; 1381 ; 1. AC -- THE AC SELECTED BY THE CURRENT INSTRUCTION. SEE DPEA ; 1382 ; ; 1383 ; 2. AC[] -- AC+N. AC[1] IS AC+1, AC[2] IS AC+2, ETC. ; 1384 ; ; 1385 ; 3. APR -- THE APR FLAGS FROM DPMA ; 1386 ; ; 1387 ; 4. EA -- THE EFFECTIVE ADDRESS. THAT IS, 0 IN THE LEFT HALF AND THE ; 1388 ; CONTENTS OF THE HR IN THE RIGHT HALF. ; 1389 ; ; 1390 ; 5. EXP -- THE F.P. EXPONENT FROM THE SCAD. [AR]_EXP WILL TAKE THE ; 1391 ; EXPONENT OUT OF THE FE AND PUT IT BACK INTO THE NUMBER IN THE AR. ; 1392 ; ; 1393 ; 6. FE -- THE FE REGISTER ; 1394 ; ; 1395 ; 7. FLAGS -- THE PC FLAGS (FROM DPE9) IN THE LEFT HALF. ; 1396 ; ; 1397 ; 8. Q -- THE Q REGISTER ; 1398 ; ; 1399 ; 9. RAM -- THE RAM FILE, RAM ADDRESS IS IN THE VMA. ; 1400 ; ; 1401 ; 10. P -- THE P FIELD OF THE BYTE POINTER. SAME IDEA AS EXP. ; 1402 ; ; 1403 ; 11. TIME -- THE 1MS. TIMER ; 1404 ; ; 1405 ; 12. VMA -- THE VMA. WHEN READ IT INCLUDES THE VMA FLAGS ; 1406 ; ; 1407 ; 13. XR -- INDEX REGISTER ; 1408 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 37 ; KS10.MIC[7,3] 14:54 7-JAN-1986 HOW TO READ MACROS ; 1409 ; 14. XWD -- HALF WORD. USED TO GENERATE CONSTANTS. FOR EXAMPLE, [AR]_0 XWD ; 1410 ; [40] WOULD LOAD THE CONSTANT 40 (OCTAL) INTO THE AR. ; 1411 ; ; 1412 ; 15. +SIGN AND -SIGN -- SIGN BITS USED TO SIGN SMEAR F.P. NUMBERS. FOR ; 1413 ; EXAMPLE, [AR]_+SIGN WOULD CLEAR AR BITS 0 TO 8. ; 1414 ; ; 1415 ; 16. WORK[] -- LOCATIONS IN THE WORKSPACE USED AS SCRATCH SPACE. FOR ; 1416 ; EXAMPLE, [AR]_WORK[CSTM] WOULD LOAD THE AR WITH THE CST MASK FROM THE ; 1417 ; RAM. CSTM IS A SYMBOL DEFINED IN THE WORK FIELD. ; 1418 ; ; 1419 ; ; 1420 ; ; 1421 ; ; 1422 ; 1.2 LONG ; 1423 ; ; 1424 ; LONG IS USED ON SHIFT OPERATIONS TO INDICATE THAT THE Q REGISTER IS ALSO ; 1425 ; SHIFTED. THIS SAYS NOTHING ABOUT HOW THE SHIFT PATHS ARE CONNECTED UP. ; 1426 ; ; 1427 ; ; 1428 ; ; 1429 ; 2.0 MEMORY MACROS ; 1430 ; ; 1431 ; MEMORY IS INDICATED BY THE SYMBOL "MEM". WHEN WE ARE WAITING FOR DATA FROM ; 1432 ; MEMORY THE "MEM READ" MACRO IS USED. WHEN WE ARE SENDING DATA TO MEMORY, THE ; 1433 ; "MEM WRITE" MACRO IS USED. EXAMPLE, ; 1434 ; MEM READ, ;WAIT FOR MEMORY ; 1435 ; [AR]_MEM ;LOAD DATA INTO AR ; 1436 ; VMA_ IS USED THE LOAD THE VMA. THUS, VMA_[PC] LOADS THE VMA FROM THE PC. ; 1437 ; ; 1438 ; ; 1439 ; ; 1440 ; 3.0 TIME CONTROL ; 1441 ; ; 1442 ; THERE ARE 2 SETS OF MACROS USED FOR TIME CONTROL. THE FIRST, SELECTS THE RAM ; 1443 ; ADDRESS TO SPEED UP THE NEXT INSTRUCTION. THESE MACROS ARE AC, AC[], XR, VMA, ; 1444 ; WORK[]. THE SECOND, SETS THE TIME FIELD. THESE ARE 2T, 3T, 4T, AND 5T TO ; 1445 ; SELECT 2, 3, 4, OR 5 TICKS. ; 1446 ; ; 1447 ; ; 1448 ; ; 1449 ; 4.0 SCAD MACROS ; 1450 ; ; 1451 ; THE SCAD MACROS LOOK LIKE THE 2901 MACROS EXECPT NO [] ARE REQUIRED. THERE ARE ; 1452 ; ONLY A FEW SYMBOLS USED. ; 1453 ; ; 1454 ; 1. FE -- THE FE REGISTER ; 1455 ; ; 1456 ; 2. SC -- THE SC REGISTER ; 1457 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 38 ; KS10.MIC[7,3] 14:54 7-JAN-1986 HOW TO READ MACROS ; 1458 ; 3. EXP -- THE EXPONENT FROM A F.P. NUMBER. FOR EXAMPLE FE_EXP LOADS THE ; 1459 ; FE FROM DP BITS 1-8. ; 1460 ; ; 1461 ; 4. SHIFT -- THE SHIFT COUNT FROM SHIFT INSTRUCTIONS. THAT IS DP BITS 18 ; 1462 ; AND 28-35. ; 1463 ; ; 1464 ; 5. S# -- THE SMALL NUMBER. THE 10 BIT MAGIC NUMBER INPUT TO THE SCADA ; 1465 ; MIXER. ; 1466 ; ; 1467 ; ; 1468 ; ; 1469 ; ; 1470 ; 5.0 CONTROL MACROS ; 1471 ; ; 1472 ; ALL CONTROL MACROS LOOK LIKE ENGLISH COMMANDS. SOME EXAMPLES, ; 1473 ; HOLD LEFT ;DO NOT CLOCK LEFT HALF OF DP ; 1474 ; SET APR ENABLES ;LOAD APR ENABLES FROM DP ; 1475 ; SET NO DIVIDE ;SET NO DIVIDE PC FLAG ; 1476 ; ; 1477 ; ; 1478 ; ; 1479 ; 6.0 SKIPS ; 1480 ; ; 1481 ; ALL SKIPS CAUSE THE NEXT MICRO INSTRUCTION TO COME FROM THE ODD WORD OF AN ; 1482 ; EVEN/ODD PAIR. THE MACROS HAVE THE FORMAT OF SKIP COND. THEY SKIP IF CONDITION ; 1483 ; IS TRUE. SOME EXAMPLES, ; 1484 ; SKIP AD.EQ.0 ;SKIP IF ADDER OUTPUT IS ZERO ; 1485 ; SKIP IRPT ;SKIP IF INTERRUPT IS PENDING ; 1486 ; ; 1487 ; ; 1488 ; ; 1489 ; 7.0 DISPATCH MACROS ; 1490 ; ; 1491 ; DISPATCH MACROS CAUSE THE MACHINE TO GO TO ONE OF MANY PLACES. IN MOST CASES ; 1492 ; THEY HAVE THE WORD "DISP" IN THE NAME OF THE MACRO. FOR EXAMPLE, MUL DISP, BYTE ; 1493 ; DISP. ; 1494 ; ; 1495 ; ; 1496 ; ; 1497 ; 8.0 SUPER MACROS ; 1498 ; ; 1499 ; THERE ARE PLACES WHERE ONE MICRO INSTRUCTION IS USED IN MANY PLACES. FOR ; 1500 ; EXAMPLE, MANY PLACES DETECT ILLEGAL OPERATIONS AND WANT TO GENERATE A TRAP TO ; 1501 ; THE MONITOR. WE COULD WRITE ; 1502 ; J/UUO ; 1503 ; BUT THIS WASTES A MICRO STEP DOING A USELESS JUMP. INSTEAD WE WRITE, ; 1504 ; UUO ; 1505 ; THIS MACRO IS THE FIRST STEP OF THE UUO ROUTINE AND JUMPS TO THE SECOND ; 1506 ; INSTRUCTION. WE WRITE THE EXPANSION OF THE UUO MACRO AS THE FIRST INSTRUCTION ; 1507 ; OF THE UUO ROUTINE SO THAT THE READER CAN SEE WHAT IT DOES. SOME EXAMPLES OF ; 1508 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 39 ; KS10.MIC[7,3] 14:54 7-JAN-1986 HOW TO READ MACROS ; 1509 ; SUPER MACROS ARE: ; 1510 ; PAGE FAIL TRAP ;GENERATE A PAGE FAIL TRAP ; 1511 ; DONE ;THIS INSTRUCTION IS NOW COMPLETE ; 1512 ; ; USED WITH A SKIP OR DISP WHERE ; 1513 ; ; SOME PATHS ARE NOP'S ; 1514 ; HALT [] ;JUMP TO HALT LOOP. ARGUMENT IS A ; 1515 ; ; CODE ; 1516 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 40 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- DATA PATH CHIP -- GENERAL ; 1517 .TOC "MACROS -- DATA PATH CHIP -- GENERAL" ; 1518 ; 1519 .NOT.[] "AD/.NOT.A,A/@1" ; 1520 []+[] "AD/A+B,A/@1,B/@2" ; 1521 []-[] "AD/A-B-.25,A/@1,B/@2,ADD .25" ; 1522 []-# "AD/A-D-.25,DBUS/DBM,DBM/#,A/@1,ADD .25" ; 1523 [].AND.# "AD/D.AND.A,DBUS/DBM,DBM/#,A/@1" ; 1524 [].AND.Q "AD/A.AND.Q,A/@1,DEST/PASS" ; 1525 [].AND.[] "AD/A.AND.B,A/@2,B/@1,DEST/PASS" ; 1526 [].AND.NOT.[] "AD/.NOT.A.AND.B,A/@2,B/@1,DEST/PASS" ; 1527 [].OR.[] "AD/A.OR.B,A/@2,B/@1,DEST/PASS" ; 1528 [].XOR.# "AD/D.XOR.A,DBUS/DBM,DBM/#,A/@1" ; 1529 [].XOR.[] "AD/A.XOR.B,A/@2,B/@1,DEST/PASS" ; 1530 []_#-[] "AD/D-A-.25,DEST/AD,A/@2,B/@1,DBUS/DBM,DBM/#,ADD .25" ; 1531 []_# "AD/D,DBUS/DBM,DBM/#,DEST/AD,B/@1" ; 1532 []_-1 "AD/-A-.25,A/ONE,DEST/AD,B/@1,ADD .25" ; 1533 []_-2 "AD/-A-.25,DEST/AD*2,A/ONE,B/@1,ADD .25" ; 1534 []_-Q "AD/-Q-.25,DEST/AD,B/@1,ADD .25" ; 1535 []_-Q*2 "AD/-Q-.25,DEST/AD*2,B/@1,ADD .25" ; 1536 []_-Q*.5 "AD/-Q-.25,DEST/AD*.5,B/@1,ADD .25" ; 1537 []_-[] "AD/-A-.25,A/@2,DEST/AD,B/@1,ADD .25" ; 1538 []_-[]-.25 "AD/-A-.25,A/@2,DEST/AD,B/@1" ; 1539 []_-[]*2 "AD/-A-.25,A/@2,DEST/AD*2,B/@1,ADD .25" ; 1540 []_.NOT.AC "AD/.NOT.D,DBUS/RAM,RAMADR/AC#,DEST/AD,B/@1" ; 1541 []_.NOT.AC[] "AD/.NOT.D,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@2,DEST/AD,B/@1,DT/3T" ; 1542 []_.NOT.Q "AD/.NOT.Q,DEST/AD,B/@1" ; 1543 []_.NOT.[] "AD/.NOT.A,A/@2,DEST/AD,B/@1" ; 1544 []_0 "AD/ZERO,DEST/AD,B/@1" ; 1545 []_0*.5 LONG "AD/ZERO,DEST/Q_Q*.5,B/@1" ; 1546 []_0 XWD [] "AD/47,DEST/AD,B/@1,DBM/#,DBUS/DBM,#/@2,RSRC/DA,A/MASK" ; 1547 []_AC "AD/D,DBUS/RAM,RAMADR/AC#,DEST/AD,B/@1,AD PARITY" ; 1548 []_-AC "AD/-D-.25,DBUS/RAM,RAMADR/AC#,DEST/AD,B/@1,ADD .25" ; 1549 []_-AC[] "AD/-D-.25,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@2,DEST/AD,B/@1,ADD .25,DT/3T" ; 1550 []_AC*.5 "AD/D,DBUS/RAM,RAMADR/AC#,DEST/AD*.5,B/@1,DT/3T" ; 1551 []_AC*.5 LONG "AD/D,DBUS/RAM,RAMADR/AC#,DEST/Q_Q*.5,B/@1,DT/3T" ; 1552 []_AC*2 "AD/D,DBUS/RAM,RAMADR/AC#,DEST/AD*2,B/@1,DT/3T" ; 1553 []_AC+1 "AD/D+A,DBUS/RAM,RAMADR/AC#,A/ONE,DEST/AD,B/@1" ; 1554 []_AC+1000001 "AD/D+A,DBUS/RAM,RAMADR/AC#,A/XWD1,DEST/AD,B/@1" ; 1555 []_AC+[] "AD/D+A,A/@2,DBUS/RAM,RAMADR/AC#,DEST/AD,B/@1,DT/3T" ; 1556 []_AC-1 "AD/D-A-.25,DBUS/RAM,RAMADR/AC#,A/ONE,DEST/AD,B/@1,ADD .25" ; 1557 []_AC-[] "AD/D-A-.25,A/@2,DBUS/RAM,RAMADR/AC#,DEST/AD,B/@1,ADD .25" ; 1558 []_AC-[]-.25 "AD/D-A-.25,A/@2,DBUS/RAM,RAMADR/AC#,DEST/AD,B/@1" ; 1559 []_AC[]-[] "AD/D-A-.25,A/@3,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@2,DEST/AD,B/@1,ADD .25,DT/3T" ; 1560 []_AC[]-1 "AD/D-A-.25,A/ONE,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@2,DEST/AD,B/@1,ADD .25,DT/3T" ; 1561 []_AC[].AND.[] "AD/D.AND.A,A/@3,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@2,DEST/AD,B/@1,DT/3T" ; 1562 []_AC.AND.MASK "AD/D.AND.A,A/MASK,DBUS/RAM,RAMADR/AC#,DEST/AD,B/@1,AD PARITY" ; 1563 []_AC[] "AD/D,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@2,DEST/AD,B/@1,AD PARITY,DT/3T" ; 1564 []_AC[]*2 "AD/D,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@2,DEST/AD*2,B/@1,AD PARITY,DT/3T" ; 1565 []_AC[]*.5 "AD/D,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@2,DEST/AD*.5,B/@1,AD PARITY,DT/3T" ; 1566 []_APR "AD/D,DBUS/DBM,DBM/APR FLAGS,DEST/AD,B/@1,DT/3T" ; 1567 []_CURRENT AC [] "AD/D,DBUS/RAM,RAMADR/#,ACALU/B,ACN/@2,DEST/AD,B/@1,AD PARITY,DT/3T" ; 1568 []_EA FROM [] "AD/57,RSRC/0A,A/@2,DEST/AD,B/@1" ; 1569 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 41 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- DATA PATH CHIP -- GENERAL ; 1570 []_EA "AD/57,RSRC/0A,A/HR,DEST/AD,B/@1" ; 1571 []_EXP "AD/D,DBUS/DBM,DBM/EXP,A/@1,B/@1,DEST/A,SCAD/A+B,SCADA/S#,S#/0,SCADB/FE,HOLD RIGHT,EXP TEST" ; 1572 []_FE "AD/D,DEST/AD*.5,B/@1,DBUS/DBM,DBM/DP,SCAD/A+B,SCADA/S#,S#/0,SCADB/FE,BYTE/BYTE5" ; 1573 []_FLAGS "AD/D.AND.A,DBUS/PC FLAGS,A/MASK,DEST/AD,B/@1,RSRC/0Q" ; 1574 []_P "AD/D,DEST/A,A/@1,B/@1,DBUS/DBM,DBM/DP,BYTE/BYTE1,SCAD/A+B,SCADA/S#,S#/0,SCADB/FE" ; 1575 []_PC WITH FLAGS "AD/D,DBUS/PC FLAGS,RSRC/0A,A/PC,DEST/AD,B/@1" ; 1576 []_Q "AD/Q,DEST/AD,B/@1" ; 1577 []_Q*.5 "AD/Q,DEST/AD*.5,B/@1" ; 1578 []_Q*2 "AD/Q,DEST/AD*2,B/@1" ; 1579 []_Q*2 LONG "AD/Q,DEST/Q_Q*2,B/@1" ; 1580 []_Q+1 "AD/A+Q,A/ONE,DEST/AD,B/@1" ; 1581 []_RAM "AD/D,DBUS/RAM,RAMADR/RAM,DEST/AD,B/@1,AD PARITY" ; 1582 []_TIME "AD/44,RSRC/DA,A/MASK,DBUS/DBM,DBM/EXP,DEST/AD,B/@1" ; 1583 []_VMA "AD/D,DEST/AD,B/@1,DBUS/DBM,DBM/VMA" ; 1584 []_XR "AD/D,DBUS/RAM,RAMADR/XR#,DEST/AD,B/@1" ; 1585 []_[] "AD/A,A/@2,DEST/AD,B/@1" ; 1586 []_[] SWAP "AD/D,DBUS/DBM,DBM/DP SWAP,DEST/A,A/@2,B/@1" ; 1587 []_[] XWD 0 "AD/45,DEST/AD,B/@1,DBM/#,DBUS/DBM,#/@2,RSRC/D0,A/MASK" ; 1588 []_[]*.5 "AD/A,A/@2,DEST/AD*.5,B/@1" ; 1589 []_[]*.5 LONG "AD/A,A/@2,DEST/Q_Q*.5,B/@1" ; 1590 []_[]*2 "AD/A,A/@2,DEST/AD*2,B/@1" ; 1591 []_[]*2 LONG "AD/A,A/@2,DEST/Q_Q*2,B/@1" ; 1592 []_[]*4 "AD/A+B,A/@2,B/@1,DEST/AD*2" ; 1593 []_[]+# "AD/D+A,DBUS/DBM,DBM/#,A/@2,DEST/AD,B/@1" ; 1594 []_[]+.25 "AD/0+A,A/@2,DEST/AD,B/@1, ADD .25" ; 1595 []_[]+0 "AD/0+A,A/@2,DEST/AD,B/@1" ; 1596 []_[]+1 "AD/A+B,A/ONE,B/@1,B/@2,DEST/AD" ; 1597 []_[]+1000001 "AD/D+A,A/@2,DBUS/DBM,DBM/#,#/1,DEST/AD,B/@1" ; 1598 []_[]+AC "AD/D+A,A/@2,DBUS/RAM,RAMADR/AC#,DEST/AD,B/@1" ; 1599 []_[]+AC[] "AD/D+A,A/@2,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@3,DEST/AD,B/@1,DT/3T" ; 1600 []_[]+Q "AD/A+Q,A/@2,DEST/AD,B/@1" ; 1601 []_[]+RAM "AD/D+A,A/@2,DBUS/RAM,RAMADR/RAM,DEST/AD,B/@1" ; 1602 []_[]+XR "AD/D+A,DBUS/RAM,RAMADR/XR#,A/@2,DEST/AD,B/@1,HOLD LEFT" ; 1603 []_[]+[] "AD/A+B,A/@3,B/@1,B/@2,DEST/AD" ; 1604 []_[]+[]+.25 "AD/A+B,A/@3,B/@1,B/@2,DEST/AD, ADD .25" ; 1605 []_[]-# "AD/A-D-.25,DBUS/DBM,DBM/#,A/@2,DEST/AD,B/@1, ADD .25" ; 1606 []_[]-1 "AD/B-A-.25,B/@1,A/ONE,DEST/AD,ADD .25" ; 1607 []_[]-1000001 "AD/A-D-.25,A/@2,DBUS/DBM,DBM/#,#/1,DEST/AD,B/@1,ADD .25" ; 1608 []_[]-AC "AD/A-D-.25,A/@2,DBUS/RAM,RAMADR/AC#,DEST/AD,B/@1,ADD .25" ; 1609 []_[]-RAM "AD/A-D-.25,A/@2,DBUS/RAM,RAMADR/RAM,DEST/AD,B/@1,ADD .25" ; 1610 []_[]-[] "AD/B-A-.25,B/@1,B/@2,A/@3,DEST/AD,ADD .25" ; 1611 []_[]-[] REV "AD/A-B-.25,B/@1,B/@3,A/@2,DEST/AD,ADD .25" ; 1612 []_[].AND.# "AD/D.AND.A,DBUS/DBM,DBM/#,DEST/AD,A/@2,B/@1" ; 1613 []_[].AND.# CLR LH "AD/ZERO,RSRC/DA,DBUS/DBM,DBM/#,DEST/AD,A/@2,B/@1" ; 1614 []_[].AND.# CLR RH "AD/D.AND.A,RSRC/0Q,DBUS/DBM,DBM/#,DEST/AD,A/@2,B/@1" ; 1615 []_(AC[].AND.[])*.5 "AD/D.AND.A,DEST/AD*.5,A/@3,B/@1,RAMADR/AC*#,DBUS/RAM,ACALU/AC+N,ACN/@2" ; 1616 []_(Q+1)*.5 "AD/A+Q,A/ONE,DEST/AD*.5,B/@1" ; 1617 []_(#-[])*2 "AD/D-A-.25,DEST/AD*2,A/@2,B/@1,DBUS/DBM,DBM/#,ADD .25" ; 1618 []_(-[])*.5 "AD/-A-.25,A/@2,DEST/AD*.5,B/@1,ADD .25" ; 1619 []_(-[]-.25)*.5 LONG "AD/-A-.25,A/@2,DEST/Q_Q*.5,B/@1" ; 1620 []_(-[]-.25)*2 LONG "AD/-A-.25,A/@2,DEST/Q_Q*2,B/@1" ; 1621 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 42 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- DATA PATH CHIP -- GENERAL ; 1622 []_([].AND.#)*.5 "AD/D.AND.A,DBUS/DBM,DBM/#,DEST/AD*.5,A/@2,B/@1" ; 1623 []_([].AND.#)*2 "AD/D.AND.A,DBUS/DBM,DBM/#,DEST/AD*2,A/@2,B/@1" ; 1624 []_([].AND.NOT.#)*.5 "AD/.NOT.D.AND.A,DBUS/DBM,DBM/#,DEST/AD*.5,A/@2,B/@1" ; 1625 []_([].AND.NOT.#)*2 "AD/.NOT.D.AND.A,DBUS/DBM,DBM/#,DEST/AD*2,A/@2,B/@1" ; 1626 []_([].AND.[])*.5 "AD/A.AND.B,DEST/AD*.5,A/@3,B/@1,B/@2" ; 1627 []_([].AND.[])*2 "AD/A.AND.B,DEST/AD*2,A/@3,B/@1,B/@2" ; 1628 []_([].OR.#)*.5 "AD/D.OR.A,DBUS/DBM,DBM/#,DEST/AD*.5,A/@2,B/@1" ; 1629 []_([].OR.#)*2 "AD/D.OR.A,DBUS/DBM,DBM/#,DEST/AD*2,A/@2,B/@1" ; 1630 []_([]+#)*2 "AD/D+A,DBUS/DBM,DBM/#,DEST/AD*2,A/@2,B/@1" ; 1631 []_([]+1)*2 "AD/A+B,A/ONE,B/@1,B/@2,DEST/AD*2" ; 1632 []_([]+[])*.5 LONG "AD/A+B,A/@3,B/@1,B/@2,DEST/Q_Q*.5" ; 1633 []_([]+[])*2 LONG "AD/A+B,A/@3,B/@1,B/@2,DEST/Q_Q*2" ; 1634 []_([]-[])*.5 LONG "AD/B-A-.25,A/@3,B/@1,B/@2,DEST/Q_Q*.5, ADD .25" ; 1635 []_([]-[])*2 LONG "AD/B-A-.25,A/@3,B/@1,B/@2,DEST/Q_Q*2, ADD .25" ; 1636 []_([]+[]+.25)*.5 LONG "AD/A+B,A/@3,B/@1,B/@2,DEST/Q_Q*.5, ADD .25" ; 1637 []_[].AND.AC "AD/D.AND.A,DBUS/RAM,RAMADR/AC#,A/@2,DEST/AD,B/@1" ; 1638 []_[].AND.NOT.# "AD/.NOT.D.AND.A,DBUS/DBM,DBM/#,A/@2,DEST/AD,B/@1" ; 1639 []_[].AND.NOT.[] "AD/.NOT.A.AND.B,DEST/AD,B/@1,B/@2,A/@3" ; 1640 []_[].AND.NOT.AC "AD/.NOT.D.AND.A,DBUS/RAM,RAMADR/AC#,A/@2,DEST/AD,B/@1" ; 1641 []_[].AND.Q "AD/A.AND.Q,A/@2,DEST/AD,B/@1" ; 1642 []_[].AND.[] "AD/A.AND.B,A/@3,B/@1,B/@2,DEST/AD" ; 1643 []_[].EQV.AC "AD/D.EQV.A,DBUS/RAM,RAMADR/AC#,A/@2,DEST/AD,B/@1" ; 1644 []_[].EQV.Q "AD/A.EQV.Q,A/@2,DEST/AD,B/@1" ; 1645 []_[].OR.# "AD/D.OR.A,DBUS/DBM,DBM/#,A/@2,DEST/AD,B/@1" ; 1646 []_[].OR.AC "AD/D.OR.A,DBUS/RAM,RAMADR/AC#,A/@2,DEST/AD,B/@1" ; 1647 []_[].OR.FLAGS "AD/D.OR.A,DBUS/PC FLAGS,RSRC/0A,A/@1,DEST/AD,B/@1" ; 1648 []_[].OR.[] "AD/A.OR.B,A/@3,B/@2,B/@1,DEST/AD" ; 1649 []_[].XOR.# "AD/D.XOR.A,DBUS/DBM,DBM/#,DEST/AD,A/@2,B/@1" ; 1650 []_[].XOR.AC "AD/D.XOR.A,DBUS/RAM,RAMADR/AC#,A/@1,DEST/AD,B/@2" ; 1651 []_[].XOR.[] "AD/A.XOR.B,A/@3,B/@1,B/@2,DEST/AD" ; 1652 ; 1653 [] LEFT_0 "AD/57,RSRC/0B,DEST/AD,B/@1" ; 1654 [] RIGHT_0 "AD/53,RSRC/D0,DEST/AD,B/@1" ; 1655 [] LEFT_-1 "AD/54,RSRC/0B,DEST/AD,A/MASK,B/@1" ; 1656 [] RIGHT_-1 "AD/53,RSRC/0A,DEST/AD,A/MASK,B/@1" ; 1657 ; 1658 ; 1659 []_+SIGN "[@1]_[@1].AND.#, #/777, HOLD RIGHT" ; 1660 []_-SIGN "[@1]_[@1].OR.#, #/777000, HOLD RIGHT" ; 1661 ;THE FOLLOWING 2 MACROS ARE USED IN DOUBLE FLOATING STUFF ; 1662 ; THEY ASSUME THAT THE OPERAND HAS BEEN SHIFTED RIGHT 1 PLACE. ; 1663 ; THEY SHIFT 1 MORE PLACE ; 1664 []_+SIGN*.5 "AD/.NOT.D.AND.A,A/@1,B/@1,DEST/AD*.5,DBUS/DBM,DBM/#,#/777400,RSRC/0A" ; 1665 []_-SIGN*.5 "AD/D.OR.A,A/@1,B/@1,DEST/AD*.5,DBUS/DBM,DBM/#,#/777400,RSRC/0A" ; 1666 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 43 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- DATA PATH CHIP -- Q ; 1667 .TOC "MACROS -- DATA PATH CHIP -- Q" ; 1668 ; 1669 Q-[] "AD/Q-A-.25,A/@1,ADD .25" ; 1670 Q.AND.NOT.[] "AD/.NOT.A.AND.Q,A/@1,DEST/PASS" ; 1671 Q_[] "AD/A,DEST/Q_AD,A/@1" ; 1672 Q_[]-[] "AD/A-B-.25,A/@1,B/@2,DEST/Q_AD,ADD .25" ; 1673 Q_[]+[] "AD/A+B,A/@1,B/@2,DEST/Q_AD" ; 1674 Q_[].AND.[] "AD/A.AND.B,A/@1,B/@2,DEST/Q_AD" ; 1675 Q_.NOT.AC[] "AD/.NOT.D,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DEST/Q_AD,DT/3T" ; 1676 Q_-[] "AD/-A-.25,DEST/Q_AD,A/@1, ADD .25" ; 1677 Q_-1 "Q_-[ONE]" ; 1678 Q_-AC[] "AD/-D-.25,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DEST/Q_AD,ADD .25,DT/3T" ; 1679 Q_-Q "AD/-Q-.25,ADD .25,DEST/Q_AD" ; 1680 Q_AC "AD/D,DBUS/RAM,RAMADR/AC#,DEST/Q_AD,CHK PARITY" ; 1681 Q_AC[] "AD/D,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DEST/Q_AD,CHK PARITY,DT/3T" ; 1682 Q_AC[].AND.MASK "AD/D.AND.A,A/MASK,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DEST/Q_AD,CHK PARITY,DT/3T" ; 1683 Q_AC[].AND.[] "AD/D.AND.A,A/@2,DBUS/RAM,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DEST/Q_AD,CHK PARITY,DT/3T" ; 1684 Q_.NOT.Q "AD/.NOT.Q,DEST/Q_AD" ; 1685 Q_# "AD/D,DBUS/DBM,DBM/#,DEST/Q_AD" ; 1686 Q_0 "AD/ZERO,DEST/Q_AD" ; 1687 Q_0 XWD [] "AD/47,DEST/Q_AD,DBM/#,DBUS/DBM,#/@1,RSRC/DA,A/MASK" ; 1688 Q_Q+.25 "AD/0+Q,DEST/Q_AD,ADD .25" ; 1689 Q_Q+1 "AD/A+Q,A/ONE,DEST/Q_AD" ; 1690 Q_Q-1 "AD/Q-A-.25,A/ONE,DEST/Q_AD, ADD .25" ; 1691 Q_Q+AC "AD/D+Q,DBUS/RAM,RAMADR/AC#,DEST/Q_AD" ; 1692 Q_Q*.5 "[MAG]_[MASK]*.5 LONG, SHSTYLE/NORM" ; 1693 Q_Q*2 "[MASK]_[MAG]*2 LONG, SHSTYLE/NORM" ; 1694 Q_Q.OR.# "AD/D.OR.Q,DBUS/DBM,DBM/#,DEST/Q_AD" ; 1695 Q_Q.AND.# "AD/D.AND.Q,DBUS/DBM,DBM/#,DEST/Q_AD" ; 1696 Q_Q.AND.[] "AD/A.AND.Q,A/@1,DEST/Q_AD" ; 1697 Q_Q.AND.NOT.[] "AD/.NOT.A.AND.Q,A/@1,DEST/Q_AD" ; 1698 Q_Q+[] "AD/A+Q,A/@1,DEST/Q_AD" ; 1699 Q_[].AND.Q "AD/A.AND.Q,A/@1,DEST/Q_AD" ; 1700 Q_[].OR.Q "AD/A.OR.Q,A/@1,DEST/Q_AD" ; 1701 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 44 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- DATA PATH CHIP -- MISC. ; 1702 .TOC "MACROS -- DATA PATH CHIP -- MISC." ; 1703 ; 1704 CLEAR []0 "AD/D.AND.A,A/@1,DBUS/DBM,DBM/#,#/377777,DEST/AD,B/@1,HOLD RIGHT" ; 1705 CLEAR ARX0 "CLEAR [ARX]0" ; 1706 ; 1707 ;CYCLE CHIP REGISTERS THRU AD SO WE CAN TEST BITS ; 1708 READ XR "AD/D,DBUS/RAM,RAMADR/XR#" ; 1709 READ [] "AD/B,B/@1" ; 1710 READ Q "AD/Q" ; 1711 ; 1712 ;TEST BITS IN REGISTERS (SKIP IF ZERO) ; 1713 TR [] "AD/D.AND.A,DBUS/DBM,DBM/#,A/@1,SKIP ADR.EQ.0,DT/3T" ; 1714 TL [] "AD/D.AND.A,DBUS/DBM,DBM/#,A/@1,SKIP ADL.EQ.0,DT/3T" ; 1715 ; 1716 ; 1717 ;CAUSE BITS -2 AND -1 TO MATCH BIT 0. ; 1718 FIX [] SIGN "AD/D,DEST/A,A/@1,B/@1,DBUS/DP,HOLD RIGHT" ; 1719 ; 1720 ;GENERATE A MASK IN Q AND ZERO A 2901 REGISTER ; 1721 GEN MSK [] "AD/ZERO,DEST/Q_Q*2,B/@1,ONES" ; 1722 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 45 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- STORE IN AC ; 1723 .TOC "MACROS -- STORE IN AC" ; 1724 ; 1725 FM WRITE "FMWRITE/1" ; 1726 ; 1727 AC[]_[] VIA AD "AD/B,DEST/PASS,B/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE,CHK PARITY" ; 1728 AC_[] VIA AD "AD/B,DEST/PASS,B/@1,RAMADR/AC#,DBUS/DP,FM WRITE,CHK PARITY" ; 1729 AC[]_[] "AD/A,DEST/A,B/@2,A/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP, FM WRITE" ; 1730 AC[]_[] TEST "AD/D,DBUS/DP,DEST/A,B/@2,A/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP, FM WRITE" ; 1731 AC[]_[]+1 "AD/A+B,DEST/PASS,A/ONE,B/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE" ; 1732 AC[]_[]*2 "AD/A+B,DEST/PASS,A/@2,B/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE" ; 1733 AC_[] "AD/A,DEST/A,B/@1,A/@1,RAMADR/AC#,DBUS/DP, FM WRITE" ; 1734 AC_[] TEST "AD/D,DBUS/DP,DEST/A,B/@1,A/@1,RAMADR/AC#,DBUS/DP, FM WRITE" ; 1735 AC_[]+1 "AD/A+B,DEST/PASS,A/ONE,B/@1,RAMADR/AC#, FM WRITE" ; 1736 AC_[]+Q "AD/A+Q,DEST/PASS,A/@1,B/@1,RAMADR/AC#, FM WRITE" ; 1737 AC[]_[]+Q "AD/A+Q,DEST/PASS,A/@2,B/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1, FM WRITE" ; 1738 AC[]_[]-[] "AD/A-B-.25,DEST/PASS,B/@3,A/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE,ADD .25" ; 1739 AC[]_[]+[] "AD/A+B,DEST/PASS,B/@3,A/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE" ; 1740 AC_[]+[] "AD/A+B,DEST/PASS,B/@2,A/@1,RAMADR/AC#,DBUS/DP,FM WRITE" ; 1741 AC[]_[].AND.[] "AD/A.AND.B,DEST/PASS,B/@3,A/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE" ; 1742 AC[]_Q.AND.[] "AD/A.AND.Q,DEST/PASS,A/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE" ; 1743 AC[]_[].EQV.Q "AD/A.EQV.Q,DEST/PASS,A/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE" ; 1744 AC[]_-[] "AD/-B-.25,DEST/PASS,B/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE,ADD .25" ; 1745 AC_-[] "AD/-A-.25,DEST/PASS,A/@1,RAMADR/AC#,DBUS/DP, ADD .25,FM WRITE" ; 1746 AC_[].OR.[] "AD/A.OR.B,A/@1,B/@2,RAMADR/AC#,DBUS/DP, FM WRITE" ; 1747 AC[]_.NOT.[] "AD/.NOT.B,DEST/PASS,B/@2,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE" ; 1748 AC_.NOT.[] "AD/.NOT.B,DEST/PASS,B/@1,RAMADR/AC#,DBUS/DP,FM WRITE" ; 1749 AC[]_-Q "AD/-Q-.25,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE,ADD .25" ; 1750 AC_Q "AD/Q,RAMADR/AC#,DBUS/DP, FM WRITE" ; 1751 AC[]_0 "AD/ZERO,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP, FM WRITE" ; 1752 AC[]_1 "AD/B,DEST/PASS,B/ONE,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP,FM WRITE" ; 1753 AC[]_Q "AD/Q,RAMADR/AC*#,ACALU/AC+N,ACN/@1,DBUS/DP, FM WRITE" ; 1754 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 46 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- MICROCODE WORK SPACE ; 1755 .TOC "MACROS -- MICROCODE WORK SPACE" ; 1756 ; 1757 ; 1758 WORK[]_Q "AD/Q,DEST/PASS,RAMADR/#,WORK/@1,FM WRITE" ; 1759 Q_WORK[] "AD/D,DEST/Q_AD,RAMADR/#,DBUS/RAM,WORK/@1,DT/3T" ; 1760 WORK[]_0 "AD/ZERO,DEST/PASS,RAMADR/#,WORK/@1,FM WRITE" ; 1761 WORK[]_1 "AD/B,DEST/PASS,RAMADR/#,WORK/@1,B/ONE,FM WRITE" ; 1762 WORK[]_[] "AD/B,DEST/PASS,RAMADR/#,WORK/@1,B/@2,FM WRITE" ; 1763 WORK[]_[] CLR LH "AD/47,RSRC/AB,DEST/PASS,RAMADR/#,WORK/@1,B/@2,A/MASK,FM WRITE" ; 1764 WORK[]_[]-1 "AD/A-B-.25,A/@2,B/ONE,DEST/PASS,RAMADR/#,WORK/@1,FM WRITE, ADD .25" ; 1765 WORK[]_.NOT.[] "AD/.NOT.B,DEST/PASS,RAMADR/#,WORK/@1,B/@2,FM WRITE" ; 1766 WORK[]_[].AND.[] "AD/A.AND.B,DEST/PASS,RAMADR/#,WORK/@1,A/@2,B/@3,FM WRITE" ; 1767 [].AND.NOT.WORK[] "AD/.NOT.D.AND.A,A/@1,DBUS/RAM,RAMADR/#,WORK/@2,DT/3T" ; 1768 [].AND.WORK[] "AD/D.AND.A,A/@1,DBUS/RAM,RAMADR/#,WORK/@2,DT/3T" ; 1769 []_[]+WORK[] "AD/D+A,A/@2,DEST/AD,B/@1,DBUS/RAM,RAMADR/#,WORK/@3,DT/3T" ; 1770 []_[].AND.WORK[] "AD/D.AND.A,A/@2,DEST/AD,B/@1,DBUS/RAM,RAMADR/#,WORK/@3,DT/3T" ; 1771 []_[].AND.NOT.WORK[] "AD/.NOT.D.AND.A,A/@2,DEST/AD,B/@1,DBUS/RAM,RAMADR/#,WORK/@3,DT/3T" ; 1772 []_[].OR.WORK[] "AD/D.OR.A,A/@2,DEST/AD,B/@1,DBUS/RAM,RAMADR/#,WORK/@3,DT/3T" ; 1773 []_WORK[] "AD/D,DEST/AD,B/@1,DBUS/RAM,RAMADR/#,WORK/@2,DT/3T" ; 1774 []_.NOT.WORK[] "AD/.NOT.D,DEST/AD,B/@1,DBUS/RAM,RAMADR/#,WORK/@2,DT/3T" ; 1775 []_-WORK[] "AD/-D-.25,ADD .25,DEST/AD,B/@1,DBUS/RAM,RAMADR/#,WORK/@2,DT/3T" ; 1776 []_WORK[]+1 "AD/D+A,A/ONE,DEST/AD,B/@1,DBUS/RAM,RAMADR/#,WORK/@2,DT/3T" ; 1777 Q_Q-WORK[] "AD/Q-D-.25,DEST/Q_AD,DBUS/RAM,RAMADR/#,WORK/@1,ADD .25,DT/3T" ; 1778 []_[]-WORK[] "AD/A-D-.25,DEST/AD,A/@2,B/@1,DBUS/RAM,RAMADR/#,WORK/@3,ADD .25,DT/3T" ; 1779 ; 1780 RAM_[] "AD/B,DEST/PASS,RAMADR/RAM,B/@1,FM WRITE" ; 1781 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 47 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- MEMORY CONTROL ; 1782 .TOC "MACROS -- MEMORY CONTROL" ; 1783 ; 1784 MEM CYCLE "MEM/1" ; 1785 ; 1786 ;THE FOLLOWING MACROS CONTROL MEMORY ADDRESS ; 1787 LOAD VMA "MEM CYCLE,LDVMA/1" ; 1788 FORCE EXEC "FORCE EXEC/1" ; 1789 VMA PHYSICAL "PHYSICAL/1,FORCE EXEC/1,FORCE USER/0,EXT ADR/1,LOAD VMA" ; 1790 VMA PHYSICAL WRITE "LOAD VMA,VMA PHYSICAL,WAIT/1,MEM/1,WRITE CYCLE/1,WRITE TEST/0" ; 1791 VMA PHYSICAL READ "LOAD VMA,VMA PHYSICAL,WAIT/1,MEM/1,READ CYCLE/1,WRITE TEST/0" ; 1792 VMA EXTENDED "EXT ADR/1" ; 1793 ; 1794 PXCT EA "PXCT/E1" ; 1795 PXCT DATA "PXCT/D1" ; 1796 PXCT BLT DEST "PXCT/D1" ; 1797 PXCT BYTE PTR EA "PXCT/E2" ; 1798 PXCT BYTE DATA "PXCT/D2" ; 1799 PXCT STACK WORD "PXCT/D2" ; 1800 PXCT BLT SRC "PXCT/D2" ; 1801 PXCT EXTEND EA "PXCT/E2" ; 1802 ; 1803 ;THE FOLLOWING MACROS GET MEMORY CYCLES STARTED ; 1804 WRITE TEST "WRITE TEST/1,WAIT/1" ; 1805 START READ "MEM CYCLE,READ CYCLE/1,WAIT/1" ; 1806 START WRITE "MEM CYCLE,WRITE TEST,WRITE CYCLE/1,WAIT/1" ; 1807 START NO TEST WRITE "MEM CYCLE,WRITE CYCLE/1,WAIT/1" ; 1808 FETCH "START READ,FETCH/1,PXCT/CURRENT,WAIT/1" ; 1809 ; 1810 ;THE FOLLOWING MACROS COMPLETE MEMORY CYCLES ; 1811 MEM WAIT "MEM CYCLE,WAIT/1" ; 1812 MEM READ "MEM WAIT,DBUS/DBM,DBM/MEM" ; 1813 MEM WRITE "MEM WAIT,DT/3T" ; 1814 SPEC MEM READ "SPEC/WAIT,DBUS/DBM,DBM/MEM" ; 1815 SPEC MEM WRITE "SPEC/WAIT,DT/3T" ; 1816 ; 1817 ; 1818 ;THINGS WHICH WRITE MEMORY ; 1819 MEM_[] "AD/B,DEST/PASS,B/@1,DBUS/DP,RAMADR/VMA,CHK PARITY" ; 1820 MEM_Q "AD/Q,DBUS/DP,RAMADR/VMA" ; 1821 ; 1822 ; 1823 ;THINGS WHICH READ MEMORY ; 1824 []_IO DATA "AD/D,DBUS/DBM,RAMADR/VMA,DEST/AD,B/@1" ; 1825 []_MEM "AD/D,DBUS/DBM,RAMADR/VMA,DEST/AD,B/@1,CHK PARITY" ; 1826 []_MEM THEN FETCH "AD/D,DBUS/DBM,RAMADR/VMA,DEST/A,A/PC,B/@1,CHK PARITY, FETCH, LOAD VMA" ; 1827 []_MEM*.5 "AD/D,DBUS/DBM,RAMADR/VMA,DEST/AD*.5,B/@1,CHK PARITY" ; 1828 []_MEM.AND.MASK "AD/D.AND.A,A/MASK,DBUS/DBM,RAMADR/VMA,DEST/AD,B/@1,CHK PARITY" ; 1829 []_(MEM.AND.[])*.5 "AD/D.AND.A,A/@2,DBUS/DBM,RAMADR/VMA,DEST/AD*.5,B/@1,CHK PARITY" ; 1830 Q_MEM "AD/D,DBUS/DBM,RAMADR/VMA,DEST/Q_AD,CHK PARITY" ; 1831 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 48 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- VMA ; 1832 .TOC "MACROS -- VMA" ; 1833 ; 1834 VMA_[] "AD/A,A/@1,DEST/PASS,LOAD VMA" ; 1835 VMA_[] WITH FLAGS "AD/A,A/@1,DEST/PASS,LOAD VMA,WAIT/1, MEM/1, EXT ADR/1, DP FUNC/1, DT/3T" ; 1836 VMA_[].OR.[] WITH FLAGS "AD/A.OR.B,A/@1,B/@2,DEST/PASS,LOAD VMA,WAIT/1, MEM/1, EXT ADR/1, DP FUNC/1, DT/3T" ; 1837 VMA_[]+1 "AD/A+B,A/ONE,B/@1,DEST/AD,HOLD LEFT,LOAD VMA" ; 1838 VMA_[]-1 "AD/B-A-.25,A/ONE,B/@1,ADD .25,HOLD LEFT,LOAD VMA" ; 1839 VMA_[]+XR "AD/D+A,DBUS/RAM,RAMADR/XR#,A/@1,LOAD VMA" ; 1840 VMA_[]+[] "AD/A+B,DEST/PASS,A/@1,B/@2,LOAD VMA" ; 1841 ; 1842 NEXT [] PHYSICAL WRITE "AD/A+B,A/ONE,B/@1,DEST/AD,HOLD LEFT,LOAD VMA, VMA PHYSICAL, START WRITE" ; 1843 ; 1844 ;MACROS TO LOAD A 2901 REGISTER WITH VMA FLAG BITS ; 1845 []_VMA FLAGS "AD/45,DEST/AD,B/@1,DBM/#,DBUS/DBM,RSRC/D0,A/MASK" ; 1846 []_VMA IO READ "[@1]_VMA FLAGS,READ CYCLE/1,IO CYCLE/1,WRITE TEST/0, PHYSICAL/1, FORCE EXEC/1, FORCE USER/0" ; 1847 []_VMA IO WRITE "[@1]_VMA FLAGS,WRITE CYCLE/1,IO CYCLE/1,WRITE TEST/0, PHYSICAL/1, FORCE EXEC/1, FORCE USER/0" ; 1848 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 49 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- TIME CONTROL ; 1849 .TOC "MACROS -- TIME CONTROL" ; 1850 ; 1851 AC "RAMADR/AC#" ; 1852 AC[] "RAMADR/AC*#,ACALU/AC+N,ACN/@1" ; 1853 XR "RAMADR/XR#" ; 1854 VMA "RAMADR/VMA" ; 1855 WORK[] "RAMADR/#, WORK/@1" ; 1856 ; 1857 2T "T/2T" ; 1858 3T "T/3T" ; 1859 4T "T/4T" ; 1860 5T "T/5T" ; 1861 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 50 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- SCAD, SC, FE LOGIC ; 1862 .TOC "MACROS -- SCAD, SC, FE LOGIC" ; 1863 ; 1864 LOAD SC "LOADSC/1" ; 1865 LOAD FE "LOADFE/1" ; 1866 STEP SC "SCAD/A-1,SCADA/SC,LOAD SC,SKIP/SC" ; 1867 SHIFT "SCAD/A+B,SCADA/S#,SCADB/FE,S#/1, LOAD FE, MULTI SHIFT/1" ; 1868 ; 1869 SC_SC-1 "SCAD/A-1,SCADA/SC,LOAD SC" ; 1870 SC_SHIFT "SCAD/A+B,SCADA/S#,S#/0,SCADB/SHIFT,LOAD SC" ; 1871 SC_SHIFT-1 "SCAD/A+B,SCADA/S#,S#/1777,SCADB/SHIFT,LOAD SC" ; 1872 SC_SHIFT-2 "SCAD/A+B,SCADA/S#,S#/1776,SCADB/SHIFT,LOAD SC" ; 1873 SC_-SHIFT "SCAD/A-B,SCADA/S#,S#/0000,SCADB/SHIFT,LOAD SC" ; 1874 SC_-SHIFT-1 "SCAD/A-B,SCADA/S#,SCADB/SHIFT,S#/1777,LOAD SC" ; 1875 SC_-SHIFT-2 "SCAD/A-B,SCADA/S#,SCADB/SHIFT,S#/1776,LOAD SC" ; 1876 SC_SC-EXP "SCAD/A-B,SCADA/SC,SCADB/EXP,LOAD SC" ; 1877 SC_SC-EXP-1 "SCAD/A-B-1,SCADA/SC,SCADB/EXP,LOAD SC" ; 1878 SC_SC-FE-1 "SCAD/A-B-1,SCADA/SC,SCADB/FE,LOAD SC" ; 1879 SC_SC-FE "SCAD/A-B,SCADA/SC,SCADB/FE,LOAD SC" ; 1880 SC_EXP "SCAD/A+B,SCADA/S#,S#/0,SCADB/EXP,LOAD SC" ; 1881 SC_S#-FE "SCAD/A-B,SCADA/S#,SCADB/FE,LOAD SC" ; 1882 SC_FE+S# "SCAD/A+B,SCADA/S#,SCADB/FE,LOAD SC" ; 1883 SC_FE "SCAD/A.OR.B,SCADA/S#,S#/0,SCADB/FE,LOAD SC" ; 1884 SC_S# "SCAD/A,SCADA/S#,LOAD SC" ; 1885 ; 1886 ; 1887 SC_36. "SC_S#,S#/36." ; 1888 SC_35. "SC_S#,S#/35." ; 1889 SC_34. "SC_S#,S#/34." ; 1890 SC_28. "SC_S#,S#/28." ; 1891 SC_27. "SC_S#,S#/27." ; 1892 SC_26. "SC_S#,S#/26." ; 1893 SC_24. "SC_S#,S#/24." ; 1894 SC_22. "SC_S#,S#/22." ; 1895 SC_20. "SC_S#,S#/20." ; 1896 SC_19. "SC_S#,S#/19." ; 1897 SC_14. "SC_S#,S#/14." ; 1898 SC_11. "SC_S#,S#/11." ; 1899 SC_9. "SC_S#,S#/9." ; 1900 SC_8. "SC_S#,S#/8." ; 1901 SC_7 "SC_S#,S#/7" ; 1902 SC_6 "SC_S#,S#/6" ; 1903 SC_5 "SC_S#,S#/5" ; 1904 SC_4 "SC_S#,S#/4" ; 1905 SC_3 "SC_S#,S#/3" ; 1906 SC_2 "SC_S#,S#/2" ; 1907 SC_1 "SC_S#,S#/1" ; 1908 SC_0 "SC_S#,S#/0." ; 1909 SC_-1 "SC_S#,S#/1777" ; 1910 SC_-2 "SC_S#,S#/1776" ; 1911 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 51 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- SCAD, SC, FE LOGIC ; 1912 FE_-FE "SCAD/A-B,SCADA/S#,S#/0,SCADB/FE,LOAD FE" ; 1913 FE_-FE-1 "SCAD/A-B,SCADA/S#,S#/1777,SCADB/FE,LOAD FE" ; 1914 FE_FE-19 "SCAD/A+B,SCADB/FE,SCADA/S#,S#/1550,LOAD FE" ; 1915 FE_-FE+S# "SCAD/A-B,SCADA/S#,SCADB/FE,LOAD FE" ; 1916 FE_FE+SC "SCAD/A+B,SCADA/SC,SCADB/FE, LOAD FE" ; 1917 FE_FE.AND.S# "SCAD/A.AND.B,SCADA/S#,SCADB/FE, LOAD FE" ; 1918 FE_P "SCAD/A,SCADA/BYTE1, LOAD FE" ; 1919 FE_S "SCAD/A+B, SCADA/S#, S#/0 ,SCADB/SIZE, LOAD FE" ; 1920 FE_S+2 "SCAD/A+B, SCADA/S#, S#/20, SCADB/SIZE, LOAD FE" ; 1921 FE_-S-20 "SCAD/A-B,SCADA/S#,S#/1760,SCADB/SIZE, LOAD FE" ; 1922 FE_-S-10 "SCAD/A-B,SCADA/S#,S#/1770,SCADB/SIZE, LOAD FE" ; 1923 FE_S# "SCAD/A,SCADA/S#,LOAD FE" ; 1924 FE_S#-FE "SCAD/A-B,SCADA/S#,SCADB/FE,LOAD FE" ; 1925 FE_-2 "FE_S#,S#/1776" ; 1926 FE_-12. "FE_S#,S#/1764" ; 1927 FE_0 "FE_S#,S#/0" ; 1928 FE_-1 "FE_S#,S#/1777" ; 1929 FE_FE+1 "SCAD/A+B,SCADA/S#,SCADB/FE,S#/1,LOAD FE" ; 1930 FE_FE+2 "SCAD/A+B,SCADA/S#,SCADB/FE,S#/2,LOAD FE" ; 1931 FE_FE+10 "SCAD/A+B,SCADA/S#,SCADB/FE,S#/10,LOAD FE" ; 1932 FE_FE-1 "SCAD/A+B,SCADA/S#,SCADB/FE,S#/1777,LOAD FE" ; 1933 FE_FE+4 "SCAD/A+B,SCADA/S#,SCADB/FE,S#/4,LOAD FE" ; 1934 FE_EXP "SCAD/A+B,SCADA/S#,S#/0,SCADB/EXP,LOAD FE" ; 1935 FE_SC+EXP "SCAD/A+B,SCADA/SC,SCADB/EXP,LOAD FE" ; 1936 FE_SC-EXP "SCAD/A-B,SCADA/SC,SCADB/EXP,LOAD FE" ; 1937 FE_FE+P "SCAD/A+B,SCADA/BYTE1,SCADB/FE, LOAD FE" ; 1938 FE_FE-200 "SCAD/A+B,SCADA/S#,S#/1600,SCADB/FE,LOAD FE" ; 1939 FE_-FE+200 "SCAD/A-B,SCADA/S#,S#/200,SCADB/FE,LOAD FE" ; 1940 FE_FE+S# "SCAD/A+B,SCADA/S#,SCADB/FE,LOAD FE" ; 1941 ; 1942 ; 1943 GEN 17-FE "SCAD/A-B,SCADA/S#,S#/210,SCADB/FE" ; 1944 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 52 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- DATA PATH FIELD CONTROL ; 1945 .TOC "MACROS -- DATA PATH FIELD CONTROL" ; 1946 ; 1947 HOLD LEFT "CLKL/0,GENL/0" ; 1948 ADL PARITY "GENL/1" ; 1949 CHK PARITY L "CHKL/1" ; 1950 ; 1951 HOLD RIGHT "CLKR/0,GENR/0" ; 1952 ADR PARITY "GENR/1" ; 1953 CHK PARITY R "CHKR/1" ; 1954 ; 1955 AD PARITY "AD PARITY OK/1" ; 1956 CHK PARITY "CHKL/1,CHKR/1" ; 1957 BAD PARITY "CHKL/0,CHKR/0" ; 1958 ; 1959 INH CRY18 "SPEC/INHCRY18" ; 1960 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 53 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- SHIFT PATH CONTROL ; 1961 .TOC "MACROS -- SHIFT PATH CONTROL" ; 1962 ; 1963 ASH "SHSTYLE/NORM" ;ASH SHIFT ; 1964 LSH "SHSTYLE/NORM" ;LSH SHIFT (SAME HARDWARE AS ASH BUT ; 1965 ; BITS -2 AND -1 ARE PRESET TO ZERO) ; 1966 ROT "SHSTYLE/ROT" ; 1967 LSHC "SHSTYLE/LSHC" ; 1968 ASHC "SHSTYLE/ASHC" ; 1969 ROTC "SHSTYLE/ROTC" ; 1970 ONES "SHSTYLE/ONES" ;SHIFT IN 1 BITS ; 1971 DIV "SHSTYLE/DIV" ;SPECIAL PATH FOR DIVIDE (LIKE ROTC BUT ; 1972 ; COMPLEMENT BIT AS IT GOES AROUND) ; 1973 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 54 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- SPECIAL FUNCTIONS ; 1974 .TOC "MACROS -- SPECIAL FUNCTIONS" ; 1975 ; 1976 LOAD IR "SPEC/LOADIR" ;LOAD INSTRUCTION REG FROM ; 1977 ; DBUS0-DBUS8, LOAD AC# FROM ; 1978 ; DBUS9-DBUS12 ; 1979 ; UPDATE LAST-INST-PUBLIC PC FLAG ; 1980 LOAD INST "SPEC/LDINST" ; 1981 LOAD INST EA "SPEC/LOADXR,PXCT/CURRENT" ; 1982 LOAD BYTE EA "SPEC/LOADXR,PXCT/E2" ; 1983 LOAD IND EA "SPEC/LOADXR,PXCT/E1" ; 1984 LOAD SRC EA "SPEC/LOADXR,PXCT/BIS-SRC-EA" ; 1985 LOAD DST EA "SPEC/LOADXR,PXCT/BIS-DST-EA" ; 1986 ADD .25 "CRY38/1" ;GENERATE CARRY IN TO BIT 37 ; 1987 CALL [] "CALL/1,J/@1" ;CALL A SUBROUTINE ; 1988 LOAD PXCT "SPEC/LDPXCT" ;LOAD PXCT FLAGS IF EXEC MODE ; 1989 TURN OFF PXCT "SPEC/PXCT OFF" ; 1990 LOAD PAGE TABLE "SPEC/LDPAGE" ; 1991 LOAD AC BLOCKS "SPEC/LDACBLK" ; 1992 SWEEP "SPEC/SWEEP,PHYSICAL/1" ; 1993 CLRCSH "SPEC/CLRCSH,PHYSICAL/1" ; 1994 LOAD PI "SPEC/LDPI" ; 1995 SET HALT "SPEC/#,#/74" ; 1996 CLEAR CONTINUE "SPEC/#,#/40" ; 1997 CLEAR EXECUTE "SPEC/#,#/20" ; 1998 CLEAR RUN "SPEC/#,#/10" ; 1999 UNHALT "SPEC/#,#/62" ; 2000 SET APR ENABLES "SPEC/APR EN" ; 2001 ABORT MEM CYCLE "DBUS/DBM,RAMADR/VMA,DBM/MEM,AD/ZERO,SPEC/MEMCLR,LOAD VMA" ; 2002 CLR IO BUSY "SPEC/CLR IO BUSY" ; 2003 CLR IO LATCH "SPEC/CLR IO LATCH" ; 2004 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 55 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- PC FLAGS ; 2005 .TOC "MACROS -- PC FLAGS" ; 2006 ; 2007 CHANGE FLAGS "SPEC/FLAGS" ; 2008 ; 2009 SET AROV "CHANGE FLAGS, HOLD USER/1, SETOV/1, TRAP1/1" ; 2010 SET FOV "CHANGE FLAGS, HOLD USER/1, SETFOV/1, TRAP1/1" ; 2011 SET NO DIVIDE "CHANGE FLAGS, HOLD USER/1, SETOV/1, SETNDV/1, TRAP1/1" ; 2012 SET FL NO DIVIDE "SET NO DIVIDE, SETFOV/1" ; 2013 ; 2014 ASH AROV "SPEC/ASHOV" ; 2015 SET FPD "CHANGE FLAGS, HOLD USER/1, SETFPD/1" ; 2016 CLR FPD "CHANGE FLAGS, HOLD USER/1, CLRFPD/1" ; 2017 ; 2018 SET PDL OV "CHANGE FLAGS, HOLD USER/1, TRAP2/1" ; 2019 SET TRAP1 "CHANGE FLAGS, HOLD USER/1, TRAP1/1" ; 2020 ; 2021 LOAD PCU "CHANGE FLAGS, LD PCU/1" ; 2022 UPDATE USER "CHANGE FLAGS, HOLD USER/1" ; 2023 LEAVE USER "CHANGE FLAGS, HOLD USER/0" ; 2024 ; 2025 JFCL FLAGS "CHANGE FLAGS, HOLD USER/1, JFCLFLG/1" ; 2026 ; 2027 LOAD FLAGS "CHANGE FLAGS, LD FLAGS/1" ; 2028 EXP TEST "SPEC/EXPTST" ; 2029 AD FLAGS "CHANGE FLAGS, ADFLGS/1, HOLD USER/1" ; 2030 ; 2031 NO DIVIDE "SET NO DIVIDE, J/NIDISP" ; 2032 FL NO DIVIDE "SET FL NO DIVIDE, J/NIDISP" ; 2033 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 56 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- PAGE FAIL FLAGS ; 2034 .TOC "MACROS -- PAGE FAIL FLAGS" ; 2035 ; 2036 STATE_[] "[FLG]_#,STATE/@1,HOLD LEFT" ; 2037 END STATE "[FLG]_0, HOLD LEFT" ; 2038 ; 2039 END BLT "END STATE" ; 2040 END MAP "END STATE" ; 2041 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 57 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- SINGLE SKIPS ; 2042 .TOC "MACROS -- SINGLE SKIPS" ; 2043 ;SKIPS IF: ; 2044 SKIP IF AC0 "SKIP/AC0" ;THE AC NUMBER IS ZERO ; 2045 SKIP DP0 "SKIP/DP0" ;DP BIT 0=1 ; 2046 SKIP DP18 "SKIP/DP18" ;DP BIT 18=1 ; 2047 SKIP AD.EQ.0 "SKIP/ADEQ0,DT/3T" ;ADDER OUTPUT IS ZERO ; 2048 SKIP AD.LE.0 "SKIP/LE,DT/3T" ;ADDER OUTPUT IS LESS THAN OR EQUAL ; 2049 ; TO ZERO. ; 2050 SKIP ADL.LE.0 "SKIP/LLE,DT/3T" ;ADDER LEFT IS LESS THAN OR EQUAL ; 2051 ; TO ZERO. ; 2052 SKIP FPD "SKIP/FPD" ;FIRST-PART-DONE PC FLAG IS SET ; 2053 SKIP KERNEL "SKIP/KERNEL" ;USER=0 ; 2054 SKIP IO LEGAL "SKIP/IOLGL" ;USER=0 OR USER IOT=1 ; 2055 SKIP CRY0 "SKIP/CRY0" ;ADDER BIT CRY0=1 (NOT PC FLAG BIT) ; 2056 SKIP CRY1 "SKIP/CRY1" ;ADDER BIT CRY1=1 (NOT PC FLAG BIT) ; 2057 SKIP CRY2 "SKIP/CRY2,DT/3T" ;ADDER BIT CRY2=1 ; 2058 SKIP JFCL "SKIP/JFCL" ;IF JFCL SHOULD JUMP ; 2059 SKIP ADL.EQ.0 "SKIP/ADLEQ0" ;ALU BITS -2 TO 17 = 0 ; 2060 SKIP ADR.EQ.0 "SKIP/ADREQ0" ;ALU BITS 18-35 = 0 ; 2061 SKIP IRPT "SKIP/INT" ;INTERRUPT IS PENDING ; 2062 SKIP -1MS "SKIP/-1 MS" ;DON'T SKIP IF 1MS TIMER HAS EXPIRED. ; 2063 SKIP AC REF "SKIP/ACREF" ;VMA IS 0-17 ; 2064 SKIP EXECUTE "SKIP/EXECUTE" ;CONSOLE EXECUTE ; 2065 TXXX TEST "SKIP/TXXX" ;TEST INSTRUCTION SHOULD SKIP ; 2066 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 58 ; KS10.MIC[7,3] 14:54 7-JAN-1986 MACROS -- SPECIAL DISPATCH MACROS ; 2067 .TOC "MACROS -- SPECIAL DISPATCH MACROS" ; 2068 ; 2069 NEXT INST "DISP/NICOND,SPEC/NICOND,J/NICOND" ; 2070 NEXT INST FETCH "DISP/NICOND,SPEC/NICOND,J/NICOND-FETCH" ; 2071 EA MODE DISP "DISP/EAMODE,RAMADR/XR#" ; 2072 AREAD "DISP/AREAD,WAIT/1,AREAD/1,MEM/1,J/0" ; 2073 B DISP "DISP/BDISP" ; 2074 BWRITE DISP "B DISP,MEM/1,BWRITE/1,WRITE CYCLE/1,J/BWRITE" ; 2075 INST DISP "DISP/DROM,J/0" ; 2076 EXIT "BWRITE DISP,SPEC/0, WRITE TEST/1" ; 2077 AD FLAGS EXIT "BWRITE DISP, WRITE TEST/0, AD FLAGS" ; 2078 FL-EXIT "WRITE CYCLE/1,WRITE TEST/1,MEM/1,BWRITE/1,B DISP,J/FL-BWRITE" ; 2079 TEST DISP "B DISP,J/TEST-TABLE" ; 2080 SKIP-COMP DISP "B DISP,J/SKIP-COMP-TABLE" ; 2081 JUMP DISP "B DISP,J/JUMP-TABLE" ; 2082 DONE "VMA_[PC],LOAD VMA, FETCH, NEXT INST FETCH" ; 2083 JUMPA "[PC]_[AR],HOLD LEFT,LOAD VMA,FETCH,NEXT INST FETCH" ; 2084 UUO "[HR]_[HR].AND.#,#/777740,HOLD RIGHT,J/UUOGO" ; 2085 LUUO "[AR]_0 XWD [40], J/LUUO1" ; 2086 PAGE FAIL TRAP "TL [FLG], FLG.PI/1, J/PFT" ; 2087 TAKE INTERRUPT "[FLG]_[FLG].OR.#,FLG.PI/1,HOLD RIGHT,J/PI" ; 2088 INTERRUPT TRAP "WORK[SV.AR]_[AR], J/ITRAP" ; 2089 MUL DISP "DISP/MUL" ; 2090 DIV DISP "DISP/DIV" ; 2091 BYTE DISP "DISP/BYTE, DT/3T" ; 2092 SCAD DISP "DISP/SCAD0" ;SKIP (2'S WEIGHT) IS SCAD IS MINUS ; 2093 RETURN [] "DISP/RETURN,J/@1" ; 2094 PI DISP "DISP/PI" ; 2095 NORM DISP "DISP/NORM,DT/3T" ; 2096 DISMISS "TR [PI], #/077400, CALL [JEN1],DT/3T" ; 2097 CALL LOAD PI "[T0]_[PI] SWAP, CALL [LDPI2]" ; 2098 HALT [] "AD/47,DEST/AD,B/T1,DBM/#,DBUS/DBM,HALT/@1,RSRC/DA,A/MASK, J/HALTED" ; 2099 CLEANUP DISP "READ [FLG], DBUS/DP, DISP/DP, 3T, J/CLEANUP" ; 2100 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 59 ; KS10.MIC[7,3] 14:54 7-JAN-1986 DISPATCH ROM MACROS ; 2101 .TOC "DISPATCH ROM MACROS" ; 2102 .DCODE ; 2103 ; 2104 ;"A FIELD" MACROS SAY HOW TO FETCH ARGUMENTS ; 2105 ; 2106 I "I/1" ; 2107 I-PF "I/1,VMA/0,READ/1" ; 2108 R "A/READ,READ/1" ; 2109 R-PF "A/RD-PF,READ/1" ; 2110 W "A/WRITE,TEST/1" ; 2111 RW "A/READ,TEST/1,READ/1" ; 2112 IW "I/1,TEST/1" ;IMMED WHICH STORE IN E. (SETZM, ETC.) ; 2113 IR "I/1,READ/1" ;START READ A GO TO EXECUTE CODE ; 2114 DBL R "A/DREAD,READ/1" ;AR!ARX _ E!E+1 ; 2115 DBL AC "A/DBLAC" ; 2116 SH "A/SHIFT,VMA/0,READ/1" ; 2117 SHC "A/DSHIFT,VMA/0,READ/1" ; 2118 FL-R "A/FP,READ/1" ;FLOATING POINT READ ; 2119 FL-RW "A/FP,READ/1,TEST/1" ; 2120 FL-I "A/FPI,READ/0" ;FLOATING POINT IMMEDIATE ; 2121 DBL FL-R "A/DFP,READ/1" ; 2122 IOT "A/IOT" ;CHECK FOR IO LEGAL ; 2123 ; 2124 ;"B FIELD" MACROS SAY HOW TO STORE RESULTS ; 2125 ; 2126 AC "B/AC" ; 2127 M "B/MEM,TEST/1,COND FUNC/1" ; 2128 B "B/BOTH,TEST/1,COND FUNC/1" ; 2129 S "B/SELF,TEST/1,COND FUNC/1" ; 2130 DAC "B/DBLAC" ; 2131 DBL B "B/DBLB,TEST/1,COND FUNC/1" ; 2132 FL-AC "FL-B/AC" ;FLOATING POINT ; 2133 FL-MEM "FL-B/MEM,TEST/1,COND FUNC/1" ;FLOATING POINT TO MEMORY ; 2134 FL-BOTH "FL-B/BOTH,TEST/1,COND FUNC/1" ;FLOATING POINT TO BOTH ; 2135 ROUND "ROUND/1" ;FLOATING POINT ROUNDED ; 2136 ; 2137 ; 2138 ;CONTROL BITS ; 2139 W TEST "TEST/1" ; 2140 AC DISP "ACDISP/1" ; 2141 .UCODE ; 2142 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 60 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 DISPATCH ROM MACROS ; 2143 .BIN ; 2144 .TOC "POWER UP SEQUENCE" ; 2145 ; 2146 .UCODE ; 2147 ; 2148 ;HERE IS WHERE WE FIRE THE MACHINE UP DURING POWER ON ; 2149 ; 2150 U 0000, 0002,3771,0012,4374,4007,0700,0000,0037,7777 ; 2151 0: [MASK]_#, #/377777 ;BUILD A MASK WITH U 0002, 0013,3445,1212,4174,4007,0700,0000,0000,0000 ; 2152 [MASK]_[MASK]*2 ; A ONE IN 36-BITS AND 0 U 0013, 0053,3551,1212,4374,4007,0700,0000,0000,0001 ; 2153 [MASK]_[MASK].OR.#,#/1 ; IN BITS -2,-1,36,37 U 0053, 0061,3447,1200,4174,4007,0700,0000,0000,0000 ; 2154 [MAG]_[MASK]*.5 ;MAKE CONSTANT U 0061, 0071,3771,0015,4374,4007,0700,0000,0000,0001 ; 2155 [XWD1]_#, #/1 ;CONSTANT WITH 1 IN EACH ; 2156 ; HALF WORD ; 2157 [ONE]_0 XWD [1], ;THE CONSTANT 1 U 0071, 0003,4751,1207,4374,4007,0700,0010,0000,0001 ; 2158 CALL/1 ;RESET STACK (CAN NEVER RETURN ; 2159 ; TO WHERE MR LEFT US) U 0003, 0100,4751,1203,4374,4007,0700,0000,0037,6000 ; 2160 3: [AR]_0 XWD [376000] ;ADDRESS OF HALT STATUS ; 2161 ; BLOCK U 0100, 0106,3333,0003,7174,4007,0700,0400,0000,0227 ; 2162 WORK[HSBADR]_[AR] ;SAVE FOR HALT LOOP U 0106, 0110,4221,0011,4364,4277,0700,0200,0000,0010 ; 2163 [UBR]_0, ABORT MEM CYCLE ;CLEAR THE UBR AND RESET ; 2164 ; MEMORY CONTROL LOGIC U 0110, 0125,4221,0010,4174,4477,0700,0000,0000,0000 ; 2165 [EBR]_0, LOAD AC BLOCKS ;CLEAR THE EBR AND FORCE ; 2166 ; PREVIOUS AND CURRENT AC ; 2167 ; BLOCKS TO ZERO U 0125, 0131,4221,0013,4174,4257,0700,0000,0000,0000 ; 2168 [FLG]_0, SET APR ENABLES ;CLEAR THE STATUS FLAGS AND ; 2169 ; DISABLE ALL APR CONDITIONS U 0131, 0162,3333,0013,7174,4007,0700,0400,0000,0230 ; 2170 WORK[APR]_[FLG] ;ZERO REMEMBERED ENABLES ; 2171 U 0162, 0212,3333,0013,7174,4007,0700,0400,0000,0300 ; 2172 WORK[TIME0]_[FLG] ;CLEAR TIME BASE U 0212, 0214,3333,0013,7174,4007,0700,0400,0000,0301 ; 2173 WORK[TIME1]_[FLG] ; .. ; 2174 .IF/FULL U 0214, 0223,4223,0000,1174,4007,0700,0400,0000,1443 ; 2175 AC[BIN0]_0 ;COMPUTE A TABLE OF POWERS OF U 0223, 0226,3333,0007,1174,4007,0700,0400,0000,1444 ; 2176 AC[BIN1]_1 ; TEN U 0226, 0235,4221,0003,4174,4007,0700,2000,0071,0023 ; 2177 [AR]_0, SC_19. ;WE WANT TO GET 22 NUMBERS U 0235, 0242,3333,0007,7174,4007,0700,0400,0000,0344 ; 2178 WORK[DECLO]_1 ;STARTING WITH 1 U 0242, 0244,4223,0000,7174,4007,0700,0400,0000,0373 ; 2179 WORK[DECHI]_0 ; .. U 0244, 0311,3771,0002,4374,4007,0700,0000,0000,0344 ; 2180 [HR]_#, WORK/DECLO ;ADDRESS OF LOW WORD U 0311, 0323,3771,0006,4374,4007,0700,0000,0000,0373 ; 2181 [BRX]_#, WORK/DECHI ;ADDRESS OF HIGH WORD U 0323, 0010,0111,0706,4174,4007,0700,0200,0000,0010 ; 2182 TENLP: [BRX]_[BRX]+1, LOAD VMA ;ADDRESS THE HIGH WORD ; 2183 =0* [ARX]_AC[BIN1], ;LOW WORD TO ARX U 0010, 0560,3771,0004,1276,6007,0701,0010,0000,1444 ; 2184 CALL [DBSLOW] ;MULTIPLY BY TEN U 0012, 0324,3333,0005,6174,4007,0700,0400,0000,0000 ; 2185 RAM_[BR] ;SAVE HIGH WORD U 0324, 0334,0111,0702,4174,4007,0700,0200,0000,0010 ; 2186 [HR]_[HR]+1, LOAD VMA ;WHERE TO STORE LOW WORD U 0334, 0224,3333,0004,6174,4007,0630,2400,0060,0000 ; 2187 RAM_[ARX], STEP SC ;STORE LOW WORD AND SEE IF ; 2188 ; WE ARE DONE U 0224, 0323,4443,0000,4174,4007,0700,0000,0000,0000 ; 2189 =0 J/TENLP ;NOT YET--KEEP GOING U 0225, 0140,6553,0500,4374,4007,0321,0000,0033,0656 ; 2190 [BR].XOR.#, 3T, SKIP ADL.EQ.0, #/330656 ; 2191 ;DID WE GET THE RIGHT ANSWER ; 2192 ; IN THE TOP 18 BITS? U 0140, 0104,4751,1217,4374,4007,0700,0000,0000,1005 ; 2193 =0**0 HALT [MULERR] ;NO--CPU IS BROKEN ; 2194 .ENDIF/FULL ; 2195 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 61 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 POWER UP SEQUENCE U 0141, 3607,4221,0014,4174,4007,0700,0010,0000,0000 ; 2196 =0**1 [PI]_0, CALL [LOADPI] ;CLEAR PI STATE ; 2197 =1**1 ;CLEAR REGISTERS SO NO ; 2198 ;PARITY ERROR HAPPEN ;;2199 .IFNOT/FULL ;;2200 [ARX]_0 ;WRITTEN WHILE COMPUTING POWERS ;;2201 [BR]_0 ;OF 10 ;;2202 [BRX]_0 ; 2203 .ENDIF/FULL U 0151, 0343,4751,1217,4374,4007,0700,0000,0000,0120 ; 2204 [T1]_0 XWD [120] ;RH OF 120 CONTAINS START ADDRESS ; 2205 ; FOR SIMULATOR. FOR THE REAL ; 2206 ; MACHINE IT IS JUST DATA WITH ; 2207 ; GOOD PARITY. ; 2208 = ; 2209 ;THE CODE UNDER .IF/SIM MUST USE THE SAME ADDRESS AS THE CODE ; 2210 ; UNDER .IFNOT/SIM SO THAT MICROCODE ADDRESSES DO NOT CHANGE BETWEEN ; 2211 ; VERSIONS ;;2212 .IF/SIM ;;2213 VMA_[T1], START READ ;READ THE WORD ;;2214 MEM READ, [PC]_MEM, HOLD LEFT, J/START ;;2215 ;GO FIRE UP SIMULATOR AT THE ;;2216 ; PROGRAMS STARTING ADDRESS ; 2217 .IFNOT/SIM ; 2218 [PC]_0, ;CLEAR LH OF PC ; 2219 LEAVE USER, ;ENTER EXEC MODE U 0343, 0346,4221,0001,4174,4467,0700,0000,0000,0004 ; 2220 LOAD FLAGS ;CLEAR TRAP FLAGS ; 2221 [T1]_#, HALT/POWER, ;LOAD T1 WITH POWER UP CODE U 0346, 0116,3771,0017,4374,4007,0700,0000,0000,0000 ; 2222 J/PWRON ;ENTER HALT LOOP. DO NOT STORE ; 2223 ; HALT STATUS BLOCK ; 2224 .ENDIF/SIM ; 2225 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 62 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 THE INSTRUCTION LOOP -- START NEXT INSTRUCTION ; 2226 .TOC "THE INSTRUCTION LOOP -- START NEXT INSTRUCTION" ; 2227 ; 2228 ;ALL INSTRUCTIONS EXCEPT JUMP'S AND UUO'S END UP HERE ; 2229 1400: U 1400, 0110,3443,0100,4174,4156,4700,0200,0014,0012 ; 2230 DONE: DONE U 1401, 0110,0111,0701,4170,4156,4700,0200,0014,0012 ; 2231 1401: VMA_[PC]+1, NEXT INST FETCH, FETCH ; 2232 =0 U 0260, 0110,0111,0701,4170,4156,4700,0200,0014,0012 ; 2233 SKIP: VMA_[PC]+1, NEXT INST FETCH, FETCH U 0261, 0110,3443,0100,4174,4156,4700,0200,0014,0012 ; 2234 DONE ; 2235 ; 2236 ; 2237 ;16-WAY DISPATCH BASED ON NEXT INSTRUCTION ; 2238 =0000 ; 2239 NICOND: ; 2240 =0001 [AR]_0 XWD [423], ;TRAP TYPE 3 ; 2241 ; GET ADDRESS OF TRAP INST ; 2242 TURN OFF PXCT, ;CLEAR PXCT U 0101, 3474,4751,1203,4374,4367,0700,0000,0000,0423 ; 2243 J/TRAP ;PROCESS TRAP (INOUT.MIC) ; 2244 =0010 [AR]_0 XWD [422], ;TRAP TYPE 2 ; 2245 TURN OFF PXCT, ;CLEAR PXCT U 0102, 3474,4751,1203,4374,4367,0700,0000,0000,0422 ; 2246 J/TRAP ;GO TRAP ; 2247 =0011 [AR]_0 XWD [421], ;TRAP TYPE 1 ; 2248 TURN OFF PXCT, ;TURN OF PXCT U 0103, 3474,4751,1203,4374,4367,0700,0000,0000,0421 ; 2249 J/TRAP ;GO TRAP U 0105, 0104,4751,1217,4374,4007,0700,0000,0000,0002 ; 2250 =0101 HALT [CSL] ;"HA" COMMAND TO 8080 ; 2251 =0111 ; 2252 VMA_[PC], ;LOAD VMA ; 2253 FETCH, ;INDICATE INSTRUCTION FETCH U 0107, 0117,3443,0100,4174,4007,0700,0200,0014,0012 ; 2254 J/XCTGO ;GO GET INSTRUCTION ; 2255 ;THE NEXT SET OF CASES ARE USED WHEN THERE IS A FETCH ; 2256 ; IN PROGESS ; 2257 =1000 ; 2258 NICOND-FETCH: ; 2259 =1001 [AR]_0 XWD [423], ;TRAP TYPE 3 ; 2260 TURN OFF PXCT, U 0111, 3474,4751,1203,4374,4367,0700,0000,0000,0423 ; 2261 J/TRAP ; 2262 =1010 [AR]_0 XWD [422], ;TRAP TYPE 2 ; 2263 TURN OFF PXCT, U 0112, 3474,4751,1203,4374,4367,0700,0000,0000,0422 ; 2264 J/TRAP ; 2265 =1011 [AR]_0 XWD [421], ;TRAP TYPE 1 ; 2266 TURN OFF PXCT, U 0113, 3474,4751,1203,4374,4367,0700,0000,0000,0421 ; 2267 J/TRAP U 0115, 0104,4751,1217,4374,4007,0700,0000,0000,0002 ; 2268 =1101 HALT [CSL] ;"HA" COMMAND TO 8080 ; 2269 =1111 ; 2270 XCTGO: MEM READ, ;WAIT FOR MEMORY ; 2271 [HR]_MEM, ;PUT DATA IN HR ; 2272 LOAD INST, ;LOAD IR & AC # U 0117, 0363,3771,0002,4365,5617,0700,0200,0000,0002 ; 2273 J/INCPC ;GO BUMP PC ; 2274 = ; 2275 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 63 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 THE INSTRUCTION LOOP -- START NEXT INSTRUCTION ; 2276 ;HERE WE POINT PC TO NEXT INSTRUCTION WHILE WE WAIT FOR ; 2277 ; EFFECTIVE ADDRESS LOGIC TO SETTLE ; 2278 INCPC: VMA_[PC]+1, ;ADDRESS OF NEXT INSTRUCTION ; 2279 FETCH/1, ;INSTRUCTION FETCH ; 2280 TURN OFF PXCT, ;CLEAR EFFECT OF PXCT U 0363, 0201,0111,0701,2170,4366,6700,0200,0010,0010 ; 2281 EA MODE DISP ;DISPACTH OF INDEXING AND @ ; 2282 ; 2283 ;MAIN EFFECTIVE ADDRESS CALCULATION ; 2284 =0001 ; 2285 EACALC: ; 2286 ; ; 2287 ; THE FIRST 4 CASES ARE USED ONLY FOR JRST ; 2288 ; ; 2289 ; 2290 ;CASE 0 -- JRST 0,FOO(XR) ; 2291 [PC]_[HR]+XR, ;UPDATE PC ; 2292 HOLD LEFT, ;ONLY RH ; 2293 LOAD VMA, FETCH, ;START GETTING IT U 0201, 0110,0551,0201,2270,4156,4700,0200,0014,0012 ; 2294 NEXT INST FETCH ;START NEXT INST ; 2295 ; 2296 ;CASE 2 -- JRST 0,FOO ; 2297 [PC]_[HR], ;NEW PC ; 2298 HOLD LEFT, ;ONLY RH ; 2299 LOAD VMA, FETCH, ;START GETTING IT U 0203, 0110,3441,0201,4170,4156,4700,0200,0014,0012 ; 2300 NEXT INST FETCH ;START NEXT INST ; 2301 ; 2302 ;CASE 4 -- JRST 0,@FOO(XR) ; 2303 [HR]_[HR]+XR, ;ADD IN INDEX ; 2304 START READ, ;START TO FETCH @ WORD ; 2305 LOAD VMA, ;PUT ADDRESS IN VMA U 0205, 0366,0551,0202,2270,4007,0700,0200,0004,0012 ; 2306 J/FETIND ;GO DO MEM WAIT (FORGET ABOUT JRST) ; 2307 ; 2308 ;CASE 6 -- JRST 0,@FOO ; 2309 VMA_[HR], ;LOAD UP ADDRESS ; 2310 START READ, ;START TO FETCH @ WORD U 0207, 0366,3443,0200,4174,4007,0700,0200,0004,0012 ; 2311 J/FETIND ;GO DO MEM WAIT (FORGET ABOUT JRST) ; 2312 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 64 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 THE INSTRUCTION LOOP -- START NEXT INSTRUCTION ; 2313 ; ; 2314 ;THESE 4 ARE FOR THE NON-JRST CASE ; 2315 ; ; 2316 ; 2317 ;CASE 10 -- JUST INDEXING ; 2318 INDEX: [HR]_[HR]+XR, ;ADD IN INDEX REGISTER U 0211, 0213,0551,0202,2270,4007,0700,0000,0000,0000 ; 2319 HOLD LEFT ;JUST DO RIGHT HALF ; 2320 ; 2321 ;CASE 12 -- NO INDEXING OR INDIRECT ; 2322 NOMOD: [AR]_EA, ;PUT 0,,E IN AR U 0213, 0000,5741,0203,4174,4001,3700,0200,0000,0342 ; 2323 PXCT DATA, AREAD ;DO ONE OR MORE OF THE FOLLWING ; 2324 ; ACCORDING TO THE DROM: ; 2325 ;1. LOAD VMA ; 2326 ;2. START READ OR WRITE ; 2327 ;3. DISPATCH TO 40-57 ; 2328 ; OR DIRECTLY TO EXECUTE CODE ; 2329 ; 2330 ;CASE 14 -- BOTH INDEXING AND INDIRECT ; 2331 BOTH: [HR]_[HR]+XR, ;ADD IN INDEX REGISTER ; 2332 LOAD VMA, PXCT EA, ;PUT ADDRESS IN VMA U 0215, 0366,0551,0202,2270,4007,0700,0200,0004,0112 ; 2333 START READ, J/FETIND ;START CYCLE AND GO WAIT FOR DATA ; 2334 ; 2335 ;CASE 16 -- JUST INDIRECT ; 2336 INDRCT: VMA_[HR], ;LOAD ADDRESS OF @ WORD U 0217, 0366,3443,0200,4174,4007,0700,0200,0004,0112 ; 2337 START READ, PXCT EA ;START CYCLE ; 2338 ; 2339 ; 2340 ;HERE TO FETCH INDIRECT WORD ; 2341 FETIND: MEM READ, [HR]_MEM, ;GET DATA WORD ; 2342 HOLD LEFT, ;JUST RIGHT HALF U 0366, 0371,3771,0002,4361,5217,0700,0200,0000,0102 ; 2343 LOAD IND EA ;RELOAD @ AND INDEX FLOPS ; 2344 ; 2345 XCT2: VMA_[PC], ;PUT PC BACK IN VMA ; 2346 FETCH/1, ;TURN ON FETCH FLAG ; 2347 EA MODE DISP, ;REDO CALCULATION FOR U 0371, 0201,3443,0100,2174,4006,6700,0200,0010,0010 ; 2348 J/EACALC ; NEW WORD ; 2349 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 65 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 THE INSTRUCTION LOOP -- FETCH ARGUMENTS ; 2350 .TOC "THE INSTRUCTION LOOP -- FETCH ARGUMENTS" ; 2351 ;HERE ON AREAD DISP TO HANDLE VARIOUS CASES OF ARGUMENT FETCH ; 2352 ; 2353 ;CASE 0 -- READ (E) ; 2354 40: MEM READ, ;WAIT FOR DATA ; 2355 [AR]_MEM, ;PUT WORD IN AR U 0040, 0000,3771,0003,4365,5001,2700,0200,0000,0002 ; 2356 INST DISP ;GO TO EXECUTE CODE ; 2357 ; 2358 ;CASE 1 -- WRITE (E) ; 2359 41: [AR]_AC, ;PUT AC IN AR U 0041, 0000,3771,0003,0276,6001,2700,0000,0000,0000 ; 2360 INST DISP ;GO TO EXECUTE CODE ; 2361 ; 2362 ;CASE 2 -- DOUBLE READ ; 2363 42: MEM READ, ;WAIT FOR DATA U 0042, 0401,3771,0003,4365,5007,0700,0200,0000,0002 ; 2364 [AR]_MEM ;PUT HI WORD IN AR ; 2365 VMA_[HR]+1, PXCT DATA, ;POINT TO E+1 U 0401, 0406,0111,0702,4170,4007,0700,0200,0004,0312 ; 2366 START READ ;START MEMORY CYCLE ; 2367 MEM READ, ;WAIT FOR DATA ; 2368 [ARX]_MEM, ;LOW WORD IN ARX U 0406, 0000,3771,0004,4365,5001,2700,0200,0000,0002 ; 2369 INST DISP ;GO TO EXECUTE CODE ; 2370 ; 2371 ;CASE 3 -- DOUBLE AC U 0043, 0415,3771,0003,0276,6007,0700,0000,0000,0000 ; 2372 43: [AR]_AC ;GET HIGH AC ; 2373 [ARX]_AC[1], ;PUT C(AC+1) IN ARX U 0415, 0000,3771,0004,1276,6001,2701,0000,0000,1441 ; 2374 INST DISP ;GO TO EXECUTE CODE ; 2375 ; 2376 ;CASE 4 -- SHIFT ; 2377 44: ; 2378 SHIFT: READ [AR], ;LOOK AT EFFECTIVE ADDRESS ; 2379 SKIP DP18, ;SEE IF LEFT OR RIGHT ; 2380 SC_SHIFT-1, ;PUT NUMBER OF PLACES TO SHIFT IN ; 2381 LOAD FE, ; SC AND FE U 0044, 0000,3333,0003,4174,4001,2530,3000,0041,5777 ; 2382 INST DISP ;GO DO THE SHIFT ; 2383 ; 2384 ;CASE 5 -- SHIFT COMBINED U 0045, 0416,3772,0000,1275,5007,0701,0000,0000,1441 ; 2385 45: Q_AC[1] ;PUT LOW WORD IN Q U 0416, 0431,3776,0005,0274,4007,0701,0000,0000,0000 ; 2386 [BR]_AC*.5 LONG ;PUT AC IN BR & SHIFT BR!Q RIGHT ; 2387 [BR]_[BR]*.5 LONG, ;SHIFT BR!Q 1 MORE PLACE RIGHT U 0431, 0044,3446,0505,4174,4007,0700,0000,0000,0000 ; 2388 J/SHIFT ;GO DO SHIFT SETUP ; 2389 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 66 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 THE INSTRUCTION LOOP -- FETCH ARGUMENTS ; 2390 ;CASE 6 -- FLOATING POINT IMMEDIATE ; 2391 46: [AR]_[AR] SWAP, ;FLIP BITS TO LEFT HALF U 0046, 0372,3770,0303,4344,4007,0700,0000,0000,0000 ; 2392 J/FPR0 ;JOIN COMMON F.P. CODE ; 2393 ; 2394 ;CASE 7 -- FLOATING POINT ; 2395 47: MEM READ, ;WAIT FOR MEMORY (SPEC/MEM WAIT) U 0047, 0372,3771,0003,4365,5007,0700,0200,0000,0002 ; 2396 [AR]_MEM ;DATA INTO AR ; 2397 =0 ; 2398 FPR0: READ [AR], ;LOOK AT NUMBER ; 2399 SC_EXP, FE_EXP, ;PUT EXPONENT IN SC & FE ; 2400 SKIP DP0, ;SEE IF NEGATIVE U 0372, 0412,3333,0003,4174,4007,0520,3010,0041,2000 ; 2401 CALL [ARSIGN] ;EXTEND AR SIGN ; 2402 FPR1: [ARX]_0, ;ZERO ARX U 0373, 0000,4221,0004,4174,4001,2700,0000,0000,0000 ; 2403 INST DISP ;GO TO EXECUTE CODE ; 2404 ; 2405 ;CASE 10 -- READ THEN PREFETCH ; 2406 50: MEM READ, ;WAIT FOR DATA ; 2407 [AR]_MEM THEN FETCH, ;PUT DATA IN AR AND START A READ ; 2408 ; VMA HAS PC+1. U 0050, 0000,3770,0103,4365,5001,2700,0200,0014,0012 ; 2409 INST DISP ;GO DO IT ; 2410 ; 2411 ;CASE 11 -- DOUBLE FLOATING READ ; 2412 51: SPEC MEM READ, ;WAIT FOR DATA ; 2413 [BR]_MEM, ;HOLD IN BR ; 2414 SC_EXP, FE_EXP, ;SAVE EXPONENT U 0051, 0402,3771,0005,4365,5177,0521,3000,0041,2000 ; 2415 SKIP DP0, 3T ;SEE IF MINUS ; 2416 =0 [AR]_[AR]+1, ;POINT TO E+1 ; 2417 LOAD VMA, PXCT DATA, ;PUT IN VMA U 0402, 0445,0111,0703,4174,4007,0700,0200,0004,0312 ; 2418 START READ, J/DFPR1 ;GO GET POSITIVE DATA ; 2419 [AR]_[AR]+1, ;POINT TO E+1 ; 2420 LOAD VMA, PXCT DATA, ;PUT IN VMA U 0403, 0432,0111,0703,4174,4007,0700,0200,0004,0312 ; 2421 START READ ;GO GET NEGATIVE DATA ; 2422 [BR]_-SIGN, ;SMEAR MINUS SIGN U 0432, 0451,3551,0505,4374,0007,0700,0000,0077,7000 ; 2423 J/DFPR2 ;CONTINUE BELOW U 0445, 0451,4551,0505,4374,0007,0700,0000,0000,0777 ; 2424 DFPR1: [BR]_+SIGN ;SMEAR PLUS SIGN ; 2425 DFPR2: MEM READ, 3T, ;WAIT FOR MEMORY ; 2426 [ARX]_(MEM.AND.[MAG])*.5, U 0451, 0452,4557,0004,4365,5007,0701,0200,0000,0002 ; 2427 ASH ;SET SHIFT PATHS U 0452, 0467,3447,0503,4174,4007,0700,0000,0000,0000 ; 2428 [AR]_[BR]*.5 ;SHIFT AR ; 2429 [AR]_[AR]*.5, ;COMPLETE SHIFTING U 0467, 0471,3447,0303,4174,4007,0700,2000,0011,0000 ; 2430 SC_FE ;PAGE FAIL MAY HAVE ZAPPED ; 2431 ; THE SC. ; 2432 VMA_[PC], FETCH, ;GET NEXT INST U 0471, 0000,3443,0100,4174,4001,2700,0200,0014,0012 ; 2433 INST DISP ;DO THIS ONE ; 2434 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 67 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 THE INSTRUCTION LOOP -- FETCH ARGUMENTS ; 2435 ;CASE 12 -- TEST FOR IO LEGAL U 0052, 0404,4443,0000,4174,4007,0040,0000,0000,0000 ; 2436 52: SKIP IO LEGAL ;IS IO LEGAL? U 0404, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 2437 =0 UUO ;NO U 0405, 0000,4443,0000,4174,4001,2700,0000,0000,0000 ; 2438 INST DISP ;YES--DO THE INSTRUCTION ; 2439 ; 2440 ; 2441 ;CASE 13 -- RESERVED ; 2442 ;53: ; 2443 ; 2444 ;CASE 14 -- RESERVED ; 2445 ;54: ; 2446 ; 2447 ;CASE 15 -- RESERVED ; 2448 ;55: ; 2449 ; 2450 ;CASE 16 -- RESERVED ; 2451 ;56: ; 2452 ; 2453 ;CASE 17 -- RESERVED ; 2454 ;57: ; 2455 ; 2456 ;EXTEND AR SIGN. ; 2457 ;CALL WITH SKIP ON AR0, RETURNS 1 ALWAYS ; 2458 =0 U 0412, 0001,4551,0303,4374,0004,1700,0000,0000,0777 ; 2459 ARSIGN: [AR]_+SIGN, RETURN [1] ;EXTEND + SIGN U 0413, 0001,3551,0303,4374,0004,1700,0000,0077,7000 ; 2460 [AR]_-SIGN, RETURN [1] ;EXTEND - SIGN ; 2461 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 68 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 THE INSTRUCTION LOOP -- STORE ANSWERS ; 2462 .TOC "THE INSTRUCTION LOOP -- STORE ANSWERS" ; 2463 ; 2464 ;NOTE: INSTRUCTIONS WHICH STORE IN BOTH AC AND MEMORY ; 2465 ; (E.G. ADDB, AOS) MUST STORE IN MEMORY FIRST ; 2466 ; SO THAT IF A PAGE FAIL HAPPENS THE AC IS ; 2467 ; STILL INTACT. ; 2468 ; 2469 1500: ; 2470 BWRITE: ;BASE ADDRESS OF BWRITE DISPATCH ; 2471 ; 2472 ;CASE 0 -- RESERVED ; 2473 ;1500: ; 2474 ; 2475 ;CASE 1 -- RESERVED ; 2476 ;1501: ; 2477 ; 2478 ;CASE 2 -- RESERVED ; 2479 ;1502: ; 2480 ; 2481 ;CASE 3 -- RESERVED ; 2482 ;1503: ; 2483 ; 2484 ;CASE 4 -- STORE SELF ; 2485 1504: ; 2486 STSELF: SKIP IF AC0, ;IS AC # ZERO? U 1504, 0434,4443,0000,4174,4007,0360,0000,0000,0000 ; 2487 J/STBTH1 ;GO TO STORE BOTH CASE ; 2488 ; 2489 ;CASE 5 -- STORE DOUBLE AC ; 2490 1505: ; 2491 DAC: AC[1]_[ARX], ;STORE AC 1 U 1505, 1515,3440,0404,1174,4007,0700,0400,0000,1441 ; 2492 J/STAC ;GO STORE AC ; 2493 ; 2494 ;CASE 6 -- STORE DOUBLE BOTH (KA10 STYLE MEM_AR ONLY) ; 2495 1506: ; 2496 STDBTH: MEM WRITE, ;WAIT FOR MEMORY ; 2497 MEM_[AR], ;STORE AR U 1506, 1505,3333,0003,4175,5007,0701,0200,0000,0002 ; 2498 J/DAC ;NOW STORE AC & AC+1 ; 2499 ; 2500 ;CASE 7 -- RESERVED ; 2501 ;1507: ; 2502 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 69 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 THE INSTRUCTION LOOP -- STORE ANSWERS ; 2503 ;CASE 10 -- RESERVED ; 2504 ;1510: ; 2505 ; 2506 ;CASE 11 -- RESERVED ; 2507 ;1511: ; 2508 ; 2509 ;CASE 12 -- RESERVED ; 2510 ;1512: ; 2511 ; 2512 ;CASE 13 -- RESERVED ; 2513 ;1513: ; 2514 ; 2515 ;CASE 14 -- RESERVED ; 2516 1514: ; 2517 FL-BWRITE: ;THE NEXT 4 CASES ARE ALSO ; 2518 ;USED IN FLOATING POINT U 1514, 0104,4751,1217,4374,4007,0700,0000,0000,1000 ; 2519 HALT [BW14] ; 2520 ; 2521 ;CASE 15 -- STORE AC ; 2522 1515: ; 2523 STAC: AC_[AR], ;STORE AC U 1515, 0100,3440,0303,0174,4156,4700,0400,0000,0000 ; 2524 NEXT INST ;DO NEXT INSTRUCTION ; 2525 ; 2526 ;CASE 16 -- STORE IN MEMORY ; 2527 1516: ; 2528 STMEM: MEM WRITE, ;WAIT FOR MEMORY ; 2529 MEM_[AR], ;STORE AR U 1516, 1400,3333,0003,4175,5007,0701,0200,0000,0002 ; 2530 J/DONE ;START FETCH OF NEXT ; 2531 ; 2532 ;CASE 17 -- STORE BOTH ; 2533 1517: ; 2534 STBOTH: MEM WRITE, ;WAIT FOR MEMORY ; 2535 MEM_[AR], ;STORE AR U 1517, 1515,3333,0003,4175,5007,0701,0200,0000,0002 ; 2536 J/STAC ;NOW STORE AC ; 2537 ; 2538 =0 ; 2539 STBTH1: MEM WRITE, ;WAIT FOR MEMORY ; 2540 MEM_[AR], ;STORE AR U 0434, 1515,3333,0003,4175,5007,0701,0200,0000,0002 ; 2541 J/STAC ;NOW STORE AC ; 2542 STORE: MEM WRITE, ;WAIT FOR MEMORY ; 2543 MEM_[AR], ;STORE AC U 0435, 1400,3333,0003,4175,5007,0701,0200,0000,0002 ; 2544 J/DONE ;START NEXT INST ; 2545 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 70 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 MOVE GROUP ; 2546 .TOC "MOVE GROUP" ; 2547 ; 2548 .DCODE D 0200, 1015,1515,1100 ; 2549 200: R-PF, AC, J/STAC ;MOVE D 0201, 0015,1515,3000 ; 2550 I-PF, AC, J/STAC ;MOVEI D 0202, 0116,1404,0700 ; 2551 W, M, J/MOVE ;MOVEM D 0203, 0004,1504,1700 ; 2552 RW, S, J/STSELF ;MOVES ; 2553 D 0204, 1015,1402,1100 ; 2554 204: R-PF, AC, J/MOVS ;MOVS D 0205, 0015,1402,3000 ; 2555 I-PF, AC, J/MOVS ;MOVSI D 0206, 0116,1402,0700 ; 2556 W, M, J/MOVS ;MOVSM D 0207, 0004,1402,1700 ; 2557 RW, S, J/MOVS ;MOVSS ; 2558 D 0210, 1015,1405,1100 ; 2559 210: R-PF, AC, J/MOVN ;MOVN D 0211, 0015,1405,3000 ; 2560 I-PF, AC, J/MOVN ;MOVNI D 0212, 0116,1405,0700 ; 2561 W, M, J/MOVN ;MOVNM D 0213, 0004,1405,1700 ; 2562 RW, S, J/MOVN ;MOVNS ; 2563 D 0214, 1015,1403,1100 ; 2564 214: R-PF, AC, J/MOVM ;MOVM D 0215, 0015,1515,3000 ; 2565 I-PF, AC, J/STAC ;MOVMI D 0216, 0116,1403,0700 ; 2566 W, M, J/MOVM ;MOVMM D 0217, 0004,1403,1700 ; 2567 RW, S, J/MOVM ;MOVNS ; 2568 .UCODE ; 2569 ; 2570 1402: U 1402, 1500,3770,0303,4344,4003,7700,0200,0003,0001 ; 2571 MOVS: [AR]_[AR] SWAP,EXIT ; 2572 ; 2573 1403: U 1403, 1404,3333,0003,4174,4007,0520,0000,0000,0000 ; 2574 MOVM: READ [AR], SKIP DP0, J/MOVE ; 2575 ; 2576 1404: U 1404, 1500,4443,0000,4174,4003,7700,0200,0003,0001 ; 2577 MOVE: EXIT ; 2578 1405: ; 2579 MOVN: [AR]_-[AR], ;NEGATE NUMBER ; 2580 AD FLAGS, 3T, ;UPDATE FLAGS U 1405, 1404,2441,0303,4174,4467,0701,4000,0001,0001 ; 2581 J/MOVE ;STORE ANSWER ; 2582 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 71 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 EXCH ; 2583 .TOC "EXCH" ; 2584 ; 2585 .DCODE D 0250, 0015,1406,1500 ; 2586 250: R,W TEST, AC, J/EXCH ; 2587 .UCODE ; 2588 ; 2589 1406: ; 2590 EXCH: [BR]_AC, ;COPY AC TO THE BR U 1406, 0506,3771,0005,0276,6007,0700,0200,0003,0002 ; 2591 START WRITE ;START A WRITE CYCLE ; 2592 MEM WRITE, ;COMPLETE WRITE CYCLE ; 2593 MEM_[BR], ;STORE BR (AC) IN MEMORY U 0506, 1515,3333,0005,4175,5007,0701,0200,0000,0002 ; 2594 J/STAC ;STORE THE AR IN AC. NOTE: AR ; 2595 ; WAS LOADED WITH MEMORY OPERAND ; 2596 ; AS PART OF INSTRUCTION DISPATCH ; 2597 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 72 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 HALFWORD GROUP ; 2598 .TOC "HALFWORD GROUP" ; 2599 ; DESTINATION LEFT HALF ; 2600 ; 2601 .DCODE D 0500, 1015,1410,1100 ; 2602 500: R-PF, AC, J/HLL D 0501, 0015,1410,3000 ; 2603 I-PF, AC, J/HLL D 0502, 0016,1407,1700 ; 2604 RW, M, J/HRR ;HLLM = HRR EXCEPT FOR STORE D 0503, 0004,1404,1700 ; 2605 RW, S, J/MOVE ;HLLS = MOVES ; 2606 D 0504, 1015,1411,1100 ; 2607 R-PF, AC, J/HRL D 0505, 0015,1411,3000 ; 2608 I-PF, AC, J/HRL D 0506, 0016,1413,1700 ; 2609 RW, M, J/HRLM D 0507, 0004,1414,1700 ; 2610 RW, S, J/HRLS ; 2611 D 0510, 1015,1432,1100 ; 2612 510: R-PF, AC, J/HLLZ D 0511, 0015,1432,3000 ; 2613 I-PF, AC, J/HLLZ D 0512, 0116,1432,0700 ; 2614 W, M, J/HLLZ D 0513, 0004,1432,1700 ; 2615 RW, S, J/HLLZ ; 2616 D 0514, 1015,1424,1100 ; 2617 R-PF, AC, J/HRLZ D 0515, 0015,1424,3000 ; 2618 I-PF, AC, J/HRLZ D 0516, 0116,1424,0700 ; 2619 W, M, J/HRLZ D 0517, 0004,1424,1700 ; 2620 RW, S, J/HRLZ ; 2621 D 0520, 1015,1433,1100 ; 2622 520: R-PF, AC, J/HLLO D 0521, 0015,1433,3000 ; 2623 I-PF, AC, J/HLLO D 0522, 0116,1433,0700 ; 2624 W, M, J/HLLO D 0523, 0004,1433,1700 ; 2625 RW, S, J/HLLO ; 2626 D 0524, 1015,1425,1100 ; 2627 R-PF, AC, J/HRLO D 0525, 0015,1425,3000 ; 2628 I-PF, AC, J/HRLO D 0526, 0116,1425,0700 ; 2629 W, M, J/HRLO D 0527, 0004,1425,1700 ; 2630 RW, S, J/HRLO ; 2631 D 0530, 1015,1430,1100 ; 2632 530: R-PF, AC, J/HLLE D 0531, 0015,1430,3000 ; 2633 I-PF, AC, J/HLLE D 0532, 0116,1430,0700 ; 2634 W, M, J/HLLE D 0533, 0004,1430,1700 ; 2635 RW, S, J/HLLE ; 2636 D 0534, 1015,1422,1100 ; 2637 R-PF, AC, J/HRLE D 0535, 0015,1422,3000 ; 2638 I-PF, AC, J/HRLE D 0536, 0116,1422,0700 ; 2639 W, M, J/HRLE D 0537, 0004,1422,1700 ; 2640 RW, S, J/HRLE ; 2641 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 73 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 HALFWORD GROUP ; 2642 ; DESTINATION RIGHT HALF ; 2643 D 0540, 1015,1407,1100 ; 2644 540: R-PF, AC, J/HRR D 0541, 0015,1407,3000 ; 2645 I-PF, AC, J/HRR D 0542, 0016,1410,1700 ; 2646 RW, M, J/HLL ;HRRM = HLL EXCEPT FOR STORE D 0543, 0004,1404,1700 ; 2647 RW, S, J/MOVE ;HRRS = MOVES ; 2648 D 0544, 1015,1412,1100 ; 2649 R-PF, AC, J/HLR D 0545, 0015,1412,3000 ; 2650 I-PF, AC, J/HLR D 0546, 0016,1415,1700 ; 2651 RW, M, J/HLRM D 0547, 0004,1416,1700 ; 2652 RW, S, J/HLRS ; 2653 D 0550, 1015,1420,1100 ; 2654 550: R-PF, AC, J/HRRZ D 0551, 0015,1420,3000 ; 2655 I-PF, AC, J/HRRZ D 0552, 0116,1420,0700 ; 2656 W, M, J/HRRZ D 0553, 0004,1420,1700 ; 2657 RW, S, J/HRRZ ; 2658 D 0554, 1015,1426,1100 ; 2659 R-PF, AC, J/HLRZ D 0555, 0015,1426,3000 ; 2660 I-PF, AC, J/HLRZ D 0556, 0116,1426,0700 ; 2661 W, M, J/HLRZ D 0557, 0004,1426,1700 ; 2662 RW, S, J/HLRZ ; 2663 D 0560, 1015,1421,1100 ; 2664 560: R-PF, AC, J/HRRO D 0561, 0015,1421,3000 ; 2665 I-PF, AC, J/HRRO D 0562, 0116,1421,0700 ; 2666 W, M, J/HRRO D 0563, 0004,1421,1700 ; 2667 RW, S, J/HRRO ; 2668 D 0564, 1015,1427,1100 ; 2669 R-PF, AC, J/HLRO D 0565, 0015,1427,3000 ; 2670 I-PF, AC, J/HLRO D 0566, 0116,1427,0700 ; 2671 W, M, J/HLRO D 0567, 0004,1427,1700 ; 2672 RW, S, J/HLRO ; 2673 D 0570, 1015,1417,1100 ; 2674 570: R-PF, AC, J/HRRE D 0571, 0015,1417,3000 ; 2675 I-PF, AC, J/HRRE D 0572, 0116,1417,0700 ; 2676 W, M, J/HRRE D 0573, 0004,1417,1700 ; 2677 RW, S, J/HRRE ; 2678 D 0574, 1015,1423,1100 ; 2679 R-PF, AC, J/HLRE D 0575, 0015,1423,3000 ; 2680 I-PF, AC, J/HLRE D 0576, 0116,1423,0700 ; 2681 W, M, J/HLRE D 0577, 0004,1423,1700 ; 2682 RW, S, J/HLRE ; 2683 ; 2684 .UCODE ; 2685 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 74 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 HALFWORD GROUP ; 2686 ;FIRST THE GUYS THAT LEAVE THE OTHER HALF ALONE ; 2687 ; 2688 ;THE AR CONTAINS THE MEMORY OPERAND. SO WE WANT TO PUT THE LH OF ; 2689 ; AC INTO AR TO DO A HRR. OBVIOUS THING FOR HLL. ; 2690 1407: U 1407, 1500,3771,0003,0276,0003,7700,0200,0003,0001 ; 2691 HRR: [AR]_AC,HOLD RIGHT,EXIT ; 2692 1410: U 1410, 1500,3771,0003,0270,6003,7700,0200,0003,0001 ; 2693 HLL: [AR]_AC,HOLD LEFT,EXIT ; 2694 ; 2695 ;HRL FLOW: ; 2696 ;AT HRL AR CONTAINS: ; 2697 ; ; 2698 ; !------------------!------------------! ; 2699 ; ! LH OF (E) ! RH OF (E) ! ; 2700 ; !------------------!------------------! ; 2701 ; ; 2702 ;AR_AR SWAP GIVES: ; 2703 ; ; 2704 ; !------------------!------------------! ; 2705 ; ! RH OF (E) ! LH OF (E) ! ; 2706 ; !------------------!------------------! ; 2707 ; ; 2708 ;AT HLL, AR_AC,HOLD LEFT GIVES: ; 2709 ; ; 2710 ; !------------------!------------------! ; 2711 ; ! RH OF (E) ! RH OF AC ! ; 2712 ; !------------------!------------------! ; 2713 ; ; 2714 ;THE EXIT MACRO CAUSES THE AR TO BE STORED IN AC (AT STAC). ; 2715 ; THE REST OF THE HALF WORD IN THIS GROUP ARE VERY SIMILAR. ; 2716 ; 2717 1411: U 1411, 1410,3770,0303,4344,4007,0700,0000,0000,0000 ; 2718 HRL: [AR]_[AR] SWAP,J/HLL ; 2719 1412: U 1412, 1407,3770,0303,4344,4007,0700,0000,0000,0000 ; 2720 HLR: [AR]_[AR] SWAP,J/HRR ; 2721 ; 2722 1413: U 1413, 0511,3770,0303,4344,4007,0700,0000,0000,0000 ; 2723 HRLM: [AR]_[AR] SWAP U 0511, 1402,3771,0003,0270,6007,0700,0000,0000,0000 ; 2724 [AR]_AC,HOLD LEFT,J/MOVS ; 2725 1414: U 1414, 1500,3770,0303,4344,0003,7700,0200,0003,0001 ; 2726 HRLS: [AR]_[AR] SWAP,HOLD RIGHT,EXIT ; 2727 ; 2728 1415: U 1415, 0512,3770,0303,4344,4007,0700,0000,0000,0000 ; 2729 HLRM: [AR]_[AR] SWAP U 0512, 1402,3771,0003,0276,0007,0700,0000,0000,0000 ; 2730 [AR]_AC,HOLD RIGHT,J/MOVS ; 2731 1416: U 1416, 1500,3770,0303,4340,4003,7700,0200,0003,0001 ; 2732 HLRS: [AR]_[AR] SWAP,HOLD LEFT,EXIT ; 2733 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 75 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 HALFWORD GROUP ; 2734 ;NOW THE HALFWORD OPS WHICH CONTROL THE "OTHER" HALF. ; 2735 ; ENTER WITH 0,,E (E) OR (AC) IN AR ; 2736 ; 2737 1417: U 1417, 1420,3333,0003,4174,4007,0530,0000,0000,0000 ; 2738 HRRE: READ [AR],SKIP DP18 ; 2739 1420: U 1420, 1500,5731,0003,4174,4003,7700,0200,0003,0001 ; 2740 HRRZ: [AR] LEFT_0, EXIT ; 2741 1421: U 1421, 1500,5431,1203,4174,4003,7700,0200,0003,0001 ; 2742 HRRO: [AR] LEFT_-1, EXIT ; 2743 ; 2744 1422: U 1422, 1424,3333,0003,4174,4007,0530,0000,0000,0000 ; 2745 HRLE: READ [AR],SKIP DP18 ; 2746 1424: U 1424, 1402,3771,0003,4374,0007,0700,0000,0000,0000 ; 2747 HRLZ: [AR]_#,#/0,HOLD RIGHT,J/MOVS ; 2748 1425: U 1425, 1402,3771,0003,4374,0007,0700,0000,0077,7777 ; 2749 HRLO: [AR]_#,#/777777,HOLD RIGHT,J/MOVS ; 2750 ; 2751 1423: U 1423, 1426,3333,0003,4174,4007,0520,0000,0000,0000 ; 2752 HLRE: READ [AR],SKIP DP0 ; 2753 1426: U 1426, 1402,3771,0003,4370,4007,0700,0000,0000,0000 ; 2754 HLRZ: [AR]_#,#/0,HOLD LEFT,J/MOVS ; 2755 1427: U 1427, 1402,3771,0003,4370,4007,0700,0000,0077,7777 ; 2756 HLRO: [AR]_#,#/777777,HOLD LEFT,J/MOVS ; 2757 ; 2758 1430: U 1430, 1432,3333,0003,4174,4007,0520,0000,0000,0000 ; 2759 HLLE: READ [AR],SKIP DP0 ; 2760 1432: U 1432, 1500,5371,0003,4174,4003,7700,0200,0003,0001 ; 2761 HLLZ: [AR] RIGHT_0, EXIT ; 2762 1433: U 1433, 1500,5341,1203,4174,4003,7700,0200,0003,0001 ; 2763 HLLO: [AR] RIGHT_-1, EXIT ; 2764 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 76 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 DMOVE, DMOVN, DMOVEM, DMOVNM ; 2765 .TOC "DMOVE, DMOVN, DMOVEM, DMOVNM" ; 2766 ; 2767 .DCODE D 0120, 0205,1505,1100 ; 2768 120: DBL R, DAC, J/DAC D 0121, 0215,1434,1100 ; 2769 DBL R, AC, J/DMOVN ; 2770 .UCODE ; 2771 ; 2772 1434: U 1434, 3070,4551,0404,4374,0007,0700,0010,0037,7777 ; 2773 DMOVN: CLEAR ARX0, CALL [DBLNGA] U 1436, 1515,3440,0404,1174,4007,0700,0400,0000,1441 ; 2774 1436: AC[1]_[ARX], J/STAC ; 2775 ; 2776 .DCODE D 0124, 0300,1567,0100 ; 2777 124: DBL AC, J/DMOVN1 D 0125, 0100,1565,0500 ; 2778 W, J/DMOVNM ; 2779 .UCODE ; 2780 ; 2781 ; 2782 1565: U 1565, 3067,3771,0004,1276,6007,0701,0010,0000,1441 ; 2783 DMOVNM: [ARX]_AC[1],CALL [DBLNEG] ; 2784 1567: ; 2785 DMOVN1: [HR]+[ONE], ;GET E+1 ; 2786 LOAD VMA, ;PUT THAT IN VMA ; 2787 START WRITE, ;STORE IN E+1 U 1567, 0531,0113,0207,4174,4007,0700,0200,0003,0312 ; 2788 PXCT DATA ;DATA CYCLE U 0531, 0532,3333,0004,4175,5007,0701,0200,0000,0002 ; 2789 MEM WRITE, MEM_[ARX] ;STORE LOW WORD ; 2790 VMA_[HR], ;GET E ; 2791 LOAD VMA, ;SAVE IN VMA ; 2792 PXCT DATA, ;OPERAND STORE ; 2793 START WRITE, ;START MEM CYCLE U 0532, 0435,3443,0200,4174,4007,0700,0200,0003,0312 ; 2794 J/STORE ;GO STORE AR ; 2795 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 77 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BOOLEAN GROUP ; 2796 .TOC "BOOLEAN GROUP" ; 2797 ; 2798 .DCODE D 0400, 0015,1441,3000 ; 2799 400: I-PF, AC, J/SETZ D 0401, 0015,1441,3000 ; 2800 I-PF, AC, J/SETZ D 0402, 0016,1441,2700 ; 2801 IW, M, J/SETZ D 0403, 0017,1441,2700 ; 2802 IW, B, J/SETZ ; 2803 .UCODE ; 2804 ; 2805 1441: U 1441, 1500,4221,0003,4174,4003,7700,0200,0003,0001 ; 2806 SETZ: [AR]_0, EXIT ; 2807 ; 2808 .DCODE D 0404, 1015,1442,1100 ; 2809 404: R-PF, AC, J/AND D 0405, 0015,1442,3000 ; 2810 I-PF, AC, J/AND D 0406, 0016,1442,1700 ; 2811 RW, M, J/AND D 0407, 0017,1442,1700 ; 2812 RW, B, J/AND ; 2813 .UCODE ; 2814 ; 2815 1442: U 1442, 1500,4551,0303,0274,4003,7700,0200,0003,0001 ; 2816 AND: [AR]_[AR].AND.AC,EXIT ; 2817 ; 2818 .DCODE D 0410, 1015,1443,1100 ; 2819 410: R-PF, AC, J/ANDCA D 0411, 0015,1443,3000 ; 2820 I-PF, AC, J/ANDCA D 0412, 0016,1443,1700 ; 2821 RW, M, J/ANDCA D 0413, 0017,1443,1700 ; 2822 RW, B, J/ANDCA ; 2823 .UCODE ; 2824 ; 2825 1443: U 1443, 1500,5551,0303,0274,4003,7700,0200,0003,0001 ; 2826 ANDCA: [AR]_[AR].AND.NOT.AC,EXIT ; 2827 ; 2828 .DCODE D 0414, 1015,1404,1100 ; 2829 414: R-PF, AC, J/MOVE ;SETM = MOVE D 0415, 0015,1404,3000 ; 2830 I-PF, AC, J/MOVE D 0416, 0016,1404,1700 ; 2831 RW, M, J/MOVE ;SETMM = NOP THAT WRITES MEMORY D 0417, 0017,1404,1700 ; 2832 RW, B, J/MOVE ;SETMB = MOVE THAT WRITES MEMORY ; 2833 D 0420, 1015,1444,1100 ; 2834 420: R-PF, AC, J/ANDCM D 0421, 0015,1444,3000 ; 2835 I-PF, AC, J/ANDCM D 0422, 0016,1444,1700 ; 2836 RW, M, J/ANDCM D 0423, 0017,1444,1700 ; 2837 RW, B, J/ANDCM ; 2838 .UCODE ; 2839 ; 2840 1444: U 1444, 1442,7441,0303,4174,4007,0700,0000,0000,0000 ; 2841 ANDCM: [AR]_.NOT.[AR],J/AND ; 2842 ; 2843 .DCODE D 0424, 0000,1400,1100 ; 2844 424: R, J/DONE D 0425, 0000,1400,2100 ; 2845 I, J/DONE D 0426, 0116,1404,0700 ; 2846 W, M, J/MOVE ;SETAM = MOVEM D 0427, 0116,1404,0700 ; 2847 W, M, J/MOVE ;SETAB, TOO ; 2848 .UCODE ; 2849 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 78 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BOOLEAN GROUP ; 2850 .DCODE D 0430, 1015,1445,1100 ; 2851 430: R-PF, AC, J/XOR D 0431, 0015,1445,3000 ; 2852 I-PF, AC, J/XOR D 0432, 0016,1445,1700 ; 2853 RW, M, J/XOR D 0433, 0017,1445,1700 ; 2854 RW, B, J/XOR ; 2855 .UCODE ; 2856 ; 2857 1445: U 1445, 1500,6551,0303,0274,4003,7700,0200,0003,0001 ; 2858 XOR: [AR]_[AR].XOR.AC,EXIT ; 2859 ; 2860 .DCODE D 0434, 1015,1446,1100 ; 2861 434: R-PF, AC, J/IOR D 0435, 0015,1446,3000 ; 2862 I-PF, AC, J/IOR D 0436, 0016,1446,1700 ; 2863 RW, M, J/IOR D 0437, 0017,1446,1700 ; 2864 RW, B, J/IOR ; 2865 .UCODE ; 2866 ; 2867 1446: U 1446, 1500,3551,0303,0274,4003,7700,0200,0003,0001 ; 2868 IOR: [AR]_[AR].OR.AC,EXIT ; 2869 ; 2870 .DCODE D 0440, 1015,1447,1100 ; 2871 440: R-PF, AC, J/ANDCB D 0441, 0015,1447,3000 ; 2872 I-PF, AC, J/ANDCB D 0442, 0016,1447,1700 ; 2873 RW, M, J/ANDCB D 0443, 0017,1447,1700 ; 2874 RW, B, J/ANDCB ; 2875 .UCODE ; 2876 ; 2877 1447: U 1447, 1443,7441,0303,4174,4007,0700,0000,0000,0000 ; 2878 ANDCB: [AR]_.NOT.[AR],J/ANDCA ; 2879 ; 2880 .DCODE D 0444, 1015,1450,1100 ; 2881 444: R-PF, AC, J/EQV D 0445, 0015,1450,3000 ; 2882 I-PF, AC, J/EQV D 0446, 0016,1450,1700 ; 2883 RW, M, J/EQV D 0447, 0017,1450,1700 ; 2884 RW, B, J/EQV ; 2885 .UCODE ; 2886 ; 2887 1450: U 1450, 1500,7551,0303,0274,4003,7700,0200,0003,0001 ; 2888 EQV: [AR]_[AR].EQV.AC,EXIT ; 2889 ; 2890 .DCODE D 0450, 0015,1451,3000 ; 2891 450: I-PF, AC, J/SETCA D 0451, 0015,1451,3000 ; 2892 I-PF, AC, J/SETCA D 0452, 0016,1451,2700 ; 2893 IW, M, J/SETCA D 0453, 0017,1451,2700 ; 2894 IW, B, J/SETCA ; 2895 .UCODE ; 2896 ; 2897 1451: U 1451, 1500,7771,0003,0274,4003,7700,0200,0003,0001 ; 2898 SETCA: [AR]_.NOT.AC,EXIT ; 2899 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 79 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BOOLEAN GROUP ; 2900 .DCODE D 0454, 1015,1452,1100 ; 2901 454: R-PF, AC, J/ORCA D 0455, 0015,1452,3000 ; 2902 I-PF, AC, J/ORCA D 0456, 0016,1452,1700 ; 2903 RW, M, J/ORCA D 0457, 0017,1452,1700 ; 2904 RW, B, J/ORCA ; 2905 .UCODE ; 2906 ; 2907 1452: U 1452, 0564,7771,0005,0274,4007,0700,0000,0000,0000 ; 2908 ORCA: [BR]_.NOT.AC U 0564, 1500,3111,0503,4174,4003,7700,0200,0003,0001 ; 2909 [AR]_[AR].OR.[BR],EXIT ; 2910 ; 2911 .DCODE D 0460, 1015,1453,1100 ; 2912 460: R-PF, AC, J/SETCM D 0461, 0015,1453,3000 ; 2913 I-PF, AC, J/SETCM D 0462, 0016,1453,1700 ; 2914 RW, M, J/SETCM D 0463, 0017,1453,1700 ; 2915 RW, B, J/SETCM ; 2916 .UCODE ; 2917 ; 2918 1453: U 1453, 1500,7441,0303,4174,4003,7700,0200,0003,0001 ; 2919 SETCM: [AR]_.NOT.[AR],EXIT ; 2920 ; 2921 .DCODE D 0464, 1015,1454,1100 ; 2922 464: R-PF, AC, J/ORCM D 0465, 0015,1454,3000 ; 2923 I-PF, AC, J/ORCM D 0466, 0016,1454,1700 ; 2924 RW, M, J/ORCM D 0467, 0017,1454,1700 ; 2925 RW, B, J/ORCM ; 2926 .UCODE ; 2927 ; 2928 1454: U 1454, 1446,7441,0303,4174,4007,0700,0000,0000,0000 ; 2929 ORCM: [AR]_.NOT.[AR],J/IOR ; 2930 ; 2931 .DCODE D 0470, 1015,1455,1100 ; 2932 470: R-PF, AC, J/ORCB D 0471, 0015,1455,3000 ; 2933 I-PF, AC, J/ORCB D 0472, 0016,1455,1700 ; 2934 RW, M, J/ORCB D 0473, 0017,1455,1700 ; 2935 RW, B, J/ORCB ; 2936 .UCODE ; 2937 ; 2938 1455: U 1455, 1453,4551,0303,0274,4007,0700,0000,0000,0000 ; 2939 ORCB: [AR]_[AR].AND.AC,J/SETCM ; 2940 ; 2941 .DCODE D 0474, 0015,1456,3000 ; 2942 474: I-PF, AC, J/SETO D 0475, 0015,1456,3000 ; 2943 I-PF, AC, J/SETO D 0476, 0016,1456,2700 ; 2944 IW, M, J/SETO D 0477, 0017,1456,2700 ; 2945 IW, B, J/SETO ; 2946 .UCODE ; 2947 ; 2948 1456: U 1456, 1500,2441,0703,4174,4003,7700,4200,0003,0001 ; 2949 SETO: [AR]_-[ONE], EXIT ; 2950 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 80 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ROTATES AND LOGICAL SHIFTS -- ROT, LSH, JFFO ; 2951 .TOC "ROTATES AND LOGICAL SHIFTS -- ROT, LSH, JFFO" ; 2952 ; 2953 .DCODE D 0240, 0400,1622,1000 ; 2954 240: SH, J/ASH D 0241, 0400,1632,1000 ; 2955 SH, J/ROT D 0242, 0400,1612,1000 ; 2956 SH, J/LSH D 0243, 0000,1462,2100 ; 2957 I, J/JFFO D 0244, 0000,1466,3000 ; 2958 I-PF, J/ASHC D 0245, 0500,1470,1000 ; 2959 245: SHC, J/ROTC D 0246, 0500,1464,1000 ; 2960 SHC, J/LSHC ; 2961 .UCODE ; 2962 ; 2963 ; 2964 ;HERE IS THE CODE FOR LOGICAL SHIFT. THE EFFECTIVE ADDRESS IS ; 2965 ; IN AR. ; 2966 1612: ; 2967 LSH: [AR]_AC, ;PICK UP AC ; 2968 FE_-FE-1, ;NEGATIVE SHIFT U 1612, 0572,3771,0003,0276,6007,0700,1000,0031,1777 ; 2969 J/LSHL ;SHIFT LEFT ; 2970 1613: [AR]_AC.AND.MASK, ;MAKE IT LOOK POSITIVE ; 2971 FE_FE+1, ;UNDO -1 AT SHIFT U 1613, 0611,4551,1203,0276,6007,0700,1000,0041,0001 ; 2972 J/ASHR ;GO SHIFT RIGHT ; 2973 ; 2974 LSHL: [AR]_[AR]*2, ;SHIFT LEFT U 0572, 1515,3445,0303,4174,4007,0700,1020,0041,0001 ; 2975 SHIFT, J/STAC ;FAST SHIFT & GO STORE AC ; 2976 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 81 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ROTATES AND LOGICAL SHIFTS -- ROT, LSH, JFFO ; 2977 ;HERE IS THE CODE FOR ARITHMETIC SHIFT. THE EFFECTIVE ADDRESS IS ; 2978 ; IN AR. ; 2979 ; 2980 ASH36 LEFT "[AR]_[AR]*2 LONG, ASHC, STEP SC, ASH AROV" ; 2981 ; 2982 1622: U 1622, 0632,4222,0000,4174,4007,0700,0000,0000,0000 ; 2983 ASH: Q_0, J/ASHL0 ;HARDWARE ONLY DOES ASHC ; 2984 1623: [AR]_AC, ;GET THE ARGUMENT U 1623, 0611,3771,0003,0276,6007,0700,1000,0041,0001 ; 2985 FE_FE+1 ;FE HAS NEGATIVE SHIFT COUNT ; 2986 ASHR: [AR]_[AR]*.5, ;SHIFT RIGHT ; 2987 ASH, SHIFT, ;FAST SHIFT U 0611, 1515,3447,0303,4174,4007,0700,1020,0041,0001 ; 2988 J/STAC ;STORE AC WHEN DONE ; 2989 ; 2990 ASHL0: [AR]_AC*.5, ;GET INTO 9 CHIPS U 0632, 0454,3777,0003,0274,4007,0631,2000,0060,0000 ; 2991 STEP SC ;SEE IF NULL SHIFT ; 2992 =0 U 0454, 0454,3444,0303,4174,4447,0630,2000,0060,0000 ; 2993 ASHL: ASH36 LEFT, J/ASHL ;SHIFT LEFT ; 2994 ;SLOW BECAUSE WE HAVE TO ; 2995 ; TEST FOR OVERFLOW ; 2996 U 0455, 1515,3445,0303,4174,4007,0700,0000,0000,0000 ; 2997 ASHX: [AR]_[AR]*2, J/STAC ;SHIFT BACK INTO 10 CHIPS ; 2998 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 82 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ROTATES AND LOGICAL SHIFTS -- ROT, LSH, JFFO ; 2999 ;HERE IS THE CODE FOR ROTATE. THE EFFECTIVE ADDRESS IS ; 3000 ; IN AR. ; 3001 1632: ; 3002 ROT: [AR]_AC*.5, ;PICK UP THE AC (& SHIFT) ; 3003 FE_-FE-1, ;NEGATIVE SHIFT COUNT U 1632, 0747,3777,0003,0274,4007,0701,1000,0031,1777 ; 3004 J/ROTL ;ROTATE LEFT ; 3005 1633: [AR]_AC*.5, ;PICK UP THE AC (& SHIFT) U 1633, 0646,3777,0003,0274,4007,0701,1000,0041,0001 ; 3006 FE_FE+1 ;NEGATIVE SHIFT COUNT U 0646, 0701,3447,0303,4174,4007,0700,0000,0000,0000 ; 3007 [AR]_[AR]*.5 ;PUT IN 9 DIPS ; 3008 [AR]_[AR]*.5, ;SHIFT RIGHT U 0701, 0706,3447,0303,4174,4037,0700,1020,0041,0001 ; 3009 ROT, SHIFT ;FAST SHIFT U 0706, 0455,3445,0303,4174,4007,0700,0000,0000,0000 ; 3010 ASHXX: [AR]_[AR]*2,J/ASHX ;SHIFT TO STD PLACE ; 3011 U 0747, 0752,3447,0303,4174,4007,0700,0000,0000,0000 ; 3012 ROTL: [AR]_[AR]*.5 ;PUT IN RIGHT 36-BITS ; 3013 [AR]_[AR]*2, ;ROTATE LEFT ; 3014 ROT, SHIFT, ;FAST SHIFT U 0752, 0706,3445,0303,4174,4037,0700,1020,0041,0001 ; 3015 J/ASHXX ;ALL DONE--SHIFT BACK ; 3016 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 83 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ROTATES AND LOGICAL SHIFTS -- ROT, LSH, JFFO ; 3017 1462: ; 3018 JFFO: [BR]_AC.AND.MASK, 4T, ;GET AC WITH NO SIGN U 1462, 0502,4551,1205,0276,6007,0622,0000,0000,0000 ; 3019 SKIP AD.EQ.0 ; EXTENSION. SKIP IF ; 3020 ; ZERO. ; 3021 =0 [PC]_[AR], ;NOT ZERO--JUMP ; 3022 LOAD VMA, FETCH, ;GET NEXT INST U 0502, 0767,3441,0301,4174,4007,0700,0200,0014,0012 ; 3023 J/JFFO1 ;ENTER LOOP U 0503, 1400,4223,0000,1174,4007,0700,0400,0000,1441 ; 3024 AC[1]_0, J/DONE ;ZERO--DONE ; 3025 U 0767, 0514,4443,0000,4174,4007,0700,1000,0071,1764 ; 3026 JFFO1: FE_-12. ;WHY -12.? WELL THE ; 3027 ; HARDWARE LOOKS AT ; 3028 ; BIT -2 SO THE FIRST ; 3029 ; 2 STEPS MOVE THE BR ; 3030 ; OVER. WE ALSO LOOK AT ; 3031 ; THE DATA BEFORE THE SHIFT ; 3032 ; SO WE END UP GOING 1 PLACE ; 3033 ; TOO MANY. THAT MEANS THE ; 3034 ; FE SHOULD START AT -3. ; 3035 ; HOWEVER, WE COUNT THE FE BY ; 3036 ; 4 (BECAUSE THE 2 LOW ORDER ; 3037 ; BITS DO NOT COME BACK) SO ; 3038 ; FE_-12. ; 3039 =0 ; 3040 JFFOL: [BR]_[BR]*2, ;SHIFT LEFT ; 3041 FE_FE+4, ;COUNT UP BIT NUMBER U 0514, 0514,3445,0505,4174,4007,0520,1000,0041,0004 ; 3042 SKIP DP0, J/JFFOL ;LOOP TILL WE FIND THE BIT U 0515, 1006,3777,0003,4334,4057,0700,0000,0041,0000 ; 3043 [AR]_FE ;GET ANSWER BACK U 1006, 1023,4251,0303,4374,4007,0700,0000,0000,0077 ; 3044 [AR]_[AR].AND.# CLR LH,#/77 ;MASK TO 1 COPY U 1023, 0100,3440,0303,1174,4156,4700,0400,0000,1441 ; 3045 AC[1]_[AR], NEXT INST ;STORE AND EXIT ; 3046 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 84 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ROTATES AND LOGICAL SHIFTS -- LSHC ; 3047 .TOC "ROTATES AND LOGICAL SHIFTS -- LSHC" ; 3048 ; 3049 ;SHIFT CONNECTIONS WHEN THE SPECIAL FUNCTION "LSHC" IS DONE: ; 3050 ; ; 3051 ; !-! !----!------------------------------------! ; 3052 ; !0!-->!0000! HIGH ORDER 36 BITS ! RAM FILE ; 3053 ; !-! !----!------------------------------------! ; 3054 ; ^ ; 3055 ; : ; 3056 ; .................................... ; 3057 ; : ; 3058 ; !----!------------------------------------! ; 3059 ; !0000! LOW ORDER 36 BITS ! Q-REGISTER ; 3060 ; !----!------------------------------------! ; 3061 ; ^ ; 3062 ; : ; 3063 ; !-! ; 3064 ; !0! ; 3065 ; !-! ; 3066 ; ; 3067 ; 3068 1464: U 1464, 0544,4443,0000,4174,4007,0630,2000,0060,0000 ; 3069 LSHC: STEP SC, J/LSHCL U 1465, 1026,3333,0003,4174,4007,0700,2000,0031,5777 ; 3070 1465: READ [AR], SC_-SHIFT-1 U 1026, 0534,4443,0000,4174,4007,0630,2000,0060,0000 ; 3071 STEP SC ; 3072 =0 U 0534, 0534,3446,0505,4174,4057,0630,2000,0060,0000 ; 3073 LSHCR: [BR]_[BR]*.5 LONG,STEP SC,LSHC,J/LSHCR U 0535, 1033,3444,0505,4174,4007,0700,0000,0000,0000 ; 3074 [BR]_[BR]*2 LONG,J/LSHCX ; 3075 ; 3076 =0 U 0544, 0544,3444,0505,4174,4057,0630,2000,0060,0000 ; 3077 LSHCL: [BR]_[BR]*2 LONG,LSHC,STEP SC,J/LSHCL U 0545, 1033,3444,0505,4174,4007,0700,0000,0000,0000 ; 3078 [BR]_[BR]*2 LONG U 1033, 1036,3444,0505,4174,4007,0700,0000,0000,0000 ; 3079 LSHCX: [BR]_[BR]*2 LONG U 1036, 1064,3440,0505,0174,4007,0700,0400,0000,0000 ; 3080 AC_[BR], J/ASHCQ1 ; 3081 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 85 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ROTATES AND LOGICAL SHIFTS -- ASHC ; 3082 .TOC "ROTATES AND LOGICAL SHIFTS -- ASHC" ; 3083 ; 3084 ; 3085 1466: ; 3086 ASHC: READ [AR], ;PUT AR ON DP ; 3087 SC_SHIFT, LOAD FE, ;PUT SHIFT IN BOTH SC AND FE U 1466, 0554,3333,0003,4174,4007,0330,3000,0041,4000 ; 3088 SKIP ADR.EQ.0 ;SEE IF NULL SHIFT ; 3089 =0 Q_AC[1], ;NOT NULL--GET LOW WORD U 0554, 1046,3772,0000,1275,5007,0701,0000,0000,1441 ; 3090 J/ASHC1 ;CONTINUE BELOW U 0555, 0100,4443,0000,4174,4156,4700,0000,0000,0000 ; 3091 NIDISP: NEXT INST ;NULL--ALL DONE ; 3092 ASHC1: [BR]_AC*.5 LONG, ;GET HIGH WORD ; 3093 ;AND SHIFT Q U 1046, 0614,3776,0005,0274,4007,0631,0000,0000,0000 ; 3094 SKIP/SC ;SEE WHICH DIRECTION ; 3095 =0 [BR]_[BR]*.5, ;ADJUST POSITION ; 3096 SC_FE+S#, S#/1776, ;SUBRTACT 2 FROM FE U 0614, 0634,3447,0505,4174,4007,0700,2000,0041,1776 ; 3097 J/ASHCL ;GO LEFT ; 3098 [BR]_[BR]*.5, ;ADJUST POSITION U 0615, 0624,3447,0505,4174,4007,0700,2000,0031,1776 ; 3099 SC_S#-FE, S#/1776 ;SC_-2-FE, SC_+# OF STEPS ; 3100 =0 ;HERE TO GO RIGHT ; 3101 ASHCR: [BR]_[BR]*.5 LONG, ;GO RIGHT ; 3102 ASHC, ;SET DATA PATHS FOR ASHC (SEE DPE1) U 0624, 0624,3446,0505,4174,4047,0630,2000,0060,0000 ; 3103 STEP SC, J/ASHCR ;COUNT THE STEP AND KEEP LOOPING ; 3104 [BR]_[BR]*2 LONG, ;PUT BACK WHERE IT GOES U 0625, 1053,3444,0505,4174,4047,0700,0000,0000,0000 ; 3105 ASHC, J/ASHCX ;COMPLETE INSTRUCTION ; 3106 ; 3107 =0 ; 3108 ASHCL: [BR]_[BR]*2 LONG, ;GO LEFT ; 3109 ASHC, ASH AROV, ;SEE IF OVERFLOW U 0634, 0634,3444,0505,4174,4447,0630,2000,0060,0000 ; 3110 STEP SC, J/ASHCL ;LOOP OVER ALL PLACES ; 3111 [BR]_[BR]*2 LONG, ;SHIFT BACK WHERE IT GOES U 0635, 1053,3444,0505,4174,4447,0700,0000,0000,0000 ; 3112 ASHC, ASH AROV ;CAN STILL OVERFLOW ; 3113 ASHCX: AC_[BR]+[BR], 3T, ;PUT BACK HIGH WORD U 1053, 0642,0113,0505,0174,4007,0521,0400,0000,0000 ; 3114 SKIP DP0 ;SEE HOW TO FIX LOW SIGN ; 3115 =0 Q_Q.AND.#, #/377777, ;POSITIVE, CLEAR LOW SIGN U 0642, 1064,4662,0000,4374,0007,0700,0000,0037,7777 ; 3116 HOLD RIGHT, J/ASHCQ1 ;GO STORE ANSWER ; 3117 Q_Q.OR.#, #/400000, ;NEGATIVE, SET LOW SIGN U 0643, 1064,3662,0000,4374,0007,0700,0000,0040,0000 ; 3118 HOLD RIGHT ;IN LEFT HALF U 1064, 0100,3223,0000,1174,4156,4700,0400,0000,1441 ; 3119 ASHCQ1: AC[1]_Q, NEXT INST ;PUT BACK Q AND EXIT ; 3120 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 86 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ROTATES AND LOGICAL SHIFTS -- ROTC ; 3121 .TOC "ROTATES AND LOGICAL SHIFTS -- ROTC" ; 3122 ; 3123 ;SHIFT CONNECTIONS WHEN THE SPECIAL FUNCTION "ROTC" IS DONE: ; 3124 ; ; 3125 ; !----!------------------------------------! ; 3126 ; .....>!0000! HIGH ORDER 36 BITS ! RAM FILE ; 3127 ; : !----!------------------------------------! ; 3128 ; : ^ ; 3129 ; : : ; 3130 ; : ............................................ ; 3131 ; : : ; 3132 ; : : !----!------------------------------------! ; 3133 ; : ..!0000! LOW ORDER 36 BITS ! Q-REGISTER ; 3134 ; : !----!------------------------------------! ; 3135 ; : ^ ; 3136 ; : : ; 3137 ; :..............................................: ; 3138 ; ; 3139 ; 3140 1470: U 1470, 0742,4443,0000,4174,4007,0630,2000,0060,0000 ; 3141 ROTC: STEP SC, J/ROTCL U 1471, 1077,3333,0003,4174,4007,0700,2000,0031,5777 ; 3142 1471: READ [AR], SC_-SHIFT-1 U 1077, 0644,4443,0000,4174,4007,0630,2000,0060,0000 ; 3143 STEP SC ; 3144 =0 U 0644, 0644,3446,0505,4174,4077,0630,2000,0060,0000 ; 3145 ROTCR: [BR]_[BR]*.5 LONG,STEP SC,ROTC,J/ROTCR U 0645, 1033,3444,0505,4174,4007,0700,0000,0000,0000 ; 3146 [BR]_[BR]*2 LONG,J/LSHCX ; 3147 ; 3148 =0 U 0742, 0742,3444,0505,4174,4077,0630,2000,0060,0000 ; 3149 ROTCL: [BR]_[BR]*2 LONG,ROTC,STEP SC,J/ROTCL ; 3150 [BR]_[BR]*2 LONG, U 0743, 1033,3444,0505,4174,4007,0700,0000,0000,0000 ; 3151 J/LSHCX ; 3152 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 87 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 TEST GROUP ; 3153 .TOC "TEST GROUP" ; 3154 ; 3155 .DCODE ; 3156 ; 3157 ;SPECIAL MACROS USED ONLY IN B-FIELD OF TEST INSTRUCTIONS ; 3158 TN- "B/4" ; 3159 TNE "B/0" ; 3160 WORD-TNE "B/10" ;USED IN TIOE ; 3161 TNA "B/0" ; 3162 TNN "B/4" ; 3163 WORD-TNN "B/14" ;USED IN TION ; 3164 TZ- "B/5" ; 3165 TZE "B/1" ; 3166 TZA "B/1" ; 3167 TZN "B/5" ; 3168 TC- "B/6" ; 3169 TCE "B/2" ; 3170 TCA "B/2" ; 3171 TCN "B/6" ; 3172 TO- "B/7" ; 3173 TOE "B/3" ; 3174 TOA "B/3" ; 3175 TON "B/7" ; 3176 D 0600, 0000,1400,2100 ; 3177 600: I, J/DONE ;TRN- IS NOP D 0601, 0000,1400,2100 ; 3178 I, J/DONE ;SO IS TLN- D 0602, 0000,1475,2100 ; 3179 I, TNE, J/TDXX D 0603, 0000,1474,2100 ; 3180 I, TNE, J/TSXX D 0604, 0000,1473,2100 ; 3181 I, TNA, J/TDX D 0605, 0000,1472,2100 ; 3182 I, TNA, J/TSX D 0606, 0004,1475,2100 ; 3183 I, TNN, J/TDXX D 0607, 0004,1474,2100 ; 3184 I, TNN, J/TSXX ; 3185 D 0610, 0000,1400,2100 ; 3186 610: I, J/DONE ;TDN- IS A NOP D 0611, 0000,1400,2100 ; 3187 I, J/DONE ;TSN- ALSO D 0612, 0000,1475,1100 ; 3188 R, TNE, J/TDXX D 0613, 0000,1474,1100 ; 3189 R, TNE, J/TSXX D 0614, 0000,1473,1100 ; 3190 R, TNA, J/TDX D 0615, 0000,1472,1100 ; 3191 R, TNA, J/TSX D 0616, 0004,1475,1100 ; 3192 R, TNN, J/TDXX D 0617, 0004,1474,1100 ; 3193 R, TNN, J/TSXX ; 3194 D 0620, 0005,1473,2100 ; 3195 620: I, TZ-, J/TDX D 0621, 0005,1472,2100 ; 3196 I, TZ-, J/TSX D 0622, 0001,1475,2100 ; 3197 I, TZE, J/TDXX D 0623, 0001,1474,2100 ; 3198 I, TZE, J/TSXX D 0624, 0001,1473,2100 ; 3199 I, TZA, J/TDX D 0625, 0001,1472,2100 ; 3200 I, TZA, J/TSX D 0626, 0005,1475,2100 ; 3201 I, TZN, J/TDXX D 0627, 0005,1474,2100 ; 3202 I, TZN, J/TSXX ; 3203 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 88 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 TEST GROUP D 0630, 0005,1473,1100 ; 3204 630: R, TZ-, J/TDX D 0631, 0005,1472,1100 ; 3205 R, TZ-, J/TSX D 0632, 0001,1475,1100 ; 3206 R, TZE, J/TDXX D 0633, 0001,1474,1100 ; 3207 R, TZE, J/TSXX D 0634, 0001,1473,1100 ; 3208 R, TZA, J/TDX D 0635, 0001,1472,1100 ; 3209 R, TZA, J/TSX D 0636, 0005,1475,1100 ; 3210 R, TZN, J/TDXX D 0637, 0005,1474,1100 ; 3211 R, TZN, J/TSXX ; 3212 D 0640, 0006,1473,2100 ; 3213 640: I, TC-, J/TDX D 0641, 0006,1472,2100 ; 3214 I, TC-, J/TSX D 0642, 0002,1475,2100 ; 3215 I, TCE, J/TDXX D 0643, 0002,1474,2100 ; 3216 I, TCE, J/TSXX D 0644, 0002,1473,2100 ; 3217 I, TCA, J/TDX D 0645, 0002,1472,2100 ; 3218 I, TCA, J/TSX D 0646, 0006,1475,2100 ; 3219 I, TCN, J/TDXX D 0647, 0006,1474,2100 ; 3220 I, TCN, J/TSXX ; 3221 D 0650, 0006,1473,1100 ; 3222 650: R, TC-, J/TDX D 0651, 0006,1472,1100 ; 3223 R, TC-, J/TSX D 0652, 0002,1475,1100 ; 3224 R, TCE, J/TDXX D 0653, 0002,1474,1100 ; 3225 R, TCE, J/TSXX D 0654, 0002,1473,1100 ; 3226 R, TCA, J/TDX D 0655, 0002,1472,1100 ; 3227 R, TCA, J/TSX D 0656, 0006,1475,1100 ; 3228 R, TCN, J/TDXX D 0657, 0006,1474,1100 ; 3229 R, TCN, J/TSXX D 0660, 0007,1473,2100 ; 3230 660: I, TO-, J/TDX D 0661, 0007,1472,2100 ; 3231 I, TO-, J/TSX D 0662, 0003,1475,2100 ; 3232 I, TOE, J/TDXX D 0663, 0003,1474,2100 ; 3233 I, TOE, J/TSXX D 0664, 0003,1473,2100 ; 3234 I, TOA, J/TDX D 0665, 0003,1472,2100 ; 3235 I, TOA, J/TSX D 0666, 0007,1475,2100 ; 3236 I, TON, J/TDXX D 0667, 0007,1474,2100 ; 3237 I, TON, J/TSXX ; 3238 D 0670, 0007,1473,1100 ; 3239 670: R, TO-, J/TDX D 0671, 0007,1472,1100 ; 3240 R, TO-, J/TSX D 0672, 0003,1475,1100 ; 3241 R, TOE, J/TDXX D 0673, 0003,1474,1100 ; 3242 R, TOE, J/TSXX D 0674, 0003,1473,1100 ; 3243 R, TOA, J/TDX D 0675, 0003,1472,1100 ; 3244 R, TOA, J/TSX D 0676, 0007,1475,1100 ; 3245 R, TON, J/TDXX D 0677, 0007,1474,1100 ; 3246 R, TON, J/TSXX ; 3247 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 89 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 TEST GROUP ; 3248 .UCODE ; 3249 ; 3250 ;THESE 64 INSTRUCTIONS ARE DECODED BY MASK MODE(IMMEDIATE OR MEMORY) ; 3251 ; IN THE A FIELD, DISPATCH TO HERE ON THE J FIELD, AND RE-DISPATCH ; 3252 ; FOR THE MODIFICATION ON THE B FIELD. ; 3253 ; 3254 ; ENTER WITH 0,E OR (E) IN AR, B FIELD BITS 2 AND 3 AS FOLLOWS: ; 3255 ; 0 0 NO MODIFICATION ; 3256 ; 0 1 0S ; 3257 ; 1 0 COMPLEMENT ; 3258 ; 1 1 ONES ; 3259 ; THIS ORDER HAS NO SIGNIFICANCE EXCEPT THAT IT CORRESPONDS TO THE ; 3260 ; ORDER OF INSTRUCTIONS AT TGROUP. ; 3261 ; 3262 ;THE BIT 1 OF THE B FIELD IS USED TO DETERMINE THE SENSE ; 3263 ; OF THE SKIP ; 3264 ; 1 SKIP IF AC.AND.MASK .NE. 0 (TXX- AND TXXN) ; 3265 ; 0 SKIP IF AC.AND.MASK .EQ. 0 (TXXA AND TXXE) ; 3266 ; 3267 ;BIT 0 IS UNUSED AND MUST BE ZERO ; 3268 ; 3269 ; 3270 1472: U 1472, 1473,3770,0303,4344,4007,0700,0000,0000,0000 ; 3271 TSX: [AR]_[AR] SWAP ;TSXX AND TLXX ; 3272 1473: U 1473, 0014,4221,0005,4174,4003,7700,0000,0000,0000 ; 3273 TDX: [BR]_0,TEST DISP ; ALWAYS AND NEVER SKIP CASES ; 3274 ; 3275 1474: U 1474, 1475,3770,0303,4344,4007,0700,0000,0000,0000 ; 3276 TSXX: [AR]_[AR] SWAP ;TSXE, TSXN, TLXE, TLXN ; 3277 1475: ; 3278 TDXX: [BR]_[AR].AND.AC, ;TDXE, TDXN, TRXE, TRXN U 1475, 0014,4551,0305,0274,4003,7700,0000,0000,0000 ; 3279 TEST DISP ; 3280 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 90 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 TEST GROUP ; 3281 ;TEST DISP DOES AN 8 WAY BRANCH BASED ON THE B-FIELD OF DROM ; 3282 ; 3283 =1100 ; 3284 TEST-TABLE: ; 3285 ; 3286 ;CASE 0 & 4 -- TXNX U 0014, 1400,3333,0005,4174,4007,0571,0000,0000,0000 ; 3287 TXXX: READ [BR], TXXX TEST, 3T, J/DONE ; 3288 ; 3289 ;CASE 1 & 5 -- TXZ AND TXZX U 0015, 1116,7441,0303,4174,4007,0700,0000,0000,0000 ; 3290 [AR]_.NOT.[AR],J/TXZX ; 3291 ; 3292 ;CASE 2 & 6 -- TXC AND TXCX U 0016, 1123,6551,0303,0274,4007,0700,0000,0000,0000 ; 3293 [AR]_[AR].XOR.AC,J/TDONE ; 3294 ; 3295 ;CASE 3 & 7 -- TXO AND TXOX U 0017, 1123,3551,0303,0274,4007,0700,0000,0000,0000 ; 3296 [AR]_[AR].OR.AC,J/TDONE ; 3297 ; 3298 ;THE SPECIAL FUNCTION TXXX TEST CAUSES A MICROCODE SKIP IF ; 3299 ; AD.EQ.0 AND DROM B IS 0-3 OR AD.NE.0 AND DROM B IS 4-7. ; 3300 U 1116, 1123,4551,0303,0274,4007,0700,0000,0000,0000 ; 3301 TXZX: [AR]_[AR].AND.AC U 1123, 0014,3440,0303,0174,4007,0700,0400,0000,0000 ; 3302 TDONE: AC_[AR],J/TXXX ; 3303 ; READ BR,TXXX TEST,J/DONE ; 3304 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 91 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 COMPARE -- CAI, CAM ; 3305 .TOC "COMPARE -- CAI, CAM" ; 3306 ; 3307 .DCODE ; 3308 ; 3309 ;SPECIAL B-FIELD ENCODING USED BY SKIP-JUMP-COMPARE CLASS ; 3310 ; INSTRUCTIONS: ; 3311 ; 3312 SJC- "B/0" ;NEVER ; 3313 SJCL "B/1" ;LESS ; 3314 SJCE "B/2" ;EQUAL ; 3315 SJCLE "B/3" ;LESS EQUAL ; 3316 SJCA "B/4" ;ALWAYS ; 3317 SJCGE "B/5" ;GREATER THAN OR EQUAL ; 3318 SJCN "B/6" ;NOT EQUAL ; 3319 SJCG "B/7" ;GREATER ; 3320 ; 3321 .UCODE ; 3322 ; 3323 ;COMPARE TABLE ; 3324 =1000 ; 3325 SKIP-COMP-TABLE: ; 3326 ; 3327 ;CASE 0 -- NEVER U 0250, 0110,3443,0100,4174,4156,4700,0200,0014,0012 ; 3328 DONE ; 3329 ; 3330 ;CASE 1 -- LESS U 0251, 1400,3333,0003,4174,4007,0520,0000,0000,0000 ; 3331 READ [AR], SKIP DP0,J/DONE ; 3332 ; 3333 ;CASE 2 -- EQUAL U 0252, 1400,3333,0003,4174,4007,0621,0000,0000,0000 ; 3334 SKIPE: READ [AR], SKIP AD.EQ.0,J/DONE ; 3335 ; 3336 ;CASE 3 -- LESS OR EQUAL U 0253, 1400,3333,0003,4174,4007,0421,0000,0000,0000 ; 3337 READ [AR], SKIP AD.LE.0,J/DONE ; 3338 ; 3339 ;CASE 4 -- ALWAYS U 0254, 0110,0111,0701,4170,4156,4700,0200,0014,0012 ; 3340 VMA_[PC]+1, NEXT INST FETCH, FETCH ; 3341 ; 3342 ;CASE 5 -- GREATER THAN OR EQUAL U 0255, 0260,3333,0003,4174,4007,0520,0000,0000,0000 ; 3343 READ [AR], SKIP DP0,J/SKIP ; 3344 ; 3345 ;CASE 6 -- NOT EQUAL U 0256, 0260,3333,0003,4174,4007,0621,0000,0000,0000 ; 3346 READ [AR], SKIP AD.EQ.0,J/SKIP ; 3347 ; 3348 ;CASE 7 -- GREATER U 0257, 0260,3333,0003,4174,4007,0421,0000,0000,0000 ; 3349 READ [AR], SKIP AD.LE.0,J/SKIP ; 3350 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 92 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 COMPARE -- CAI, CAM ; 3351 .DCODE D 0300, 0000,1400,2100 ; 3352 300: I, SJC-, J/DONE ;CAI D 0301, 0001,1476,2100 ; 3353 I, SJCL, J/CAIM D 0302, 0002,1476,2100 ; 3354 I, SJCE, J/CAIM D 0303, 0003,1476,2100 ; 3355 I, SJCLE, J/CAIM D 0304, 0004,1476,2100 ; 3356 I, SJCA, J/CAIM D 0305, 0005,1476,2100 ; 3357 I, SJCGE, J/CAIM D 0306, 0006,1476,2100 ; 3358 I, SJCN, J/CAIM D 0307, 0007,1476,2100 ; 3359 I, SJCG, J/CAIM ; 3360 D 0310, 0000,1476,1100 ; 3361 310: R, SJC-, J/CAIM ;CAM D 0311, 0001,1476,1100 ; 3362 R, SJCL, J/CAIM D 0312, 0002,1476,1100 ; 3363 R, SJCE, J/CAIM D 0313, 0003,1476,1100 ; 3364 R, SJCLE, J/CAIM D 0314, 0004,1476,1100 ; 3365 R, SJCA, J/CAIM D 0315, 0005,1476,1100 ; 3366 R, SJCGE, J/CAIM D 0316, 0006,1476,1100 ; 3367 R, SJCN, J/CAIM D 0317, 0007,1476,1100 ; 3368 R, SJCG, J/CAIM ; 3369 .UCODE ; 3370 ; 3371 1476: U 1476, 0250,2551,0303,0274,4003,7701,4000,0000,0000 ; 3372 CAIM: [AR]_AC-[AR], 3T, SKIP-COMP DISP ; 3373 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 93 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC SKIPS -- AOS, SOS, SKIP ; 3374 .TOC "ARITHMETIC SKIPS -- AOS, SOS, SKIP" ; 3375 ;ENTER WITH (E) IN AR ; 3376 ; 3377 .DCODE D 0330, 0000,1477,1100 ; 3378 330: R, SJC-, J/SKIPS ;NOT A NOP IF AC .NE. 0 D 0331, 0001,1477,1100 ; 3379 R, SJCL, J/SKIPS D 0332, 0002,1477,1100 ; 3380 R, SJCE, J/SKIPS D 0333, 0003,1477,1100 ; 3381 R, SJCLE, J/SKIPS D 0334, 0004,1477,1100 ; 3382 R, SJCA, J/SKIPS D 0335, 0005,1477,1100 ; 3383 R, SJCGE, J/SKIPS D 0336, 0006,1477,1100 ; 3384 R, SJCN, J/SKIPS D 0337, 0007,1477,1100 ; 3385 R, SJCG, J/SKIPS ; 3386 .UCODE ; 3387 ; 3388 1477: ; 3389 SKIPS: FIX [AR] SIGN, U 1477, 0744,3770,0303,4174,0007,0360,0000,0000,0000 ; 3390 SKIP IF AC0 U 0744, 0250,3440,0303,0174,4003,7700,0400,0000,0000 ; 3391 =0 AC_[AR],SKIP-COMP DISP U 0745, 0250,4443,0000,4174,4003,7700,0000,0000,0000 ; 3392 SKIP-COMP DISP ; 3393 ; 3394 .DCODE D 0350, 0000,1431,1500 ; 3395 350: RW, SJC-, J/AOS D 0351, 0001,1431,1500 ; 3396 RW, SJCL, J/AOS D 0352, 0002,1431,1500 ; 3397 RW, SJCE, J/AOS D 0353, 0003,1431,1500 ; 3398 RW, SJCLE, J/AOS D 0354, 0004,1431,1500 ; 3399 RW, SJCA, J/AOS D 0355, 0005,1431,1500 ; 3400 RW, SJCGE, J/AOS D 0356, 0006,1431,1500 ; 3401 RW, SJCN, J/AOS D 0357, 0007,1431,1500 ; 3402 RW, SJCG, J/AOS ; 3403 .UCODE ; 3404 ; 3405 1431: U 1431, 1136,0111,0703,4174,4467,0701,0000,0001,0001 ; 3406 AOS: [AR]_[AR]+1, 3T, AD FLAGS U 1136, 1143,4443,0000,4174,4007,0700,0200,0003,0002 ; 3407 XOS: START WRITE U 1143, 1477,3333,0003,4175,5007,0701,0200,0000,0002 ; 3408 MEM WRITE,MEM_[AR],J/SKIPS ; 3409 ; 3410 .DCODE D 0370, 0000,1437,1500 ; 3411 370: RW, SJC-, J/SOS D 0371, 0001,1437,1500 ; 3412 RW, SJCL, J/SOS D 0372, 0002,1437,1500 ; 3413 RW, SJCE, J/SOS D 0373, 0003,1437,1500 ; 3414 RW, SJCLE, J/SOS D 0374, 0004,1437,1500 ; 3415 RW, SJCA, J/SOS D 0375, 0005,1437,1500 ; 3416 RW, SJCGE, J/SOS D 0376, 0006,1437,1500 ; 3417 RW, SJCN, J/SOS D 0377, 0007,1437,1500 ; 3418 RW, SJCG, J/SOS ; 3419 .UCODE ; 3420 ; 3421 1437: U 1437, 1136,1111,0703,4174,4467,0701,4000,0001,0001 ; 3422 SOS: [AR]_[AR]-1, 3T, AD FLAGS, J/XOS ; 3423 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 94 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 CONDITIONAL JUMPS -- JUMP, AOJ, SOJ, AOBJ ; 3424 .TOC "CONDITIONAL JUMPS -- JUMP, AOJ, SOJ, AOBJ" ; 3425 ; ENTER WITH E IN AR ; 3426 ; 3427 =1000 ; 3428 JUMP-TABLE: ; 3429 ; 3430 ;CASE 0 -- NEVER U 0270, 0100,3440,0505,0174,4156,4700,0400,0000,0000 ; 3431 AC_[BR], NEXT INST ; 3432 ; 3433 ;CASE 1 -- LESS U 0271, 0762,3770,0505,0174,4007,0520,0400,0000,0000 ; 3434 AC_[BR] TEST, SKIP DP0, J/JUMP- ; 3435 ; 3436 ;CASE 2 -- EQUAL U 0272, 0762,3770,0505,0174,4007,0621,0400,0000,0000 ; 3437 AC_[BR] TEST, SKIP AD.EQ.0, J/JUMP- ; 3438 ; 3439 ;CASE 3 -- LESS THAN OR EQUAL U 0273, 0762,3770,0505,0174,4007,0421,0400,0000,0000 ; 3440 AC_[BR] TEST, SKIP AD.LE.0, J/JUMP- ; 3441 ; 3442 ;CASE 4 -- ALWAYS U 0274, 0764,3440,0505,0174,4007,0700,0400,0000,0000 ; 3443 JMPA: AC_[BR], J/JUMPA ; 3444 ; 3445 ;CASE 5 -- GREATER THAN OR EQUAL TO U 0275, 0764,3770,0505,0174,4007,0520,0400,0000,0000 ; 3446 AC_[BR] TEST, SKIP DP0, J/JUMPA ; 3447 ; 3448 ;CASE 6 -- NOT EQUAL U 0276, 0764,3770,0505,0174,4007,0621,0400,0000,0000 ; 3449 AC_[BR] TEST, SKIP AD.EQ.0, J/JUMPA ; 3450 ; 3451 ;CASE 7 -- GREATER U 0277, 0764,3770,0505,0174,4007,0421,0400,0000,0000 ; 3452 AC_[BR] TEST, SKIP AD.LE.0, J/JUMPA ; 3453 ; 3454 =0 U 0762, 0110,3443,0100,4174,4156,4700,0200,0014,0012 ; 3455 JUMP-: DONE U 0763, 0110,3441,0301,4170,4156,4700,0200,0014,0012 ; 3456 JUMPA ; 3457 ; 3458 =0 U 0764, 0110,3441,0301,4170,4156,4700,0200,0014,0012 ; 3459 JUMPA: JUMPA U 0765, 0110,3443,0100,4174,4156,4700,0200,0014,0012 ; 3460 DONE ; 3461 ; 3462 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 95 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 CONDITIONAL JUMPS -- JUMP, AOJ, SOJ, AOBJ ; 3463 .DCODE D 0320, 0000,1400,2100 ; 3464 320: I, SJC-, J/DONE D 0321, 0001,1440,2100 ; 3465 I, SJCL, J/JUMP D 0322, 0002,1440,2100 ; 3466 I, SJCE, J/JUMP D 0323, 0003,1440,2100 ; 3467 I, SJCLE, J/JUMP D 0324, 0004,1520,2100 ; 3468 I, SJCA, J/JRST D 0325, 0005,1440,2100 ; 3469 I, SJCGE, J/JUMP D 0326, 0006,1440,2100 ; 3470 I, SJCN, J/JUMP D 0327, 0007,1440,2100 ; 3471 I, SJCG, J/JUMP ; 3472 .UCODE ; 3473 ; 3474 1440: U 1440, 0270,3771,0005,0276,6003,7700,0000,0000,0000 ; 3475 JUMP: [BR]_AC,JUMP DISP ; 3476 ; 3477 .DCODE D 0340, 0000,1611,3000 ; 3478 340: I-PF, SJC-, J/AOJ D 0341, 0001,1611,2100 ; 3479 I, SJCL, J/AOJ D 0342, 0002,1611,2100 ; 3480 I, SJCE, J/AOJ D 0343, 0003,1611,2100 ; 3481 I, SJCLE, J/AOJ D 0344, 0004,1611,2100 ; 3482 I, SJCA, J/AOJ D 0345, 0005,1611,2100 ; 3483 I, SJCGE, J/AOJ D 0346, 0006,1611,2100 ; 3484 I, SJCN, J/AOJ D 0347, 0007,1611,2100 ; 3485 I, SJCG, J/AOJ ; 3486 .UCODE ; 3487 ; 3488 1611: U 1611, 0270,0551,0705,0274,4463,7702,0000,0001,0001 ; 3489 AOJ: [BR]_AC+1, AD FLAGS, 4T, JUMP DISP ; 3490 ; 3491 .DCODE D 0360, 0000,1542,3000 ; 3492 360: I-PF, SJC-, J/SOJ D 0361, 0001,1542,2100 ; 3493 I, SJCL, J/SOJ D 0362, 0002,1542,2100 ; 3494 I, SJCE, J/SOJ D 0363, 0003,1542,2100 ; 3495 I, SJCLE, J/SOJ D 0364, 0004,1542,2100 ; 3496 I, SJCA, J/SOJ D 0365, 0005,1542,2100 ; 3497 I, SJCGE, J/SOJ D 0366, 0006,1542,2100 ; 3498 I, SJCN, J/SOJ D 0367, 0007,1542,2100 ; 3499 I, SJCG, J/SOJ ; 3500 .UCODE ; 3501 ; 3502 1542: U 1542, 0270,2551,0705,0274,4463,7702,4000,0001,0001 ; 3503 SOJ: [BR]_AC-1, AD FLAGS, 4T, JUMP DISP ; 3504 ; 3505 .DCODE D 0252, 0005,1547,2100 ; 3506 252: I, SJCGE, J/AOBJ D 0253, 0001,1547,2100 ; 3507 I, SJCL, J/AOBJ ; 3508 .UCODE ; 3509 ; 3510 1547: ; 3511 AOBJ: [BR]_AC+1000001, ;ADD 1 TO BOTH HALF WORDS ; 3512 INH CRY18, 3T, ;NO CARRY INTO LEFT HALF U 1547, 0270,0551,1505,0274,4403,7701,0000,0000,0000 ; 3513 JUMP DISP ;HANDLE EITHER AOBJP OR AOBJN ; 3514 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 96 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 AC DECODE JUMPS -- JRST, JFCL ; 3515 .TOC "AC DECODE JUMPS -- JRST, JFCL" ; 3516 ; 3517 .DCODE D 0254, 0000,1520,6000 ; 3518 254: I,VMA/0, AC DISP, J/JRST ;DISPATCHES TO 1 OF 16 ; 3519 ; PLACES ON AC BITS D 0255, 0000,1540,2100 ; 3520 I, J/JFCL ; 3521 .UCODE ; 3522 ; 3523 ;JRST DISPATCHES TO ONE OF 16 LOC'NS ON AC BITS ; 3524 ; 3525 =0000 ; 3526 1520: U 1520, 0110,3441,0301,4170,4156,4700,0200,0014,0012 ; 3527 JRST: JUMPA ;(0) JRST 0, U 1521, 0110,3441,0301,4170,4156,4700,0200,0014,0012 ; 3528 1521: JUMPA ;(1) PORTAL IS SAME AS JRST ; 3529 1522: VMA_[PC]-1, START READ, ;(2) JRSTF U 1522, 0150,1113,0701,4170,4007,0700,4200,0004,0012 ; 3530 J/JRSTF U 1523, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3531 1523: UUO ;(3) U 1524, 1004,4443,0000,4174,4007,0340,0000,0000,0000 ; 3532 1524: SKIP KERNEL, J/HALT ;(4) HALT ; 3533 1525: ; 3534 XJRSTF0: VMA_[AR], START READ, ;(5) XJRSTF U 1525, 2606,3443,0300,4174,4007,0700,0200,0004,0012 ; 3535 J/XJRSTF U 1526, 0320,4443,0000,4174,4007,0340,0000,0000,0000 ; 3536 1526: SKIP KERNEL, J/XJEN ;(6) XJEN U 1527, 1014,4443,0000,4174,4007,0340,0000,0000,0000 ; 3537 1527: SKIP KERNEL, J/XPCW ;(7) XPCW ; 3538 1530: VMA_[PC]-1, START READ, ;(10) U 1530, 1010,1113,0701,4170,4007,0040,4200,0004,0012 ; 3539 SKIP IO LEGAL, J/JRST10 U 1531, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3540 1531: UUO ;(11) ; 3541 1532: VMA_[PC]-1, START READ, ;(12) JEN U 1532, 0300,1113,0701,4170,4007,0040,4200,0004,0012 ; 3542 SKIP IO LEGAL, J/JEN U 1533, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3543 1533: UUO ;(13) U 1534, 1024,4443,0000,4174,4007,0340,0000,0000,0000 ; 3544 1534: SKIP KERNEL, J/SFM ;(14) SFM U 1535, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3545 1535: UUO ;(15) U 1536, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3546 1536: UUO ;(16) U 1537, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3547 1537: UUO ;(17) ; 3548 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 97 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 AC DECODE JUMPS -- JRST, JFCL ; 3549 =0* ; 3550 JRSTF: MEM READ, ;WAIT FOR DATA ; 3551 [HR]_MEM, ;STICK IN HR ; 3552 LOAD INST EA, ;LOAD @ AND XR U 0150, 2551,3771,0002,4365,5217,0700,0210,0000,0002 ; 3553 CALL [JRST0] ;COMPUTE EA AGAIN U 0152, 0110,3441,0301,4170,4156,4700,0200,0014,0012 ; 3554 JUMPA ;JUMP ; 3555 U 2551, 0030,4443,0000,2174,4006,6700,0000,0000,0000 ; 3556 JRST0: EA MODE DISP ;WHAT TYPE OF EA? ; 3557 =100* ; 3558 READ XR, ;INDEXED ; 3559 LOAD FLAGS, ;GET FLAGS FROM XR ; 3560 UPDATE USER, ;ALLOW USER TO SET U 0030, 0002,3773,0000,2274,4464,1700,0000,0001,0004 ; 3561 RETURN [2] ;ALL DONE ; 3562 READ [HR], ;PLAIN ; 3563 LOAD FLAGS, ;LOAD FLAGS FROM INST ; 3564 UPDATE USER, ;ALLOW USER TO SET U 0032, 0002,3333,0002,4174,4464,1700,0000,0001,0004 ; 3565 RETURN [2] ;RETURN ; 3566 [HR]_[HR]+XR, ;BOTH ; 3567 LOAD VMA, ;FETCH IND WORD ; 3568 START READ, ;START MEM CYCLE U 0034, 2556,0551,0202,2270,4007,0700,0200,0004,0012 ; 3569 J/JRST1 ;CONTINUE BELOW ; 3570 VMA_[HR], ;INDIRECT ; 3571 START READ, ;FETCH IND WORD ; 3572 PXCT EA, ;SETUP PXCT STUFF U 0036, 2556,3443,0200,4174,4007,0700,0200,0004,0112 ; 3573 J/JRST1 ;CONTINUE BELOW ; 3574 JRST1: MEM READ, ;WAIT FOR DATA ; 3575 [HR]_MEM, ;LOAD THE HR ; 3576 LOAD INST EA, ;LOAD @ AND XR U 2556, 2551,3771,0002,4365,5217,0700,0200,0000,0002 ; 3577 J/JRST0 ;LOOP BACK ; 3578 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 98 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 AC DECODE JUMPS -- JRST, JFCL ; 3579 =0 U 1004, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3580 HALT: UUO ;USER MODE U 1005, 2601,3441,0301,4174,4007,0700,0000,0000,0000 ; 3581 [PC]_[AR] ;EXEC MODE--CHANGE PC U 2601, 0104,4751,1217,4374,4007,0700,0000,0000,0001 ; 3582 HALT [HALT] ;HALT INSTRUCTION ; 3583 ; 3584 =0 U 1010, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3585 JRST10: UUO U 1011, 0303,4443,0000,4174,4007,0700,0000,0000,0000 ; 3586 J/JEN2 ;DISMISS INTERRUPT ; 3587 =0000 U 0300, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3588 JEN: UUO ; FLAGS ; 3589 MEM READ, ; 3590 [HR]_MEM, ;GET INST ; 3591 LOAD INST EA, ;LOAD XR & @ U 0301, 2551,3771,0002,4365,5217,0700,0210,0000,0002 ; 3592 CALL [JRST0] ;COMPUTE FLAGS ; 3593 =0011 U 0303, 2432,4553,1400,4374,4007,0331,0010,0007,7400 ; 3594 JEN2: DISMISS ;DISMISS INTERRUPT U 0307, 3610,3770,1416,4344,4007,0700,0010,0000,0000 ; 3595 =0111 CALL LOAD PI ;RELOAD PI HARDWARE U 0317, 0110,3441,0301,4170,4156,4700,0200,0014,0012 ; 3596 =1111 JUMPA ;GO JUMP ; 3597 = ; 3598 ; 3599 1540: ; 3600 JFCL: JFCL FLAGS, ;ALL DONE IN HARDWARE ; 3601 SKIP JFCL, ;SEE IF SKIPS ; 3602 3T, ;ALLOW TIME U 1540, 0762,4443,0000,4174,4467,0551,0000,0001,0010 ; 3603 J/JUMP- ;JUMP IF WE SHOULD ; 3604 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 99 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 EXTENDED ADDRESSING INSTRUCTIONS ; 3605 .TOC "EXTENDED ADDRESSING INSTRUCTIONS" ; 3606 ; 3607 =0000 U 0320, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3608 XJEN: UUO ;HERE IF USER MODE U 0321, 2432,4553,1400,4374,4007,0331,0010,0007,7400 ; 3609 DISMISS ;CLEAR HIGHEST INTERRUPT U 0325, 0335,3333,0012,4174,4437,0700,0000,0000,0000 ; 3610 =0101 READ [MASK], LOAD PI ;NO MORE INTERRUPTS ; 3611 =1101 ABORT MEM CYCLE, ;AVOID INTERRUPT PAGE FAIL U 0335, 1525,4223,0000,4364,4277,0700,0200,0000,0010 ; 3612 J/XJRSTF0 ;START READING FLAG WORD ; 3613 = ; 3614 U 2606, 2623,3771,0005,4365,5007,0700,0200,0000,0002 ; 3615 XJRSTF: MEM READ, [BR]_MEM ;PUT FLAGS IN BR ; 3616 [AR]_[AR]+1, ;INCREMENT ADDRESS ; 3617 LOAD VMA, ;PUT RESULT IN VMA U 2623, 2627,0111,0703,4174,4007,0700,0200,0004,0012 ; 3618 START READ ;START MEMORY ; 3619 MEM READ, [PC]_MEM, ;PUT DATA IN PC U 2627, 2701,3771,0001,4361,5007,0700,0200,0000,0002 ; 3620 HOLD LEFT ;IGNORE SECTION NUMBER ; 3621 READ [BR], LOAD FLAGS, ;LOAD NEW FLAGS U 2701, 2714,3333,0005,4174,4467,0700,0000,0001,0004 ; 3622 UPDATE USER ;BUT HOLD USER FLAG ; 3623 PISET: [FLG]_[FLG].AND.NOT.#, ;CLEAR PI CYCLE U 2714, 0305,5551,1313,4374,4007,0700,0000,0001,0000 ; 3624 FLG.PI/1, J/PIEXIT ;RELOAD PI HARDWARE ; 3625 ; INCASE THIS IS AN ; 3626 ; INTERRUPT INSTRUCTION ; 3627 ; 3628 =0 U 1014, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3629 XPCW: UUO ;USER MODE U 1015, 0060,4521,1205,4074,4007,0700,0000,0000,0000 ; 3630 [BR]_FLAGS ;PUT FLAGS IN BR ; 3631 =0*0 ; 3632 PIXPCW: VMA_[AR], START WRITE, ;STORE FLAGS U 0060, 3667,3443,0300,4174,4007,0700,0210,0003,0012 ; 3633 CALL [STOBR] ;PUT BR IN MEMORY ; 3634 =1*0 VMA_[AR]+1, LOAD VMA, ; 3635 START WRITE, ;PREPEARE TO STORE PC U 0064, 3670,0111,0703,4170,4007,0700,0210,0003,0012 ; 3636 CALL [STOPC] ;PUT PC IN MEMORY ; 3637 =1*1 [AR]_[AR]+1, ;DO NEW PC PART U 0065, 2606,0111,0703,4174,4007,0700,0200,0004,0002 ; 3638 START READ, J/XJRSTF ; 3639 = ; 3640 ; 3641 =0 U 1024, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3642 SFM: UUO U 1025, 2715,3443,0300,4174,4007,0700,0200,0003,0012 ; 3643 VMA_[AR], START WRITE ;STORE FLAGS U 2715, 0435,4521,1203,4074,4007,0700,0000,0000,0000 ; 3644 [AR]_FLAGS, J/STORE ;STORE AND EXIT ; 3645 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 100 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 XCT ; 3646 .TOC "XCT" ; 3647 ; 3648 .DCODE D 0256, 0000,1541,1100 ; 3649 256: R, J/XCT ;OPERAND FETCHED AS DATA ; 3650 .UCODE ; 3651 ; 3652 1541: U 1541, 1034,4443,0000,4174,4007,0340,0000,0000,0000 ; 3653 XCT: SKIP KERNEL ;SEE IF MAY BE PXCT ; 3654 =0 ; 3655 XCT1A: [HR]_[AR], ;STUFF INTO HR ; 3656 DBUS/DP, ;PLACE ON DBUS FOR IR ; 3657 LOAD INST, ;LOAD IR, AC, XR, ETC. ; 3658 PXCT/E1, ;ALLOW XR TO BE PREVIOUS U 1034, 2716,3441,0302,4174,4617,0700,0000,0000,0100 ; 3659 J/XCT1 ;CONTINUE BELOW ; 3660 ; 3661 READ [HR], ;LOAD PXCT FLAGS ; 3662 LOAD PXCT, ; .. U 1035, 1034,3333,0002,4174,4167,0700,0000,0000,0000 ; 3663 J/XCT1A ;CONTINUE WITH NORMAL FLOW ; 3664 ; 3665 XCT1: WORK[YSAVE]_[HR] CLR LH,;SAVE FOR IO INSTRUCTIONS U 2716, 0371,4713,1202,7174,4007,0700,0400,0000,0422 ; 3666 J/XCT2 ;GO EXECUTE IT ; 3667 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 101 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 STACK INSTRUCTIONS -- PUSHJ, PUSH, POP, POPJ ; 3668 .TOC "STACK INSTRUCTIONS -- PUSHJ, PUSH, POP, POPJ" ; 3669 ; 3670 .DCODE D 0260, 0000,1544,2100 ; 3671 260: I, B/0, J/PUSHJ D 0261, 0002,1543,3100 ; 3672 IR, B/2, J/PUSH D 0262, 0002,1545,2100 ; 3673 I, B/2, J/POP D 0263, 0000,1546,2100 ; 3674 I, J/POPJ ; 3675 .UCODE ; 3676 ; 3677 ;ALL START WITH E IN AR ; 3678 1543: ; 3679 PUSH: MEM READ, ;PUT MEMOP IN BR U 1543, 2717,3771,0005,4365,5007,0700,0200,0000,0002 ; 3680 [BR]_MEM ; .. ; 3681 PUSH1: [ARX]_AC+1000001, ;BUMP BOTH HALVES OF AC ; 3682 INH CRY18, ;NO CARRY ; 3683 LOAD VMA, ;START TO STORE ITEM ; 3684 START WRITE, ;START MEM CYCLE ; 3685 PXCT STACK WORD, ;THIS IS THE STACK DATA WORD ; 3686 3T, ;ALLOW TIME ; 3687 SKIP CRY0, ;GO TO STMAC, SKIP IF PDL OV U 2717, 1044,0551,1504,0274,4407,0311,0200,0003,0712 ; 3688 J/STMAC ; .. ; 3689 ; 3690 1544: ; 3691 PUSHJ: [BR]_PC WITH FLAGS, ;COMPUTE UPDATED FLAGS ; 3692 CLR FPD, ;CLEAR FIRST-PART-DONE U 1544, 2717,3741,0105,4074,4467,0700,0000,0005,0000 ; 3693 J/PUSH1 ; AND JOIN PUSH CODE ; 3694 ; 3695 =0 ; 3696 STMAC: MEM WRITE, ;WAIT FOR MEMORY ; 3697 MEM_[BR], ;STORE BR ON STACK ; 3698 B DISP, ;SEE IF PUSH OR PUSHJ U 1044, 0220,3333,0005,4175,5003,7701,0200,0000,0002 ; 3699 J/JSTAC ;BELOW ; 3700 ;WE MUST STORE THE STACK WORD PRIOR TO SETTING PDL OV IN CASE OF ; 3701 ; PAGE FAIL. ; 3702 MEM WRITE, ;WAIT FOR MEMORY U 1045, 2720,3333,0005,4175,5007,0701,0200,0000,0002 ; 3703 MEM_[BR] ;STORE BR ; 3704 SETPDL: SET PDL OV, ;OVERFLOW ; 3705 B DISP, ;SEE IF PUSH OR PUSHJ U 2720, 0220,4443,0000,4174,4463,7700,0000,0001,2000 ; 3706 J/JSTAC ;BELOW ; 3707 ; 3708 =00 ; 3709 JSTAC: [PC]_[AR], ;PUSHJ--LOAD PC ; 3710 LOAD VMA, ;LOAD ADDRESS U 0220, 0221,3441,0301,4174,4007,0700,0200,0014,0012 ; 3711 FETCH ;GET NEXT INST ; 3712 JSTAC1: AC_[ARX], ;STORE BACK STACK PTR U 0221, 0100,3440,0404,0174,4156,4700,0400,0000,0000 ; 3713 NEXT INST ;DO NEXT INST ; 3714 AC_[ARX], ;UPDATE STACK POINTER U 0222, 1400,3440,0404,0174,4007,0700,0400,0000,0000 ; 3715 J/DONE ;DO NEXT INST ; 3716 = ; 3717 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 102 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 STACK INSTRUCTIONS -- PUSHJ, PUSH, POP, POPJ ; 3718 1545: ; 3719 POP: [ARX]_AC, ;GET POINTER ; 3720 LOAD VMA, ;ADDRESS OF STACK WORD ; 3721 START READ, 3T, ;START CYCLE U 1545, 2721,3771,0004,0276,6007,0701,0200,0004,0712 ; 3722 PXCT STACK WORD ;FOR PXCT ; 3723 ; 3724 MEM READ, ;LOAD BR (QUIT IF PAGE FAIL) U 2721, 2722,3771,0005,4365,5007,0700,0200,0000,0002 ; 3725 [BR]_MEM ;STACK WORD TO BR ; 3726 ; 3727 [ARX]_[ARX]+#, ;UPDATE POINTER ; 3728 #/777777, ;-1 IN EACH HALF ; 3729 INH CRY18, 3T, ;BUT NO CARRY U 2722, 1144,0551,0404,4374,4407,0311,0000,0077,7777 ; 3730 SKIP CRY0 ;SEE IF OVERFLOW ; 3731 ; 3732 =0 VMA_[AR], ;EFFECTIVE ADDRESS ; 3733 PXCT DATA, ;FOR PXCT ; 3734 START WRITE, ;WHERE TO STORE RESULT U 1144, 2724,3443,0300,4174,4007,0700,0200,0003,0312 ; 3735 J/POPX1 ;OVERFLOW ; 3736 ; 3737 VMA_[AR], ;EFFECTIVE ADDRESS ; 3738 PXCT DATA, ;FOR PXCT U 1145, 2723,3443,0300,4174,4007,0700,0200,0003,0312 ; 3739 START WRITE ;WHERE TO STORE RESULT ; 3740 ; 3741 MEM WRITE, ;WAIT FOR MEM ; 3742 MEM_[BR], ;STORE BR ; 3743 B DISP, ;POP OR POPJ? U 2723, 0220,3333,0005,4175,5003,7701,0200,0000,0002 ; 3744 J/JSTAC ;STORE POINTER ; 3745 ; 3746 ; 3747 POPX1: MEM WRITE, ;WAIT FOR MEMORY ; 3748 MEM_[BR], ;STORE BR U 2724, 2720,3333,0005,4175,5007,0701,0200,0000,0002 ; 3749 J/SETPDL ;GO SET PDL OV ; 3750 ; 3751 1546: ; 3752 POPJ: [ARX]_AC, ;GET POINTER ; 3753 LOAD VMA, ;POINT TO STACK WORD ; 3754 PXCT STACK WORD, 3T, ;FOR PXCT U 1546, 2725,3771,0004,0276,6007,0701,0200,0004,0712 ; 3755 START READ ;START READ ; 3756 [ARX]_[ARX]+#, ;UPDATE POINTER ; 3757 #/777777, ;-1 IN BOTH HALFS ; 3758 INH CRY18, 3T, ;INHIBIT CARRY 18 U 2725, 1146,0551,0404,4374,4407,0311,0000,0077,7777 ; 3759 SKIP CRY0 ;SEE IF OVERFLOW U 1146, 1147,4443,0000,4174,4467,0700,0000,0001,2000 ; 3760 =0 SET PDL OV ;SET OVERFLOW ; 3761 MEM READ, [PC]_MEM, ;STICK DATA IN PC ; 3762 HOLD LEFT, ;NO FLAGS U 1147, 0221,3771,0001,4361,5007,0700,0200,0000,0002 ; 3763 J/JSTAC1 ;STORE POINTER ; 3764 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 103 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 STACK INSTRUCTIONS -- ADJSP ; 3765 .TOC "STACK INSTRUCTIONS -- ADJSP" ; 3766 ; 3767 .DCODE D 0105, 0000,1551,3000 ; 3768 105: I-PF, B/0, J/ADJSP ; 3769 .UCODE ; 3770 ; 3771 1551: ; 3772 ADJSP: [AR]_[AR] SWAP, ;MAKE 2 COPIES OF RH U 1551, 2726,3770,0303,4344,0007,0700,0000,0000,0000 ; 3773 HOLD RIGHT ; 3774 [BR]_AC, ;READ AC, SEE IF MINUS ; 3775 3T, U 2726, 1150,3771,0005,0276,6007,0521,0000,0000,0000 ; 3776 SKIP DP0 ; 3777 =0 AC_[BR]+[AR], ;UPDATE AC ; 3778 INH CRY18, ;NO CARRY ; 3779 SKIP DP0, ;SEE IF STILL OK ; 3780 3T, ;ALLOW TIME U 1150, 1152,0113,0503,0174,4407,0521,0400,0000,0000 ; 3781 J/ADJSP1 ;TEST FOR OFLO ; 3782 AC_[BR]+[AR], ;UPDATE AC ; 3783 INH CRY18, ;NO CARRY ; 3784 SKIP DP0, ;SEE IF STILL MINUS ; 3785 3T, ;ALLOW TIME FOR SKIP U 1151, 1154,0113,0503,0174,4407,0521,0400,0000,0000 ; 3786 J/ADJSP2 ;CONTINUE BELOW ; 3787 ; 3788 =0 U 1152, 0100,4443,0000,4174,4156,4700,0000,0000,0000 ; 3789 ADJSP1: NEXT INST ;NO OVERFLOW ; 3790 SET PDL OV, ;SET PDL OV U 1153, 0555,4443,0000,4174,4467,0700,0000,0001,2000 ; 3791 J/NIDISP ;GO DO NICOND DISP ; 3792 ; 3793 =0 ; 3794 ADJSP2: SET PDL OV, ;SET PDL OV U 1154, 0555,4443,0000,4174,4467,0700,0000,0001,2000 ; 3795 J/NIDISP ;GO DO NICOND DISP U 1155, 0100,4443,0000,4174,4156,4700,0000,0000,0000 ; 3796 NEXT INST ;NO OVERFLOW ; 3797 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 104 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 SUBROUTINE CALL/RETURN -- JSR, JSP, JSA, JRA ; 3798 .TOC "SUBROUTINE CALL/RETURN -- JSR, JSP, JSA, JRA" ; 3799 ; 3800 .DCODE D 0264, 0000,1552,2100 ; 3801 264: I, J/JSR D 0265, 0000,1550,2100 ; 3802 I, J/JSP D 0266, 0000,1554,2100 ; 3803 I, J/JSA D 0267, 0000,1555,2100 ; 3804 I, J/JRA ; 3805 .UCODE ; 3806 ; 3807 1550: U 1550, 2727,3741,0105,4074,4007,0700,0000,0000,0000 ; 3808 JSP: [BR]_PC WITH FLAGS ;GET PC WITH FLAGS ; 3809 CLR FPD, ;CLEAR FIRST-PART-DONE ; 3810 AC_[BR], ;STORE FLAGS U 2727, 0764,3440,0505,0174,4467,0700,0400,0005,0000 ; 3811 J/JUMPA ;GO JUMP ; 3812 ; 3813 1552: ; 3814 JSR: [BR]_PC WITH FLAGS, ;GET PC WITH FLAGS U 1552, 2730,3741,0105,4074,4467,0700,0000,0005,0000 ; 3815 CLR FPD ;CLEAR FIRST-PART-DONE ; 3816 VMA_[AR], ;EFFECTIVE ADDRESS U 2730, 2731,3443,0300,4174,4007,0700,0200,0003,0012 ; 3817 START WRITE ;STORE OLD PC WORD ; 3818 MEM WRITE, ;WAIT FOR MEMORY U 2731, 2732,3333,0005,4175,5007,0701,0200,0000,0002 ; 3819 MEM_[BR] ;STORE ; 3820 [PC]_[AR]+1000001, ;PC _ E+1 ; 3821 HOLD LEFT, ;NO JUNK IN LEFT ; 3822 3T, ;ALLOW TIME FOR DBM U 2732, 1400,0551,0301,4370,4007,0701,0000,0000,0001 ; 3823 J/DONE ;[127] START AT E+1 ; 3824 ;[127] MUST NICOND TO CLEAR TRAP CYCLE ; 3825 ; 3826 ; 3827 ; 3828 1554: ; 3829 JSA: [BR]_[AR], ;SAVE E U 1554, 2733,3441,0305,4174,4007,0700,0200,0003,0002 ; 3830 START WRITE ;START TO STORE U 2733, 0130,3770,0304,4344,4007,0700,0000,0000,0000 ; 3831 [ARX]_[AR] SWAP ;ARX LEFT _ E ; 3832 =0*0 [AR]_AC, ;GET OLD AC U 0130, 3075,3771,0003,0276,6007,0700,0010,0000,0000 ; 3833 CALL [IBPX] ;SAVE AR IN MEMORY ; 3834 =1*0 [ARX]_[PC], ;ARX NOW HAS E,,PC ; 3835 HOLD LEFT, ; .. U 0134, 3671,3441,0104,4170,4007,0700,0010,0000,0000 ; 3836 CALL [AC_ARX] ;GO PUT ARX IN AC ; 3837 =1*1 [PC]_[BR]+1000001, ;NEW PC ; 3838 3T, ;ALLOW TIME ; 3839 HOLD LEFT, ;NO JUNK IN PC LEFT U 0135, 1400,0551,0501,4370,4007,0701,0000,0000,0001 ; 3840 J/DONE ;[127] START AT E+1 ; 3841 ;[127] NICOND MUST CLEAR TRAP CYCLE ; 3842 = ; 3843 ; 3844 1555: U 1555, 2734,3771,0005,0276,6007,0700,0000,0000,0000 ; 3845 JRA: [BR]_AC ;GET AC U 2734, 2735,3770,0505,4344,4007,0700,0000,0000,0000 ; 3846 [BR]_[BR] SWAP ;OLD E IN BR RIGHT ; 3847 VMA_[BR], ;LOAD VMA U 2735, 2736,3443,0500,4174,4007,0700,0200,0004,0012 ; 3848 START READ ;FETCH SAVED AC ; 3849 MEM READ, ;WAIT FOR MEMORY ; 3850 [BR]_MEM, ;LOAD BR WITH SAVE AC U 2736, 0274,3771,0005,4365,5007,0700,0200,0000,0002 ; 3851 J/JMPA ;GO JUMP ; 3852 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 105 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ILLEGAL INSTRUCTIONS AND UUO'S ; 3853 .TOC "ILLEGAL INSTRUCTIONS AND UUO'S" ; 3854 ;LUUO'S TRAP TO CURRENT CONTEXT ; 3855 ; 3856 .DCODE D 0030, 0000,1557,2100 ; 3857 030: I, B/0, J/LUUO D 0031, 0001,1557,2100 ; 3858 I, B/1, J/LUUO D 0032, 0002,1557,2100 ; 3859 I, B/2, J/LUUO D 0033, 0003,1557,2100 ; 3860 I, B/3, J/LUUO D 0034, 0004,1557,2100 ; 3861 I, B/4, J/LUUO D 0035, 0005,1557,2100 ; 3862 I, B/5, J/LUUO D 0036, 0006,1557,2100 ; 3863 I, B/6, J/LUUO D 0037, 0007,1557,2100 ; 3864 I, B/7, J/LUUO ; 3865 ; 3866 ;MONITOR UUO'S -- TRAP TO EXEC ; 3867 D 0040, 0000,1556,2100 ; 3868 040: I, J/MUUO ;CALL D 0041, 0000,1556,2100 ; 3869 I, J/MUUO ;INIT D 0042, 0000,1556,2100 ; 3870 I, J/MUUO D 0043, 0000,1556,2100 ; 3871 I, J/MUUO D 0044, 0000,1556,2100 ; 3872 I, J/MUUO D 0045, 0000,1556,2100 ; 3873 I, J/MUUO D 0046, 0000,1556,2100 ; 3874 I, J/MUUO D 0047, 0000,1556,2100 ; 3875 I, J/MUUO ;CALLI D 0050, 0000,1556,2100 ; 3876 I, J/MUUO ;OPEN D 0051, 0000,1556,2100 ; 3877 I, J/MUUO ;TTCALL D 0052, 0000,1556,2100 ; 3878 I, J/MUUO D 0053, 0000,1556,2100 ; 3879 I, J/MUUO D 0054, 0000,1556,2100 ; 3880 I, J/MUUO D 0055, 0000,1556,2100 ; 3881 I, J/MUUO ;RENAME D 0056, 0000,1556,2100 ; 3882 I, J/MUUO ;IN D 0057, 0000,1556,2100 ; 3883 I, J/MUUO ;OUT D 0060, 0000,1556,2100 ; 3884 I, J/MUUO ;SETSTS D 0061, 0000,1556,2100 ; 3885 I, J/MUUO ;STATO D 0062, 0000,1556,2100 ; 3886 I, J/MUUO ;GETSTS D 0063, 0000,1556,2100 ; 3887 I, J/MUUO ;STATZ D 0064, 0000,1556,2100 ; 3888 I, J/MUUO ;INBUF D 0065, 0000,1556,2100 ; 3889 I, J/MUUO ;OUTBUF D 0066, 0000,1556,2100 ; 3890 I, J/MUUO ;INPUT D 0067, 0000,1556,2100 ; 3891 I, J/MUUO ;OUTPUT D 0070, 0000,1556,2100 ; 3892 I, J/MUUO ;CLOSE D 0071, 0000,1556,2100 ; 3893 I, J/MUUO ;RELEAS D 0072, 0000,1556,2100 ; 3894 I, J/MUUO ;MTAPE D 0073, 0000,1556,2100 ; 3895 I, J/MUUO ;UGETF D 0074, 0000,1556,2100 ; 3896 I, J/MUUO ;USETI D 0075, 0000,1556,2100 ; 3897 I, J/MUUO ;USETO D 0076, 0000,1556,2100 ; 3898 I, J/MUUO ;LOOKUP D 0077, 0000,1556,2100 ; 3899 I, J/MUUO ;ENTER ; 3900 ; 3901 ;EXPANSION OPCODES ; 3902 D 0100, 0000,1556,2100 ; 3903 100: I, J/UUO ;UJEN D 0101, 0000,1661,2100 ; 3904 I, J/UUO101 D 0102, 0000,1662,2100 ; 3905 I, J/UUO102 ;GFAD D 0103, 0000,1663,2100 ; 3906 I, J/UUO103 ;GFSB ; 3907 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 106 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ILLEGAL INSTRUCTIONS AND UUO'S ; 3908 ;RESERVED OPCODES ; 3909 D 0000, 0000,1556,2100 ; 3910 000: I, J/UUO D 0104, 0000,1664,2100 ; 3911 104: I, J/JSYS ;JSYS D 0106, 0000,1666,2100 ; 3912 106: I, J/UUO106 ;GFMP D 0107, 0000,1667,2100 ; 3913 I, J/UUO107 ;GFDV D 0130, 0000,1660,2100 ; 3914 130: I, B/0, J/FP-LONG ;UFA D 0131, 0001,1660,2100 ; 3915 I, B/1, J/FP-LONG ;DFN D 0141, 0002,1660,2100 ; 3916 141: I, B/2, J/FP-LONG ;FADL D 0151, 0003,1660,2100 ; 3917 151: I, B/3, J/FP-LONG ;FSBL D 0161, 0004,1660,2100 ; 3918 161: I, B/4, J/FP-LONG ;FMPL D 0171, 0005,1660,2100 ; 3919 171: I, B/5, J/FP-LONG ;FDVL D 0247, 0000,1665,2100 ; 3920 247: I, J/UUO247 ;RESERVED ; 3921 .UCODE ; 3922 ; 3923 1661: U 1661, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3924 UUO101: UUO ; 3925 1662: U 1662, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3926 UUO102: UUO ; 3927 1663: U 1663, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3928 UUO103: UUO ; 3929 1664: U 1664, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3930 JSYS: UUO ; 3931 1666: U 1666, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3932 UUO106: UUO ; 3933 1667: U 1667, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3934 UUO107: UUO ; 3935 1660: U 1660, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3936 FP-LONG:UUO ; 3937 1665: U 1665, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3938 UUO247: UUO ; 3939 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 107 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ILLEGAL INSTRUCTIONS AND UUO'S ; 3940 ;HERE FOR UUO'S WHICH TRAP TO EXEC ; 3941 1556: ; 3942 UUO: ;THIS TAG IS USED FOR ILLEGAL THINGS WHICH DO UUO TRAPS ; 3943 MUUO: ;THIS TAG IS USED FOR MONITOR CALL INSTRUCTIONS ; 3944 [HR]_[HR].AND.#, ;MASK OUT @ AND XR ; 3945 #/777740, ;MASK U 1556, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 3946 HOLD RIGHT ;KEEP RIGHT ; 3947 ;THE UUO MACRO DOES THE ABOVE INSTRUCTION AND GOES TO UUOGO U 2737, 1156,4751,1204,4374,4007,0700,0000,0000,0424 ; 3948 UUOGO: [ARX]_0 XWD [424] ;HERE FROM UUO MACRO ; 3949 ;GET OFFSET TO UPT ; 3950 =0 [ARX]_[ARX]+[UBR], ;ADDRESS OF MUUO WORD U 1156, 1510,0111,1104,4174,4007,0700,0010,0000,0000 ; 3951 CALL [ABORT] ;STOP MEMORY ; 3952 .IF/KIPAGE ; 3953 .IF/KLPAGE ; 3954 READ [EBR], ;IF BOTH POSSIBLE, SEE WHICH IS ENABLED U 1157, 1160,3333,0010,4174,4007,0520,0000,0000,0000 ; 3955 SKIP DP0 ;KL PAGING ?? ; 3956 =0 ; 3957 .ENDIF/KLPAGE ; 3958 READ [ARX], ;GET THE ADDRESS ; 3959 LOAD VMA, ;START WRITE ; 3960 VMA PHYSICAL WRITE, ;ABSOLUTE ADDRESS U 1160, 0310,3333,0004,4174,4007,0700,0200,0021,1016 ; 3961 J/KIMUUO ;GO STORE KI STYLE ; 3962 .ENDIF/KIPAGE ; 3963 .IF/KLPAGE U 1161, 1162,3770,0203,4344,4007,0700,0000,0000,0000 ; 3964 [AR]_[HR] SWAP ;PUT IN RIGHT HALF ; 3965 =0 [AR]_FLAGS, ;FLAGS IN LEFT HALF ; 3966 HOLD RIGHT, ;JUST WANT FLAGS U 1162, 2745,4521,1203,4074,0007,0700,0010,0000,0000 ; 3967 CALL [UUOFLG] ;CLEAR TRAP FLAGS ; 3968 READ [ARX], ;LOOK AT ADDRESS ; 3969 LOAD VMA, ;LOAD THE VMA U 1163, 0314,3333,0004,4174,4007,0700,0200,0021,1016 ; 3970 VMA PHYSICAL WRITE ;STORE FLAG WORD ; 3971 =0* MEM WRITE, ;WAIT FOR MEMORY U 0314, 2746,3333,0003,4175,5007,0701,0210,0000,0002 ; 3972 MEM_[AR], CALL [NEXT] ;STORE ; 3973 MEM WRITE, ;WAIT FOR MEMORY U 0316, 0020,3333,0001,4175,5007,0701,0200,0000,0002 ; 3974 MEM_[PC] ;STORE FULL WORD PC ; 3975 =000 [HR]_0, ;SAVE E U 0020, 2746,4221,0002,4174,0007,0700,0010,0000,0000 ; 3976 HOLD RIGHT, CALL [NEXT] ;BUT CLEAR OPCODE ; 3977 .ENDIF/KLPAGE ; 3978 =010 ; 3979 UUOPCW: MEM WRITE, ;WAIT FOR MEMORY ; 3980 MEM_[HR], ;STORE INSTRUCTION IN KI ; 3981 ; OR FULL WORD E IN KL U 0022, 3541,3333,0002,4175,5007,0701,0210,0000,0002 ; 3982 CALL [GETPCW] ;GET PROCESS-CONTEXT-WORD ; 3983 ; 3984 =011 NEXT [ARX] PHYSICAL WRITE, ;POINT TO NEXT WORD U 0023, 3667,0111,0704,4170,4007,0700,0210,0023,1016 ; 3985 CALL [STOBR] ;STORE PROCESS CONTEXT WORD ; 3986 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 108 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ILLEGAL INSTRUCTIONS AND UUO'S ; 3987 ;NOW WE MUST PICK ONE OF 8 NEW PC WORDS BASED ON PC FLAGS U 0027, 2740,4751,1205,4374,4007,0700,0000,0000,0430 ; 3988 =111 [BR]_0 XWD [430] ;OFFSET INTO UPT ; 3989 = U 2740, 2741,0111,1105,4174,4007,0700,0000,0000,0000 ; 3990 [BR]_[BR]+[UBR] ;ADDRESS OF WORD U 2741, 2742,4521,1203,4074,4007,0700,0000,0000,0000 ; 3991 [AR]_FLAGS ;GET FLAGS ; 3992 TL [AR], ;LOOK AT FLAGS U 2742, 1164,4553,0300,4374,4007,0321,0000,0000,0600 ; 3993 #/600 ;TRAP SET? ; 3994 =0 [BR]_[BR].OR.#, ;YES--POINT TO TRAP CASE ; 3995 #/1, ; .. U 1164, 1165,3551,0505,4370,4007,0700,0000,0000,0001 ; 3996 HOLD LEFT ;LEAVE LEFT ALONE ; 3997 TL [AR], ;USER OR EXEC U 1165, 1166,4553,0300,4374,4007,0321,0000,0001,0000 ; 3998 #/10000 ; .. ; 3999 =0 [BR]_[BR].OR.#, ;USER ; 4000 #/4, ;POINT TO USER WORDS U 1166, 1167,3551,0505,4370,4007,0700,0000,0000,0004 ; 4001 HOLD LEFT ; 4002 READ [BR], ;LOOK AT ADDRESS ; 4003 LOAD VMA, ;PLACE IN VMA ; 4004 VMA PHYSICAL, ;PHYSICAL ADDRESS U 1167, 2743,3333,0005,4174,4007,0700,0200,0024,1016 ; 4005 START READ ;GET NEW PC WORD ; 4006 GOEXEC: MEM READ, ;WAIT FOR DATA U 2743, 2744,3771,0003,4365,5007,0700,0200,0000,0002 ; 4007 [AR]_MEM ;STICK IN AR ; 4008 READ [AR], ;LOOK AT DATA ; 4009 LOAD FLAGS, ;LOAD NEW FLAGS ; 4010 LEAVE USER, ;ALLOW USER TO LOAD ; 4011 LOAD PCU, ;SET PCU FROM USER U 2744, 0764,3333,0003,4174,4467,0700,0000,0000,0404 ; 4012 J/JUMPA ;JUMP ; 4013 ; 4014 .IF/KIPAGE ; 4015 ;HERE FOR TOPS-10 STYLE PAGING ; 4016 ; 4017 =00 ; 4018 KIMUUO: MEM WRITE, ;STORE INSTRUCTION U 0310, 2746,3333,0002,4175,5007,0701,0210,0000,0002 ; 4019 MEM_[HR], CALL [NEXT] ;IN MEMORY ; 4020 =10 [AR]_PC WITH FLAGS, ;GET PC WORD U 0312, 2745,3741,0103,4074,4007,0700,0010,0000,0000 ; 4021 CALL [UUOFLG] ;CLEAR TRAP FLAGS ; 4022 =11 MEM WRITE, ;STORE PC WORD ; 4023 MEM_[AR], ; .. U 0313, 0022,3333,0003,4175,5007,0701,0200,0000,0002 ; 4024 J/UUOPCW ;GO STORE PROCESS CONTEXT ; 4025 .ENDIF/KIPAGE ; 4026 ; 4027 UUOFLG: [AR]_[AR].AND.NOT.#, ;CLEAR TRAP FLAGS ; 4028 #/600, HOLD RIGHT, ; IN WORD TO SAVE U 2745, 0001,5551,0303,4374,0004,1700,0000,0000,0600 ; 4029 RETURN [1] ; BACK TO CALLER ; 4030 ; 4031 NEXT: NEXT [ARX] PHYSICAL WRITE, ;POINT TO NEXT WORD U 2746, 0002,0111,0704,4170,4004,1700,0200,0023,1016 ; 4032 RETURN [2] ; 4033 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 109 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ILLEGAL INSTRUCTIONS AND UUO'S ; 4034 ;HERE FOR LUUO'S ; 4035 1557: U 1557, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 4036 LUUO: [AR]_0 XWD [40] ;AR GET CONSTANT 40 ; 4037 ;THE LUUO MACRO DOES THE ABOVE INSTRUCTION AND GOES TO LUUO1 ; 4038 400: ;FOR SIMULATOR ; 4039 LUUO1: READ [AR], ;LOAD 40 INTO ; 4040 LOAD VMA, ; THE VMA AND U 0400, 2747,3333,0003,4174,4007,0700,0200,0003,0012 ; 4041 START WRITE ; PREPARE TO STORE ; 4042 [HR]_[HR].AND.#, ;CLEAR OUT INDEX AND @ ; 4043 #/777740, ; .. U 2747, 2750,4551,0202,4374,0007,0700,0000,0077,7740 ; 4044 HOLD RIGHT ; 4045 MEM WRITE, ;STORE LUUO IN 40 U 2750, 2751,3333,0002,4175,5007,0701,0200,0000,0002 ; 4046 MEM_[HR] ; 4047 VMA_[AR]+1, ;POINT TO 41 ; 4048 LOAD VMA, ;PUT 41 IN VMA ; 4049 START READ, ;START FETCH U 2751, 2501,0111,0703,4170,4007,0700,0200,0004,0012 ; 4050 J/CONT1 ;GO EXECUTE THE INSTRUCTION ; 4051 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 110 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- ADD, SUB ; 4052 .TOC "ARITHMETIC -- ADD, SUB" ; 4053 ; 4054 .DCODE D 0270, 1015,1560,1100 ; 4055 270: R-PF, AC, J/ADD D 0271, 0015,1560,3000 ; 4056 I-PF, AC, J/ADD D 0272, 0016,1560,1700 ; 4057 RW, M, J/ADD D 0273, 0017,1560,1700 ; 4058 RW, B, J/ADD ; 4059 .UCODE ; 4060 ; 4061 1560: ; 4062 ADD: [AR]_[AR]+AC, ;DO THE ADD U 1560, 1500,0551,0303,0274,4463,7701,0200,0001,0001 ; 4063 AD FLAGS EXIT, 3T ;UPDATE CARRY FLAGS ; 4064 ;STORE ANSWER ; 4065 ;MISSES 3-TICKS BY 3 NS. ; 4066 ; 4067 ; 4068 .DCODE D 0274, 1015,1561,1100 ; 4069 274: R-PF, AC, J/SUB D 0275, 0015,1561,3000 ; 4070 I-PF, AC, J/SUB D 0276, 0016,1561,1700 ; 4071 RW, M, J/SUB D 0277, 0017,1561,1700 ; 4072 RW, B, J/SUB ; 4073 .UCODE ; 4074 ; 4075 1561: ; 4076 SUB: [AR]_AC-[AR], ;DO THE SUBTRACT U 1561, 1500,2551,0303,0274,4463,7701,4200,0001,0001 ; 4077 AD FLAGS EXIT, 3T ;UPDATE PC CARRY FLAGS ; 4078 ;ALL DONE ; 4079 ;MISSES 3-TICKS BY 3 NS. ; 4080 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 111 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DADD, DSUB ; 4081 .TOC "ARITHMETIC -- DADD, DSUB" ; 4082 ; 4083 .DCODE D 0114, 0205,1457,1100 ; 4084 114: DBL R, DAC, J/DADD D 0115, 0205,1615,1100 ; 4085 DBL R, DAC, J/DSUB ; 4086 .UCODE ; 4087 ; 4088 1457: ; 4089 DADD: [ARX]_[ARX]+AC[1], 4T, ;ADD LOW WORDS U 1457, 1170,0551,0404,1274,4007,0562,0000,0000,1441 ; 4090 SKIP CRY1 ;SEE IF CARRY TO HIGH WORD ; 4091 =0 ; 4092 DADD1: [AR]_[AR]+AC, ;ADD HIGH WORDS ; 4093 ADD .25, ;ADD IN ANY CARRY FROM LOW WORD ; 4094 AD FLAGS, 4T, ;UPDATE PC FLAGS U 1170, 2753,0551,0303,0274,4467,0702,4000,0001,0001 ; 4095 J/CPYSGN ;COPY SIGN TO LOW WORD U 1171, 2752,7441,1205,4174,4007,0700,0000,0000,0000 ; 4096 [BR]_.NOT.[MASK] ;SET BITS 35 AND 36 IN ; 4097 [AR]_[AR].OR.[BR], ; AR SO THAT ADD .25 WILL U 2752, 1170,3111,0503,4170,4007,0700,0000,0000,0000 ; 4098 HOLD LEFT, J/DADD1 ; ADD 1. ; 4099 ; 4100 1615: ; 4101 DSUB: [ARX]_AC[1]-[ARX], 4T, ;SUBTRACT LOW WORD U 1615, 1172,2551,0404,1274,4007,0562,4000,0000,1441 ; 4102 SKIP CRY1 ;SEE IF CARRY ; 4103 =0 [AR]_AC-[AR]-.25, ;NO CARRY ; 4104 AD FLAGS, 4T, ;UPDATE PC FLAGS U 1172, 2753,2551,0303,0274,4467,0702,0000,0001,0001 ; 4105 J/CPYSGN ;GO COPY SIGN ; 4106 [AR]_AC-[AR], 4T, ;THERE WAS A CARRY U 1173, 2753,2551,0303,0274,4467,0702,4000,0001,0001 ; 4107 AD FLAGS ;UPDATE CARRY FLAGS ; 4108 U 2753, 1174,3770,0303,4174,0007,0520,0000,0000,0000 ; 4109 CPYSGN: FIX [AR] SIGN, SKIP DP0 U 1174, 1404,4551,0404,4374,0007,0700,0000,0037,7777 ; 4110 =0 [ARX]_[ARX].AND.#, #/377777, HOLD RIGHT, J/MOVE U 1175, 1404,3551,0404,4374,0007,0700,0000,0040,0000 ; 4111 [ARX]_[ARX].OR.#, #/400000, HOLD RIGHT, J/MOVE ; 4112 ; 4113 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 112 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- MUL, IMUL ; 4114 .TOC "ARITHMETIC -- MUL, IMUL" ; 4115 ; 4116 .DCODE D 0220, 1015,1641,1100 ; 4117 220: R-PF, AC, J/IMUL D 0221, 0015,1641,3000 ; 4118 I-PF, AC, J/IMUL D 0222, 0016,1641,1700 ; 4119 RW, M, J/IMUL D 0223, 0017,1641,1700 ; 4120 RW, B, J/IMUL ; 4121 .UCODE ; 4122 1641: U 1641, 2754,3441,0306,0174,4007,0700,0000,0000,0000 ; 4123 IMUL: [BRX]_[AR], AC ;COPY C(E) U 2754, 0021,3772,0000,0275,5007,0700,2000,0071,0043 ; 4124 Q_AC, SC_35. ;GET THE AC ; 4125 =0** [BRX]_[BRX]*.5 LONG, ;SHIFT RIGHT U 0021, 3000,3446,0606,4174,4007,0700,0010,0000,0000 ; 4126 CALL [MULSUB] ;MULTIPLY U 0025, 1176,3333,0004,4174,4007,0621,0000,0000,0000 ; 4127 READ [ARX], SKIP AD.EQ.0 ;SEE IF FITS U 1176, 2755,3445,0404,4174,4007,0700,0000,0000,0000 ; 4128 =0 [ARX]_[ARX]*2, J/IMUL2 ;NOT ZERO--SHIFT LEFT U 1177, 1500,3221,0003,4174,4003,7700,0200,0003,0001 ; 4129 IMUL1: [AR]_Q, EXIT ;POSITIVE ; 4130 ; 4131 IMUL2: [MASK].AND.NOT.[ARX], ;SEE IF ALL SIGN BITS U 2755, 1200,5113,0412,4174,4007,0621,0000,0000,0000 ; 4132 SKIP AD.EQ.0 ; .. ; 4133 =0 FIX [ARX] SIGN, ;NOT ALL SIGN BITS U 1200, 1202,3770,0404,4174,0007,0520,0000,0000,0000 ; 4134 SKIP DP0, J/IMUL3 ;GIVE + OR - OVERFLOW U 1201, 1500,7001,0003,4174,4003,7700,0200,0003,0001 ; 4135 [AR]_[MAG].EQV.Q, EXIT ;NEGATIVE ; 4136 =0 U 1202, 1404,3221,0003,4174,4467,0700,0000,0041,1000 ; 4137 IMUL3: [AR]_Q, SET AROV, J/MOVE U 1203, 1404,7001,0003,4174,4467,0700,0000,0041,1000 ; 4138 [AR]_[MAG].EQV.Q, SET AROV, J/MOVE ; 4139 ; 4140 ; 4141 .DCODE D 0224, 1005,1571,1100 ; 4142 224: R-PF, DAC, J/MUL D 0225, 0005,1571,3000 ; 4143 I-PF, DAC, J/MUL D 0226, 0016,1571,1700 ; 4144 RW, M, J/MUL D 0227, 0006,1571,1700 ; 4145 RW, DBL B, J/MUL ; 4146 .UCODE ; 4147 ; 4148 ; 4149 1571: U 1571, 2756,3442,0300,0174,4007,0700,0000,0000,0000 ; 4150 MUL: Q_[AR], AC ;COPY C(E) U 2756, 2757,3441,0316,4174,4007,0700,0000,0000,0000 ; 4151 [T0]_[AR] ;SAVE FOR OVERFLOW TEST U 2757, 0031,3771,0006,0276,6007,0700,2000,0071,0043 ; 4152 [BRX]_AC, SC_35. ;GET THE AC ; 4153 =0** [BRX]_[BRX]*.5 LONG, ;SHIFT OVER U 0031, 3000,3446,0606,4174,4007,0700,0010,0000,0000 ; 4154 CALL [MULSUB] ;MULTIPLY U 0035, 2760,3445,0403,4174,4007,0700,0000,0000,0000 ; 4155 [AR]_[ARX]*2 ;SHIFT OVER U 2760, 1204,3770,0303,4174,0007,0520,0000,0000,0000 ; 4156 FIX [AR] SIGN, SKIP DP0 ;SEE IF NEGATIVE ; 4157 =0 [ARX]_[MAG].AND.Q, ;POSITIVE U 1204, 1500,4001,0004,4174,4003,7700,0200,0003,0001 ; 4158 EXIT U 1205, 1206,4113,0616,4174,4007,0520,0000,0000,0000 ; 4159 [T0].AND.[BRX], SKIP DP0 ;TRIED TO SQUARE 1B0? U 1206, 1500,7001,0004,4174,4003,7700,0200,0003,0001 ; 4160 =0 [ARX]_[MAG].EQV.Q, EXIT ;NO ; 4161 [ARX]_[MAG].EQV.Q, ;YES U 1207, 1404,7001,0004,4174,4467,0700,0000,0041,1000 ; 4162 SET AROV, J/MOVE ; 4163 ; 4164 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 113 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DMUL ; 4165 .TOC "ARITHMETIC -- DMUL" ; 4166 ; 4167 .DCODE D 0116, 0205,1566,1100 ; 4168 116: DBL R, DAC, J/DMUL ; 4169 .UCODE ; 4170 ; 4171 .IF/FULL ; 4172 1566: U 1566, 2761,3447,0303,4174,4007,0700,0000,0000,0000 ; 4173 DMUL: [AR]_[AR]*.5 ;SHIFT MEM OPERAND RIGHT U 2761, 2762,4117,0004,4174,4007,0700,0000,0000,0000 ; 4174 [ARX]_([ARX].AND.[MAG])*.5 ; 4175 [BR]_[ARX], ;COPY LOW WORD U 2762, 0120,3441,0405,4174,4007,0350,0000,0000,0000 ; 4176 SKIP FPD ;SEE IF FIRST PART DONE ; 4177 ; ; 4178 ; BRX * BR ==> C(E+1) * C(AC+1) ; 4179 ; ; 4180 =000 [BRX]_(AC[1].AND.[MAG])*.5, 3T, ;GET LOW AC U 0120, 2774,4557,0006,1274,4007,0701,0010,0000,1441 ; 4181 CALL [DMULGO] ;START MULTIPLY ; 4182 [ARX]_(AC[2].AND.[MAG])*.5, 3T, ;FIRST PART DONE U 0121, 2764,4557,0004,1274,4007,0701,0000,0000,1442 ; 4183 J/DMUL1 ;GO DO SECOND PART U 0124, 0171,3223,0000,1174,4007,0700,0400,0000,1443 ; 4184 =100 AC[3]_Q ;SALT AWAY 1 WORD OF PRODUCT ; 4185 = ; 4186 ; ; 4187 ; BRX * Q ==> C(E) * C(AC+1) ; 4188 ; ; 4189 =0** Q_[AR], SC_35., ;GO MULT NEXT HUNK U 0171, 0563,3442,0300,4174,4007,0700,2010,0071,0043 ; 4190 CALL [QMULT] ; .. U 0175, 2763,3441,0416,4174,4007,0700,0000,0000,0000 ; 4191 [T0]_[ARX] ;SAVE PRODUCT ; 4192 AC[2]_Q, [ARX]_Q*.5, ;SAVE PRODUCT U 2763, 0410,3227,0004,1174,4007,0700,0400,0000,1442 ; 4193 J/DMUL2 ;GO DO HIGH HALF U 2764, 0410,3777,0016,1276,6007,0701,0000,0000,1441 ; 4194 DMUL1: [T0]_AC[1]*.5 ;RESTORE T0 ; 4195 =0*0 ; 4196 ; ; 4197 ; BRX * BR ==> C(AC) * C(E+1) ; 4198 ; ; 4199 DMUL2: [BRX]_AC*.5, ;PREPARE TO DO HIGH HALF U 0410, 2775,3777,0006,0274,4007,0701,0010,0000,0000 ; 4200 CALL [DBLMUL] ; GO DO IT ; 4201 AC[1]_[T0]*2, 3T, ;INTERRUPT, SAVE T0 U 0411, 2777,0113,1616,1174,4007,0701,0400,0000,1441 ; 4202 J/DMLINT ;SET FPD AND INTERRUPT U 0414, 2765,3223,0000,1174,4007,0700,0400,0000,1442 ; 4203 AC[2]_Q ;SAVE PRODUCT ; 4204 = U 2765, 0543,0111,1604,4174,4007,0700,0000,0000,0000 ; 4205 [ARX]_[ARX]+[T0] ;PREPARE FOR LAST MUL ; 4206 ; ; 4207 ; BRX * Q ==> C(AC) * C(E) ; 4208 ; ; 4209 =0** Q_[AR], SC_35., ;DO THE LAST MULTIPLY U 0543, 0563,3442,0300,4174,4007,0700,2010,0071,0043 ; 4210 CALL [QMULT] ; GO DO IT ; 4211 [ARX]_[ARX]*2, ;SHIFT BACK U 0547, 2766,3445,0404,4174,4467,0700,0000,0005,0000 ; 4212 CLR FPD ;CLEAR FPD ; 4213 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 114 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DMUL U 2766, 1210,3770,0404,0174,4007,0520,0400,0000,0000 ; 4214 AC_[ARX] TEST, SKIP DP0 ;PUT BACK INTO AC U 1210, 2773,3223,0000,1174,4007,0700,0400,0000,1441 ; 4215 =0 AC[1]_Q, J/DMTRAP ;POSITIVE U 1211, 2767,7003,0000,1174,4007,0700,0400,0000,1441 ; 4216 AC[1]_[MAG].EQV.Q ;NEGATIVE U 2767, 2770,3772,0000,1275,5007,0701,0000,0000,1442 ; 4217 Q_AC[2] U 2770, 2771,7003,0000,1174,4007,0700,0400,0000,1442 ; 4218 AC[2]_[MAG].EQV.Q U 2771, 2772,3772,0000,1275,5007,0701,0000,0000,1443 ; 4219 Q_AC[3] U 2772, 2773,7003,0000,1174,4007,0700,0400,0000,1443 ; 4220 AC[3]_[MAG].EQV.Q ; 4221 DMTRAP: [AR]_PC WITH FLAGS, ;LOOK AT FLAGS U 2773, 1212,3741,0103,4074,4007,0520,0000,0000,0000 ; 4222 SKIP DP0 ;SEE IF AROV SET? U 1212, 0110,3443,0100,4174,4156,4700,0200,0014,0012 ; 4223 =0 DONE ;NO--ALL DONE U 1213, 1400,4443,0000,4174,4467,0700,0000,0041,1000 ; 4224 SET AROV, J/DONE ;YES--FORCE TRAP 1 ALSO ; 4225 ; 4226 ; 4227 ;WAYS TO CALL MULTIPLY U 2774, 2775,4221,0004,4174,4007,0700,0000,0000,0000 ; 4228 DMULGO: [ARX]_0 ;CLEAR ARX U 2775, 2776,3442,0500,4174,4007,0700,2000,0071,0043 ; 4229 DBLMUL: Q_[BR], SC_35. U 2776, 0563,3447,0606,4174,4007,0700,0000,0000,0000 ; 4230 [BRX]_[BRX]*.5 ; 4231 =0** ; 4232 QMULT: Q_Q*.5, U 0563, 3002,3446,1200,4174,4007,0700,0010,0000,0000 ; 4233 CALL [MULTIPLY] ; 4234 [ARX]+[ARX], AD FLAGS, ;TEST FOR OVERFLOW U 0567, 0004,0113,0404,4174,4464,1701,0000,0001,0001 ; 4235 3T, RETURN [4] ;AND RETURN ; 4236 U 2777, 2677,4443,0000,4174,4467,0700,0000,0003,0000 ; 4237 DMLINT: SET FPD, J/FIXPC ;SET FPD, BACKUP PC ; 4238 ; INTERRUPT ;;4239 .IFNOT/FULL ;;4240 1566: ;;4241 DMUL: UUO ; 4242 .ENDIF/FULL ; 4243 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 115 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DMUL ; 4244 ;MULTIPLY SUBROUTINE ; 4245 ;ENTERED WITH: ; 4246 ; MULTIPLIER IN Q ; 4247 ; MULTIPLICAND IN BRX ; 4248 ;RETURNS 4 WITH PRODUCT IN ARX!Q ; 4249 ; 4250 MUL STEP "A/BRX,B/ARX,DEST/Q_Q*.5,ASHC,STEP SC,MUL DISP" ; 4251 MUL FINAL "A/BRX,B/ARX,DEST/Q_Q*2" ; 4252 U 3000, 3001,3446,0606,4174,4007,0700,0000,0000,0000 ; 4253 MULSUB: [BRX]_[BRX]*.5 LONG ; 4254 MULSB1: [ARX]_0*.5 LONG, ;CLEAR ARX AND SHIFT Q ; 4255 STEP SC, ;COUNT FIRST STEP U 3001, 0122,4226,0004,4174,4007,0630,2000,0060,0000 ; 4256 J/MUL+ ;ENTER LOOP ; 4257 ; 4258 ;MULTIPLY SUBROUTINE ; 4259 ;ENTERED WITH: ; 4260 ; MULTIPLIER IN Q ; 4261 ; MULTIPLICAND IN BRX ; 4262 ; PARTIAL PRODUCT IN ARX ; 4263 ;RETURNS 4 WITH Q*BRX+ARX IN ARX!Q ; 4264 ; 4265 MULTIPLY: ; 4266 Q_Q*.5, ;SHIFT Q ; 4267 STEP SC, ;COUNT FIRST STEP U 3002, 0122,3446,1200,4174,4007,0630,2000,0060,0000 ; 4268 J/MUL+ ;ENTER LOOP ; 4269 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 116 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DMUL ; 4270 ;HERE FOR POSITIVE STEPS ; 4271 =010 ;0 IN A POSITIVE STEP ; 4272 MUL+: AD/B, ;DON'T ADD ; 4273 MUL STEP, ;SHIFT U 0122, 0122,3336,0604,4174,4046,2630,2000,0060,0000 ; 4274 J/MUL+ ;KEEP POSITIVE ; 4275 =011 ;DONE ; 4276 AD/B, ;DON'T ADD ; 4277 MUL FINAL, ;SHIFT U 0123, 0004,3334,0604,4174,4004,1700,0000,0000,0000 ; 4278 RETURN [4] ;SHIFT Q AND RETURN ; 4279 =110 ;1 IN A POSITIVE STEP ; 4280 AD/B-A-.25, ADD .25, ;SUBTRACT ; 4281 MUL STEP, ;SHIFT AND COUNT U 0126, 0142,1116,0604,4174,4046,2630,6000,0060,0000 ; 4282 J/MUL- ;NEGATIVE NOW ; 4283 =111 ;DONE ; 4284 AD/B-A-.25, ADD .25, ;SUBTRACT ; 4285 MUL FINAL, ;SHIFT U 0127, 0004,1114,0604,4174,4004,1700,4000,0000,0000 ; 4286 RETURN [4] ; AND RETURN ; 4287 ; 4288 ;HERE FOR NEGATIVE STEPS ; 4289 =010 ;0 IN NEGATIVE STEP ; 4290 MUL-: AD/A+B, ;ADD ; 4291 MUL STEP, ;SHIFT AND COUNT U 0142, 0122,0116,0604,4174,4046,2630,2000,0060,0000 ; 4292 J/MUL+ ;POSITIVE NOW ; 4293 =011 ;DONE ; 4294 AD/A+B, ;ADD ; 4295 MUL FINAL, ;SHIFT U 0143, 0004,0114,0604,4174,4004,1700,0000,0000,0000 ; 4296 RETURN [4] ;FIX Q AND RETURN ; 4297 =110 ;1 IN NEGATIVE STEP ; 4298 AD/B, ;DON'T ADD ; 4299 MUL STEP, ;SHIFT AND COUNT U 0146, 0142,3336,0604,4174,4046,2630,2000,0060,0000 ; 4300 J/MUL- ;STILL NEGATIVE ; 4301 =111 ;DONE ; 4302 AD/B, ;DON'T ADD ; 4303 MUL FINAL, ;SHIFT U 0147, 0004,3334,0604,4174,4004,1700,0000,0000,0000 ; 4304 RETURN [4] ;FIX Q AND RETURN ; 4305 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 117 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DIV, IDIV ; 4306 .TOC "ARITHMETIC -- DIV, IDIV" ; 4307 ; 4308 .DCODE D 0230, 1005,1600,1100 ; 4309 230: R-PF, DAC, J/IDIV D 0231, 0005,1600,3000 ; 4310 I-PF, DAC, J/IDIV D 0232, 0016,1600,1700 ; 4311 RW, M, J/IDIV D 0233, 0006,1600,1700 ; 4312 RW, DBL B, J/IDIV ; 4313 D 0234, 1005,1601,1100 ; 4314 234: R-PF, DAC, J/DIV D 0235, 0005,1601,3000 ; 4315 I-PF, DAC, J/DIV D 0236, 0016,1601,1700 ; 4316 RW, M, J/DIV D 0237, 0006,1601,1700 ; 4317 RW, DBL B, J/DIV ; 4318 .UCODE ; 4319 ; 4320 1600: U 1600, 3003,3441,0305,0174,4007,0700,0000,0000,0000 ; 4321 IDIV: [BR]_[AR], AC ;COPY MEMORY OPERAND ; 4322 Q_AC, ;LOAD Q U 3003, 1214,3772,0000,0275,5007,0520,0000,0000,0000 ; 4323 SKIP DP0 ;SEE IF MINUS ; 4324 =0 [AR]_0, ;EXTEND + SIGN U 1214, 0161,4221,0003,4174,4007,0700,0000,0000,0000 ; 4325 J/DIV1 ;NOW SAME AS DIV ; 4326 [AR]_-1, ;EXTEND - SIGN U 1215, 0161,2441,0703,4174,4007,0700,4000,0000,0000 ; 4327 J/DIV1 ;SAME AS DIV ; 4328 ; 4329 1601: U 1601, 3004,3441,0305,4174,4007,0700,0000,0000,0000 ; 4330 DIV: [BR]_[AR] ;COPY MEM OPERAND U 3004, 3005,3771,0003,0276,6007,0700,0000,0000,0000 ; 4331 [AR]_AC ;GET AC U 3005, 3006,3772,0000,1275,5007,0701,0000,0000,1441 ; 4332 Q_AC[1] ;AND AC+1 ; 4333 READ [AR], ;TEST FOR NO DIVIDE U 3006, 0160,3333,0003,4174,4007,0621,0000,0000,0000 ; 4334 SKIP AD.EQ.0 ; 4335 =000 .NOT.[AR], ;SEE IF ALL SIGN BITS IN AR ; 4336 SKIP AD.EQ.0, ; .. U 0160, 1216,7443,0300,4174,4007,0621,0000,0000,0000 ; 4337 J/DIVA ;CONTINUE BELOW ; 4338 =001 ; 4339 DIV1: READ [BR], ;SEE IF DIVIDE BY U 0161, 0164,3333,0005,4174,4007,0621,0000,0000,0000 ; 4340 SKIP AD.EQ.0 ; ZERO ; 4341 =100 ; 4342 DIV2: SC_34., ;NOT ZERO--LOAD STEP COUNT U 0164, 0370,4443,0000,4174,4007,0700,2010,0071,0042 ; 4343 CALL [DIVSUB] ;DIVIDE U 0165, 0555,4443,0000,4174,4467,0700,0000,0051,1000 ; 4344 =101 NO DIVIDE ;DIVIDE BY ZERO ; 4345 =110 [ARX]_[AR], ;COPY REMAINDER U 0166, 1177,3441,0304,4174,4007,0700,0000,0000,0000 ; 4346 J/IMUL1 ;STORE ANSWER ; 4347 = ; 4348 ; 4349 ; 4350 =0 ; 4351 DIVA: [BRX]_[AR], ;HIGH WORD IS NOT SIGNS U 1216, 3007,3441,0306,4174,4007,0700,0000,0000,0000 ; 4352 J/DIVB ;GO TEST FOR NO DIVIDE ; 4353 READ [BR], ;ALL SIGN BITS ; 4354 SKIP AD.EQ.0, ;SEE IF ZERO DIVIDE U 1217, 0164,3333,0005,4174,4007,0621,0000,0000,0000 ; 4355 J/DIV2 ;BACK TO MAIN FLOW ; 4356 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 118 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DIV, IDIV U 3007, 3010,3221,0004,4174,4007,0700,0000,0000,0000 ; 4357 DIVB: [ARX]_Q ;MAKE ABS VALUES ; 4358 READ [AR], ;SEE IF + U 3010, 0330,3333,0003,4174,4007,0520,0000,0000,0000 ; 4359 SKIP DP0 ; 4360 =00 READ [BR], ;SEE IF + ; 4361 SKIP DP0, U 0330, 1220,3333,0005,4174,4007,0520,0000,0000,0000 ; 4362 J/DIVC ;CONTINUE BELOW ; 4363 CLEAR [ARX]0, ;FLUSH DUPLICATE SIGN U 0331, 3071,4551,0404,4374,0007,0700,0010,0037,7777 ; 4364 CALL [DBLNG1] ;NEGATE AR!ARX ; 4365 =11 READ [BR], ;SEE IF TOO BIG ; 4366 SKIP DP0, U 0333, 1220,3333,0005,4174,4007,0520,0000,0000,0000 ; 4367 J/DIVC ; 4368 = ; 4369 =0 ; 4370 DIVC: [AR]-[BR], ;COMPUTE DIFFERENCE ; 4371 SKIP DP0, ;SEE IF IT GOES ; 4372 3T, ;ALLOW TIME U 1220, 1222,2113,0305,4174,4007,0521,4000,0000,0000 ; 4373 J/NODIV ;TEST ; 4374 [AR]+[BR], ; 4375 SKIP DP0, ;SAME TEST FOR -VE BR ; 4376 3T, U 1221, 1222,0113,0305,4174,4007,0521,0000,0000,0000 ; 4377 J/NODIV ; 4378 =0 U 1222, 0555,4443,0000,4174,4467,0700,0000,0051,1000 ; 4379 NODIV: NO DIVIDE ;TOO BIG ; 4380 [AR]_[BRX], ;FITS U 1223, 0161,3441,0603,4174,4007,0700,0000,0000,0000 ; 4381 J/DIV1 ;GO BACK AND DIVIDE ; 4382 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 119 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DDIV ; 4383 .TOC "ARITHMETIC -- DDIV" ; 4384 ; 4385 .DCODE D 0117, 0205,1627,1100 ; 4386 117: DBL R, DAC, J/DDIV ; 4387 .UCODE ; 4388 ; 4389 .IF/FULL ; 4390 1627: U 1627, 3011,4112,0400,4174,4007,0700,0000,0000,0000 ; 4391 DDIV: Q_[ARX].AND.[MAG] ;COPY LOW WORD ; 4392 [BR]_[AR]*.5, ;COPY MEMORY OPERAND U 3011, 1224,3447,0305,4174,4007,0421,0000,0000,0000 ; 4393 SKIP AD.LE.0 ;SEE IF POSITIVE ; 4394 =0 [BR]_[BR]*.5 LONG, ;POSITIVE U 1224, 1230,3446,0505,4174,4007,0700,0000,0000,0000 ; 4395 J/DDIV1 ;CONTINUE BELOW ; 4396 [BR]_[BR]*.5 LONG, ;NEGATIVE OR ZERO U 1225, 1226,3446,0505,4174,4007,0520,0000,0000,0000 ; 4397 SKIP DP0 ;SEE WHICH? ; 4398 =0 [MAG].AND.Q, ;SEE IF ALL ZERO U 1226, 1230,4003,0000,4174,4007,0621,0000,0000,0000 ; 4399 SKIP AD.EQ.0, J/DDIV1 ;CONTINUE BELOW U 1227, 3012,4751,1217,4374,4007,0700,0000,0000,0005 ; 4400 [T1]_0 XWD [5] ;NEGATE MEM OP ; 4401 Q_Q.OR.#, #/600000, ;SIGN EXTEND THE LOW U 3012, 3013,3662,0000,4374,0007,0700,0000,0060,0000 ; 4402 HOLD RIGHT ; WORD U 3013, 3014,2222,0000,4174,4007,0700,4000,0000,0000 ; 4403 Q_-Q ;MAKE Q POSITIVE ; 4404 [BR]_(-[BR]-.25)*.5 LONG, ;NEGATE HIGH WORD ; 4405 ASHC, MULTI PREC/1, ;USE CARRY FROM LOW WORD U 3014, 3016,2446,0505,4174,4047,0700,0040,0000,0000 ; 4406 J/DDIV3 ;CONTINUE BELOW ; 4407 =0 ; 4408 DDIV1: [BR]_[BR]*.5 LONG, ;SHIFT OVER 1 PLACE U 1230, 3015,3446,0505,4174,4047,0700,0000,0000,0000 ; 4409 ASHC, J/DDIV2 ;CONTINUE BELOW U 1231, 0555,4443,0000,4174,4467,0700,0000,0051,1000 ; 4410 NO DIVIDE ;DIVIDE BY ZERO U 3015, 3016,4751,1217,4374,4007,0700,0000,0000,0004 ; 4411 DDIV2: [T1]_0 XWD [4] ;MEM OPERAND IS POSITIVE U 3016, 3017,3221,0006,0174,4007,0700,0000,0000,0000 ; 4412 DDIV3: [BRX]_Q, AC ;COPY Q ; 4413 U 3017, 0054,3777,0003,0274,4007,0520,0000,0000,0000 ; 4414 [AR]_AC*.5, 2T, SKIP DP0 ;GET AC--SEE IF NEGATIVE ; 4415 =0*1*0 ; 4416 DDIV3A: Q_AC[1].AND.[MAG], ;POSITIVE (OR ZERO) U 0054, 1232,4552,0000,1275,5007,0701,0000,0000,1441 ; 4417 J/DDIV4 ;CONTINUE BELOW ; 4418 [T1]_[T1].XOR.#, ;NEGATIVE U 0055, 3060,6551,1717,4374,4007,0700,0010,0000,0007 ; 4419 #/7, CALL [QDNEG] ;UPDATE SAVED FLAGS ; 4420 =1*1*1 [AR]_[AR]*.5, ;SHIFT AR OVER U 0075, 0054,3447,0303,4174,4007,0700,0000,0000,0000 ; 4421 J/DDIV3A ;GO BACK AND LOAD Q ; 4422 = ; 4423 =0 ; 4424 DDIV4: [AR]_[AR]*.5 LONG, ;SHIFT AR OVER U 1232, 3042,3446,0303,4174,4007,0700,0010,0000,0000 ; 4425 CALL [DDIVS] ;SHIFT 1 MORE PLACE U 1233, 1234,2113,0305,4174,4007,0521,4000,0000,0000 ; 4426 [AR]-[BR], 3T, SKIP DP0 ;TEST MAGNITUDE ; 4427 =0 [AR]-[BR], 2T, U 1234, 1236,2113,0305,4174,4007,0620,4000,0000,0000 ; 4428 SKIP AD.EQ.0, J/DDIV5 U 1235, 3020,3221,0004,4174,4007,0700,0000,0000,0000 ; 4429 [ARX]_Q, J/DDIV5A ;ANSWER FITS ; 4430 ; 4431 =0 U 1236, 0033,3333,0017,4174,4003,5701,0000,0000,0000 ; 4432 DDIV5: READ [T1], 3T, DISP/DP, J/NODDIV U 1237, 1240,1003,0600,4174,4007,0521,4000,0000,0000 ; 4433 Q-[BRX], 3T, SKIP DP0 U 1240, 0033,3333,0017,4174,4003,5701,0000,0000,0000 ; 4434 =0 READ [T1], 3T, DISP/DP, J/NODDIV U 1241, 3020,3221,0004,4174,4007,0700,0000,0000,0000 ; 4435 [ARX]_Q ;COPY LOW WORD ; 4436 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 120 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DDIV ; 4437 ;HERE WITH EVERYTHING SETUP AND READY TO GO U 3020, 0354,4552,0000,1275,5007,0701,0000,0000,1442 ; 4438 DDIV5A: Q_AC[2].AND.[MAG] U 0354, 1264,3446,1200,4174,4007,0700,2010,0071,0042 ; 4439 =0* Q_Q*.5, SC_34., CALL [DBLDIV] U 0356, 3021,3224,0016,4174,4007,0700,0000,0000,0000 ; 4440 [T0]_Q*2 LONG U 3021, 3022,0002,1600,4174,4007,0700,0000,0000,0000 ; 4441 Q_Q+[T0] U 3022, 1242,4003,0000,1174,4007,0700,0400,0000,1440 ; 4442 AC[0]_Q.AND.[MAG] ;STORE ANSWER U 1242, 3042,3442,0400,4174,4007,0700,0010,0000,0000 ; 4443 =0 Q_[ARX], CALL [DDIVS] ;SHIFT OUT EXTRA ZERO BIT U 1243, 3023,3221,0004,4174,4007,0700,0000,0000,0000 ; 4444 [ARX]_Q ; .. U 3023, 0551,4552,0000,1275,5007,0701,0000,0000,1443 ; 4445 Q_AC[3].AND.[MAG] ; 4446 =0* [T0]_[AR]*.5 LONG, ;SHIFT Q, PUT AR ON DP ; 4447 SC_34., ;LOAD SHIFT COUNT ; 4448 SKIP DP0, ;LOOK AT AR SIGN U 0551, 1264,3446,0316,4174,4007,0520,2010,0071,0042 ; 4449 CALL [DBLDIV] ;GO DIVIDE U 0553, 3024,3224,0016,4174,4007,0700,0000,0000,0000 ; 4450 [T0]_Q*2 LONG U 3024, 0056,3333,0017,4174,4003,5701,0000,0000,0000 ; 4451 READ [T1], 3T, DISP/DP ;WHAT SIGN IS QUO ; 4452 =1110 [T0]_[T0]+Q, ;POSITIVE QUO U 0056, 3027,0001,1616,4174,4007,0700,0000,0000,0000 ; 4453 J/DDIV5B ;CONTINUE BELOW U 0057, 3025,2225,0016,4174,4007,0700,4000,0000,0000 ; 4454 [T0]_-Q*2 ;NEGATIVE QUO ; 4455 AD/-D-.25, DBUS/RAM, 3T, ; 4456 RAMADR/AC#, DEST/Q_AD, U 3025, 3026,1772,0000,0274,4007,0701,0040,0000,0000 ; 4457 MULTI PREC/1 U 3026, 1244,3223,0000,0174,4007,0621,0400,0000,0000 ; 4458 AC_Q, SKIP AD.EQ.0 U 1244, 3030,3440,1616,1174,4007,0700,0400,0000,1441 ; 4459 =0 AC[1]_[T0], J/DDIV5C U 1245, 3032,4223,0000,1174,4007,0700,0400,0000,1441 ; 4460 AC[1]_0, J/DDIV6 ; 4461 U 3027, 3032,4113,1600,1174,4007,0700,0400,0000,1441 ; 4462 DDIV5B: AC[1]_[T0].AND.[MAG], J/DDIV6 ;STORE LOW WORD IN + CASE ; 4463 U 3030, 3031,3551,1616,4374,0007,0700,0000,0040,0000 ; 4464 DDIV5C: [T0]_[T0].OR.#, #/400000, HOLD RIGHT U 3031, 3032,3440,1616,1174,4007,0700,0400,0000,1441 ; 4465 AC[1]_[T0] ; 4466 U 3032, 1246,3333,0003,4174,4007,0520,0000,0000,0000 ; 4467 DDIV6: READ [AR], SKIP DP0 ;LOOK AT AR SIGN ; 4468 =0 U 1246, 3036,3442,0400,4174,4007,0700,0000,0000,0000 ; 4469 DDIV7: Q_[ARX], J/DDIV8 U 1247, 3033,0112,0406,4174,4007,0700,0000,0000,0000 ; 4470 Q_[ARX]+[BRX] ; 4471 [AR]_[AR]+[BR], U 3033, 3034,0111,0503,4174,4007,0700,0040,0000,0000 ; 4472 MULTI PREC/1 U 3034, 3035,0002,0600,4174,4007,0700,0000,0000,0000 ; 4473 Q_Q+[BRX] ; 4474 [AR]_[AR]+[BR], U 3035, 3036,0111,0503,4174,4007,0700,0040,0000,0000 ; 4475 MULTI PREC/1 U 3036, 0355,3333,0017,4174,4003,5701,0000,0000,0000 ; 4476 DDIV8: READ [T1], 3T, DISP/DP ; 4477 =1101 ; 4478 DDIV8A: [AR]_[AR]*2 LONG, ASHC, ;POSITIVE REMAINDER U 0355, 3040,3444,0303,4174,4047,0700,0000,0000,0000 ; 4479 J/DDIV9 ;CONTINUE BELOW U 0357, 3037,2222,0000,4174,4007,0700,4000,0000,0000 ; 4480 Q_-Q ;NEGATE REMAINDER IN AR!Q ; 4481 [AR]_(-[AR]-.25)*2 LONG, U 3037, 3040,2444,0303,4174,4047,0700,0040,0000,0000 ; 4482 MULTI PREC/1, ASHC ; 4483 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 121 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DDIV ; 4484 DDIV9: AC[2]_[AR]+[AR], 3T, U 3040, 1250,0113,0303,1174,4007,0521,0400,0000,1442 ; 4485 SKIP DP0 ; 4486 =0 AC[3]_Q.AND.[MAG], U 1250, 0100,4003,0000,1174,4156,4700,0400,0000,1443 ; 4487 NEXT INST U 1251, 3041,4002,0000,1174,4007,0700,0000,0000,1443 ; 4488 Q_Q.AND.[MAG], AC[3] ; 4489 AC[3]_[MAG].EQV.Q, U 3041, 0100,7003,0000,1174,4156,4700,0400,0000,1443 ; 4490 NEXT INST ; 4491 ; 4492 ; 4493 ;HERE IF WE WANT TO SET NO DIVIDE ; 4494 =11011 U 0033, 3060,4443,0000,4174,4007,0700,0010,0000,0000 ; 4495 NODDIV: CALL [QDNEG] ;FIXUP AC TO AC+3 U 0037, 0555,4443,0000,4174,4467,0700,0000,0051,1000 ; 4496 NO DIVIDE ;ABORT DIVIDE ; 4497 U 3042, 0001,3446,0303,4174,4044,1700,0000,0000,0000 ; 4498 DDIVS: [AR]_[AR]*.5 LONG, ASHC, RETURN [1] ;;4499 .IFNOT/FULL ;;4500 1627: ;;4501 DDIV: UUO ; 4502 .ENDIF/FULL ; 4503 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 122 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DIVIDE SUBROUTINE ; 4504 .TOC "ARITHMETIC -- DIVIDE SUBROUTINE" ; 4505 ; 4506 ;HERE IS THE SUBROUTINE TO DO DIVIDE ; 4507 ;ENTER WITH: ; 4508 ; AR!Q = D'END ; 4509 ; BR = D'SOR ; 4510 ;RETURN 2 WITH: ; 4511 ; AR = REMAINDER ; 4512 ; Q = QUOTIENT ; 4513 ;CALLER MUST CHECK FOR ZERO DIVIDE PRIOR TO CALL ; 4514 ; ; 4515 =1000 ; 4516 DIVSUB: Q_Q.AND.#, ;CLEAR SIGN BIT IN ; 4517 #/377777, ;MASK ; 4518 HOLD RIGHT, ;JUST CLEAR BIT 0 U 0370, 3043,4662,0000,4374,0007,0700,0010,0037,7777 ; 4519 CALL [DIVSGN] ;DO REAL DIVIDE U 0374, 0002,4443,0000,4174,4004,1700,0000,0000,0000 ; 4520 =1100 RETURN [2] ;ALL POSITIVE U 0375, 0002,2222,0000,4174,4004,1700,4000,0000,0000 ; 4521 =1101 Q_-Q, RETURN [2] ;-QUO +REM U 0376, 0377,2222,0000,4174,4007,0700,4000,0000,0000 ; 4522 =1110 Q_-Q ;ALL NEGATIVE U 0377, 0002,2441,0303,4174,4004,1700,4000,0000,0000 ; 4523 =1111 [AR]_-[AR], RETURN [2] ;NEGATIVE REMAINDER ; 4524 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 123 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DIVIDE SUBROUTINE ; 4525 ;HERE IS THE INNER DIVIDE SUBROUTINE ; 4526 ;SAME SETUP AS DIVSUB ; 4527 ;RETURNS WITH AR AND Q POSITIVE AND ; 4528 ; 14 IF ALL POSITIVE ; 4529 ; 15 IF -QUO ; 4530 ; 16 IF ALL NEGATIVE ; 4531 ; 17 IF NEGATIVE REMAINDER ; 4532 ; 4533 BASIC DIV STEP "DEST/Q_Q*2, DIV, A/BR, B/AR, STEP SC" ; 4534 DIV STEP "BASIC DIV STEP, AD/A+B, DIVIDE/1" ; 4535 FIRST DIV STEP "BASIC DIV STEP, AD/B-A-.25, ADD .25" ; 4536 U 3043, 1252,3333,0003,4174,4007,0520,0000,0000,0000 ; 4537 DIVSGN: READ [AR], SKIP DP0 U 1252, 3045,4221,0004,4174,4007,0700,0000,0000,0000 ; 4538 =0 [ARX]_0, J/DVSUB2 ;REMAINDER IS POSITIVE U 1253, 1254,2222,0000,4174,4007,0621,4000,0000,0000 ; 4539 Q_-Q, SKIP AD.EQ.0 ;COMPLEMENT LOW WORD U 1254, 3044,7441,0303,4174,4007,0700,0000,0000,0000 ; 4540 =0 [AR]_.NOT.[AR], J/DVSUB1 ;COMPLEMENT HI WORD U 1255, 3044,2441,0303,4174,4007,0700,4000,0000,0000 ; 4541 [AR]_-[AR] ;TWO'S COMPLEMENT HI WORD SINCE ; 4542 ; LOW WORD WAS ZERO U 3044, 3045,3771,0004,4374,4007,0700,0000,0010,0000 ; 4543 DVSUB1: [ARX]_#, #/100000 ;REMAINDER IS NEGATIVE U 3045, 1256,3333,0005,4174,4007,0520,0000,0000,0000 ; 4544 DVSUB2: READ [BR], SKIP DP0 ;IS THE DIVISOR NEGATIVE ; 4545 =0 ; 4546 DVSUB3: [AR]_[AR]*.5 LONG, ;START TO PUT IN 9-CHIPS U 1256, 3047,3446,0303,4174,4007,0700,0000,0000,0000 ; 4547 J/DIVSET ;JOIN MAIN STREAM U 1257, 3046,2441,0505,4174,4007,0700,4000,0000,0000 ; 4548 [BR]_-[BR] ;COMPLEMENT DIVISOR ; 4549 [ARX]_[ARX].OR.#, ;ADJUST SIGN OF QUOTIENT U 3046, 1256,3551,0404,4374,4007,0700,0000,0004,0000 ; 4550 #/40000, J/DVSUB3 ;USE 9 CHIPS U 3047, 3050,3447,0303,4174,4007,0700,0000,0000,0000 ; 4551 DIVSET: [AR]_[AR]*.5 U 3050, 3051,3447,0505,4174,4007,0700,0000,0000,0000 ; 4552 [BR]_[BR]*.5 U 3051, 3052,3447,0505,4174,4007,0700,0000,0000,0000 ; 4553 [BR]_[BR]*.5 U 3052, 1260,1114,0503,4174,4067,0630,6000,0060,0000 ; 4554 FIRST DIV STEP ; 4555 ;HERE IS THE MAIN DIVIDE LOOP ; 4556 =0 U 1260, 1260,0114,0503,4174,4067,0630,2100,0060,0000 ; 4557 DIVIDE: DIV STEP, J/DIVIDE U 1261, 3053,3444,1717,4174,4067,0700,0100,0000,0000 ; 4558 [T1]_[T1]*2 LONG, DIVIDE/1, DIV U 3053, 1262,3447,0303,4174,4007,0520,0000,0000,0000 ; 4559 [AR]_[AR]*.5, SKIP DP0 ; 4560 =0 U 1262, 3054,3444,0303,4174,4007,0700,0000,0000,0000 ; 4561 FIX++: [AR]_[AR]*2 LONG, J/FIX1++ U 1263, 1262,0111,0503,4174,4007,0700,0000,0000,0000 ; 4562 [AR]_[AR]+[BR], J/FIX++ U 3054, 3055,3444,0303,4174,4007,0700,0000,0000,0000 ; 4563 FIX1++: [AR]_[AR]*2 LONG U 3055, 3056,4002,1200,4174,4007,0700,0000,0000,0000 ; 4564 Q_[MASK].AND.Q ; 4565 READ [ARX], 3T, ;RETURN TO 1 OF 4 PLACES ; 4566 DISP/1, ;BASED ON SIGN OF RESULT U 3056, 0014,3333,0004,4174,4000,1701,0000,0000,0000 ; 4567 J/14 ;RETURN ; 4568 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 124 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- DOUBLE DIVIDE SUBROUTINE ; 4569 .TOC "ARITHMETIC -- DOUBLE DIVIDE SUBROUTINE" ; 4570 .IF/FULL ; 4571 ;CALL WITH: ; 4572 ; AR!ARX!Q = 3 WORD DV'END ; 4573 ; BR!BRX = 2 WORD DV'SOR ; 4574 ;RETURN 2 WITH: ; 4575 ; AR!ARX = 2 WORD REMAINDER ; 4576 ; CORRECT IF POSITIVE (Q IS ODD) ; 4577 ; WRONG (BY BR!BRX) IF NEGATIVE (Q IS EVEN) ; 4578 ; Q = 1 WORD QUOTIENT ; 4579 ;CALLER MUST CHECK FOR ZERO DIVIDE PRIOR TO CALL ; 4580 ; ; 4581 ;NOTE: THIS SUBROUTINE ONLY WORKS FOR POSITIVE NUMBERS ; 4582 ; ; 4583 =0 ; 4584 ;HERE FOR NORMAL STARTUP ; 4585 DBLDIV: [ARX]_([ARX]-[BRX])*2 LONG, ;SUBTRACT LOW WORD U 1264, 3057,1114,0604,4174,4057,0700,4000,0000,0000 ; 4586 LSHC, J/DIVHI ;GO ENTER LOOP ; 4587 ;SKIP ENTRY POINT IF FINAL STEP IN PREVIOUS ENTRY WAS IN ERROR ; 4588 [ARX]_([ARX]+[BRX])*2 LONG, ;CORRECTION STEP U 1265, 3057,0114,0604,4174,4057,0700,0000,0000,0000 ; 4589 LSHC, J/DIVHI ;GO ENTER LOOP ; 4590 ; 4591 ;HERE IS DOUBLE DIVIDE LOOP ; 4592 DIVHI: AD/A+B, ;ADD (HARDWARE MAY OVERRIDE) ; 4593 A/BR, B/AR, ;OPERANDS ARE AR AND BR ; 4594 DEST/AD*2, ;SHIFT LEFT ; 4595 SHSTYLE/NORM, ;SET SHIFT PATHS (SEE DPE1) ; 4596 MULTI PREC/1, ;INJECT SAVED BITS U 3057, 1266,0115,0503,4174,4007,0630,2040,0060,0000 ; 4597 STEP SC ;COUNT DOWN LOOP ; 4598 =0 AD/A+B, ;ADD (HARDWARE MAY OVERRIDE) ; 4599 A/BRX, B/ARX, ;LOW WORDS ; 4600 DEST/Q_Q*2, ;SHIFT WHOLE MESS LEFT ; 4601 SHSTYLE/DIV, ;SET SHIFT PATHS (SEE DPE1) ; 4602 DIVIDE/1, ;SAVE BITS U 1266, 3057,0114,0604,4174,4067,0700,0100,0000,0000 ; 4603 J/DIVHI ;KEEP LOOPING ; 4604 ;HERE WHEN ALL DONE ; 4605 DEST/Q_Q*2, DIV, ;SHIFT IN LAST Q BIT ; 4606 DIVIDE/1, ;GENERATE BIT U 1267, 0002,4444,0002,4174,4064,1700,0100,0000,0000 ; 4607 B/HR, RETURN [2] ;ZERO HR AND RETURN ; 4608 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 125 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- SUBROUTINES FOR ARITHMETIC ; 4609 .TOC "ARITHMETIC -- SUBROUTINES FOR ARITHMETIC" ; 4610 ; 4611 ;QUAD WORD NEGATE ; 4612 ;ARGUMENT IN AC!AC1!AC2!AC3 ; 4613 ;LEAVES COPY OF AC!AC1 IN AR!Q ; 4614 ;RETURNS TO CALL!24 U 3060, 3061,1772,0000,1274,4007,0701,4000,0000,1443 ; 4615 QDNEG: Q_-AC[3] ; 4616 AC[3]_Q.AND.[MAG], ;PUT BACK LOW WORD U 3061, 1270,4003,0000,1174,4007,0621,0400,0000,1443 ; 4617 SKIP AD.EQ.0 ;SEE IF ANY CARRY ; 4618 =0 U 1270, 3064,7772,0000,1274,4007,0701,0000,0000,1442 ; 4619 COM2A: Q_.NOT.AC[2], J/COM2 ;CARRY--DO 1'S COMPLEMENT U 1271, 3062,1772,0000,1274,4007,0701,4000,0000,1442 ; 4620 Q_-AC[2] ;NEXT WORD ; 4621 AC[2]_Q.AND.[MAG], ;PUT BACK WORD U 3062, 1272,4003,0000,1174,4007,0621,0400,0000,1442 ; 4622 SKIP AD.EQ.0 ; 4623 =0 U 1272, 3065,7772,0000,1274,4007,0701,0000,0000,1441 ; 4624 COM1A: Q_.NOT.AC[1], J/COM1 U 1273, 3063,1772,0000,1274,4007,0701,4000,0000,1441 ; 4625 Q_-AC[1] ; 4626 AC[1]_Q.AND.[MAG], U 3063, 1274,4003,0000,1174,4007,0621,0400,0000,1441 ; 4627 SKIP AD.EQ.0 ; 4628 =0 U 1274, 3066,7771,0003,0274,4007,0700,0000,0000,0000 ; 4629 COM0A: [AR]_.NOT.AC, J/COM0 U 1275, 3066,1771,0003,0274,4007,0701,4000,0000,0000 ; 4630 [AR]_-AC, 3T, J/COM0 ; 4631 U 3064, 1272,4003,0000,1174,4007,0700,0400,0000,1442 ; 4632 COM2: AC[2]_Q.AND.[MAG], J/COM1A U 3065, 1274,4003,0000,1174,4007,0700,0400,0000,1441 ; 4633 COM1: AC[1]_Q.AND.[MAG], J/COM0A U 3066, 0024,3440,0303,0174,4004,1700,0400,0000,0000 ; 4634 COM0: AC_[AR], RETURN [24] ; 4635 .ENDIF/FULL ; 4636 ; 4637 ;DOUBLE WORD NEGATE ; 4638 ;ARGUMENT IN AR AND ARX ; 4639 ;RETURNS TO CALL!2 ; 4640 U 3067, 3070,4551,0404,4374,0007,0700,0000,0037,7777 ; 4641 DBLNEG: CLEAR ARX0 ;FLUSH DUPLICATE SIGN ; 4642 DBLNGA: [ARX]_-[ARX], ;FLIP LOW WORD U 3070, 1276,2441,0404,4174,4007,0621,4000,0000,0000 ; 4643 SKIP AD.EQ.0 ;SEE IF CARRY ; 4644 =0 [AR]_.NOT.[AR], ;NO CARRY-- 1 COMP U 1276, 2220,7441,0303,4174,4467,0700,0000,0001,0001 ; 4645 AD FLAGS, J/CLARX0 ;CLEAR LOW SIGN ; 4646 [AR]_-[AR], ;CARRY U 1277, 2220,2441,0303,4174,4467,0701,4000,0001,0001 ; 4647 AD FLAGS, 3T, J/CLARX0 ; 4648 ; 4649 ;SAME THING BUT DOES NOT SET PC FLAGS U 3071, 1300,2441,0404,4174,4007,0621,4000,0000,0000 ; 4650 DBLNG1: [ARX]_-[ARX], SKIP AD.EQ.0 U 1300, 2220,7441,0303,4174,4007,0700,0000,0000,0000 ; 4651 =0 [AR]_.NOT.[AR], J/CLARX0 U 1301, 2220,2441,0303,4174,4007,0700,4000,0000,0000 ; 4652 [AR]_-[AR], J/CLARX0 ; 4653 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 126 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 ARITHMETIC -- SUBROUTINES FOR ARITHMETIC ; 4654 .NOBIN ; 4655 .TOC "BYTE GROUP -- IBP, ILDB, LDB, IDPB, DPB" ; 4656 ; 4657 ; 4658 ;ALL FIVE INSTRUCTIONS OF THIS GROUP ARE CALLED WITH THE BYTE POINTER ; 4659 ;IN THE AR. ALL INSTRUCTIONS SHARE COMMON SUBROUTINES. ; 4660 ; 4661 ;IBP OR ADJBP ; 4662 ;IBP IF AC#0, ADJBP OTHERWISE ; 4663 ; HERE WITH THE BASE POINTER IN AR ; 4664 ; 4665 ;HERE IS A MACRO TO DO IBP. WHAT HAPPENS IS: ; 4666 ; THE AR IS PUT ON THE DP. ; 4667 ; THE BR IS LOADED FROM THE DP WITH BITS 0-5 FROM SCAD ; 4668 ; THE SCAD COMPUTES P-S ; 4669 ; IBPS IS CALLED WITH A 4-WAY DISPATCH ON SCAD0 AND FIRST-PART-DONE ; 4670 ;THE MACRO IS WRITTEN WITH SEVERAL SUB-MACROS BECAUSE OF RESTRICTIONS ; 4671 ; IN THE MICRO ASSEMBLER ; 4672 ; 4673 IBP DP "AD/D, DEST/A, A/AR, B/BR, DBUS/DBM, DBM/DP, BYTE/BYTE1" ; 4674 IBP SCAD "SCAD/A-B, SCADA/BYTE1, SCADB/SIZE" ; 4675 IBP SPEC "SCAD DISP, SKIP FPD" ; 4676 CALL IBP "IBP DP, IBP SCAD, IBP SPEC, CALL [IBPS], DT/3T" ; 4677 ; 4678 SET P TO 36-S "AD/D,DEST/A,A/BR,B/AR,DBUS/DBM,DBM/DP,SCAD/A-B,SCADB/SIZE,BYTE/BYTE1,SCADA/PTR44" ; 4679 ; 4680 ;THE FOLLOWING MACRO IS USED FOR COUNTING SHIFTS IN THE BYTE ROUTINES. IT ; 4681 ; USES THE FE AND COUNTS BY 8. NOTE: BYTE STEP IS A 2S WEIGHT SKIP NOT 1S. ; 4682 BYTE STEP "SCAD/A+B,SCADA/S#,S#/1770,SCADB/FE,LOAD FE, 3T,SCAD DISP" ; 4683 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 127 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- IBP, ILDB, LDB, IDPB, DPB ; 4684 .BIN ; 4685 ; 4686 .DCODE D 0133, 0015,1610,1100 ; 4687 133: R, AC, J/IBP ;OR ADJBP D 0134, 0000,1620,1500 ; 4688 134: R,W TEST, J/ILDB ;CAN'T USE RPW BECAUSE OF FPD D 0135, 0000,1624,1100 ; 4689 R, J/LDB D 0136, 0000,1630,1500 ; 4690 R,W TEST, J/IDPB D 0137, 0000,1634,1100 ; 4691 R, J/DPB ; 4692 .UCODE ; 4693 1610: U 1610, 0240,4443,0000,4174,4007,0360,0000,0000,0000 ; 4694 IBP: SKIP IF AC0 ;SEE IF ADJBP ; 4695 =000 WORK[ADJPTR]_[AR], ;SAVE POINTER U 0240, 3127,3333,0003,7174,4007,0700,0400,0000,0223 ; 4696 J/ADJBP ;GO ADJUST BYTE POINTER U 0241, 0350,3770,0305,4334,4016,7351,0010,0033,6000 ; 4697 =001 CALL IBP ;BUMP BYTE POINTER U 0245, 0110,3443,0100,4174,4156,4700,0200,0014,0012 ; 4698 =101 DONE ;POINTER STORED ; 4699 = ; 4700 ; 4701 1620: U 1620, 0350,3770,0305,4334,4016,7351,0010,0033,6000 ; 4702 ILDB: CALL IBP ;BUMP BYTE POINTER ; 4703 1624: ; 4704 LDB: READ [AR], ;LOOK AT POINTER ; 4705 LOAD BYTE EA, FE_P, 3T, ;GET STUFF OUT OF POINTER U 1624, 3077,3333,0003,4174,4217,0701,1010,0073,0500 ; 4706 CALL [BYTEA] ;COMPUTE EFFECTIVE ADDRESS U 1625, 0604,3443,0100,4174,4007,0700,0200,0014,0012 ; 4707 1625: VMA_[PC], FETCH ;START FETCH OF NEXT INST ; 4708 =0* READ [AR], ;LOOK AT POINTER ; 4709 FE_FE.AND.S#, S#/0770, ;MASK OUT JUNK IN FE ; 4710 BYTE DISP, ;DISPATCH ON BYTE SIZE U 0604, 0340,3333,0003,4174,4006,5701,1010,0051,0770 ; 4711 CALL [LDB1] ;GET BYTE ; 4712 AC_[AR], CLR FPD, ;STORE AC U 0606, 0555,3440,0303,0174,4467,0700,0400,0005,0000 ; 4713 J/NIDISP ;GO DO NEXT INST ; 4714 ; 4715 1630: U 1630, 0350,3770,0305,4334,4016,7351,0010,0033,6000 ; 4716 IDPB: CALL IBP ;BUMP BYTE POINTER ; 4717 1634: U 1634, 3072,3775,0004,0274,4007,0701,0000,0000,0000 ; 4718 DPB: [ARX]_AC*2 ;PUT 7 BIT BYTE IN 28-34 ; 4719 AD/A, A/ARX, SCAD/A, ;PUT THE BYTE INTO ; 4720 SCADA/BYTE5, 3T, ; INTO THE FE REGISTER U 3072, 3073,3443,0400,4174,4007,0701,1000,0077,0000 ; 4721 LOAD FE ; FE REGISTER U 3073, 0264,3771,0004,0276,6007,0700,0000,0000,0000 ; 4722 [ARX]_AC ;PUT BYTE IN ARX ; 4723 =100 READ [AR], ;LOOK AT BYTE POINTER ; 4724 LOAD BYTE EA, ;LOAD UP EFFECTIVE ADDRESS U 0264, 3077,3333,0003,4174,4217,0700,0010,0000,0500 ; 4725 CALL [BYTEA] ;COMPUTE EFFECTIVE ADDRESS ; 4726 READ [AR], ;LOOK AT POINTER AGAIN ; 4727 BYTE DISP, ;DISPATCH ON SIZE U 0265, 0360,3333,0003,4174,4006,5701,0010,0000,0000 ; 4728 CALL [DPB1] ;GO STORE BYTE U 0267, 1400,4443,0000,4174,4467,0700,0000,0005,0000 ; 4729 =111 CLR FPD, J/DONE ;ALL DONE ; 4730 = ; 4731 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 128 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- INCREMENT BYTE POINTER SUBROUTINE ; 4732 .TOC "BYTE GROUP -- INCREMENT BYTE POINTER SUBROUTINE" ; 4733 ; 4734 =00 U 0350, 3075,3441,0503,4174,4007,0700,0200,0003,0002 ; 4735 IBPS: [AR]_[BR], START WRITE, J/IBPX ;NO OVERFLOW, BR HAS ANSWER U 0351, 0004,4443,0000,4174,4004,1700,0000,0000,0000 ; 4736 RETURN [4] ;FIRST PART DONE SET U 0352, 3074,3770,0503,4334,4017,0700,0000,0032,6000 ; 4737 SET P TO 36-S, J/NXTWRD ;WORD OVERFLOW U 0353, 0004,4443,0000,4174,4004,1700,0000,0000,0000 ; 4738 RETURN [4] ;FPD WAS SET IGNORE OVERFLOW ; 4739 ; AND RETURN ; 4740 U 3074, 3075,0111,0703,4170,4007,0700,0200,0003,0002 ; 4741 NXTWRD: [AR]_[AR]+1, HOLD LEFT, START WRITE ;BUMP Y AND RETURN U 3075, 0004,3333,0003,4175,5004,1701,0200,0000,0002 ; 4742 IBPX: MEM WRITE, MEM_[AR], RETURN [4] ; 4743 ; 4744 ; 4745 .TOC "BYTE GROUP -- BYTE EFFECTIVE ADDRESS EVALUATOR" ; 4746 ; 4747 ;ENTER WITH POINTER IN AR ; 4748 ;RETURN1 WITH (EA) IN VMA AND WORD IN BR ; 4749 BYTEAS: EA MODE DISP, ;HERE TO AVOID FPD U 3076, 0070,4443,0000,2174,4006,6700,0000,0000,0000 ; 4750 J/BYTEA0 ;GO COMPUTE EA ; 4751 BYTEA: SET FPD, ;SET FIRST-PART-DONE U 3077, 0070,4443,0000,2174,4466,6700,0000,0003,0000 ; 4752 EA MODE DISP ;DISPATCH ; 4753 =100* ; 4754 BYTEA0: VMA_[AR]+XR, ;INDEXING ; 4755 START READ, ;FETCH DATA WORD ; 4756 PXCT BYTE DATA, ;FOR PXCT U 0070, 3101,0553,0300,2274,4007,0700,0200,0004,0712 ; 4757 J/BYTFET ;GO WAIT ; 4758 VMA_[AR], ;PLAIN ; 4759 START READ, ;START CYCLE ; 4760 PXCT BYTE DATA, ;FOR PXCT U 0072, 3101,3443,0300,4174,4007,0700,0200,0004,0712 ; 4761 J/BYTFET ;GO WAIT ; 4762 VMA_[AR]+XR, ;BOTH ; 4763 START READ, ;START CYCLE ; 4764 PXCT BYTE PTR EA, ;FOR PXCT U 0074, 3100,0553,0300,2274,4007,0700,0200,0004,0512 ; 4765 J/BYTIND ;GO DO INDIRECT ; 4766 VMA_[AR], ;JUST @ ; 4767 START READ, ;START READ U 0076, 3100,3443,0300,4174,4007,0700,0200,0004,0512 ; 4768 PXCT BYTE PTR EA ;FOR PXCT ; 4769 BYTIND: MEM READ, ;WAIT FOR @ WORD ; 4770 [AR]_MEM, ;PUT IN AR ; 4771 HOLD LEFT, ;JUST IN RH (SAVE P & S) ; 4772 LOAD BYTE EA, ;LOOP BACK U 3100, 3076,3771,0003,4361,5217,0700,0200,0000,0502 ; 4773 J/BYTEAS ; .. ; 4774 ; 4775 BYTFET: MEM READ, ;WAIT FOR BYTE DATA ; 4776 [BR]_MEM.AND.MASK, ; WORD. UNSIGNED U 3101, 0001,4551,1205,4365,5004,1700,0200,0000,0002 ; 4777 RETURN [1] ;RETURN TO CALLER ; 4778 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 129 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- LOAD BYTE SUBROUTINE ; 4779 .TOC "BYTE GROUP -- LOAD BYTE SUBROUTINE" ; 4780 ; 4781 ;CALL WITH: ; 4782 ; WORD IN BR ; 4783 ; POINTER IN AR ; 4784 ; P IN FE ; 4785 ; BYTE DISPATCH ; 4786 ;RETURN2 WITH BYTE IN AR ; 4787 LDB SCAD "SCAD/A,BYTE/BYTE5" ; 4788 7-BIT LDB "AD/D,DBUS/DBM,DBM/DP,DEST/A,A/BR,B/BR, LDB SCAD" ; 4789 ; 4790 =000 ; 4791 LDB1: GEN 17-FE, 3T, ;GO SEE IF ALL THE BITS ; 4792 SCAD DISP, ; ARE IN THE LEFT HALF U 0340, 0550,4443,0000,4174,4006,7701,0000,0031,0210 ; 4793 J/LDBSWP ;GO TO LDBSWP & SKIP IF LH ; 4794 ; 4795 ;HERE ARE THE 7-BIT BYTES U 0341, 3102,3770,0505,4334,4057,0700,0000,0073,0000 ; 4796 =001 7-BIT LDB, SCADA/BYTE1, J/LDB7 U 0342, 3102,3770,0505,4334,4057,0700,0000,0074,0000 ; 4797 =010 7-BIT LDB, SCADA/BYTE2, J/LDB7 U 0344, 3102,3770,0505,4334,4057,0700,0000,0075,0000 ; 4798 =100 7-BIT LDB, SCADA/BYTE3, J/LDB7 U 0345, 3102,3770,0505,4334,4057,0700,0000,0076,0000 ; 4799 =101 7-BIT LDB, SCADA/BYTE4, J/LDB7 U 0347, 3102,3770,0505,4334,4057,0700,0000,0077,0000 ; 4800 =111 7-BIT LDB, SCADA/BYTE5, J/LDB7 ; 4801 = ; 4802 ; 4803 ;FOR 7-BIT BYTES WE HAVE BYTE IN BR 28-35 AND JUNK IN REST OF BR. ; 4804 ; WE JUST MASK THE SELECTED BYTE AND SHIFT ONE PLACE RIGHT. ; 4805 LDB7: AD/ZERO,RSRC/DA, ;LH_ZERO, RH_D.AND.A ; 4806 DBUS/DBM,DBM/#,#/376, ;D INPUT IS 376 ; 4807 A/BR, ;A IS BR ; 4808 B/AR, ;PUT RESULT IN AR ; 4809 DEST/AD*.5, 3T, ;SHIFT RESULT 1 PLACE U 3102, 0002,4257,0503,4374,4004,1701,0000,0000,0376 ; 4810 RETURN [2] ;RETURN TO CALLER ; 4811 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 130 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- LOAD BYTE SUBROUTINE ; 4812 ;HERE FOR NORMAL BYTES ; 4813 =00 ; 4814 LDBSWP: FE_-FE, ;MAKE P NEGATIVE U 0550, 3104,4443,0000,4174,4007,0700,1000,0031,0000 ; 4815 J/LDBSH ;JOIN MAIN LDB LOOP U 0552, 3103,3770,0505,4344,4007,0700,0000,0000,0000 ; 4816 =10 [BR]_[BR] SWAP ;SHIFT 18 STEPS ; 4817 = ; 4818 [BR]_0, HOLD RIGHT, ;PUT ZERO IN LH U 3103, 3104,4221,0005,4174,0007,0700,1000,0031,0220 ; 4819 FE_-FE+S#, S#/220 ;UPDATE FE ; 4820 LDBSH: [BR]_[BR]*.5, ;SHIFT RIGHT ; 4821 FE_FE+10, ;UPDATE THE FE U 3104, 3105,3447,0505,4174,4007,0700,1020,0041,0010 ; 4822 MULTI SHIFT/1 ;FAST SHIFT U 3105, 3106,3333,0003,4174,4007,0700,1000,0031,7770 ; 4823 READ [AR], FE_-S-10 ;GET SIZE U 3106, 3107,4222,0000,4174,4007,0700,0000,0000,0000 ; 4824 Q_0 ;CLEAR Q ; 4825 GEN MSK [AR], ;PUT MASK IN Q (WIPEOUT AR) ; 4826 FE_FE+10, ;COUNT UP ALL STEPS U 3107, 3110,4224,0003,4174,4027,0700,1020,0041,0010 ; 4827 MULTI SHIFT/1 ;FAST SHIFT U 3110, 3111,4224,0003,4174,4027,0700,0000,0000,0000 ; 4828 GEN MSK [AR] ;ONE MORE BIT U 3111, 0002,4001,0503,4174,4004,1700,0000,0000,0000 ; 4829 [AR]_[BR].AND.Q, RETURN [2] ; 4830 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 131 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- LOAD BYTE SUBROUTINE ; 4831 .NOBIN ; 4832 .TOC "BYTE GROUP -- DEPOSIT BYTE IN MEMORY" ; 4833 ; 4834 ;FLOW FOR DPB (NOT 7-BIT BYTE) ; 4835 ; ; 4836 ;FIRST SET ARX TO -1 AND Q TO ZERO AND ROTATE LEFT ; 4837 ; S PLACES GIVING: ; 4838 ; 4839 ; ARX Q ; 4840 ; +------------------!------------------+ ; 4841 ; !111111111111000000!000000000000111111! ; 4842 ; +------------------!------------------+ ; 4843 ; !<--->! ; 4844 ; S BITS ; 4845 ; ; 4846 ; 4847 ;NOW THE AC IS LOAD INTO THE ARX AND BOTH THE ARX AND Q ; 4848 ; ARE SHIFTED LEFT P BITS GIVING: ; 4849 ; 4850 ; +------------------!------------------+ ; 4851 ; !??????BBBBBB000000!000000111111000000! ; 4852 ; +------------------!------------------+ ; 4853 ; <----><----> <----><----> ; 4854 ; JUNK BYTE MASK P BITS ; 4855 ; ; 4856 ; 4857 ;AT THIS POINT WE ARE ALMOST DONE. WE NEED TO AND ; 4858 ; THE BR WITH .NOT. Q TO ZERO THE BITS FOR THE BYTE ; 4859 ; AND AND ARX WITH Q TO MASK OUT THE JUNK THIS GIVES: ; 4860 ; ; 4861 ; ARX ; 4862 ; +------------------+ ; 4863 ; !000000BBBBBB000000! ; 4864 ; +------------------! ; 4865 ; ; 4866 ; AR ; 4867 ; +------------------+ ; 4868 ; !DDDDDD000000DDDDDD! ; 4869 ; +------------------+ ; 4870 ; ; 4871 ;WE NOW OR THE AR WITH ARX TO GENERATE THE ANSWER. ; 4872 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 132 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- DEPOSIT BYTE IN MEMORY ; 4873 .BIN ; 4874 ; 4875 ;DEPOSIT BYTE SUBROUTINE ; 4876 ;CALL WITH: ; 4877 ; BYTE POINTER IN AR ; 4878 ; BYTE TO STORE IN ARX ; 4879 ; WORD TO MERGE WITH IN BR ; 4880 ; (E) OF BYTE POINTER IN VMA ; 4881 ; 7-BIT BYTE IN FE ; 4882 ; BYTE DISPATCH ; 4883 ;RETURN2 WITH BYTE IN MEMORY ; 4884 ; ; 4885 DPB SCAD "SCAD/A+B,SCADA/S#,SCADB/FE,S#/0" ; 4886 7-BIT DPB "AD/D,DEST/A,A/BR,DBUS/DBM,DBM/DP,B/AR, DPB SCAD" ; 4887 ; 4888 =000 U 0360, 3114,3333,0003,4174,4007,0700,1000,0031,7770 ; 4889 DPB1: READ [AR], FE_-S-10, J/DPBSLO ;NOT SPECIAL U 0361, 3112,3770,0503,4334,4017,0700,0000,0041,0000 ; 4890 =001 7-BIT DPB, BYTE/BYTE1, J/DPB7 U 0362, 3112,3770,0503,4334,4027,0700,0000,0041,0000 ; 4891 =010 7-BIT DPB, BYTE/BYTE2, J/DPB7 U 0364, 3112,3770,0503,4334,4037,0700,0000,0041,0000 ; 4892 =100 7-BIT DPB, BYTE/BYTE3, J/DPB7 U 0365, 3112,3770,0503,4334,4047,0700,0000,0041,0000 ; 4893 =101 7-BIT DPB, BYTE/BYTE4, J/DPB7 U 0367, 3112,3770,0503,4334,4057,0700,0000,0041,0000 ; 4894 =111 7-BIT DPB, BYTE/BYTE5, J/DPB7 ; 4895 = U 3112, 3113,3447,1200,4174,4007,0700,0200,0003,0002 ; 4896 DPB7: [MAG]_[MASK]*.5, START WRITE U 3113, 0002,3333,0003,4175,5004,1701,0200,0000,0002 ; 4897 MEM WRITE, MEM_[AR], RETURN [2] ; 4898 ; 4899 U 3114, 3115,4222,0000,4174,4007,0700,0000,0000,0000 ; 4900 DPBSLO: Q_0 ;CLEAR Q ; 4901 GEN MSK [MAG], ;GENERATE MASK IN Q (ZAP MAG) ; 4902 FE_FE+10, ;COUNT STEPS U 3115, 3116,4224,0000,4174,4027,0700,1020,0041,0010 ; 4903 MULTI SHIFT/1 ;FAST SHIFT U 3116, 3117,4224,0000,4174,4027,0700,0000,0000,0000 ; 4904 GEN MSK [MAG] ;ONE MORE BITS U 3117, 3120,3333,0003,4174,4007,0701,1000,0073,0000 ; 4905 READ [AR], 3T, FE_P ;AMOUNT TO SHIFT U 3120, 3121,4443,0000,4174,4007,0700,1000,0051,0770 ; 4906 FE_FE.AND.S#, S#/0770 ;MASK OUT JUNK ; 4907 Q_Q.AND.[MASK], ;CLEAR BITS 36 AND 37 U 3121, 3122,4002,1200,4174,4007,0700,1000,0031,0000 ; 4908 FE_-FE ;MINUS NUMBER OF STEPS ; 4909 [ARX]_[ARX]*2 LONG, ;SHIFT BYTE AND MASK ; 4910 FE_FE+10, ;COUNT OUT STEPS U 3122, 3123,3444,0404,4174,4007,0700,1020,0041,0010 ; 4911 MULTI SHIFT/1 ;FAST SHIFT ; 4912 ;AT THIS POINT WE HAVE DONE ALL THE SHIFTING WE NEED. THE BYTE IS ; 4913 ; IN ARX AND THE MASK IS IN Q. U 3123, 3124,7221,0003,4174,4007,0700,0000,0000,0000 ; 4914 [AR]_.NOT.Q U 3124, 3125,4111,0503,4174,4007,0700,0000,0000,0000 ; 4915 [AR]_[AR].AND.[BR] U 3125, 3126,4001,0404,4174,4007,0700,0000,0000,0000 ; 4916 [ARX]_[ARX].AND.Q ; 4917 [AR]_[AR].OR.[ARX], U 3126, 3112,3111,0403,4174,4007,0700,0000,0000,0000 ; 4918 J/DPB7 ; 4919 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 133 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- ADJUST BYTE POINTER ; 4920 .TOC "BYTE GROUP -- ADJUST BYTE POINTER" ; 4921 .IF/FULL ; 4922 ;FIRST THE NUMBER OF BYTES PER WORD IS COMPUTED FROM THE ; 4923 ; FOLLOWING FORMULA: ; 4924 ; ; 4925 ; ( P ) ( 36-P ) ; 4926 ; BYTES PER WORD = INT( --- ) + INT( ---- ) ; 4927 ; ( S ) ( S ) ; 4928 ; ; 4929 ;THIS GIVES 2 BYTES PER WORD FOR THE FOLLOWING 12 BIT BYTE: ; 4930 ; !=====================================! ; 4931 ; ! 6 !////////////! 12 ! 6 ! ; 4932 ; !=====================================! ; 4933 ; P=18 AND S=12 ; 4934 ; ; 4935 ;WE GET 3 BYTES/WORD IF THE BYTES FALL IN THE NATURAL PLACE: ; 4936 ; !=====================================! ; 4937 ; ! 12 !\\\\\\\\\\\\! 12 ! ; 4938 ; !=====================================! ; 4939 ; P=12 AND S=12 ; 4940 ; 4941 ;WE COME HERE WITH THE BYTE POINTER IN AR, AND ADJPTR ; 4942 ADJBP: [ARX]_[AR] SWAP, ;MOVE SIZE OVER U 3127, 1302,3770,0304,4344,4007,0700,2000,0071,0011 ; 4943 SC_9. ;READY TO SHIFT ; 4944 =0 ; 4945 ADJBP0: [ARX]_[ARX]*.5, ;SHIFT P OVER ; 4946 STEP SC, ; .. U 1302, 1302,3447,0404,4174,4007,0630,2000,0060,0000 ; 4947 J/ADJBP0 ; .. ; 4948 [ARX]_([ARX].AND.#)*.5, ;SHIFT AND MASK ; 4949 3T, ;WAIT U 1303, 3130,4557,0404,4374,4007,0701,0000,0000,0176 ; 4950 #/176 ;6 BIT MASK ; 4951 [ARX]_#, ;CLEAR LH ; 4952 #/0, ; .. U 3130, 3131,3771,0004,4374,0007,0700,0000,0000,0000 ; 4953 HOLD RIGHT ; .. U 3131, 3132,3333,0004,7174,4007,0700,0400,0000,0221 ; 4954 WORK[ADJP]_[ARX] ;SAVE P ; 4955 [BR]_([AR].AND.#)*.5, ;START ON S ; 4956 3T, ;EXTRACT S U 3132, 3133,4557,0305,4374,4007,0701,0000,0000,7700 ; 4957 #/007700 ; .. ; 4958 [BR]_[BR] SWAP, ;SHIFT 18 PLACES U 3133, 3134,3770,0505,4344,4007,0700,2000,0071,0003 ; 4959 SC_3 ; .. ; 4960 [BR]_0, ;CLEAR LH U 3134, 1304,4221,0005,4174,0007,0700,0000,0000,0000 ; 4961 HOLD RIGHT ; .. ; 4962 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 134 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- ADJUST BYTE POINTER ; 4963 =0 ; 4964 ADJBP1: [BR]_[BR]*.5, ;SHIFT S OVER ; 4965 STEP SC, ; .. U 1304, 1304,3447,0505,4174,4007,0630,2000,0060,0000 ; 4966 J/ADJBP1 ; .. ; 4967 WORK[ADJS]_[BR], ;SALT S AWAY U 1305, 1306,3333,0005,7174,4007,0621,0400,0000,0222 ; 4968 SKIP AD.EQ.0 ;SEE IF ZERO ; 4969 =0 Q_[ARX], ;DIVIDE P BY S ; 4970 SC_34., ;STEP COUNT U 1306, 0660,3442,0400,4174,4007,0700,2000,0071,0042 ; 4971 J/ADJBP2 ;SKIP NEXT WORD U 1307, 1404,3771,0003,7274,4007,0701,0000,0000,0223 ; 4972 [AR]_WORK[ADJPTR], J/MOVE ;S=0 -- SAME AS MOVE ; 4973 =0* ; 4974 ADJBP2: [AR]_#, ;FILL AR WITH SIGN BITS ; 4975 #/0, ;POSITIVE U 0660, 0370,3771,0003,4374,4007,0700,0010,0000,0000 ; 4976 CALL [DIVSUB] ;GO DIVIDE U 0662, 3135,3223,0000,7174,4007,0700,0400,0000,0224 ; 4977 WORK[ADJQ1]_Q ;SAVE QUOTIENT ; 4978 Q_#, ;COMPUTE (36-P)/S ; 4979 #/36., ; .. U 3135, 3136,3772,0000,4370,4007,0700,0000,0000,0044 ; 4980 HOLD LEFT ;SMALL ANSWER U 3136, 3137,1662,0000,7274,4007,0701,4000,0000,0221 ; 4981 Q_Q-WORK[ADJP] ;SUBTRACT P U 3137, 3140,3771,0005,7274,4007,0701,0000,0000,0222 ; 4982 [BR]_WORK[ADJS] ;DIVIDE BY S U 3140, 0664,4443,0000,4174,4007,0700,2000,0071,0042 ; 4983 SC_34. ;STEP COUNT ; 4984 =0* [AR]_#, ;MORE SIGN BITS ; 4985 #/0, ; .. U 0664, 0370,3771,0003,4374,4007,0700,0010,0000,0000 ; 4986 CALL [DIVSUB] ;GO DIVIDE U 0666, 3141,3333,0003,7174,4007,0700,0400,0000,0225 ; 4987 WORK[ADJR2]_[AR] ;SAVE REMAINDER ; 4988 [AR]_#, ;ASSUME NEGATIVE ADJ U 3141, 3142,3771,0003,4374,4007,0700,0000,0077,7777 ; 4989 #/777777 ;EXTEND SIGN ; 4990 AD/D+Q, ;BR_(P/S)+((36-P)/S) ; 4991 DEST/AD, ; .. ; 4992 B/BR, ; .. ; 4993 RAMADR/#, ; .. ; 4994 DBUS/RAM, ; .. ; 4995 WORK/ADJQ1, ; .. ; 4996 4T, ; .. U 3142, 1310,0661,0005,7274,4007,0622,0000,0000,0224 ; 4997 SKIP AD.EQ.0 ;SEE IF ZERO ; 4998 =0 Q_Q+AC, ;GET ADJUSTMENT ; 4999 SC_34., ;STEP COUNT ; 5000 SKIP DP0, ;GO DO DIVIDE ; 5001 4T, ;WAIT FOR DP U 1310, 0570,0662,0000,0274,4007,0522,2000,0071,0042 ; 5002 J/ADJBP3 ;BELOW U 1311, 0555,4443,0000,4174,4467,0700,0000,0051,1000 ; 5003 NO DIVIDE ;0 BYTES/WORD ; 5004 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 135 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- ADJUST BYTE POINTER ; 5005 ;WE NOW DIVIDE THE ADJUSTMENT BY THE BYTES PER WORD AND FORCE THE ; 5006 ; REMAINDER (R) TO BE A POSITIVE NUMBER (MUST NOT BE ZERO). THE ; 5007 ; QUOTIENT IS ADDED TO THE Y FIELD IN THE BYTE POINTER AND THE NEW ; 5008 ; P FIELD IS COMPUTED BY: ; 5009 ; ; 5010 ; ( ( 36-P )) ; 5011 ; NEW P = 36-((R * S) + RMDR( ---- )) ; 5012 ; ( ( S )) ; 5013 ; ; 5014 ;WE NOW HAVE BYTES/WORD IN BR AND ADJUSTMENT IN Q. DIVIDE TO GET ; 5015 ; WORDS TO ADJUST BY. ; 5016 =00 ; 5017 ADJBP3: [AR]_#, ;POSITIVE ADJUSTMENT U 0570, 0571,3771,0003,4374,4007,0700,0000,0000,0000 ; 5018 #/0. ; 5019 WORK[ADJBPW]_[BR], ;SAVE BYTES/WORD & COMPUTE U 0571, 0370,3333,0005,7174,4007,0700,0410,0000,0226 ; 5020 CALL [DIVSUB] ; ADJ/(BYTES/WORD) ; 5021 ;WE NOW WANT TO ADJUST THE REMAINDER SO THAT IT IS POSITIVE ; 5022 =11 Q_#, ;ONLY RIGHT HALF ; 5023 #/0, ; .. U 0573, 3143,3772,0000,4374,0007,0700,0000,0000,0000 ; 5024 HOLD RIGHT ; .. ; 5025 = ; 5026 READ [AR], ;ALREADY + U 3143, 1312,3333,0003,4174,4007,0421,0000,0000,0000 ; 5027 SKIP AD.LE.0 ; .. ; 5028 =0 ; 5029 ADJBP4: AD/D+Q, ;ADD Q TO POINTER AND STORE ; 5030 DEST/AD, ; .. ; 5031 B/BR, ;RESULT TO BR ; 5032 RAMADR/#, ;PTR IS IN RAM ; 5033 DBUS/RAM, ; .. ; 5034 WORK/ADJPTR, ; .. ; 5035 INH CRY18, ;JUST RH ; 5036 3T, ;WAIT FOR RAM U 1312, 3145,0661,0005,7274,4407,0701,0000,0000,0223 ; 5037 J/ADJBP5 ;CONTINUE BELOW ; 5038 Q_Q-1, ;NO--MAKE Q SMALLER U 1313, 3144,1002,0700,4170,4007,0700,4000,0000,0000 ; 5039 HOLD LEFT ; .. ; 5040 [AR]_[AR]+WORK[ADJBPW], ;MAKE REM BIGGER U 3144, 1312,0551,0303,7274,4007,0701,0000,0000,0226 ; 5041 J/ADJBP4 ;NOW HAVE + REMAINDER ; 5042 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 136 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- ADJUST BYTE POINTER ; 5043 ADJBP5: [BRX]_[AR], ;COMPUTE R*S U 3145, 3146,3441,0306,4174,4007,0700,2000,0071,0043 ; 5044 SC_35. ;STEP COUNT U 3146, 0062,3772,0000,7274,4007,0701,0000,0000,0222 ; 5045 Q_WORK[ADJS] ;GET S ; 5046 =01* [BRX]_[BRX]*.5 LONG, ;SHIFT OVER U 0062, 3000,3446,0606,4174,4007,0700,0010,0000,0000 ; 5047 CALL [MULSUB] ; .. ; 5048 AD/D+Q, ;AR_(R*S)+RMDR(36-P)/S ; 5049 DEST/AD, ; .. ; 5050 B/AR, ; .. ; 5051 RAMADR/#, ; .. ; 5052 3T, ; .. ; 5053 DBUS/RAM, ; .. U 0066, 3147,0661,0003,7274,4007,0701,0000,0000,0225 ; 5054 WORK/ADJR2 ; .. ; 5055 [AR]_(#-[AR])*2, ;COMPUTE 36-AR ; 5056 3T, ;AND START LEFT U 3147, 3150,2555,0303,4374,4007,0701,4000,0000,0044 ; 5057 #/36. ; .. ; 5058 [AR]_[AR] SWAP, ;PUT THE POSITION BACK U 3150, 3151,3770,0303,4344,4007,0700,2000,0071,0011 ; 5059 SC_9. ; .. ; 5060 [AR]_#, ;CLEAR JUNK FROM RH ; 5061 #/0, ; .. U 3151, 1314,3771,0003,4370,4007,0700,0000,0000,0000 ; 5062 HOLD LEFT ; .. ; 5063 =0 ; 5064 ADJBP6: [AR]_[AR]*2, ;LOOP OVER ALL BITS ; 5065 STEP SC, ; .. U 1314, 1314,3445,0303,4174,4007,0630,2000,0060,0000 ; 5066 J/ADJBP6 ; .. ; 5067 [BR]_[BR].AND.#, ; .. ; 5068 #/007777, ; .. U 1315, 3152,4551,0505,4374,0007,0700,0000,0000,7777 ; 5069 HOLD RIGHT ; .. ; 5070 AC_[AR].OR.[BR], ;ALL DONE U 3152, 1400,3113,0305,0174,4007,0700,0400,0000,0000 ; 5071 J/DONE ;;5072 .IFNOT/FULL ;;5073 ;;5074 ADJBP: UUO ;NO ADJBP IN SMALL ;;5075 ; MICROCODE ; 5076 .ENDIF/FULL ; 5077 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 137 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BYTE GROUP -- ADJUST BYTE POINTER ; 5078 .NOBIN ; 5079 .TOC "BLT" ; 5080 ; 5081 ;THIS CODE PROVIDES A GUARANTEED RESULT IN AC ON COMPLETION OF ; 5082 ; THE TRANSFER (EXCEPT IN THE CASE AC IS PART OF BUT NOT THE LAST WORD ; 5083 ; OF THE DESTINATION BLOCK). WHEN AC IS NOT PART OF THE DESTINATION ; 5084 ; BLOCK, IT IS LEFT CONTAINING THE ADDRESSES OF THE FIRST WORD FOLLOWING ; 5085 ; THE SOURCE BLOCK (IN THE LH), AND THE FIRST WORD FOLLOWING THE DEST- ; 5086 ; INATION BLOCK (IN THE RH). IF AC IS THE LAST WORD OF THE DESTINATION ; 5087 ; BLOCK, IT WILL BE A COPY OF THE LAST WORD OF THE SOURCE BLOCK. ; 5088 ; 5089 ;IN ADDITION, A SPECIAL-CASE CHECK IS MADE FOR THE CASE IN WHICH EACH ; 5090 ; WORD STORED IS USED AS THE SOURCE OF THE NEXT TRANSFER. IN THIS CASE, ; 5091 ; ONLY ONE READ NEED BE PERFORMED, AND THAT DATA MAY BE STORED FOR EACH ; 5092 ; TRANSFER. THUS THE COMMON USE OF BLT TO CLEAR CORE IS SPEEDED UP. ; 5093 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 138 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BLT ; 5094 .BIN ; 5095 ; 5096 ;HERE TO SETUP FOR A BLT/UBABLT ; 5097 U 3153, 1316,3770,0604,4344,4007,0700,0000,0000,0000 ; 5098 SETBLT: [ARX]_[BRX] SWAP ;COPY TO ARX (SRC IN RH) ; 5099 =0 VMA_[ARX], ;ADDRESS OF FIRST WORD ; 5100 START READ, ; 5101 PXCT BLT SRC, U 1316, 3663,3443,0400,4174,4007,0700,0210,0004,0712 ; 5102 CALL [CLARXL] ;CLEAR THE LEFT HALF OF ; 5103 [BRX]_0, ; BOTH SRC AND DEST U 1317, 3154,4221,0006,4174,0007,0700,0000,0000,0000 ; 5104 HOLD RIGHT U 3154, 3155,2112,0306,4174,4007,0700,4000,0000,0000 ; 5105 Q_[AR]-[BRX] ;NUMBER OF WORDS TO MOVE U 3155, 3156,0001,0705,4174,4007,0700,0000,0000,0000 ; 5106 [BR]_Q+1 ;LENGTH +1 ; 5107 [BR]_[BR] SWAP, ;COPY TO BOTH HALFS U 3156, 3157,3770,0505,4344,0007,0700,0000,0000,0000 ; 5108 HOLD RIGHT ; 5109 [BR]_AC+[BR], ;FINAL AC U 3157, 3160,0551,0505,0274,4407,0701,0000,0000,0000 ; 5110 INH CRY18 ;KEEP AC CORRECT IF DEST IS 777777 U 3160, 0002,3771,0013,4370,4004,1700,0000,0000,0001 ; 5111 STATE_[BLT],RETURN [2] ;SET PAGE FAIL FLAGS ; 5112 ; 5113 .DCODE D 0251, 0000,1640,2100 ; 5114 251: I, J/BLT ; 5115 .UCODE ; 5116 ; 5117 1640: U 1640, 3153,3771,0006,0276,6007,0700,0010,0000,0000 ; 5118 BLT: [BRX]_AC,CALL [SETBLT] ;FETCH THE AC (DEST IN RH) ; 5119 1642: AC_[BR], ;STORE BACK IN AC U 1642, 3662,3440,0505,0174,4007,0700,0410,0000,0000 ; 5120 CALL [LOADQ] ;LOAD FIRST WORD INTO Q ; 5121 1643: [BR]_[ARX]+1000001, ;SRC+1 ; 5122 3T, U 1643, 3161,0551,0405,4370,4007,0701,0000,0000,0001 ; 5123 HOLD LEFT ; 5124 [BR]-[BRX], 3T, ;IS THIS THE CORE CLEAR CASE U 3161, 1320,2113,0506,4174,4007,0331,4000,0000,0000 ; 5125 SKIP ADR.EQ.0 ; 5126 =0 ; 5127 BLTLP1: VMA_[BRX], ;NO, GET DEST ADR ; 5128 START WRITE, ;START TO STORE NEXT WORD ; 5129 PXCT BLT DEST, ;WHERE TO STORE U 1320, 3164,3443,0600,4174,4007,0700,0200,0003,0312 ; 5130 J/BLTGO ; 5131 ; 5132 ;SKIP TO NEXT PAGE IF CLEARING CORE ; 5133 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 139 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BLT ; 5134 ;CLEAR CORE CASE ; 5135 VMA_[BRX], ; 5136 START WRITE, U 1321, 3162,3443,0600,4174,4007,0700,0200,0003,0312 ; 5137 PXCT BLT DEST ; 5138 BLTCLR: MEM WRITE, ;STORE WORD ; 5139 MEM_Q, U 3162, 1322,3223,0000,4174,4007,0671,0200,0000,0002 ; 5140 SKIP/-1 MS ;1 MS TIMER UP U 1322, 3165,4443,0000,4174,4007,0700,0000,0000,0000 ; 5141 =0 J/BLTGOT ;GO TAKE INTERRUPT ; 5142 [BRX]-[AR], ;BELOW E? ; 5143 3T, U 1323, 1324,2113,0603,4174,4007,0521,4000,0000,0000 ; 5144 SKIP DP0 ; 5145 =0 END BLT, ;NO--STOP BLT U 1324, 1400,4221,0013,4170,4007,0700,0000,0000,0000 ; 5146 J/DONE ; 5147 [ARX]_[ARX]+1, ;FOR PAGE FAIL LOGIC U 1325, 1326,0111,0704,4174,4007,0370,0000,0000,0000 ; 5148 SKIP IRPT ; 5149 =0 VMA_[BRX]+1, ; 5150 LOAD VMA, ; 5151 PXCT BLT DEST, ; 5152 START WRITE, ;YES--KEEP STORING U 1326, 3162,0111,0706,4170,4007,0700,0200,0003,0312 ; 5153 J/BLTCLR ; 5154 VMA_[BRX]+1, ;INTERRUPT ; 5155 LOAD VMA, ; 5156 PXCT BLT DEST, ; 5157 START WRITE, U 1327, 3164,0111,0706,4170,4007,0700,0200,0003,0312 ; 5158 J/BLTGO ; 5159 ; 5160 ;HERE FOR NORMAL BLT ; 5161 BLTLP: MEM READ, ;FETCH ; 5162 Q_MEM, U 3163, 1320,3772,0000,4365,5007,0700,0200,0000,0002 ; 5163 J/BLTLP1 ; 5164 BLTGO: MEM WRITE, ;STORE U 3164, 3165,3223,0000,4174,4007,0701,0200,0000,0002 ; 5165 MEM_Q ; 5166 BLTGOT: [BRX]-[AR], ;BELOW E? ; 5167 3T, U 3165, 1330,2113,0603,4174,4007,0521,4000,0000,0000 ; 5168 SKIP DP0 ; 5169 =0 END BLT, ;NO--STOP BLT U 1330, 1400,4221,0013,4170,4007,0700,0000,0000,0000 ; 5170 J/DONE U 1331, 3166,0111,0706,4174,4007,0700,0000,0000,0000 ; 5171 [BRX]_[BRX]+1 ;UPDATE DEST ADDRESS ; 5172 VMA_[ARX]+1, ; 5173 LOAD VMA, ; 5174 PXCT BLT SRC, ; 5175 START READ, ;YES--MOVE 1 MORE WORD U 3166, 3163,0111,0704,4170,4007,0700,0200,0004,0712 ; 5176 J/BLTLP ; 5177 ; 5178 ;HERE TO CLEAN UP AFTER BLT PAGE FAILS ; 5179 BLT-CLEANUP: U 3167, 3170,3770,0303,4344,4007,0700,0000,0000,0000 ; 5180 [AR]_[AR] SWAP ;PUT SRC IN LEFT HALF ; 5181 [AR]_WORK[SV.BRX], U 3170, 3171,3771,0003,7270,4007,0701,0000,0000,0214 ; 5182 HOLD LEFT ; 5183 AC_[AR], ;STORE THE AC AND RETURN U 3171, 1100,3440,0303,0174,4007,0700,0400,0000,0000 ; 5184 J/CLEANED ; 5185 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 140 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BLT ;;5186 .IF/UBABLT ;;5187 .TOC "UBABLT - BLT BYTES TO/FROM UNIBUS FORMAT" ;;5188 ;;5189 ;THESE INSTRUCTION MOVE WORDS FROM BYTE TO UNIBUS AND UNIBUS TO BYTE ;;5190 ;FORMAT. FORMATS ARE: ;;5191 ; ;;5192 ;BYTE FORMAT: ;;5193 ; ;;5194 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;5195 ; ;; BYTE 0 ;; BYTE 1 ;; BYTE 2 ;; BYTE 3 ;; 4 BITS ;; ;;5196 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;5197 ; ;;5198 ;UNIBUS FORMAT: ;;5199 ; ;;5200 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;5201 ; ;; 2 BITS ;; BYTE 1 ;; BYTE 0 ;; 2 BITS ;; BYTE 3 ;; BYTE 2 ;; ;;5202 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;5203 ; ;;5204 ;;5205 =0* ;;5206 BLTX: [BRX]_AC, ;FETCH THE AC (DEST IN RH) ;;5207 CALL [SETBLT] ;DO THE REST OF THE SETUP ;;5208 AC_[BR] ;STORE THE FINAL AC IN AC ;;5209 ;;5210 BLTXLP: MEM READ, ;READ THE SOURCE WORD ;;5211 Q_MEM, ;FROM MEMORY ;;5212 B DISP ;SKIP IF BLTUB (OPCODE 717) ;;5213 =110 Q_Q*.5, ;BLTBU (OPCODE 716) - SHIFT RIGHT 1 BIT ;;5214 J/BLTBU1 ;CONTINUE INSTRUCTION ;;5215 ;;5216 AD/D.AND.Q,DBUS/DBM, ;BLTUB - MASK LOW BYTES, SHIFT LEFT ;;5217 DBM/#,#/377,DEST/AD*2,B/T1 ;AND STORE RESULT ;;5218 =00 FE_S#,S#/1767, ;-9 MORE BITS TO PUT LOW BYTE OF LH ;;5219 CALL [T1LSH] ; IN TOP OF LH SHIFT LEFT ;;5220 =01 FE_S#,S#/1772, ;-6 BITS TO PUT HI BYTE TO RIGHT ;;5221 CALL [Q_RSH] ; OF LOW BYTE. ;;5222 =11 Q_Q.AND.#,#/001774 ;KEEP ONLY HI BYTES ;;5223 = ;;5224 AD/A.OR.Q,A/T1,DEST/AD, ;MERGE PAIRS OF BYTES. NOW SWAPPED, ;;5225 B/T1 ;BUT STILL IN HALF-WORDS ;;5226 AD/57,RSRC/0A,A/T1, ;CLEAR LH OF Q WHILE LOADING ;;5227 DEST/Q_AD ;RH WITH LOW WORD ;;5228 Q_Q*2 ;SHIFT LOW WORD ACROSS 1/2 WORD ;;5229 Q_Q*2 ;AND INTO FINAL POSITION ;;5230 [T1]_[T1].AND.# CLR RH, ;CLEAR ALL BUT HIGH 16-BIT WORD ;;5231 #/777774,J/BLTXV ;FROM T1 AND CONTINUE ;;5232 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 141 ; SIMPLE.MIC[7,3] 16:49 11-NOV-1985 BLT ;;5233 BLTBU1: Q_Q*.5 ;NOW IN 1/2 WORDS ;;5234 Q_Q*.5,HOLD LEFT ;INSERT A NULL BIT IN RH ;;5235 Q_Q*.5,HOLD LEFT ;ONE MORE - NOW IN HALF WORDS ;;5236 AD/D.AND.Q,DBUS/DBM, ;BUT NOT SWAPPED. COPY RIGHT BYTE ;;5237 DBM/#,#/377,DEST/AD*2,B/T1 ;TO T1 AND SHIFT LEFT 1 POSITION ;;5238 =00 FE_S#,S#/1771, ;-7 BITS MORE ;;5239 CALL [T1LSH] ;TO FINAL RESTING PLACE ;;5240 =01 FE_S#,S#/1770, ;-8. LEFT BYTES MOVE RIGHT ;;5241 CALL [Q_RSH] ;TO FINAL RESTING PLACE ;;5242 =11 Q_Q.AND.#,#/377 ;WANT ONLY THE NEW BYTES ;;5243 = ;;5244 ;;5245 BLTXV: Q_[T1].OR.Q, ;MERGE RESULTS ;;5246 J/BLTXW ;AND STUFF IN MEMORY ;;5247 ;;5248 T1LSH: [T1]_[T1]*2,SHIFT,RETURN [1] ;;5249 Q_RSH: Q_Q*.5,SHIFT,RETURN [2] ;;5250 ;;5251 BLTXW: VMA_[BRX],START WRITE, ;DEST TO VMA ;;5252 PXCT BLT DEST ;;5253 MEM WRITE,MEM_Q ;STORE ;;5254 [BRX]-[AR],3T,SKIP DP0 ;DONE? ;;5255 =0 END BLT,J/DONE ;YES ;;5256 [BRX]_[BRX]+1 ;NO, INC DEST ;;5257 VMA_[ARX]+1,LOAD VMA, ; AND SOURCE (LOADING VMA) ;;5258 PXCT BLT SRC,START READ,;START UP MEMORY ;;5259 J/BLTXLP ;AND CONTINUE WITH NEXT WORD ; 5260 .ENDIF/UBABLT ; 5261 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 142 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- FAD, FSB ; 5262 .TOC "FLOATING POINT -- FAD, FSB" ; 5263 ; 5264 .DCODE D 0140, 0701,1577,1100 ; 5265 140: FL-R, FL-AC, J/FAD D 0142, 0702,1577,1700 ; 5266 142: FL-RW, FL-MEM, J/FAD D 0143, 0703,1577,1700 ; 5267 FL-RW, FL-BOTH, J/FAD D 0144, 0711,1577,1100 ; 5268 FL-R, FL-AC, ROUND, J/FAD D 0145, 0611,1577,0100 ; 5269 FL-I, FL-AC, ROUND, J/FAD D 0146, 0712,1577,1700 ; 5270 FL-RW, FL-MEM, ROUND, J/FAD D 0147, 0713,1577,1700 ; 5271 FL-RW, FL-BOTH, ROUND, J/FAD ; 5272 D 0150, 0701,1576,1100 ; 5273 150: FL-R, FL-AC, J/FSB D 0152, 0702,1576,1700 ; 5274 152: FL-RW, FL-MEM, J/FSB D 0153, 0703,1576,1700 ; 5275 FL-RW, FL-BOTH, J/FSB D 0154, 0711,1576,1100 ; 5276 FL-R, FL-AC, ROUND, J/FSB D 0155, 0611,1576,0100 ; 5277 FL-I, FL-AC, ROUND, J/FSB D 0156, 0712,1576,1700 ; 5278 FL-RW, FL-MEM, ROUND, J/FSB D 0157, 0713,1576,1700 ; 5279 FL-RW, FL-BOTH, ROUND, J/FSB ; 5280 .UCODE ; 5281 ; 5282 ;BOTH FAD & FSB ARE ENTERED WITH THE MEMORY OPERAND IN AR ; 5283 ; SIGN SMEARED. THE EXPONENT IN BOTH SC AND FE. ; 5284 1576: U 1576, 1577,2441,0303,4174,4007,0700,4000,0000,0000 ; 5285 FSB: [AR]_-[AR] ;MAKE MEMOP NEGATIVE ; 5286 ; 5287 1577: U 1577, 0670,3771,0005,0276,6006,7701,2000,0020,2000 ; 5288 FAD: [BR]_AC, SC_SC-EXP-1, 3T, SCAD DISP ; 5289 =0* U 0670, 1334,3333,0005,4174,4007,0520,0000,0000,0000 ; 5290 FAS1: READ [BR], SKIP DP0, J/FAS2 ;BR .LE. AR U 0672, 3172,3441,0304,4174,4007,0700,0000,0000,0000 ; 5291 [ARX]_[AR] ;SWAP AR AND BR U 3172, 3173,3441,0503,4174,4007,0700,2000,0041,2000 ; 5292 [AR]_[BR], SC_EXP U 3173, 3174,3441,0405,4174,4007,0700,2000,0020,0000 ; 5293 [BR]_[ARX], SC_SC-FE-1 ;NUMBER OF SHIFT STEPS U 3174, 1332,3333,0003,4174,4007,0520,1000,0041,2000 ; 5294 READ [AR], FE_EXP, 2T, SKIP DP0 U 1332, 3175,4551,0303,4374,0007,0700,0000,0000,0777 ; 5295 =0 [AR]_+SIGN, J/FAS3 U 1333, 3175,3551,0303,4374,0007,0700,0000,0077,7000 ; 5296 [AR]_-SIGN, J/FAS3 ; 5297 ; 5298 =0 ;SIGN SMEAR BR AND UNNORMALIZE U 1334, 3175,4551,0505,4374,0007,0700,0000,0000,0777 ; 5299 FAS2: [BR]_+SIGN, J/FAS3 U 1335, 3175,3551,0505,4374,0007,0700,0000,0077,7000 ; 5300 [BR]_-SIGN, J/FAS3 ; 5301 U 3175, 1336,4222,0000,4174,4007,0630,2000,0060,0000 ; 5302 FAS3: Q_0, STEP SC ; 5303 =0 U 1336, 1336,3446,0505,4174,4047,0630,2000,0060,0000 ; 5304 FAS4: [BR]_[BR]*.5 LONG, STEP SC, ASHC, J/FAS4 U 1337, 0420,0111,0503,4174,4003,4701,0000,0000,0000 ; 5305 [AR]_[AR]+[BR], NORM DISP, J/SNORM ; 5306 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 143 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLAOTING POINT -- FMP ; 5307 .TOC "FLAOTING POINT -- FMP" ; 5308 ; 5309 .DCODE D 0160, 0701,1570,1100 ; 5310 160: FL-R, FL-AC, J/FMP D 0162, 0702,1570,1700 ; 5311 162: FL-RW, FL-MEM, J/FMP D 0163, 0703,1570,1700 ; 5312 FL-RW, FL-BOTH, J/FMP ; 5313 D 0164, 0711,1570,1100 ; 5314 FL-R, FL-AC, ROUND, J/FMP D 0165, 0611,1570,0100 ; 5315 FL-I, FL-AC, ROUND, J/FMP D 0166, 0712,1570,1700 ; 5316 FL-RW, FL-MEM, ROUND, J/FMP D 0167, 0713,1570,1700 ; 5317 FL-RW, FL-BOTH, ROUND, J/FMP ; 5318 .UCODE ; 5319 ; 5320 1570: ; 5321 FMP: [BRX]_AC, ;GET AC ; 5322 FE_SC+EXP, 3T, ;EXPONENT OF ANSWER U 1570, 1340,3771,0006,0276,6007,0521,1000,0040,2000 ; 5323 SKIP DP0 ;GET READY TO SMEAR SIGN U 1340, 3176,4551,0606,4374,0007,0700,0000,0000,0777 ; 5324 =0 [BRX]_+SIGN, J/FMP1 ;POSITIVE U 1341, 3176,3551,0606,4374,0007,0700,0000,0077,7000 ; 5325 [BRX]_-SIGN, J/FMP1 ;NEGATIVE U 3176, 0163,3442,0300,4174,4007,0700,2000,0071,0033 ; 5326 FMP1: Q_[AR], SC_27. ;GET MEMORY OPERAND ; 5327 =01* [BRX]_[BRX]*.5 LONG, ;SHIFT RIGHT U 0163, 3000,3446,0606,4174,4007,0700,0010,0000,0000 ; 5328 CALL [MULSUB] ;MULTIPLY ; 5329 Q_Q.AND.#, #/777000, ;WE ONLY COMPUTED U 0167, 3177,4662,0000,4370,4007,0700,0000,0077,7000 ; 5330 HOLD LEFT ; 27 BITS U 3177, 3200,3441,0403,4174,4007,0700,1000,0041,0002 ; 5331 [AR]_[ARX], FE_FE+2 ;SET SHIFT PATHS ; 5332 [AR]_[AR]*.5 LONG, ;SHIFT OVER ; 5333 FE_FE-200, ;ADJUST EXPONENT U 3200, 0420,3446,0303,4174,4003,4701,1000,0041,1600 ; 5334 NORM DISP, J/SNORM ;NORMALIZE & EXIT ; 5335 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 144 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- FDV ; 5336 .TOC "FLOATING POINT -- FDV" ; 5337 ; 5338 .DCODE D 0170, 0701,1574,1100 ; 5339 170: FL-R, FL-AC, J/FDV D 0172, 0702,1574,1700 ; 5340 172: FL-RW, FL-MEM, J/FDV D 0173, 0703,1574,1700 ; 5341 FL-RW, FL-BOTH, J/FDV ; 5342 D 0174, 0711,1574,1100 ; 5343 FL-R, FL-AC, ROUND, J/FDV D 0175, 0611,1574,0100 ; 5344 FL-I, FL-AC, ROUND, J/FDV D 0176, 0712,1574,1700 ; 5345 FL-RW, FL-MEM, ROUND, J/FDV D 0177, 0713,1574,1700 ; 5346 FL-RW, FL-BOTH, ROUND, J/FDV ; 5347 .UCODE ; 5348 ; 5349 ; 5350 1574: U 1574, 1342,3441,0305,0174,4007,0621,0000,0000,0000 ; 5351 FDV: [BR]_[AR], SKIP AD.EQ.0, AC ;COPY DIVSOR SEE IF 0 ; 5352 =0 ; 5353 [AR]_AC, FE_SC-EXP, SKIP DP0, ;GET AC & COMPUTE NEW U 1342, 1344,3771,0003,0276,6007,0520,1000,0030,2000 ; 5354 J/FDV0 ; EXPONENT U 1343, 0555,4443,0000,4174,4467,0700,0000,0071,1000 ; 5355 FL NO DIVIDE ;DIVIDE BY ZERO ; 5356 =0 U 1344, 3201,4551,0303,4374,0007,0700,0000,0000,0777 ; 5357 FDV0: [AR]_+SIGN, J/FDV1 U 1345, 3202,3551,0303,4374,0007,0700,0000,0077,7000 ; 5358 [AR]_-SIGN, J/FDV2 U 3201, 3203,3441,0304,4174,4007,0700,1000,0031,0200 ; 5359 FDV1: [ARX]_[AR],FE_-FE+200,J/FDV3 ;COMPUTE 2*DVND U 3202, 3203,2441,0304,4174,4007,0700,5000,0031,0200 ; 5360 FDV2: [ARX]_-[AR],FE_-FE+200,J/FDV3 ;ABSOLUTE VALUE U 3203, 1346,3445,0506,4174,4007,0520,0000,0000,0000 ; 5361 FDV3: [BRX]_[BR]*2, SKIP DP0 ;ABSOLUTE VALUE ; 5362 =0 U 1346, 1350,2113,0406,4174,4007,0311,4000,0000,0000 ; 5363 FDV4: [ARX]-[BRX], SKIP CRY0, 3T, J/FDV5 ;FLOATING NO DIV? U 1347, 1346,2445,0506,4174,4007,0700,4000,0000,0000 ; 5364 [BRX]_-[BR]*2, J/FDV4 ;FORCE ABSOLUTE VALUE ; 5365 =0 U 1350, 1352,3447,0606,4174,4007,0700,0000,0000,0000 ; 5366 FDV5: [BRX]_[BRX]*.5, J/FDV6 ;SHIFT BACK ARX U 1351, 0555,4443,0000,4174,4467,0700,0000,0071,1000 ; 5367 FL NO DIVIDE ;UNNORMALIZED INPUT ; 5368 =0 ; 5369 FDV6: [AR]_[AR]*2, ;DO NOT DROP A BIT U 1352, 3665,3445,0303,4174,4007,0700,0010,0000,0000 ; 5370 CALL [SBRL] ;AT FDV7+1 U 1353, 0144,2113,0604,4174,4007,0421,4000,0000,0000 ; 5371 [BRX]-[ARX], SKIP AD.LE.0 ;IS ANSWER .LE. 1? ; 5372 =00100 U 0144, 3043,4222,0000,4174,4007,0700,2010,0071,0033 ; 5373 FDV7: Q_0, SC_27., CALL [DIVSGN] ;DIVIDE U 0145, 0144,3447,0303,4174,4007,0700,1000,0041,0001 ; 5374 =00101 [AR]_[AR]*.5, FE_FE+1, J/FDV7 ;SCALE DV'END ; 5375 =01100 U 0154, 3204,3227,0003,4174,4007,0700,0000,0000,0000 ; 5376 FDV8: [AR]_Q*.5, J/FDV9 ;PUT ANSWER IN AR ; 5377 =01101 READ [AR], SKIP AD.EQ.0, ;-VE ANSWER, LOOK AT RMDR U 0155, 2054,3333,0003,4174,4007,0621,0010,0000,0000 ; 5378 CALL [SETSN] ; SEE HOW TO NEGATE ; 5379 =01110 READ [AR], SKIP AD.EQ.0, ;-VE ANSWER, LOOK AT RMDR U 0156, 2054,3333,0003,4174,4007,0621,0010,0000,0000 ; 5380 CALL [SETSN] ; SEE HOW TO NEGATE U 0157, 3204,3227,0003,4174,4007,0700,0000,0000,0000 ; 5381 =01111 [AR]_Q*.5, J/FDV9 ;PUT ANSWER IN AR U 0177, 3204,2227,0003,4174,4007,0700,4000,0000,0000 ; 5382 =11111 [AR]_-Q*.5, J/FDV9 ;ZERO RMDR ; 5383 U 3204, 1363,4222,0000,4174,4007,0700,0000,0000,0000 ; 5384 FDV9: Q_0, J/SNORM0 ;GO NORMALIZE ; 5385 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 145 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- FLTR, FSC ; 5386 .TOC "FLOATING POINT -- FLTR, FSC" ; 5387 ; 5388 .DCODE D 0127, 0011,1616,1100 ; 5389 127: R, FL-AC,ROUND, J/FLTR D 0132, 0001,1621,2100 ; 5390 132: I, FL-AC, J/FSC ; 5391 .UCODE ; 5392 ; 5393 1616: U 1616, 1354,4553,0300,4374,4007,0321,0000,0077,7000 ; 5394 FLTR: [AR].AND.#, #/777000, 3T, SKIP ADL.EQ.0 ;SMALL POS NUMBER? U 1354, 1356,2441,0305,4174,4007,0521,4000,0000,0000 ; 5395 =0 [BR]_-[AR], SKIP DP0, 3T, J/FLTR1 ;NO--SEE IF MINUS U 1355, 1363,4222,0000,4174,4007,0700,1000,0071,0233 ; 5396 Q_0, FE_S#, S#/233, J/SNORM0 ;FITS IN 27 BITS ; 5397 =0 ; 5398 FLTR1: [BR].AND.#, #/777000, 3T, U 1356, 1360,4553,0500,4374,4007,0321,0000,0077,7000 ; 5399 SKIP ADL.EQ.0, J/FLTR1A ;SMALL NEGATIVE NUMBER U 1357, 3205,4222,0000,4174,4007,0700,1000,0071,0244 ; 5400 Q_0, FE_S#, S#/244, J/FLTR2 ;LARGE POS NUMBER ; 5401 =0 U 1360, 3205,4222,0000,4174,4007,0700,1000,0071,0244 ; 5402 FLTR1A: Q_0, FE_S#, S#/244, J/FLTR2 ;BIG NUMBER U 1361, 1363,4222,0000,4174,4007,0700,1000,0071,0233 ; 5403 Q_0, FE_S#, S#/233, J/SNORM0 ;FITS IN 27 BITS ; 5404 ;AT THIS POINT WE KNOW THE NUMBER TAKES MORE THAN 27 BITS. WE JUST ; 5405 ; SHIFT 8 PLACES RIGHT AND NORMALIZE. WE COULD BE MORE CLEVER BUT ; 5406 ; THIS IS THE RARE CASE ANYWAY. U 3205, 1362,3446,0303,4174,4047,0700,2000,0071,0006 ; 5407 FLTR2: [AR]_[AR]*.5 LONG, ASHC, SC_6 ;SHOVE OVER TO THE RIGHT ; 5408 =0 ; 5409 FLTR3: [AR]_[AR]*.5 LONG, ASHC, ;SHIFT RIGHT 9 PLACES U 1362, 1362,3446,0303,4174,4047,0630,2000,0060,0000 ; 5410 STEP SC, J/FLTR3 ; SO IT WILL FIT U 1363, 0420,3333,0003,4174,4003,4701,0000,0000,0000 ; 5411 SNORM0: READ [AR], NORM DISP, J/SNORM ;NORMALIZE ANSWER ; 5412 ; 5413 ; 5414 1621: U 1621, 3206,3333,0003,4174,4007,0700,2000,0041,4000 ; 5415 FSC: READ [AR], SC_SHIFT U 3206, 3207,4222,0000,0174,4007,0700,0000,0000,0000 ; 5416 Q_0, AC ;DON'T SHIFT IN JUNK U 3207, 1364,3771,0003,0276,6007,0520,1000,0040,2000 ; 5417 [AR]_AC, FE_SC+EXP, SKIP DP0 ;SIGN SMEAR U 1364, 1363,4551,0303,4374,0007,0700,0000,0000,0777 ; 5418 =0 [AR]_+SIGN, J/SNORM0 U 1365, 1363,3551,0303,4374,0007,0700,0000,0077,7000 ; 5419 [AR]_-SIGN, J/SNORM0 ; 5420 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 146 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- FIX AND FIXR ; 5421 .TOC "FLOATING POINT -- FIX AND FIXR" ; 5422 ; 5423 .DCODE D 0122, 0701,1626,1100 ; 5424 122: FL-R, FL-AC, J/FIX D 0126, 0711,1626,1100 ; 5425 126: FL-R, FL-AC,ROUND, J/FIX ; 5426 .UCODE ; 5427 ; 5428 1626: ; 5429 FIX: Q_0, SCAD/A+B, SCADA/S#, ;CLEAR Q, SEE IF ; 5430 S#/1534, SCADB/FE, 3T, ; ANSWER FITS IN U 1626, 0674,4222,0000,4174,4006,7701,0000,0041,1534 ; 5431 SCAD DISP ; 35 BITS. U 0674, 0555,4443,0000,4174,4467,0700,0000,0041,1000 ; 5432 =0* SET AROV, J/NIDISP ;TOO BIG U 0676, 0720,4443,0000,4174,4006,7701,2000,0041,1544 ; 5433 SC_FE+S#, S#/1544, 3T, SCAD DISP ;NEED TO MOVE LEFT? U 0720, 1370,4443,0000,4174,4007,0630,2000,0060,0000 ; 5434 =0* STEP SC, J/FIXL U 0722, 3210,4443,0000,4174,4007,0700,2000,0031,0232 ; 5435 SC_S#-FE, S#/232 ;NUMBER OF PLACES TO SHIFT ; 5436 ; RIGHT U 3210, 1366,4443,0000,4174,4007,0630,2000,0060,0000 ; 5437 STEP SC ;ALREADY THERE ; 5438 =0 ; 5439 FIXR: [AR]_[AR]*.5 LONG, ASHC, ;SHIFT BINARY POINT U 1366, 1366,3446,0303,4174,4047,0630,2000,0060,0000 ; 5440 STEP SC, J/FIXR ; TO BIT 35.5 U 1367, 0063,3447,0705,4174,4003,7700,0000,0000,0000 ; 5441 [BR]_[ONE]*.5, B DISP, J/FIXX ;WHICH KIND OF FIX? ; 5442 ; 5443 =0 U 1370, 1370,3445,0303,4174,4007,0630,2000,0060,0000 ; 5444 FIXL: [AR]_[AR]*2, STEP SC, J/FIXL ;SHIFT LEFT U 1371, 0100,3440,0303,0174,4156,4700,0400,0000,0000 ; 5445 AC_[AR], NEXT INST ;WE ARE NOW DONE ; 5446 ; 5447 =0*11 U 0063, 1372,3333,0003,4174,4007,0520,0000,0000,0000 ; 5448 FIXX: READ [AR], SKIP DP0, J/FIXT ;FIX--SEE IF MINUS U 0073, 1514,0111,0503,4174,4003,7700,0200,0003,0001 ; 5449 FIXX1: [AR]_[AR]+[BR], FL-EXIT ;FIXR--ROUND UP ; 5450 =0 U 1372, 0100,3440,0303,0174,4156,4700,0400,0000,0000 ; 5451 FIXT: AC_[AR], NEXT INST ;FIX & +, TRUNCATE U 1373, 1374,3223,0000,4174,4007,0621,0000,0000,0000 ; 5452 READ Q, SKIP AD.EQ.0 ;NEGATIVE--ANY FRACTION? U 1374, 1514,0111,0703,4174,4003,7700,0200,0003,0001 ; 5453 =0 [AR]_[AR]+1, FL-EXIT ;YES--ROUND UP ; 5454 [BR]_.NOT.[MASK], ;MAYBE--GENERATE .75 U 1375, 0073,7441,1205,4174,4007,0700,0000,0000,0000 ; 5455 J/FIXX1 ;ROUND UP IF BIT 36 OR ; 5456 ; 37 SET ; 5457 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 147 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- SINGLE PRECISION NORMALIZE ; 5458 .TOC "FLOATING POINT -- SINGLE PRECISION NORMALIZE" ; 5459 ; 5460 ;NORMALIZE DISPATCH IS A 9-WAY DISPATCH. THE HARDWARE LOOKS AT ; 5461 ; 4 SIGNALS: DP=0, DP BIT 8, DP BIT 9, DP BIT -2. THE 9 CASES ; 5462 ; ARE: ; 5463 ; 5464 ; DP=0 DP08 DP09 DP00 ACTION TO TAKE ; 5465 ; 0 0 0 0 SHIFT LEFT ; 5466 ; ; 5467 ; 0 0 0 1 NEGATE AND RETRY ; 5468 ; ; 5469 ; 0 0 1 0 ALL DONE ; 5470 ; ; 5471 ; 0 0 1 1 NEGATE AND RETRY ; 5472 ; ; 5473 ; 0 1 0 0 SHIFT RIGHT ; 5474 ; ; 5475 ; 0 1 0 1 NEGATE AND RETRY ; 5476 ; ; 5477 ; 0 1 1 0 SHIFT RIGHT ; 5478 ; ; 5479 ; 0 1 1 1 NEGATE AND RETRY ; 5480 ; ; 5481 ; 1 - - - LOOK AT Q BITS ; 5482 ; 5483 ;ENTER HERE WITH UNNORMALIZED NUMBER IN AR!Q. FE HOLDS THE NEW ; 5484 ; EXPONENT. CALL WITH NORM DISP ; 5485 =0000 ;9-WAY DISPATCH U 0420, 0420,3444,0303,4174,4063,4701,1000,0041,1777 ; 5486 SNORM: [AR]_[AR]*2 LONG, DIV, FE_FE-1, NORM DISP, J/SNORM U 0421, 2000,2222,0000,4174,4007,0311,4000,0000,0000 ; 5487 Q_-Q, SKIP CRY0, 3T, J/SNNEG U 0422, 0262,3333,0003,4174,4003,4701,0010,0000,0000 ; 5488 READ [AR], NORM DISP, CALL [SROUND] U 0423, 2000,2222,0000,4174,4007,0311,4000,0000,0000 ; 5489 Q_-Q, SKIP CRY0, 3T, J/SNNEG U 0424, 0262,3447,0303,4174,4007,0700,1010,0041,0001 ; 5490 [AR]_[AR]*.5, FE_FE+1, CALL [SROUND] U 0425, 2000,2222,0000,4174,4007,0311,4000,0000,0000 ; 5491 Q_-Q, SKIP CRY0, 3T, J/SNNEG U 0426, 0262,3447,0303,4174,4007,0700,1010,0041,0001 ; 5492 [AR]_[AR]*.5, FE_FE+1, CALL [SROUND] U 0427, 2000,2222,0000,4174,4007,0311,4000,0000,0000 ; 5493 Q_-Q, SKIP CRY0, 3T, J/SNNEG U 0430, 1376,3223,0000,4174,4007,0621,0000,0000,0000 ; 5494 READ Q, SKIP AD.EQ.0, J/SNORM1 U 0436, 1377,3770,0303,4324,0457,0700,0000,0041,0000 ; 5495 =1110 [AR]_EXP, J/FLEX ; 5496 = ; 5497 =0 U 1376, 0420,3444,0303,4174,4063,4701,1000,0041,1777 ; 5498 SNORM1: [AR]_[AR]*2 LONG, DIV, FE_FE-1, NORM DISP, J/SNORM U 1377, 1514,4443,0000,4174,4003,7700,0200,0003,0001 ; 5499 FLEX: FL-EXIT ; 5500 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 148 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- SINGLE PRECISION NORMALIZE ; 5501 =0 U 2000, 0440,7441,0303,4174,4003,4701,0000,0000,0000 ; 5502 SNNEG: [AR]_.NOT.[AR], NORM DISP, J/SNNORM ;NEGATE HIGH WORD ; 5503 ; (NO CARRY) U 2001, 0440,2441,0303,4174,4003,4701,4000,0000,0000 ; 5504 [AR]_-[AR], NORM DISP, J/SNNORM ;NEGATE HIGH WORD (W/CARRY) ; 5505 =0000 U 0440, 0440,3444,0303,4174,4063,4701,1000,0041,1777 ; 5506 SNNORM: [AR]_[AR]*2 LONG, DIV, FE_FE-1, NORM DISP, J/SNNORM U 0442, 0262,3333,0003,4174,4003,4701,0010,0000,0000 ; 5507 =0010 READ [AR], NORM DISP, CALL [SROUND] U 0444, 0262,3447,0303,4174,4007,0700,1010,0041,0001 ; 5508 =0100 [AR]_[AR]*.5, FE_FE+1, CALL [SROUND] U 0446, 0262,3447,0303,4174,4007,0700,1010,0041,0001 ; 5509 =0110 [AR]_[AR]*.5, FE_FE+1, CALL [SROUND] U 0450, 0440,3444,0303,4174,4063,4701,1000,0041,1777 ; 5510 =1000 [AR]_[AR]*2 LONG, DIV, FE_FE-1, NORM DISP, J/SNNORM U 0456, 0327,3770,0303,4324,0453,7700,0000,0041,0000 ; 5511 =1110 [AR]_EXP, B DISP ; 5512 = U 0327, 2002,4553,1300,4374,4007,0321,0000,0000,2000 ; 5513 =0111 TL [FLG], FLG.SN/1, J/SNNOT ; 5514 [AR]_[AR].AND.[MASK], ;CLEAR ANY LEFT OVER BITS U 0337, 2005,4111,1203,4174,4007,0700,0000,0000,0000 ; 5515 J/SNNOT1 ; 5516 =0 U 2002, 3211,7441,0303,4174,4007,0700,0000,0000,0000 ; 5517 SNNOT: [AR]_.NOT.[AR], J/SNNOT2 U 2003, 2004,3223,0000,4174,4007,0621,0000,0000,0000 ; 5518 READ Q, SKIP AD.EQ.0 U 2004, 3211,7441,0303,4174,4007,0700,0000,0000,0000 ; 5519 =0 [AR]_.NOT.[AR], J/SNNOT2 U 2005, 3211,2441,0303,4174,4007,0700,4000,0000,0000 ; 5520 SNNOT1: [AR]_-[AR], J/SNNOT2 ;NORMAL NEGATE AND EXIT U 3211, 1514,4221,0013,4174,4003,7700,0200,0003,0001 ; 5521 SNNOT2: [FLG]_0, FL-EXIT ; 5522 ; 5523 ; 5524 ; 5525 .TOC "FLOATING POINT -- ROUND ANSWER" ; 5526 ; 5527 =*01* U 0262, 0407,3447,0705,4174,4003,7700,0000,0000,0000 ; 5528 SROUND: [BR]_[ONE]*.5, B DISP, J/SRND1 U 0266, 0262,3447,0303,4174,4007,0700,1000,0041,0001 ; 5529 [AR]_[AR]*.5, FE_FE+1, J/SROUND ;WE WENT TOO FAR ; 5530 =0111 U 0407, 0016,4443,0000,4174,4004,1700,0000,0000,0000 ; 5531 SRND1: RETURN [16] ;NOT ROUNDING INSTRUCTION U 0417, 0302,0111,0503,4174,4003,4701,0000,0000,0000 ; 5532 [AR]_[AR]+[BR], NORM DISP U 0302, 0016,4443,0000,4174,4004,1700,0000,0000,0000 ; 5533 =*01* RETURN [16] U 0306, 0016,3447,0303,4174,4004,1700,1000,0041,0001 ; 5534 [AR]_[AR]*.5, FE_FE+1, RETURN [16] ; 5535 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 149 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- DFAD, DFSB ; 5536 .TOC "FLOATING POINT -- DFAD, DFSB" ; 5537 ; 5538 .DCODE D 0110, 1100,1637,1100 ; 5539 110: DBL FL-R, J/DFAD D 0111, 1100,1635,1100 ; 5540 111: DBL FL-R, J/DFSB ; 5541 .UCODE ; 5542 ; 5543 ;ENTER FROM A-READ CODE WITH: ; 5544 ;FE/ EXP ; 5545 ;SC/ EXP ; 5546 ;AR/ C(E) SHIFT RIGHT 2 PLACES ; 5547 ;ARX/ C(E+1) SHIFTED RIGHT 1 PLACE ; 5548 1635: U 1635, 3212,2441,0404,4174,4007,0700,4000,0000,0000 ; 5549 DFSB: [ARX]_-[ARX] ;NEGATE LOW WORD U 3212, 1637,2441,0303,4174,4007,0700,0040,0000,0000 ; 5550 [AR]_-[AR]-.25, MULTI PREC/1 ; 5551 1637: U 1637, 3213,4557,0006,1274,4007,0701,0000,0000,1441 ; 5552 DFAD: [BRX]_(AC[1].AND.[MAG])*.5, 3T ;GET LOW WORD ; 5553 [BR]_AC*.5, 3T, ;GET AC AND START TO SHIFT ; 5554 SC_SC-EXP-1, ;NUMBER OF PLACES TO SHIFT U 3213, 2006,3777,0005,0274,4007,0521,2000,0020,2000 ; 5555 SKIP DP0 ;SEE WHAT SIGN ; 5556 =0 [BR]_+SIGN*.5, 3T, ;SIGN SMEAR U 2006, 2010,5547,0505,0374,4007,0631,0000,0077,7400 ; 5557 AC, SKIP/SC, J/DFAS1 ;SEE WHICH IS BIGGER ; 5558 [BR]_-SIGN*.5, 3T, ;SIGN SMEAR U 2007, 2010,3547,0505,0374,4007,0631,0000,0077,7400 ; 5559 AC, SKIP/SC, J/DFAS1 ;SEE WHICH IS BIGGER ; 5560 =0 ; 5561 DFAS1: Q_[BRX], ;AR IS BIGGER U 2010, 2012,3442,0600,4174,4007,0700,0000,0000,0000 ; 5562 J/DFAS2 ;ADJUST BR!Q ; 5563 [T0]_AC, ;BR IS BIGGER OR EQUAL U 2011, 3215,3771,0016,0276,6007,0700,2000,0041,2000 ; 5564 SC_EXP, 2T, J/DFAS3 ;SET SC TO THAT EXPONENT ; 5565 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 150 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- DFAD, DFSB ; 5566 ;HERE IF AR!ARX IS GREATER THAN BR!BRX ; 5567 =0 U 2012, 0153,3441,0516,4174,4007,0700,0010,0000,0000 ; 5568 DFAS2: [T0]_[BR], CALL [DFADJ] ;ADJUST BR!Q U 2013, 3214,3441,1605,4174,4007,0700,0000,0000,0000 ; 5569 [BR]_[T0] ;PUT ANSWER BACK U 3214, 3220,0002,0400,4174,4007,0700,0000,0000,0000 ; 5570 Q_Q+[ARX], J/DFAS5 ;ADD LOW WORDS ; 5571 ; 5572 ;HERE IS BR!BRX IF GREATER THAN OR EQUAL TO AR!ARX ; 5573 DFAS3: Q_[ARX], ;SETUP TO SHIFT AR!ARX U 3215, 3216,3442,0400,4174,4007,0700,2000,0020,0000 ; 5574 SC_SC-FE-1 ;COMPUTE # OF PLACES U 3216, 2014,3333,0016,4174,4007,0700,1000,0041,2000 ; 5575 READ [T0], FE_EXP ;EXPONENT OF ANSWER U 2014, 0153,3441,0316,4174,4007,0700,0010,0000,0000 ; 5576 =0 [T0]_[AR], CALL [DFADJ] ;ADJUST AR!Q U 2015, 3217,3441,1603,4174,4007,0700,0000,0000,0000 ; 5577 [AR]_[T0] ;PUT ANSWER BACK U 3217, 3220,0002,0600,4174,4007,0700,0000,0000,0000 ; 5578 Q_Q+[BRX], J/DFAS5 ;ADD LOW WORDS ; 5579 ; 5580 ;BIT DIDDLE TO GET THE ANSWER (INCLUDING 2 GUARD BITS) INTO ; 5581 ; AR!Q ; 5582 DFAS5: [AR]_([AR]+[BR])*.5 LONG, ;ADD HIGH WORDS U 3220, 3221,0116,0503,4174,4047,0700,0040,0000,0000 ; 5583 MULTI PREC/1, ASHC ;INJECT SAVED CRY2 ; 5584 [AR]_[AR]*2 LONG, ;SHIFT BACK LEFT U 3221, 0433,3444,0303,4174,4046,2700,0000,0000,0000 ; 5585 ASHC, MUL DISP ;SEE IF WE LOST A 1 ; 5586 =1011 U 0433, 3222,5111,1217,4174,4007,0700,0000,0000,0000 ; 5587 DFAS6: [T1]_[T1].AND.NOT.[MASK], J/DFAS7 U 0437, 0433,0222,0000,4174,4007,0700,4000,0000,0000 ; 5588 Q_Q+.25, J/DFAS6 ; 5589 DFAS7: [AR]_[AR]*2 LONG, ASHC, ;PUT IN GUARD BITS U 3222, 3223,3444,0303,4174,4047,0700,1000,0041,1777 ; 5590 FE_FE-1 ; 5591 [AR]_[AR]*2 LONG, ASHC, U 3223, 3224,3444,0303,4174,4047,0700,1000,0041,1777 ; 5592 FE_FE-1 U 3224, 2027,3002,1700,4170,4007,0700,0000,0000,0000 ; 5593 Q_[T1].OR.Q, HOLD LEFT, J/DNORM0 ; 5594 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 151 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- DFAD, DFSB ; 5595 ;SUBROUTINE TO ADJUST NUMBER IN T0!Q ; 5596 ;RETURNS 1 WITH ; 5597 ; T0!Q ADJUSTED ; 5598 ; FLG.SN=1 IF WE SHIFTED OUT ANY 1 BITS (STICKY BIT) ; 5599 ; T1 HAS Q TWO STEPS PRIOR TO BEING DONE ; 5600 DFADJ "STEP SC, ASHC, MUL DISP" ; 5601 ; 5602 =0**11 ; 5603 DFADJ: [T0]_[T0]*2 LONG, DIV, ;MOVE EVERYTHING 2 PLACES U 0153, 2055,3444,1616,4174,4067,0700,0010,0000,0000 ; 5604 CALL [CLRSN] U 0173, 3225,3444,1616,4174,4067,0700,0000,0000,0000 ; 5605 [T0]_[T0]*2 LONG, DIV U 3225, 3226,3444,1616,4174,4067,0700,0000,0000,0000 ; 5606 [T0]_[T0]*2 LONG, DIV ; 5607 [T0]_[T0]*.5 LONG, ASHC, ;SHIFT AT LEAST 1 PLACE U 3226, 0472,3446,1616,4174,4047,0630,2000,0060,0000 ; 5608 STEP SC ; 5609 =1010 ; 5610 DFADJ1: [T0]_[T0]*.5 LONG, ;UNNORMALIZE T0!Q U 0472, 0472,3446,1616,4174,4046,2630,2000,0060,0000 ; 5611 DFADJ, J/DFADJ1 ;LOOP TILL DONE ; 5612 DFADJ2: [T1]_Q, ;SAVE GUARD BITS U 0473, 0453,3221,0017,4174,4006,2700,0000,0000,0000 ; 5613 MUL DISP, J/DFADJ5 ;LOOK AT LAST BIT U 0476, 2016,3551,1313,4374,0007,0700,0000,0000,2000 ; 5614 [FLG]_[FLG].OR.#, FLG.SN/1, HOLD RIGHT, J/DFADJ3 U 0477, 2017,3551,1313,4374,0007,0700,0000,0000,2000 ; 5615 [FLG]_[FLG].OR.#, FLG.SN/1, HOLD RIGHT, J/DFADJ4 ; 5616 ; 5617 =0 U 2016, 2016,3446,1616,4174,4047,0630,2000,0060,0000 ; 5618 DFADJ3: [T0]_[T0]*.5 LONG, ASHC, STEP SC, J/DFADJ3 U 2017, 0453,3221,0017,4174,4007,0700,0000,0000,0000 ; 5619 DFADJ4: [T1]_Q ;SAVE 2 GUARD BITS ; 5620 =1011 U 0453, 3227,3446,1616,4174,4047,0700,0000,0000,0000 ; 5621 DFADJ5: [T0]_[T0]*.5 LONG, ASHC, J/DFADJ6 U 0457, 0453,3551,1313,4374,0007,0700,0000,0000,2000 ; 5622 [FLG]_[FLG].OR.#, FLG.SN/1, HOLD RIGHT, J/DFADJ5 U 3227, 0001,3446,1616,4174,4044,1700,0000,0000,0000 ; 5623 DFADJ6: [T0]_[T0]*.5 LONG, ASHC, RETURN [1] ; 5624 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 152 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- DFMP ; 5625 .TOC "FLOATING POINT -- DFMP" ; 5626 ; 5627 .DCODE D 0112, 1105,1631,1100 ; 5628 112: DBL FL-R, DAC, J/DFMP ; 5629 .UCODE ; 5630 ; 5631 ;SAME ENTRY CONDITIONS AS DFAD/DFSB ; 5632 1631: U 1631, 2020,3442,0400,4174,4007,0700,2000,0071,0006 ; 5633 DFMP: Q_[ARX], SC_6 ;SHIFT MEM OP 8 PLACES ; 5634 =0 ; 5635 DFMP1: [AR]_[AR]*2 LONG, ASHC, ;SHIFT U 2020, 2020,3444,0303,4174,4047,0630,2000,0060,0000 ; 5636 STEP SC, J/DFMP1 U 2021, 3230,3446,1200,4174,4007,0700,0000,0000,0000 ; 5637 Q_Q*.5 U 3230, 3231,4662,0000,4374,0007,0700,0000,0007,7777 ; 5638 Q_Q.AND.#, #/077777, HOLD RIGHT U 3231, 3232,3221,0005,4174,4007,0700,0000,0000,0000 ; 5639 [BR]_Q ;COPY LOW WORD ; 5640 ; ; 5641 ; BRX * BR ==> C(E+1) * C(AC+1) ; 5642 ; U 3232, 0623,4557,0006,1274,4007,0700,0000,0000,1441 ; 5643 [BRX]_(AC[1].AND.[MAG])*.5 ;GET LOW AC U 0623, 3001,3447,0606,4174,4007,0700,2010,0071,0043 ; 5644 =0** [BRX]_[BRX]*.5, SC_35., CALL [MULSB1] ; 5645 ; ; 5646 ; BRX * Q ==> C(E) * C(AC+1) ; 5647 ; U 0627, 0730,3442,0300,4174,4007,0700,2000,0071,0043 ; 5648 Q_[AR], SC_35. ;GO MULT NEXT HUNK U 0730, 3002,4443,0000,4174,4007,0700,0010,0000,0000 ; 5649 =0** CALL [MULTIPLY] U 0734, 3233,3441,0416,4174,4007,0700,0000,0000,0000 ; 5650 [T0]_[ARX] ;SAVE PRODUCT U 3233, 3234,3227,0004,4174,4007,0700,2000,0011,0000 ; 5651 [ARX]_Q*.5, SC_FE ;PUT IN NEXT STEP ; 5652 ; ; 5653 ; BRX * BR ==> C(AC) * C(E+1) ; 5654 ; ; 5655 [BRX]_AC*.5, ;PREPARE TO DO HIGH HALF ; 5656 FE_SC+EXP, ;EXPONENT ON ANSWER U 3234, 2022,3777,0006,0274,4007,0521,1000,0040,2000 ; 5657 SKIP DP0, 3T U 2022, 0732,5547,0606,4374,4007,0701,0000,0077,7400 ; 5658 =0 [BRX]_+SIGN*.5, 3T, J/DFMP2 U 2023, 0732,3547,0606,4374,4007,0701,0000,0077,7400 ; 5659 [BRX]_-SIGN*.5, 3T ; 5660 =0** U 0732, 3002,3442,0500,4174,4007,0700,2010,0071,0043 ; 5661 DFMP2: Q_[BR], SC_35., CALL [MULTIPLY] ;GO MULTIPLY U 0736, 3235,3221,0017,4174,4007,0700,0000,0000,0000 ; 5662 [T1]_Q ;SAVE FOR ROUNDING U 3235, 1012,0111,1604,4174,4007,0700,0000,0000,0000 ; 5663 [ARX]_[ARX]+[T0] ;PREPARE FOR LAST MUL ; 5664 ; ; 5665 ; BRX * Q ==> C(AC) * C(E) ; 5666 ; ; 5667 =0** Q_[AR], SC_35., ;DO THE LAST MULTIPLY U 1012, 3002,3442,0300,4174,4007,0700,2010,0071,0043 ; 5668 CALL [MULTIPLY] ; .. ; 5669 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 153 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- DFMP ; 5670 ;OK, WE NOW HAVE THE PRODUCT IN ARX!Q!T1. ALL WE NEED TO DO ; 5671 ; IS SOME BIT DIDDLES TO GET EVERYTHING IN THE RIGHT PLACE ; 5672 [AR]_[ARX]*.5 LONG, ;SHIFT THE ANSWER U 1016, 0243,3446,0403,4174,4007,0700,1000,0041,1576 ; 5673 FE_FE+S#, S#/1576 ;CORRECT EXPONENT ; 5674 =0**11 READ [T1], SKIP AD.EQ.0, ;SEE IF LOW ORDER 1 U 0243, 2054,3333,0017,4174,4007,0621,0010,0000,0000 ; 5675 CALL [SETSN] ; BITS AROUND SOMEPLACE U 0263, 3236,3444,0303,4174,4047,0700,0000,0000,0000 ; 5676 [AR]_[AR]*2 LONG, ASHC ;SHIFT LEFT U 3236, 3237,3447,0705,4174,4007,0700,0000,0000,0000 ; 5677 [BR]_[ONE]*.5 ;PLACE TO INSTERT BITS U 3237, 2024,4553,1700,4374,4007,0321,0000,0020,0000 ; 5678 TL [T1], #/200000 ;ANYTHING TO INJECT? U 2024, 2025,0002,0500,4174,4007,0700,0000,0000,0000 ; 5679 =0 Q_Q+[BR] ;YES--PUT IT IN U 2025, 3240,3444,0303,4174,4047,0700,0000,0000,0000 ; 5680 [AR]_[AR]*2 LONG, ASHC ;MAKE ROOM FOR MORE U 3240, 2026,4553,1700,4374,4007,0321,0000,0010,0000 ; 5681 TL [T1], #/100000 ;ANOTHER BIT NEEDED U 2026, 2027,0002,0500,4174,4007,0700,0000,0000,0000 ; 5682 =0 Q_Q+[BR] ;YES--PUT IN LAST BIT ; 5683 DNORM0: READ [AR], NORM DISP, ;SEE WHAT WE NEED TO DO U 2027, 0520,3333,0003,4174,4003,4701,1000,0041,0002 ; 5684 FE_FE+S#, S#/2, J/DNORM ;ADJUST FOR INITIAL SHIFTS ; 5685 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 154 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- DFDV ; 5686 .TOC "FLOATING POINT -- DFDV" ; 5687 ; 5688 .DCODE D 0113, 1105,1636,1100 ; 5689 113: DBL FL-R, DAC, J/DFDV ; 5690 .UCODE ; 5691 1636: U 1636, 0132,3441,0406,4174,4007,0700,0000,0000,0000 ; 5692 DFDV: [BRX]_[ARX] ;COPY OPERAND (COULD SAVE TIME ; 5693 ; WITH SEPERATE A-READ FOR DFDV) U 0132, 2055,4221,0017,4174,4007,0700,0010,0000,0000 ; 5694 =1**10 [T1]_0, CALL [CLRSN] ;CLEAR FLAG ; 5695 [BR]_[AR], SKIP AD.LE.0, ;SEE IF POSITIVE U 0133, 2030,3441,0305,1174,4007,0421,0000,0000,1441 ; 5696 AC[1] ;WARM UP RAM ; 5697 =0 ; 5698 DFDV1: [ARX]_(AC[1].AND.[MAG])*.5, ;POSITIVE--GET AC U 2030, 3243,4557,0004,1274,4007,0700,0000,0000,1441 ; 5699 J/DFDV2 ; AND CONTINUE BELOW U 2031, 3241,7441,1717,4174,4007,0700,0000,0000,0000 ; 5700 [T1]_.NOT.[T1] ;DV'SOR NEGATIVE (OR ZERO) U 3241, 3242,2441,0606,4174,4007,0700,4000,0000,0000 ; 5701 [BRX]_-[BRX] ;NEGATE LOW WORD ; 5702 AD/-B-.25, B/BR, DEST/AD, ;NEGATE HIGH WORD ; 5703 MULTI PREC/1, 3T, ;ADDING IN CRY02 ; 5704 SKIP DP0, AC[1], ;SEE IF STILL NEGATIVE U 3242, 2030,2331,0005,1174,4007,0521,0040,0000,1441 ; 5705 J/DFDV1 ; .. ; 5706 DFDV2: [AR]_AC*.5, ;GET AC AND SHIFT ; 5707 FE_SC-EXP, 3T, ;COMPUTE NEW EXPONENT U 3243, 2032,3777,0003,0274,4007,0521,1000,0030,2000 ; 5708 SKIP DP0 ;SEE IF NEGATIVE U 2032, 2034,5547,0303,4374,4007,0701,0000,0077,7400 ; 5709 =0 [AR]_+SIGN*.5, 3T, J/DFDV3 ;POSITIVE U 2033, 3244,7441,1717,4174,4007,0700,0000,0000,0000 ; 5710 [T1]_.NOT.[T1] ;NEGATIVE OR ZERO U 3244, 3245,3547,0303,4374,4007,0701,0000,0077,7400 ; 5711 [AR]_-SIGN*.5, 3T ;SIGN SMEAR U 3245, 3246,2442,0400,4174,4007,0700,4000,0000,0000 ; 5712 Q_-[ARX] ;NEGATE OPERAND ; 5713 [AR]_(-[AR]-.25)*.5 LONG, ;NEGATE HIGH WORD ; 5714 MULTI PREC/1, ;USE SAVED CARRY U 3246, 2035,2446,0303,4174,4047,0700,0040,0000,0000 ; 5715 ASHC, J/DFDV4 ;CONTINUE BELOW ; 5716 =0 ; 5717 DFDV3: Q_[ARX], ;COPY OPERAND U 2034, 3042,3442,0400,4174,4007,0700,0010,0000,0000 ; 5718 CALL [DDIVS] ;SHIFT OVER U 2035, 2036,2113,0305,4174,4007,0521,4000,0000,0000 ; 5719 DFDV4: [AR]-[BR], 3T, SKIP DP0 ;SEE IF OVERFLOW U 2036, 0555,4443,0000,4174,4467,0700,0000,0071,1000 ; 5720 =0 FL NO DIVIDE U 2037, 0724,3221,0004,4174,4007,0700,0000,0000,0000 ; 5721 [ARX]_Q ;START DIVISION U 0724, 1264,4222,0000,4174,4007,0700,2010,0071,0032 ; 5722 =0* Q_0, SC_26., CALL [DBLDIV] U 0726, 1054,3221,0016,4174,4007,0700,2000,0071,0043 ; 5723 [T0]_Q, SC_35. ; 5724 =0* Q_Q.AND.NOT.[MAG], ;SEE IF ODD ; 5725 SKIP AD.EQ.0, ;SKIP IF EVEN U 1054, 1264,5002,0000,4174,4007,0621,0010,0000,0000 ; 5726 CALL [DBLDIV] ;GO DIVIDE U 1056, 3247,3446,1200,4174,4007,0700,0000,0000,0000 ; 5727 Q_Q*.5 ;MOVE ANSWER OVER ; 5728 = ; 5729 [T0]_[T0]*2 LONG, ASHC, ;DO FIRST NORM STEP U 3247, 0513,3444,1616,4174,4046,2700,0000,0000,0000 ; 5730 MUL DISP ; SEE IF A 1 FELL OUT ; 5731 =1011 ; 5732 DFDV4A: READ [T1], SKIP DP0, ;SHOULD RESULT BE NEGATIVE ; 5733 FE_S#-FE, S#/202, ;CORRECT EXPONENT U 0513, 2040,3333,0017,4174,4007,0520,1000,0031,0202 ; 5734 J/DFDV4B ;LOOK BELOW U 0517, 0513,0222,0000,4174,4007,0700,4000,0000,0000 ; 5735 Q_Q+.25, J/DFDV4A ;PUT BACK THE BIT ; 5736 =0 U 2040, 0520,3441,1603,4174,4003,4701,0000,0000,0000 ; 5737 DFDV4B: [AR]_[T0], NORM DISP, J/DNORM ;PLUS U 2041, 0200,3441,1603,4174,4003,4701,0000,0000,0000 ; 5738 [AR]_[T0], NORM DISP, J/DNNORM ;MINUS ; 5739 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 155 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- DOUBLE PRECISION NORMALIZE ; 5740 .TOC "FLOATING POINT -- DOUBLE PRECISION NORMALIZE" ; 5741 ; 5742 ;NORMALIZE AR!Q ; 5743 ;DNORM0: READ [AR], NORM DISP, ;SEE WHAT WE NEED TO DO ; 5744 ; FE_FE+S#, S#/2, J/DNORM ;ADJUST FOR INITIAL SHIFTS ; 5745 =0000 ; 5746 DNORM: [AR]_[AR]*2 LONG, ;SHIFT LEFT ; 5747 FE_FE-1, ASHC, ;ADJUST EXPONENT U 0520, 0520,3444,0303,4174,4043,4701,1000,0041,1777 ; 5748 NORM DISP, J/DNORM ;TRY AGAIN U 0521, 2044,4553,1300,4374,4007,0321,0000,0000,2000 ; 5749 TL [FLG], FLG.SN/1, J/DNEG ;RESULT IS NEGATIVE ; 5750 READ [AR], NORM DISP, ;SEE IF WE WENT TOO FAR U 0522, 0322,3333,0003,4174,4003,4701,0010,0000,0000 ; 5751 CALL [DROUND] ; AND ROUND ANSWER U 0523, 2044,4553,1300,4374,4007,0321,0000,0000,2000 ; 5752 TL [FLG], FLG.SN/1, J/DNEG ;RESULT IS NEGATIVE ; 5753 [AR]_[AR]*.5 LONG, ASHC, U 0524, 0322,3446,0303,4174,4047,0700,1010,0041,0001 ; 5754 FE_FE+1, CALL [DROUND] U 0525, 2044,4553,1300,4374,4007,0321,0000,0000,2000 ; 5755 TL [FLG], FLG.SN/1, J/DNEG ;RESULT IS NEGATIVE ; 5756 [AR]_[AR]*.5 LONG, ASHC, U 0526, 0322,3446,0303,4174,4047,0700,1010,0041,0001 ; 5757 FE_FE+1, CALL [DROUND] U 0527, 2044,4553,1300,4374,4007,0321,0000,0000,2000 ; 5758 TL [FLG], FLG.SN/1, J/DNEG ;RESULT IS NEGATIVE ; 5759 Q_[MAG].AND.Q, ;HIGH WORD IS ZERO U 0530, 3251,4002,0000,4174,0007,0700,0000,0000,0000 ; 5760 HOLD RIGHT, J/DNORM1 ;GO TEST LOW WORD U 0536, 3250,4221,0013,4174,4007,0700,0000,0000,0000 ; 5761 =1110 [FLG]_0 ;[122] CLEAR FLAG WORD ; 5762 = ; 5763 AC[1]_[ARX].AND.[MAG], ;STORE LOW WORD U 3250, 1515,4113,0400,1174,4007,0700,0400,0000,1441 ; 5764 J/STAC ;GO DO HIGH WORD ; 5765 ; 5766 U 3251, 2042,3223,0000,4174,4007,0621,0000,0000,0000 ; 5767 DNORM1: READ Q, SKIP AD.EQ.0 ;TEST LOW WORD ; 5768 =0 [AR]_[AR]*2 LONG, ;LOW WORD IS NON-ZERO ; 5769 FE_FE-1, ASHC, ;ADJUST EXPONENT U 2042, 0520,3444,0303,4174,4043,4701,1000,0041,1777 ; 5770 NORM DISP, J/DNORM ;KEEP LOOKING U 2043, 1515,3440,0303,1174,4007,0700,0400,0000,1441 ; 5771 AC[1]_[AR], J/STAC ;WHOLE ANSWER IS ZERO ; 5772 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 156 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- DOUBLE PRECISION NORMALIZE ; 5773 ;HERE TO NORMALIZE NEGATIVE D.P. RESULTS ; 5774 =0 U 2044, 3252,7222,0000,4174,4007,0700,0000,0000,0000 ; 5775 DNEG: Q_.NOT.Q, J/DNEG1 ;ONES COMP U 2045, 2046,2222,0000,4174,4007,0511,4000,0000,0000 ; 5776 Q_-Q, SKIP CRY2, J/DNEG2 U 3252, 2046,4221,0013,4174,4007,0700,0000,0000,0000 ; 5777 DNEG1: [FLG]_0 ; 5778 =0 ; 5779 DNEG2: [AR]_.NOT.[AR], ;NO CARRY U 2046, 0200,7441,0303,4174,4003,4701,0000,0000,0000 ; 5780 NORM DISP, J/DNNORM ;GO NORMALIZE ; 5781 [AR]_-[AR], ;CARRY U 2047, 0200,2441,0303,4174,4003,4701,4000,0000,0000 ; 5782 NORM DISP, J/DNNORM ;NORMALIZE ; 5783 ; 5784 =000* ; 5785 DNNORM: [AR]_[AR]*2 LONG, ;SHIFT 1 PLACE ; 5786 FE_FE-1, ASHC, ;ADJUST EXPONENT U 0200, 0200,3444,0303,4174,4043,4701,1000,0041,1777 ; 5787 NORM DISP, J/DNNORM ;LOOP TILL DONE ; 5788 =001* READ [AR], NORM DISP, ;SEE IF WE WENT TOO FAR U 0202, 0322,3333,0003,4174,4003,4701,0010,0000,0000 ; 5789 CALL [DROUND] ; AND ROUND ANSWER ; 5790 =010* [AR]_[AR]*.5 LONG, ASHC, U 0204, 0322,3446,0303,4174,4047,0700,1010,0041,0001 ; 5791 FE_FE+1, CALL [DROUND] ; 5792 =011* [AR]_[AR]*.5 LONG, ASHC, U 0206, 0322,3446,0303,4174,4047,0700,1010,0041,0001 ; 5793 FE_FE+1, CALL [DROUND] ; 5794 =100* Q_[MAG].AND.Q, ;HIGH WORD IS ZERO U 0210, 3255,4002,0000,4174,0007,0700,0000,0000,0000 ; 5795 HOLD RIGHT, J/DNNRM1 ;GO TEST LOW WORD U 0216, 0610,4111,1204,4174,4007,0700,0000,0000,0000 ; 5796 =111* [ARX]_[ARX].AND.[MASK] ;REMOVE ROUNDING BIT ; 5797 = ; 5798 =00 [ARX]_[ARX].AND.[MAG], ;ALSO CLEAR SIGN U 0610, 3256,4111,0004,4174,4007,0700,0010,0000,0000 ; 5799 CALL [CHKSN] ;ONES COMP? ; 5800 =10 [ARX]_[ARX].XOR.[MAG], ;YES--ONES COMP U 0612, 3253,6111,0004,4174,4007,0700,0000,0000,0000 ; 5801 J/DNN1 ;CONTINUE BELOW ; 5802 =11 [ARX]_-[ARX], 3T, ;NEGATE RESULT U 0613, 2050,2441,0404,4174,4007,0561,4000,0000,0000 ; 5803 SKIP CRY1, J/DNN2 ; 5804 = U 3253, 2050,4221,0013,4174,4007,0700,0000,0000,0000 ; 5805 DNN1: [FLG]_0 ;CLEAR FLAG ; 5806 =0 U 2050, 3254,7333,0003,0174,4007,0700,0400,0000,0000 ; 5807 DNN2: AC_.NOT.[AR], J/DNORM2 U 2051, 3254,2443,0300,0174,4007,0701,4400,0000,0000 ; 5808 AC_-[AR], 3T ; 5809 DNORM2: AC[1]_[ARX].AND.[MAG], ;STORE LOW WORD U 3254, 0100,4113,0400,1174,4156,4700,0400,0000,1441 ; 5810 NEXT INST ;ALL DONE ; 5811 U 3255, 2052,3223,0000,4174,4007,0621,0000,0000,0000 ; 5812 DNNRM1: READ Q, SKIP AD.EQ.0 ;TEST LOW WORD ; 5813 =0 [AR]_[AR]*2 LONG, ;LOW WORD IS NON-ZERO ; 5814 FE_FE-1, ASHC, ;ADJUST EXPONENT U 2052, 0200,3444,0303,4174,4043,4701,1000,0041,1777 ; 5815 NORM DISP, J/DNNORM ;KEEP LOOKING U 2053, 1515,3440,0303,1174,4007,0700,0400,0000,1441 ; 5816 AC[1]_[AR], J/STAC ;WHOLE ANSWER IS ZERO ; 5817 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 157 ; FLT.MIC[7,3] 01:46 20-MAR-1981 FLOATING POINT -- DOUBLE PRECISION NORMALIZE U 3256, 0002,4553,1300,4374,4004,1321,0000,0000,2000 ; 5818 CHKSN: TL [FLG], FLG.SN/1, RETURN [2] ; 5819 ; 5820 ;SUBROUTINE TO SET/CLEAR FLG.SN ; 5821 ;CALL WITH: ; 5822 ; CALL [SETSN], SKIP IF WE SHOULD CLEAR ; 5823 ;RETURNS 23 ; 5824 =0 U 2054, 0023,3551,1313,4374,0004,1700,0000,0000,2000 ; 5825 SETSN: [FLG]_[FLG].OR.#, FLG.SN/1, HOLD RIGHT, RETURN [23] U 2055, 0023,5551,1313,4374,0004,1700,0000,0000,2000 ; 5826 CLRSN: [FLG]_[FLG].AND.NOT.#, FLG.SN/1, HOLD RIGHT, RETURN [23] ; 5827 ; 5828 ; 5829 ;SUBROUTINE TO ROUND A FLOATING POINT NUMBER ; 5830 ;CALL WITH: ; 5831 ; NUMBER IN AR!Q AND NORM DISP ; 5832 ;RETURNS 16 WITH ROUNDED NUMBER IN AR!ARX ; 5833 ; ; 5834 =*01* ; 5835 DROUND: [ARX]_(Q+1)*.5, ;ROUND AND SHIFT ; 5836 SKIP CRY2, ;SEE IF OVERFLOW U 0322, 0462,0007,0704,4174,4007,0511,0000,0000,0000 ; 5837 J/DRND1 ;COMPLETE ROUNDING ; 5838 [AR]_[AR]*.5 LONG, ;WE WENT TOO FAR U 0326, 0322,3446,0303,4174,4047,0700,1000,0041,0001 ; 5839 FE_FE+1, ASHC, J/DROUND ;SHIFT BACK AND ROUND ; 5840 =*010 U 0462, 0016,3770,0303,4324,0454,1700,0000,0041,0000 ; 5841 DRND1: [AR]_EXP, RETURN [16] ;NO OVERFLOW ; 5842 =011 [AR]_[AR]+.25, ;ADD CARRY (BITS 36 AND 37 ; 5843 ; ARE COPIES OF Q BITS) ; 5844 NORM DISP, ;SEE IF OVERFLOW U 0463, 0462,0441,0303,4174,4003,4701,4000,0000,0000 ; 5845 J/DRND1 ; .. ; 5846 =110 [AR]_[AR]*.5, ;SHIFT RIGHT ; 5847 FE_FE+1, ;KEEP EXP RIGHT U 0466, 0462,3447,0303,4174,4007,0700,1000,0041,0001 ; 5848 J/DRND1 ;ALL SET NOW ; 5849 = ; 5850 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 158 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- DISPATCH ROM ENTRIES ; 5851 .TOC "EXTEND -- DISPATCH ROM ENTRIES" ; 5852 ; 5853 .DCODE D 0001, 0001,1740,2100 ; 5854 001: I, SJCL, J/L-CMS D 0002, 0002,1740,2100 ; 5855 I, SJCE, J/L-CMS D 0003, 0003,1740,2100 ; 5856 I, SJCLE, J/L-CMS D 0004, 0002,1741,2100 ; 5857 I, B/2, J/L-EDIT D 0005, 0005,1740,2100 ; 5858 I, SJCGE, J/L-CMS D 0006, 0006,1740,2100 ; 5859 I, SJCN, J/L-CMS D 0007, 0007,1740,2100 ; 5860 I, SJCG, J/L-CMS ; 5861 D 0010, 0001,1742,2100 ; 5862 010: I, B/1, J/L-DBIN ;CVTDBO D 0011, 0004,1742,2100 ; 5863 I, B/4, J/L-DBIN ;CVTDBT D 0012, 0001,1743,2100 ; 5864 I, B/1, J/L-BDEC ;CVTBDO D 0013, 0000,1743,2100 ; 5865 I, B/0, J/L-BDEC ;CVTBDT ; 5866 D 0014, 0001,1744,2100 ; 5867 014: I, B/1, J/L-MVS ;MOVSO D 0015, 0000,1744,2100 ; 5868 I, B/0, J/L-MVS ;MOVST D 0016, 0002,1744,2100 ; 5869 I, B/2, J/L-MVS ;MOVSLJ D 0017, 0003,1744,2100 ; 5870 I, B/3, J/L-MVS ;MOVSRJ ; 5871 D 0020, 0000,1746,2100 ; 5872 020: I, J/L-XBLT ;XBLT D 0021, 0000,1747,2100 ; 5873 I, J/L-SPARE-A ;GSNGL D 0022, 0000,1750,2100 ; 5874 I, J/L-SPARE-B ;GDBLE D 0023, 0000,1751,2100 ; 5875 I, B/0, J/L-SPARE-C ;GDFIX D 0024, 0001,1751,2100 ; 5876 I, B/1, J/L-SPARE-C ;GFIX D 0025, 0002,1751,2100 ; 5877 I, B/2, J/L-SPARE-C ;GDFIXR D 0026, 0004,1751,2100 ; 5878 I, B/4, J/L-SPARE-C ;GFIXR D 0027, 0010,1751,2100 ; 5879 I, B/10, J/L-SPARE-C ;DGFLTR ; 5880 ;30: ;GFLTR ; 5881 ;GFSC ; 5882 .UCODE ; 5883 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 159 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- DISPATCH ROM ENTRIES ; 5884 1740: U 1740, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 5885 L-CMS: LUUO ; 5886 1741: U 1741, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 5887 L-EDIT: LUUO ; 5888 1742: U 1742, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 5889 L-DBIN: LUUO ; 5890 1743: U 1743, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 5891 L-BDEC: LUUO ; 5892 1744: U 1744, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 5893 L-MVS: LUUO ; 5894 1746: U 1746, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 5895 L-XBLT: LUUO ; 5896 1747: U 1747, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 5897 L-SPARE-A: LUUO ; 5898 1750: U 1750, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 5899 L-SPARE-B: LUUO ; 5900 1751: U 1751, 0400,4751,1203,4374,4007,0700,0000,0000,0040 ; 5901 L-SPARE-C: LUUO ; 5902 ; 5903 ;NOTE: WE DO NOT NEED TO RESERVE 3746 TO 3751 BECAUSE THE CODE ; 5904 ; AT EXTEND DOES A RANGE CHECK. ; 5905 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 160 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- INSTRUCTION SET DECODING ; 5906 .TOC "EXTEND -- INSTRUCTION SET DECODING" ; 5907 ; 5908 ;EACH INSTRUCTION IN THE RANGE 1-23 GOES TO 1 OF 2 PLACES ; 5909 ; 1740-1747 IF NOT UNDER EXTEND ; 5910 ; 3740-3747 IF UNDER EXTEND ; 5911 ; 5912 .DCODE D 0123, 0000,1467,3100 ; 5913 123: I,READ/1, J/EXTEND ; 5914 .UCODE ; 5915 ; 5916 1467: U 1467, 1062,3771,0005,4365,5007,0700,0200,0000,0002 ; 5917 EXTEND: MEM READ, [BR]_MEM ;FETCH INSTRUCTION ; 5918 =0** TL [BR], #/760740, ;IN RANGE 0-17 (AND AC#=0) U 1062, 3556,4553,0500,4374,4007,0321,0010,0076,0740 ; 5919 CALL [BITCHK] ;TRAP IF NON-ZERO BITS FOUND ; 5920 [BRX]_[HR].AND.# CLR RH, ;SPLIT OUT AC NUMBER U 1066, 3257,4521,0206,4374,4007,0700,0000,0000,0740 ; 5921 #/000740 ; FROM EXTEND INSTRUCTION ; 5922 [BR]_[BR].OR.[BRX], ;LOAD IR AND AC # U 3257, 3260,3111,0605,4174,0417,0700,0000,0000,0000 ; 5923 HOLD RIGHT, LOAD IR ; .. ; 5924 READ [BR], LOAD BYTE EA, ;LOAD XR # U 3260, 3261,3333,0005,4174,4217,0700,0000,0000,0500 ; 5925 J/EXTEA0 ;COMPUTE E1 ; 5926 U 3261, 3262,3333,0003,7174,4007,0700,0400,0000,0240 ; 5927 EXTEA0: WORK[E0]_[AR] U 3262, 0170,4443,0000,2174,4006,6700,0000,0000,0000 ; 5928 EXTEA1: EA MODE DISP ; 5929 =100* U 0170, 0172,0551,0505,2270,4007,0700,0000,0000,0000 ; 5930 EXTEA: [BR]_[BR]+XR ; 5931 EXTDSP: [BR]_EA FROM [BR], LOAD VMA, U 0172, 0556,5741,0505,4174,4003,7700,0200,0000,0010 ; 5932 B DISP, J/EXTEXT U 0174, 3263,0551,0505,2270,4007,0700,0200,0004,0512 ; 5933 [BR]_[BR]+XR, START READ, PXCT EXTEND EA, LOAD VMA, J/EXTIND U 0176, 3263,3443,0500,4174,4007,0700,0200,0004,0512 ; 5934 VMA_[BR], START READ, PXCT EXTEND EA ; 5935 U 3263, 3262,3771,0005,4361,5217,0700,0200,0000,0502 ; 5936 EXTIND: MEM READ, [BR]_MEM, HOLD LEFT, LOAD BYTE EA, J/EXTEA1 ; 5937 ; 5938 ;HERE TO EXTEND SIGN FOR OFFSET MODES ; 5939 =1110 ; 5940 EXTEXT: WORK[E1]_[BR], ;SAVE E1 U 0556, 3400,3333,0005,7174,4001,2700,0400,0000,0241 ; 5941 DISP/DROM, J/3400 ;GO TO EXTENDED EXECUTE CODE U 0557, 2056,3333,0005,4174,4007,0530,0000,0000,0000 ; 5942 READ [BR], SKIP DP18 ;NEED TO EXTEND SIGN ; 5943 =0 WORK[E1]_[BR], ;POSITIVE U 2056, 3400,3333,0005,7174,4001,2700,0400,0000,0241 ; 5944 DISP/DROM, J/3400 ; 5945 [BR]_#, #/777777, HOLD RIGHT, ;NEGATIVE U 2057, 0556,3771,0005,4374,0007,0700,0000,0077,7777 ; 5946 J/EXTEXT ; 5947 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 161 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- MOVE STRING -- SETUP ; 5948 .TOC "EXTEND -- MOVE STRING -- SETUP" ; 5949 ; 5950 ;HERE TO MOVE A STRING ; 5951 ;COME HERE WITH: ; 5952 ; AR/ E0 ; 5953 ; BR/ E1 ; 5954 ; ; 5955 3744: ; 5956 MVS: [AR]_[AR]+1, ;GO FETCH FILL ; 5957 LOAD VMA, ; BYTE ; 5958 START READ, ; .. U 3744, 3456,0111,0703,4174,4007,0700,0210,0004,0012 ; 5959 CALL [GTFILL] ;SUBROUTINE TO COMPLETE U 3754, 2060,3771,0005,1276,6007,0701,0000,0000,1443 ; 5960 3754: [BR]_AC[DLEN] ;GET DEST LENGTH AND FLAGS ; 5961 =0** TL [BR], #/777000, ;ANY FLAGS SET? U 2060, 3556,4553,0500,4374,4007,0321,0010,0077,7000 ; 5962 CALL [BITCHK] ;SEE IF ILLEGAL U 2064, 2062,3771,0003,0276,6007,0700,0000,0000,0000 ; 5963 [AR]_AC ;GET SRC LENGTH AND FLAGS ; 5964 =0 [BRX]_[AR].AND.# CLR RH, ;COPY FLAGS TO BRX ; 5965 #/777000, ; .. U 2062, 3460,4521,0306,4374,4007,0700,0010,0077,7000 ; 5966 CALL [CLRFLG] ;CLEAR FLAGS IN AR ; 5967 ;NEW DLEN IS - ; 5968 AC[DLEN]_[AR]-[BR], 3T, ;COMPUTE DIFFERENCE U 2063, 2066,2113,0305,1174,4007,0521,4400,0000,1443 ; 5969 SKIP DP0 ;WHICH IS SHORTER? ; 5970 =0 [AR]_.NOT.[BR], ;DESTINATION U 2066, 3264,7441,0503,4174,4007,0700,0000,0000,0000 ; 5971 J/MVS1 ;GET NEGATIVE LENGTH U 2067, 3264,7441,0303,4174,4007,0700,0000,0000,0000 ; 5972 [AR]_.NOT.[AR] ;SOURCE ; 5973 MVS1: WORK[SLEN]_[AR], ; .. U 3264, 0574,3333,0003,7174,4003,7700,0400,0000,0242 ; 5974 B DISP ;SEE WHAT TYPE OF MOVE ; 5975 ;SLEN NOW HAS --1 ; 5976 =1100 U 0574, 0500,3771,0013,4370,4007,0700,0000,0000,0003 ; 5977 STATE_[SRC], J/MOVELP ;TRANSLATE--ALL SET U 0575, 3265,3771,0005,1276,6007,0701,0000,0000,1444 ; 5978 [BR]_AC[DSTP], J/MVSO ;OFFSET BUILD MASK ; 5979 [ARX]_[AR], ;LEFT JUSTIFY U 0576, 3305,3441,0304,4174,4007,0700,0000,0000,0000 ; 5980 J/MOVST0 ; .. ; 5981 [ARX]_AC[DLEN], ;RIGHT JUSTIFY ; 5982 SKIP DP0, 4T, ;WHICH IS SHORTER? U 0577, 0630,3771,0004,1276,6007,0522,0000,0000,1443 ; 5983 J/MOVRJ ; 5984 U 3265, 3266,3333,0005,4174,4007,0700,1000,0041,6020 ; 5985 MVSO: READ [BR], FE_S+2 ;GET DST BYTE SIZE U 3266, 2070,4222,0000,4174,4006,7701,1000,0041,1770 ; 5986 Q_0, BYTE STEP ;BUILD AN S BIT MASK ; 5987 =0* U 2070, 2070,4224,0003,4174,4026,7701,1000,0041,1770 ; 5988 MVSO1: GEN MSK [AR], BYTE STEP, J/MVSO1 U 2072, 3267,7221,0003,4174,4007,0700,0000,0000,0000 ; 5989 [AR]_.NOT.Q ;BITS WHICH MUST NOT BE SET ; 5990 WORK[MSK]_[AR].AND.[MASK], ;SAVE FOR SRCMOD U 3267, 0507,4113,0312,7174,4007,0700,0400,0000,0243 ; 5991 J/MOVLP0 ;GO ENTER LOOP ; 5992 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 162 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- MOVE STRING -- OFFSET/TRANSLATE ; 5993 .TOC "EXTEND -- MOVE STRING -- OFFSET/TRANSLATE" ; 5994 ; 5995 ;HERE IS THE LOOP FOR OFFSET AND TRANSLATED MOVES ; 5996 =000 ; 5997 MOVELP: [AR]_WORK[SLEN]+1, ;UPDATE STRING LENGTH U 0500, 1074,0551,0703,7274,4007,0701,0010,0000,0242 ; 5998 CALL [SRCMOD] ;GET A SOURCE BYTE ; 5999 =001 [ARX]_[AR], SKIP DP0, ;(1) LENGTH EXHAUSTED U 0501, 0750,3441,0304,4174,4007,0520,0000,0000,0000 ; 6000 J/MOVST2 ; SEE IF FILL IS NEEDED ; 6001 =100 [AR]_-WORK[SLEN], ;(4) ABORT U 0504, 3270,1771,0003,7274,4007,0701,4000,0000,0242 ; 6002 J/MVABT ; .. ; 6003 STATE_[SRC+DST], ;(5) NORMAL--STORE DST BYTE U 0505, 3450,3771,0013,4370,4007,0700,0010,0000,0005 ; 6004 CALL [PUTDST] ; .. ; 6005 =111 U 0507, 0500,3771,0013,4370,4007,0700,0000,0000,0003 ; 6006 MOVLP0: STATE_[SRC], J/MOVELP ;(7) DPB DONE ; 6007 = ; 6008 ; 6009 ;HERE TO ABORT A STRING MOVE DUE TO TRANSLATE OR OFFSET FAILURE ; 6010 ; 6011 MVABT: [BR]_AC[DLEN], ;WHICH STRING IS LONGER U 3270, 2074,3771,0005,1276,6007,0522,0000,0000,1443 ; 6012 SKIP DP0, 4T ; 6013 =0 U 2074, 3271,3440,0303,1174,4007,0700,0400,0000,1443 ; 6014 MVABT1: AC[DLEN]_[AR], J/MVABT2 ;PUT AWAY DEST LEN ; 6015 [AR]_[AR]-[BR], ;DEST LEN WAS GREATER U 2075, 2074,1111,0503,4174,4007,0700,4000,0000,0000 ; 6016 J/MVABT1 ;STICK BACK IN AC ; 6017 U 3271, 3272,7771,0003,7274,4007,0701,0000,0000,0242 ; 6018 MVABT2: [AR]_.NOT.WORK[SLEN] ;GET UNDECREMENTED SLEN U 3272, 2076,3333,0005,4174,4007,0520,0000,0000,0000 ; 6019 READ [BR], SKIP DP0 ;NEED TO FIXUP SRC? U 2076, 2077,0111,0503,4174,4007,0700,0000,0000,0000 ; 6020 =0 [AR]_[AR]+[BR] ;SRC LONGER BY (DLEN) U 2077, 3273,3111,0603,4174,4007,0700,0000,0000,0000 ; 6021 MVEND: [AR]_[AR].OR.[BRX] ;PUT BACK SRC FLAGS U 3273, 1515,4221,0013,4170,4007,0700,0000,0000,0000 ; 6022 END STATE, J/STAC ;ALL DONE ; 6023 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 163 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- MOVE STRING -- MOVSRJ ; 6024 .TOC "EXTEND -- MOVE STRING -- MOVSRJ" ; 6025 ; 6026 =00 U 0630, 3274,3771,0003,1276,6007,0701,0000,0000,1441 ; 6027 MOVRJ: [AR]_AC[SRCP], J/MVSKP ;SRC LONGER, SKIP OVER SOME ; 6028 STATE_[DSTF], ;DST LONGER, FILL IT U 0631, 2263,3771,0013,4370,4007,0700,0010,0000,0006 ; 6029 CALL [MOVFIL] ; .. ; 6030 =11 [ARX]_WORK[SLEN]+1, ;DONE FILLING U 0633, 3306,0551,0704,7274,4007,0701,0000,0000,0242 ; 6031 J/MOVST1 ;GO MOVE STRING ; 6032 ; 6033 ;HERE TO SKIP OVER EXTRA SOURCE BYTES U 3274, 2100,3440,0303,1174,4007,0670,0400,0000,1441 ; 6034 MVSKP: AC[SRCP]_[AR], SKIP -1MS ;[121] Is there a timer interrupt? U 2100, 3277,3333,0003,7174,4007,0700,0400,0000,0211 ; 6035 =0 WORK[SV.AR]_[AR], J/MVSK2 ;[121][123] Yes, save regs for interrupt. ; 6036 [ARX]_[ARX]-1, 3T, ;DONE SKIPPING? U 2101, 2102,1111,0704,4174,4007,0521,4000,0000,0000 ; 6037 SKIP DP0 ; 6038 =0 IBP DP, IBP SCAD, ;NO--START THE IBP ; 6039 SCAD DISP, SKIP IRPT, ;4-WAY DISPATCH U 2102, 0650,3770,0305,4334,4016,7371,0000,0033,6000 ; 6040 3T, J/MVSKP1 ;GO BUMP POINTER ; 6041 AC[DLEN]_0, ;LENGTHS ARE NOW EQUAL U 2103, 0546,4223,0000,1174,4007,0700,0400,0000,1443 ; 6042 J/MOVST4 ;GO MOVE STRING ; 6043 ; 6044 =00 U 0650, 3274,3441,0503,4174,4007,0700,0000,0000,0000 ; 6045 MVSKP1: [AR]_[BR], J/MVSKP ;NO OVERFLOW ; 6046 [AR]_.NOT.WORK[SLEN], ;INTERRUPT U 0651, 3275,7771,0003,7274,4007,0701,0000,0000,0242 ; 6047 J/MVSK3 ; .. ; 6048 SET P TO 36-S, ;WORD OVERFLOW U 0652, 3276,3770,0503,4334,4017,0700,0000,0032,6000 ; 6049 J/MVSKP2 ;FIXUP Y U 0653, 3275,7771,0003,7274,4007,0701,0000,0000,0242 ; 6050 [AR]_.NOT.WORK[SLEN] ;[121] INTERRUPT or timer. U 3275, 2104,3440,0303,1174,4007,0700,0400,0000,1443 ; 6051 MVSK3: AC[DLEN]_[AR] ;RESET DLEN ; 6052 =0 [AR]_[AR]+[ARX], U 2104, 3664,0111,0403,4174,4007,0700,0010,0000,0000 ; 6053 CALL [INCAR] ;ADD 1 TO AR ; 6054 AC_[AR].OR.[BRX], ;PUT BACK FLAGS U 2105, 3720,3113,0306,0174,4007,0700,0400,0000,0000 ; 6055 J/ITRAP ;DO INTERRUPT TRAP ; 6056 ; 6057 MVSKP2: [AR]_[AR]+1, HOLD LEFT, ;BUMP Y U 3276, 3274,0111,0703,4170,4007,0700,0000,0000,0000 ; 6058 J/MVSKP ;KEEP GOING ; 6059 ; 6060 ;BEGIN EDIT [123] U 3277, 3300,3333,0005,7174,4007,0700,0400,0000,0213 ; 6061 MVSK2: WORK[SV.BR]_[BR] ;SAVE ALL U 3300, 3301,3333,0004,7174,4007,0700,0400,0000,0212 ; 6062 WORK[SV.ARX]_[ARX] ;THE REGISTERS U 3301, 2071,3333,0006,7174,4007,0700,0400,0000,0214 ; 6063 WORK[SV.BRX]_[BRX] ;FOR THE TICK U 2071, 3560,4443,0000,4174,4007,0700,0010,0000,0000 ; 6064 =0* CALL [TICK] ;UPDATE CLOCK AND SET INTERUPT U 2073, 3302,3771,0003,7274,4007,0701,0000,0000,0211 ; 6065 [AR]_WORK[SV.AR] ;NOW PUT U 3302, 3303,3771,0005,7274,4007,0701,0000,0000,0213 ; 6066 [BR]_WORK[SV.BR] ;THEM ALL U 3303, 3304,3771,0004,7274,4007,0701,0000,0000,0212 ; 6067 [ARX]_WORK[SV.ARX] ;BACK SO WE ; 6068 [BRX]_WORK[SV.BRX], ;CAN CONTINUE U 3304, 3274,3771,0006,7274,4007,0701,0000,0000,0214 ; 6069 J/MVSKP ; 6070 ;END EDIT [123] ; 6071 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 164 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- MOVE STRING -- SIMPLE MOVE LOOP ; 6072 .TOC "EXTEND -- MOVE STRING -- SIMPLE MOVE LOOP" ; 6073 ; 6074 ;HERE FOR NO-MODIFICATION STRING MOVES U 3305, 3306,0111,0704,4174,4007,0700,0000,0000,0000 ; 6075 MOVST0: [ARX]_[ARX]+1 ;CANT DO [ARX]_[AR]+1 U 3306, 0540,3771,0013,4370,4007,0700,0000,0000,0003 ; 6076 MOVST1: STATE_[SRC] ;PREPARE FOR PAGE FAIL ; 6077 =000 ; 6078 WORK[SLEN]_[ARX], ;GO GET A SOURCE BYTE U 0540, 2274,3333,0004,7174,4007,0520,0410,0000,0242 ; 6079 SKIP DP0, CALL [GSRC] ; .. ; 6080 MOVSTX: [ARX]_[AR], ;SHORT STRING RAN OUT U 0541, 0750,3441,0304,4174,4007,0520,0000,0000,0000 ; 6081 SKIP DP0, J/MOVST2 ;GO SEE IF FILL NEEDED ; 6082 =010 STATE_[SRC+DST], ;WILL NEED TO BACK UP BOTH POINTERS U 0542, 3450,3771,0013,4370,4007,0700,0010,0000,0005 ; 6083 CALL [PUTDST] ;STORE BYTE ; 6084 =110 ; 6085 MOVST4: [ARX]_WORK[SLEN]+1, ;COUNT DOWN LENGTH U 0546, 3306,0551,0704,7274,4007,0701,0000,0000,0242 ; 6086 J/MOVST1 ;LOOP OVER STRING ; 6087 = ; 6088 =00 U 0750, 3307,4223,0000,1174,4007,0700,0400,0000,1443 ; 6089 MOVST2: AC[DLEN]_0, J/MOVST3 ;CLEAR DEST LEN, REBUILD SRC U 0751, 2263,3771,0013,4370,4007,0700,0010,0000,0004 ; 6090 STATE_[DST], CALL [MOVFIL] ;FILL OUT DEST U 0753, 2147,3440,0606,0174,4007,0700,0400,0000,0000 ; 6091 =11 AC_[BRX], J/ENDSKP ;ALL DONE ; 6092 U 3307, 3310,3113,0406,0174,4007,0700,0400,0000,0000 ; 6093 MOVST3: AC_[ARX].OR.[BRX] ;REBUILD SRC U 3310, 0252,4221,0013,4170,4007,0700,0000,0000,0000 ; 6094 END STATE, J/SKIPE ; .. ; 6095 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 165 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- COMPARE STRING ; 6096 .TOC "EXTEND -- COMPARE STRING" ; 6097 ; 6098 3740: U 3740, 2061,3771,0004,1276,6007,0701,0000,0000,1443 ; 6099 CMS: [ARX]_AC[DLEN] ;GET DEST LEN U 2061, 3556,4553,0400,4374,4007,0321,0010,0077,7000 ; 6100 =0** TL [ARX], #/777000, CALL [BITCHK] U 2065, 2110,3771,0006,0276,6007,0700,0000,0000,0000 ; 6101 [BRX]_AC ;GET SRC LEN U 2110, 3556,4553,0600,4374,4007,0321,0010,0077,7000 ; 6102 =0** TL [BRX], #/777000, CALL [BITCHK] U 2114, 2106,2113,0604,4174,4007,0521,4000,0000,0000 ; 6103 [BRX]-[ARX], 3T, SKIP DP0 ;WHICH STRING IS LONGER? U 2106, 2107,0111,0703,4174,4007,0700,0000,0000,0000 ; 6104 =0 [AR]_[AR]+1 ;SRC STRING IS LONGER U 2107, 2112,0111,0703,4170,4007,0700,0200,0004,0012 ; 6105 VMA_[AR]+1, START READ ;DST STRING ; 6106 =0 [AR]_0, ;FORCE FIRST COMPARE TO BE ; 6107 ;EQUAL U 2112, 3662,4221,0003,4174,4007,0700,0010,0000,0000 ; 6108 CALL [LOADQ] ;PUT FILL INTO Q ; 6109 WORK[FILL]_Q, ;SAVE FILLER U 2113, 3320,3223,0000,7174,4007,0700,0400,0000,0244 ; 6110 J/CMS2 ;ENTER LOOP ; 6111 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 166 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- COMPARE STRING ; 6112 ;HERE IS THE COMPARE LOOP. ; 6113 ; ARX/ CONATINS REMAINING DEST LENGTH ; 6114 ; BRX/ CONTAINS REMAINING SOURCE LENGTH ; 6115 =0 ; 6116 CMS3: ;BYTES ARE NOT EQUAL ; 6117 END STATE, ;NO MORE SPECIAL PAGE FAIL ACTION U 2116, 0250,4221,0013,4170,4003,7700,0000,0000,0000 ; 6118 SKIP-COMP DISP ;SEE SKIP-COMP-TABLE U 2117, 3311,3771,0003,1276,6007,0701,0000,0000,1441 ; 6119 CMS4: [AR]_AC[SRCP] ;GET BYTE POINTER U 3311, 1020,3333,0006,4174,4007,0520,0000,0000,0000 ; 6120 READ [BRX], SKIP DP0 ;MORE IN SOURCE STRING? ; 6121 =00 STATE_[EDIT-SRC], ;PREPARE FOR PAGE FAIL U 1020, 2275,3771,0013,4370,4007,0700,0010,0000,0011 ; 6122 CALL [GETSRC] ; GO GET BYTE ; 6123 READ [ARX], SKIP DP0, ;NO MORE SRC--SEE IF MORE DEST U 1021, 2120,3333,0004,4174,4007,0520,0000,0000,0000 ; 6124 J/CMS5 ; .. U 1022, 3312,3333,0003,7174,4007,0700,0400,0000,0245 ; 6125 WORK[CMS]_[AR] ;SAVE SRC BYTE ; 6126 = U 3312, 3313,3440,0606,0174,4007,0700,0400,0000,0000 ; 6127 AC_[BRX] ;PUT BACK SRC LEN U 3313, 3314,3771,0013,4370,4007,0700,0000,0000,0010 ; 6128 STATE_[COMP-DST] ;HAVE TO BACK UP IF DST FAILS U 3314, 1030,3333,0004,4174,4007,0520,0000,0000,0000 ; 6129 READ [ARX], SKIP DP0 ;ANY MORE DEST? ; 6130 =00 U 1030, 2122,4443,0000,4174,4007,0700,0010,0000,0000 ; 6131 CMS6: CALL [CMPDST] ;MORE DEST BYTES ; 6132 [AR]_WORK[FILL], ;OUT OF DEST BYTES U 1031, 3315,3771,0003,7274,4007,0701,0000,0000,0244 ; 6133 J/CMS7 ;GO DO COMPARE U 1032, 3315,3440,0404,1174,4007,0700,0400,0000,1443 ; 6134 AC[DLEN]_[ARX] ;GOT A BYTE, UPDATE LENGTH ; 6135 = ; 6136 CMS7: [AR]_[AR].AND.[MASK], ;MAKE MAGNITUDES U 3315, 3316,4111,1203,7174,4007,0700,0000,0000,0245 ; 6137 WORK[CMS] ;WARM UP RAM U 3316, 3317,4551,1205,7274,4007,0700,0000,0000,0245 ; 6138 [BR]_[MASK].AND.WORK[CMS], 2T ;GET SRC MAGNITUDE U 3317, 3320,2111,0503,4174,4007,0700,4000,0000,0000 ; 6139 [AR]_[BR]-[AR] REV ;UNSIGNED COMPARE U 3320, 3321,1111,0704,4174,4007,0700,4000,0000,0000 ; 6140 CMS2: [ARX]_[ARX]-1 ;UPDATE LENGTHS U 3321, 3322,1111,0706,4174,4007,0700,4000,0000,0000 ; 6141 [BRX]_[BRX]-1 ; .. U 3322, 2116,3333,0003,4174,4007,0621,0000,0000,0000 ; 6142 READ [AR], SKIP AD.EQ.0, J/CMS3 ;SEE IF EQUAL ; 6143 ; 6144 =0 U 2120, 3323,3772,0000,7274,4007,0701,0000,0000,0244 ; 6145 CMS5: Q_WORK[FILL], J/CMS8 ;MORE DST--GET SRC FILL U 2121, 2116,4221,0003,4174,4007,0700,0000,0000,0000 ; 6146 [AR]_0, J/CMS3 ;STRINGS ARE EQUAL U 3323, 3324,3771,0013,4370,4007,0700,0000,0000,0012 ; 6147 CMS8: STATE_[EDIT-DST] ;JUST DST POINTER ON PAGE FAIL U 3324, 1030,3223,0000,7174,4007,0700,0400,0000,0245 ; 6148 WORK[CMS]_Q, J/CMS6 ;MORE DST--SAVE SRC FILL ; 6149 ; 6150 =0 ; 6151 CMPDST: [AR]_AC[DSTP], ;GET DEST POINTER U 2122, 3451,3771,0003,1276,6007,0701,0010,0000,1444 ; 6152 CALL [IDST] ;UPDATE IT ; 6153 READ [AR], ;LOOK AT BYTE POINTER ; 6154 FE_FE.AND.S#, S#/0770, ;MASK OUT BIT 6 U 2123, 0340,3333,0003,4174,4006,5701,1000,0051,0770 ; 6155 BYTE DISP, J/LDB1 ;GO LOAD BYTE ; 6156 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 167 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- DECIMAL TO BINARY CONVERSION ; 6157 .TOC "EXTEND -- DECIMAL TO BINARY CONVERSION" ; 6158 ; 6159 3742: U 3742, 3325,4571,1203,4374,4007,0700,0000,0077,7777 ; 6160 DBIN: [AR]_[777777] XWD 0 ;IF WE ARE IN OFFSET MODE U 3325, 3326,3333,0003,7174,4007,0700,0400,0000,0243 ; 6161 WORK[MSK]_[AR] ; ONLY ALLOW 18 BITS ; 6162 ;RANGE CHECKED (0-10) LATER U 3326, 3327,3771,0003,0276,6007,0700,0000,0000,0000 ; 6163 [AR]_AC ;GET SRC LENGTH ; 6164 [BRX]_[AR].AND.# CLR RH, ;SPLIT OUT FLAGS U 3327, 2124,4521,0306,4374,4007,0700,0000,0077,7000 ; 6165 #/777000 ; .. ; 6166 =0* [ARX]_AC[BIN1], ;GET LOW WORD U 2124, 2220,3771,0004,1276,6007,0701,0010,0000,1444 ; 6167 CALL [CLARX0] ;CLEAR BIT 0 OF ARX U 2126, 2130,3440,0404,1174,4007,0700,0400,0000,1444 ; 6168 AC[BIN1]_[ARX] ;STORE BACK ; 6169 =0 READ [BRX], SKIP DP0, ;IS S ALREADY SET? U 2130, 2154,3333,0006,4174,4007,0520,0010,0000,0000 ; 6170 CALL [CLRBIN] ;GO CLEAR BIN IF NOT ; 6171 [AR]_[AR].AND.#, ;CLEAR FLAGS FROM LENGTH ; 6172 #/000777, HOLD RIGHT, ; .. U 2131, 0616,4551,0303,4374,0003,7700,0000,0000,0777 ; 6173 B DISP ;SEE IF OFFSET OR TRANSLATE ; 6174 =1110 U 0616, 3330,3771,0013,4370,4007,0700,0000,0000,0007 ; 6175 DBIN1: STATE_[CVTDB], J/DBIN2 ;TRANSLATE--LEAVE S ALONE ; 6176 [BRX]_[BRX].OR.#, ;OFFSET--FORCE S TO 1 ; 6177 #/400000, HOLD RIGHT, U 0617, 0616,3551,0606,4374,0007,0700,0000,0040,0000 ; 6178 J/DBIN1 U 3330, 0460,7333,0003,7174,4007,0700,0400,0000,0242 ; 6179 DBIN2: WORK[SLEN]_.NOT.[AR] ;STORE -SLEN-1 ; 6180 ; 6181 ;HERE IS THE MAIN LOOP ; 6182 =0*0 U 0460, 1074,0551,0703,7274,4007,0701,0010,0000,0242 ; 6183 DBINLP: [AR]_WORK[SLEN]+1, CALL [SRCMOD] ;(0) GET MODIFIED SRC BYTE ; 6184 TL [BRX], #/100000, ;(1) DONE, IS M SET? U 0461, 2142,4553,0600,4374,4007,0321,0000,0010,0000 ; 6185 J/DBXIT ; 6186 [AR]_.NOT.WORK[SLEN], ;(4) ABORT U 0464, 3335,7771,0003,7274,4007,0701,0000,0000,0242 ; 6187 J/DBABT ; .. ; 6188 [AR]-#, #/10., ;(5) NORMAL--SEE IF 0-9 U 0465, 2132,1553,0300,4374,4007,0532,4000,0000,0012 ; 6189 4T, SKIP DP18 ; .. ; 6190 =0 [AR]_.NOT.WORK[SLEN], ;DIGIT TOO BIG U 2132, 3335,7771,0003,7274,4007,0701,0000,0000,0242 ; 6191 J/DBABT ;GO ABORT CVT ; 6192 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 168 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- DECIMAL TO BINARY CONVERSION ; 6193 ;HERE TO ADD IN A DIGIT ; 6194 [BR]_AC[BIN0], 4T, ;GET HIGH BINARY U 2133, 1050,3771,0005,1276,6007,0622,0000,0000,1443 ; 6195 SKIP AD.EQ.0 ;SEE IF SMALL ; 6196 =00 ; 6197 DBSLO: [ARX]_AC[BIN1], ;TOO BIG U 1050, 0560,3771,0004,1276,6007,0701,0010,0000,1444 ; 6198 CALL [DBSLOW] ;GO USE DOUBLE PRECISION PATHS ; 6199 [BR]_AC[BIN1], ;GET LOW WORD U 1051, 3331,3771,0005,1276,6007,0701,0000,0000,1444 ; 6200 J/DBFAST ;MIGHT FIT IN 1 WORD U 1052, 0460,4443,0000,4174,4007,0700,0000,0000,0000 ; 6201 J/DBINLP ;RETURN FROM DBSLOW ; 6202 ;GO DO NEXT DIGIT ; 6203 = U 3331, 2134,4553,0500,4374,4007,0321,0000,0076,0000 ; 6204 DBFAST: TL [BR], #/760000 ;WILL RESULT FIT IN 36 BITS? U 2134, 1050,4443,0000,4174,4007,0700,0000,0000,0000 ; 6205 =0 J/DBSLO ;MAY NOT FIT--USE DOUBLE WORD U 2135, 3332,3775,0005,1276,6007,0701,0000,0000,1444 ; 6206 [BR]_AC[BIN1]*2 ;COMPUTE AC*2 U 3332, 2136,3445,0505,1174,4007,0700,0000,0000,1444 ; 6207 [BR]_[BR]*2, AC[BIN1] ;COMPUTE AC*4 ; 6208 =0 [BR]_[BR]+AC[BIN1], 2T, ;COMPUTE AC*5 U 2136, 3665,0551,0505,1274,4007,0700,0010,0000,1444 ; 6209 CALL [SBRL] ;COMPUTE AC*10 ; 6210 AC[BIN1]_[AR]+[BR], 3T, ;NEW BINARY RESULT U 2137, 0460,0113,0305,1174,4007,0701,0400,0000,1444 ; 6211 J/DBINLP ;DO NEXT DIGIT ; 6212 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 169 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- DECIMAL TO BINARY CONVERSION ; 6213 ;HERE IF NUMBER DOES NOT FIT IN ONE WORD ; 6214 ; 6215 =000 ; 6216 DBSLOW: [BR]_AC[BIN0], ;FETCH HIGH WORD U 0560, 0620,3771,0005,1276,6007,0701,0010,0000,1443 ; 6217 CALL [MULBY4] ;MULTIPLY BY 4 ; 6218 [ARX]_[ARX]+AC[BIN1], ;COMPUTE VALUE * 5 ; 6219 SKIP CRY1, 4T, ;SEE IF OVERFLOW U 0561, 2140,0551,0404,1274,4007,0562,0010,0000,1444 ; 6220 CALL [ADDCRY] ;GO ADD CARRY U 0565, 0600,0551,0505,1274,4007,0701,0000,0000,1443 ; 6221 =101 [BR]_[BR]+AC[BIN0] ;ADD IN HIGH WORD ; 6222 = U 0600, 0621,4443,0000,4174,4007,0700,0010,0000,0000 ; 6223 =000 CALL [DBLDBL] ;MAKE * 10 ; 6224 [ARX]_[ARX]+[AR], 3T, ;ADD IN NEW DIGIT ; 6225 SKIP CRY1, ;SEE IF OVERFLOW U 0601, 2140,0111,0304,4174,4007,0561,0010,0000,0000 ; 6226 CALL [ADDCRY] ;ADD IN THE CARRY U 0605, 3333,3440,0404,1174,4007,0700,0400,0000,1444 ; 6227 =101 AC[BIN1]_[ARX] ;PUT BACK ANSWER ; 6228 = ; 6229 AC[BIN0]_[BR], ; .. U 3333, 0002,3440,0505,1174,4004,1700,0400,0000,1443 ; 6230 RETURN [2] ;GO DO NEXT BYTE ; 6231 ; 6232 ;HERE TO DOUBLE BR!ARX ; 6233 =000 U 0620, 0621,4443,0000,4174,4007,0700,0010,0000,0000 ; 6234 MULBY4: CALL [DBLDBL] ;DOUBLE TWICE U 0621, 0622,0111,0505,4174,4007,0700,0000,0000,0000 ; 6235 DBLDBL: [BR]_[BR]+[BR] ;DOUBLE HIGH WORD FIRST ; 6236 ;(SO WE DON'T DOUBLE CARRY) ; 6237 [ARX]_[ARX]+[ARX], ;DOUBLE LOW WORD ; 6238 SKIP CRY1, 3T, ;SEE IF CARRY U 0622, 2140,0111,0404,4174,4007,0561,0010,0000,0000 ; 6239 CALL [ADDCRY] ;ADD IN CARRY U 0626, 0001,4443,0000,4174,4004,1700,0000,0000,0000 ; 6240 =110 RETURN [1] ;ALL DONE ; 6241 = ; 6242 ; 6243 ;HERE TO ADD THE CARRY ; 6244 =0 U 2140, 0004,4443,0000,4174,4004,1700,0000,0000,0000 ; 6245 ADDCRY: RETURN [4] ;NO CARRY U 2141, 3334,4551,0404,4374,0007,0700,0000,0037,7777 ; 6246 CLEAR [ARX]0 ;KEEP LOW WORD POSITIVE ; 6247 [BR]_[BR]+1, ;ADD CARRY U 3334, 0004,0111,0705,4174,4004,1700,0000,0000,0000 ; 6248 RETURN [4] ;ALL DONE ; 6249 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 170 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- DECIMAL TO BINARY CONVERSION ; 6250 ;HERE TO ABORT CONVERSION U 3335, 3336,3111,0306,4174,4007,0700,0000,0000,0000 ; 6251 DBABT: [BRX]_[BRX].OR.[AR] ;PUT BACK UNUSED LENGTH ; 6252 [PC]_[PC]-1, HOLD LEFT, ;DO NOT SKIP U 3336, 2143,1111,0701,4170,4007,0700,4000,0000,0000 ; 6253 J/DBDONE ;GO FIX UP SIGN COPY ; 6254 ; 6255 ;HERE AT END ; 6256 =0 ; 6257 DBXIT: [ARX]_AC[BIN1], ;GET LOW WORD U 2142, 3341,3771,0004,1276,6007,0701,0000,0000,1444 ; 6258 J/DBNEG ;GO NEGATE U 2143, 3337,3771,0003,1276,6007,0701,0000,0000,1444 ; 6259 DBDONE: [AR]_AC[BIN1] ;FETCH LOW WORD ; 6260 [BR]_AC[BIN0], 4T, ;GET HIGH WORD U 3337, 2144,3771,0005,1276,6007,0522,0000,0000,1443 ; 6261 SKIP DP0 ;WHAT SIGN U 2144, 3340,4551,0303,4374,0007,0700,0000,0037,7777 ; 6262 =0 CLEAR [AR]0, J/DBDN1 ;POSITIVE U 2145, 3340,3551,0303,4374,0007,0700,0000,0040,0000 ; 6263 [AR]_[AR].OR.#, #/400000, HOLD RIGHT U 3340, 2146,3440,0303,1174,4007,0700,0400,0000,1444 ; 6264 DBDN1: AC[BIN1]_[AR] ;STORE AC BACK ; 6265 =0 AC_[BRX] TEST, ;RETURN FLAGS U 2146, 2154,3770,0606,0174,4007,0520,0410,0000,0000 ; 6266 SKIP DP0, CALL [CLRBIN] ;CLEAR BIN IS S=0 U 2147, 0260,4221,0013,4170,4007,0700,0000,0000,0000 ; 6267 ENDSKP: END STATE, J/SKIP ;NO--ALL DONE ; 6268 U 3341, 3342,4551,0404,4374,0007,0700,0000,0037,7777 ; 6269 DBNEG: CLEAR ARX0 ;CLEAR EXTRA SIGN BIT ; 6270 [ARX]_-[ARX], 3T, ;NEGATE AND SEE IF U 3342, 2150,2441,0404,1174,4007,0621,4000,0000,1443 ; 6271 SKIP AD.EQ.0, AC[BIN0] ; ANY CARRY U 2150, 2153,7771,0003,1274,4007,0700,0000,0000,1443 ; 6272 =0 [AR]_.NOT.AC[BIN0], 2T, J/STAC34 ;NO CARRY ; 6273 [AR]_-AC[BIN0], 3T, ;CARRY U 2151, 2152,1771,0003,1274,4007,0621,4000,0000,1443 ; 6274 SKIP AD.EQ.0 ;SEE IF ALL ZERO U 2152, 2153,4571,1204,4374,4007,0700,0000,0040,0000 ; 6275 =0 [ARX]_[400000] XWD 0 ;MAKE COPY OF SIGN ; 6276 ; UNLESS HIGH WORD IS ZERO U 2153, 3343,3440,0303,1174,4007,0700,0400,0000,1443 ; 6277 STAC34: AC[BIN0]_[AR] ;PUT BACK ANSWER U 3343, 2143,3440,0404,1174,4007,0700,0400,0000,1444 ; 6278 AC[BIN1]_[ARX], J/DBDONE ; .. ; 6279 ; 6280 ;HELPER SUBROUTINE TO CLEAR AC[BIN0] AND AC[BIN1] IF S=0 ; 6281 ;CALL WITH: ; 6282 ; READ [BRX], SKIP DP0, CALL [CLRBIN] ; 6283 ;RETURNS 1 ALWAYS ; 6284 =0 U 2154, 3344,4223,0000,1174,4007,0700,0400,0000,1443 ; 6285 CLRBIN: AC[BIN0]_0, J/CLRB1 U 2155, 0001,4443,0000,4174,4004,1700,0000,0000,0000 ; 6286 RETURN [1] U 3344, 0001,4223,0000,1174,4004,1700,0400,0000,1444 ; 6287 CLRB1: AC[BIN1]_0, RETURN [1] ; 6288 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 171 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- BINARY TO DECIMAL CONVERSION ; 6289 .TOC "EXTEND -- BINARY TO DECIMAL CONVERSION" ; 6290 ; 6291 3743: ; 6292 BDEC: [BRX]_AC[DLEN], ;GET LENGTH AND FLAGS U 3743, 2156,3771,0006,1276,6007,0351,0000,0000,1443 ; 6293 SKIP FPD ;CONTINUE FROM INTERUPT? ; 6294 =0 [BRX]_[BRX].AND.#, ;JUST KEEP THE FLAGS ; 6295 #/777000, ; .. U 2156, 3345,4551,0606,4374,4007,0700,0000,0077,7000 ; 6296 J/BDEC0 ;COMPUTE NEW FLAGS U 2157, 3363,3771,0003,0276,6007,0700,0000,0000,0000 ; 6297 DOCVT: [AR]_AC, J/DOCVT1 ;ALL SET PRIOR TO TRAP U 3345, 3346,3771,0004,1276,6007,0701,0000,0000,1441 ; 6298 BDEC0: [ARX]_AC[1] ;GET LOW BINARY U 3346, 2125,3771,0003,0276,6007,0700,2000,0071,0024 ; 6299 [AR]_AC, SC_20. ;GET HIGH WORD, SET STEP COUNT ; 6300 =0* WORK[BDL]_[ARX], ;SAVE IN CASE OF ABORT U 2125, 2220,3333,0004,7174,4007,0700,0410,0000,0250 ; 6301 CALL [CLARX0] ;MAKE SURE BIT 0 IS OFF ; 6302 WORK[BDH]_[AR], ;SAVE HIGH WORD AND U 2127, 2160,3333,0003,7174,4007,0520,0400,0000,0247 ; 6303 SKIP DP0 ; TEST SIGN ; 6304 =0 ; 6305 BDEC1: [BRX]_0, HOLD LEFT, ;POSITIVE, CLEAR RH OF BRX U 2160, 2170,4221,0006,4170,4007,0700,0000,0000,0000 ; 6306 J/BDEC3 ;COMPUTE # OF DIGITS REQUIRED ; 6307 [BRX]_[BRX].OR.#, ;NEGATIVE, SET M U 2161, 2164,3551,0606,4374,0007,0700,0000,0010,0000 ; 6308 #/100000, HOLD RIGHT ; .. ; 6309 =0* U 2164, 3071,4551,0404,4374,0007,0700,0010,0037,7777 ; 6310 BDEC2: CLEAR ARX0, CALL [DBLNG1] ;NEGATE AR!ARX ; 6311 AC_[AR] TEST, ;PUT BACK ANSWER U 2166, 2162,3770,0303,0174,4007,0520,0400,0000,0000 ; 6312 SKIP DP0 ;IF STILL MINUS WE HAVE ; 6313 ; 1B0, AND NO OTHER BITS U 2162, 2160,3440,0404,1174,4007,0700,0400,0000,1441 ; 6314 =0 AC[1]_[ARX], J/BDEC1 ;POSITIVE NOW U 2163, 3347,0111,0704,4174,4007,0700,0000,0000,0000 ; 6315 [ARX]_[ARX]+1 ;JUST 1B0--ADD 1 ; 6316 [BRX]_[BRX].OR.#, ;AND REMEMBER THAT WE DID ; 6317 #/040000, HOLD RIGHT, ; IN LEFT HALF OF AC+3 U 3347, 2164,3551,0606,4374,0007,0700,0000,0004,0000 ; 6318 J/BDEC2 ; NEGATE IT AGAIN ; 6319 =0 U 2170, 0441,3771,0003,0276,6007,0700,0000,0000,0000 ; 6320 BDEC3: [AR]_AC, J/BDEC4 ;GET HIGH AC ; 6321 [BRX]_[BRX].OR.#, ;NO LARGER POWER OF 10 FITS ; 6322 #/200000, ;SET N FLAG (CLEARLY NOT 0) U 2171, 2174,3551,0606,4374,0007,0700,0000,0020,0000 ; 6323 HOLD RIGHT, J/BDEC5 ;SETUP TO FILL, ETC. ; 6324 =001 ; 6325 BDEC4: [ARX]_AC[1], ;GET HIGH WORD U 0441, 2214,3771,0004,1276,6007,0701,0010,0000,1441 ; 6326 CALL [BDSUB] ;SEE IF 10**C(BRX) FITS ; 6327 =011 [BRX]_[BRX]+1, ;NUMBER FITS--TRY A LARGER ONE U 0443, 2170,0111,0706,4174,4007,0630,2000,0060,0000 ; 6328 STEP SC, J/BDEC3 ;UNLESS WE ARE OUT OF NUMBERS U 0447, 2172,4553,0600,4374,4007,0331,0000,0077,7777 ; 6329 =111 TR [BRX], #/777777 ;ANY DIGITS REQUIRED? ; 6330 = ; 6331 =0 [BRX]_[BRX].OR.#, ;SOME DIGITS NEEDED, ; 6332 #/200000, HOLD RIGHT, ; SET N FLAG U 2172, 2174,3551,0606,4374,0007,0700,0000,0020,0000 ; 6333 J/BDEC5 ;CONTINUE BELOW U 2173, 2174,0111,0706,4174,4007,0700,0000,0000,0000 ; 6334 [BRX]_[BRX]+1 ;ZERO--FORCE AT LEAST 1 DIGIT ; 6335 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 172 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- BINARY TO DECIMAL CONVERSION ; 6336 =0 ; 6337 BDEC5: [AR]_AC[DLEN], ;GET LENGTH U 2174, 3460,3771,0003,1276,6007,0701,0010,0000,1443 ; 6338 CALL [CLRFLG] ;REMOVE FLAGS FROM AR U 2175, 3350,4221,0005,4174,4007,0700,0000,0000,0000 ; 6339 [BR]_0 U 3350, 3351,3441,0605,4170,4007,0700,0000,0000,0000 ; 6340 [BR]_[BRX], HOLD LEFT ;GET # OF DIGITS NEEDED ; 6341 [BR]_[BR]-[AR], ;NUMBER OF FILLS NEEDED U 3351, 2176,1111,0305,4174,4007,0421,4000,0000,0000 ; 6342 SKIP AD.LE.0 ;SEE IF ENOUGH ROOM ; 6343 =0 [ARX]_WORK[BDL], ;DOES NOT FIT IN SPACE ALLOWED U 2176, 3373,3771,0004,7274,4007,0701,0000,0000,0250 ; 6344 J/BDABT ; DO NOT DO CONVERT U 2177, 2200,3333,0006,4174,4007,0520,0000,0000,0000 ; 6345 READ [BRX], SKIP DP0 ;IS L ALREADY SET ; 6346 =0 AC[DLEN]_[BRX], ;NO--NO FILLERS U 2200, 2157,3440,0606,1174,4007,0700,0400,0000,1443 ; 6347 J/DOCVT ;GO CHURN OUT THE NUMBER ; 6348 ; 6349 ; 6350 ;HERE TO STORE LEADING FILLERS U 2201, 3352,3441,0603,4174,0007,0700,0000,0000,0000 ; 6351 [AR]_[BRX], HOLD RIGHT ;MAKE SURE THE FLAGS GET SET U 3352, 3353,3440,0303,1174,4007,0700,0400,0000,1443 ; 6352 AC[DLEN]_[AR] ; BEFORE WE PAGE FAIL U 3353, 3354,3771,0003,7274,4007,0701,0000,0000,0240 ; 6353 [AR]_WORK[E0] ;ADDRESS OF FILL (-1) ; 6354 [AR]_[AR]+1, LOAD VMA, ;FETCH FILLER U 3354, 3355,0111,0703,4174,4007,0700,0200,0004,0012 ; 6355 START READ U 3355, 3356,3771,0016,4365,5007,0700,0200,0000,0002 ; 6356 MEM READ, [T0]_MEM ;GET FILLER INTO AR U 3356, 3357,3771,0013,4370,4007,0700,0000,0000,0012 ; 6357 STATE_[EDIT-DST] ;PAGE FAILS BACKUP DST U 3357, 3360,2113,0507,7174,4007,0701,4400,0000,0242 ; 6358 WORK[SLEN]_[BR]-1, 3T ;SAVE # OF FILLERS U 3360, 3361,3441,1603,7174,4007,0700,0000,0000,0242 ; 6359 BDFILL: [AR]_[T0], WORK[SLEN] ;RESTORE FILL BYTE AND ; 6360 ; WARM UP RAM FILE ; 6361 [BR]_WORK[SLEN]+1, 3T, ;MORE FILLERS NEEDED? U 3361, 0640,0551,0705,7274,4007,0521,0000,0000,0242 ; 6362 SKIP DP0 U 0640, 2157,3440,0606,1174,4007,0700,0400,0000,1443 ; 6363 =000 AC[DLEN]_[BRX], J/DOCVT ;ALL DONE FIX FLAGS AND CONVERT ; 6364 =001 WORK[SLEN]_[BR], ;SAVE UPDATED LENGTH U 0641, 3450,3333,0005,7174,4007,0700,0410,0000,0242 ; 6365 CALL [PUTDST] ; AND STORE FILLER U 0647, 3362,2551,0705,1274,4007,0701,4000,0000,1443 ; 6366 =111 [BR]_AC[DLEN]-1 ;COUNT DOWN STRING LENGTH ; 6367 = U 3362, 3360,3440,0505,1174,4007,0700,0400,0000,1443 ; 6368 AC[DLEN]_[BR], J/BDFILL ;KEEP FILLING ; 6369 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 173 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- BINARY TO DECIMAL CONVERSION ; 6370 ;HERE TO STORE THE ANSWER ; 6371 ; 6372 DOCVT1: [ARX]_AC[1], ;GET LOW WORD U 3363, 3372,3771,0004,1276,6007,0701,0000,0000,1441 ; 6373 J/DOCVT2 ;ENTER LOOP FROM BOTTOM ; 6374 =010 ; 6375 BDECLP: [BR]_[BR]+1, ;COUNT DIGITS U 0562, 2214,0111,0705,4174,4007,0700,0010,0000,0000 ; 6376 CALL [BDSUB] ;KEEP SUBTRACTING 10**C(BRX) U 0566, 3364,3333,0003,7174,4007,0700,0400,0000,0247 ; 6377 =110 WORK[BDH]_[AR] ;SAVE BINARY ; 6378 = ; 6379 [AR]_[BR]+WORK[E1], ;OFFSET DIGIT U 3364, 0636,0551,0503,7274,4003,7701,0000,0000,0241 ; 6380 B DISP ;SEE WHICH MODE ; 6381 =1110 READ [AR], LOAD VMA, ;TRANSLATE, START READING TABLE U 0636, 2206,3333,0003,4174,4007,0700,0200,0004,0012 ; 6382 START READ, J/BDTBL ; GO GET ENTRY FROM TABLE U 0637, 0510,3333,0004,7174,4007,0700,0400,0000,0250 ; 6383 BDSET: WORK[BDL]_[ARX] ;SAVE LOW BINARY U 0510, 3450,3771,0013,4370,4007,0700,0010,0000,0012 ; 6384 =00* STATE_[EDIT-DST], CALL [PUTDST] U 0516, 3365,2551,0705,1274,4007,0701,4000,0000,1443 ; 6385 =11* [BR]_AC[DLEN]-1 ;UPDATE STRING LENGTH U 3365, 3366,3771,0003,7274,4007,0701,0000,0000,0247 ; 6386 [AR]_WORK[BDH] U 3366, 3367,3771,0004,7274,4007,0701,0000,0000,0250 ; 6387 [ARX]_WORK[BDL] U 3367, 2202,4553,0500,4374,4007,0321,0000,0004,0000 ; 6388 TL [BR], #/040000 ;ARE WE CONVERTING 1B0? U 2202, 3374,0111,0704,4174,4007,0700,0000,0000,0000 ; 6389 =0 [ARX]_[ARX]+1, J/BDCFLG ;YES--FIX THE NUMBER AND CLEAR FLAG U 2203, 3370,3440,0303,0174,4007,0700,0400,0000,0000 ; 6390 DOCVT3: AC_[AR] U 3370, 3371,3440,0404,1174,4007,0700,0400,0000,1441 ; 6391 AC[1]_[ARX] U 3371, 3372,3440,0505,1174,4007,0700,0400,0000,1443 ; 6392 AC[DLEN]_[BR] ;STORE BACK NEW STRING LENGTH U 3372, 2204,1111,0706,4174,4007,0531,4000,0000,0000 ; 6393 DOCVT2: [BRX]_[BRX]-1, 3T, SKIP DP18 U 2204, 0562,2441,0705,4174,4467,0701,4000,0003,0000 ; 6394 =0 [BR]_-1, SET FPD, 3T, J/BDECLP U 2205, 0260,4221,0013,4170,4467,0700,0000,0005,0000 ; 6395 END STATE, CLR FPD, J/SKIP ; 6396 ; 6397 ;HERE TO TRANSLATE 1 DIGIT ; 6398 =0 ; 6399 BDTBL: END STATE, ;DON'T CHANGE BYTE POINTER IF ; 6400 ; THIS PAGE FAILS U 2206, 3660,4221,0013,4170,4007,0700,0010,0000,0000 ; 6401 CALL [LOADAR] ;GO PUT WORD IN AR U 2207, 2210,4553,0600,4374,4007,0331,0000,0077,7777 ; 6402 TR [BRX], #/777777 ;LAST DIGIT U 2210, 0637,4221,0003,4174,0007,0700,0000,0000,0000 ; 6403 =0 [AR]_0, HOLD RIGHT, J/BDSET U 2211, 2212,4553,0600,4374,4007,0321,0000,0010,0000 ; 6404 TL [BRX], #/100000 ;AND NEGATIVE U 2212, 2213,3770,0303,4344,4007,0700,0000,0000,0000 ; 6405 =0 [AR]_[AR] SWAP ;LAST AND MINUS, USE LH U 2213, 0637,4221,0003,4174,0007,0700,0000,0000,0000 ; 6406 [AR]_0, HOLD RIGHT, J/BDSET ; 6407 U 3373, 1505,3771,0003,7274,4007,0701,0000,0000,0247 ; 6408 BDABT: [AR]_WORK[BDH], J/DAC ; 6409 ; 6410 BDCFLG: [BR]_[BR].AND.NOT.#, ;CLEAR FLAG THAT TELLS US ; 6411 #/040000, HOLD RIGHT, ; TO SUBTRACT 1 AND U 3374, 2203,5551,0505,4374,0007,0700,0000,0004,0000 ; 6412 J/DOCVT3 ; CONTINUE CONVERTING ; 6413 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 174 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- BINARY TO DECIMAL CONVERSION ; 6414 ;SUBROUTINE TO SUBRTACT A POWER OF 10 FROM AR!ARX ; 6415 ;CALL WITH: ; 6416 ; AR!ARX/ NUMBER TO BE CONVERTED ; 6417 ; BRX(RIGHT)/ POWER OF 10 ; 6418 ;RETURNS: ; 6419 ; 2 RESULT IS STILL POSITIVE ; 6420 ; 6 RESULT WOULD HAVE BEEN NEGATIVE (RESTORE DONE) ; 6421 =0 ; 6422 BDSUB: [T0]_[BRX]+#, 3T, WORK/DECLO, ;ADDRESS OF LOW WORD U 2214, 2165,0551,0616,4374,4007,0701,0000,0000,0344 ; 6423 J/BDSUB1 ;NO INTERRUPT U 2215, 2677,4443,0000,4174,4007,0700,0000,0000,0000 ; 6424 J/FIXPC ;INTERRUPT ; 6425 =0* ; 6426 BDSUB1: [T1]_[T0], LOAD VMA, ;PUT IN VMA, U 2165, 2220,3441,1617,4174,4007,0700,0210,0000,0010 ; 6427 CALL [CLARX0] ;FIX UP SIGN OF LOW WORD ; 6428 [ARX]_[ARX]-RAM, 3T, ;SUBTRACT U 2167, 2216,1551,0404,6274,4007,0561,4000,0000,0000 ; 6429 SKIP CRY1 ;SEE IF OVERFLOW U 2216, 2217,1111,0703,4174,4007,0700,4000,0000,0000 ; 6430 =0 [AR]_[AR]-1 ;PROCESS CARRY U 2217, 3375,0551,0616,4374,4007,0701,0000,0000,0373 ; 6431 [T0]_[BRX]+#, 3T, WORK/DECHI ;ADDRESS OF HIGH WORD U 3375, 3376,3333,0016,4174,4007,0700,0200,0000,0010 ; 6432 READ [T0], LOAD VMA ;PLACE IN VMA ; 6433 [AR]_[AR]-RAM, 4T, ;SUBTRACT U 3376, 2220,1551,0303,6274,4007,0522,4000,0000,0000 ; 6434 SKIP DP0 ;SEE IF IT FIT ; 6435 =0 ; 6436 CLARX0: CLEAR ARX0, ;IT FIT, KEEP LOW WORD + U 2220, 0002,4551,0404,4374,0004,1700,0000,0037,7777 ; 6437 RETURN [2] ; AND RETURN U 2221, 3377,0551,0303,6274,4007,0700,0000,0000,0000 ; 6438 [AR]_[AR]+RAM ;RESTORE U 3377, 3400,3333,0017,4174,4007,0700,0200,0000,0010 ; 6439 READ [T1], LOAD VMA U 3400, 2222,0551,0404,6274,4007,0561,0000,0000,0000 ; 6440 [ARX]_[ARX]+RAM, 3T, SKIP CRY1 ; 6441 =0 ; 6442 BDSUB2: CLEAR ARX0, ;KEEP LOW WORD + U 2222, 0006,4551,0404,4374,0004,1700,0000,0037,7777 ; 6443 RETURN [6] ;RETURN OVERFLOW ; 6444 [AR]_[AR]+1, ;ADD BACK THE CARRY U 2223, 2222,0111,0703,4174,4007,0700,0000,0000,0000 ; 6445 J/BDSUB2 ;COMPLETE SUBTRACT ; 6446 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 175 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- EDIT -- MAIN LOOP ; 6447 .TOC "EXTEND -- EDIT -- MAIN LOOP" ; 6448 ; 6449 ;HERE FOR EDIT INSTRUCTION ; 6450 ;CALL WITH: ; 6451 ; AR/ E0 ADDRESS OF FILL, FLOAT, AND MESSAGE TABLE ; 6452 ; BR/ E1 TRANSLATE TABLE ; 6453 ; ; 6454 3741: ; 6455 EDIT: VMA_[AR]+1, START READ, ;FIRST GET FILL BYTE U 3741, 3456,0111,0703,4170,4007,0700,0210,0004,0012 ; 6456 CALL [GTFILL] ;GO GET IT U 3751, 2111,3771,0006,0276,6007,0700,0000,0000,0000 ; 6457 3751: [BRX]_AC ;GET PATTERN POINTER ; 6458 =0** TL [BRX], #/047777, ;MAKE SURE SECTION 0 U 2111, 3556,4553,0600,4374,4007,0321,0010,0004,7777 ; 6459 CALL [BITCHK] ; .. U 2115, 3401,3443,0600,4174,4007,0700,0200,0004,0012 ; 6460 EDITLP: VMA_[BRX], START READ ;FETCH PATTERN WORD U 3401, 3402,4221,0013,4170,4007,0700,0000,0000,0000 ; 6461 END STATE ;NO SPECIAL PAGE FAIL ACTION U 3402, 2224,3770,0605,4344,4007,0700,0000,0000,0000 ; 6462 [BR]_[BRX] SWAP ;GET PBN IN BITS 20 & 21 ; 6463 =0 [BR]_[BR]*4, ; .. U 2224, 3660,0115,0505,4174,4007,0700,0010,0000,0000 ; 6464 CALL [LOADAR] ;GET PATTERN WORD U 2225, 0654,3333,0005,4174,4003,1701,0000,0000,0000 ; 6465 READ [BR], 3T, DISP/DP LEFT ; 6466 =1100 U 0654, 2226,3770,0303,4344,4007,0700,2000,0071,0007 ; 6467 [AR]_[AR] SWAP, SC_7, J/MOVPAT ;(0) BITS 0-8 U 0655, 2227,3770,0303,4344,4007,0700,0000,0000,0000 ; 6468 [AR]_[AR] SWAP, J/MSKPAT ;(1) BITS 9-17 U 0656, 2226,3447,0303,4174,4007,0700,2000,0071,0006 ; 6469 [AR]_[AR]*.5, SC_6, J/MOVPAT ;(2) BITS 18-27 U 0657, 3403,4551,0303,4374,4007,0700,0000,0000,0777 ; 6470 [AR]_[AR].AND.#, #/777, J/EDISP ;(3) BITS 28-35 ; 6471 =0 U 2226, 2226,3447,0303,4174,4007,0630,2000,0060,0000 ; 6472 MOVPAT: [AR]_[AR]*.5, STEP SC, J/MOVPAT ;SHIFT OVER U 2227, 3403,4551,0303,4374,4007,0700,0000,0000,0777 ; 6473 MSKPAT: [AR]_[AR].AND.#, #/777 ; 6474 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 176 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- EDIT -- MAIN LOOP ; 6475 ;HERE WITH PATTERN BYTE RIGHT ADJUSTED IN AR U 3403, 2230,3447,0305,4174,4007,0700,2000,0071,0002 ; 6476 EDISP: [BR]_[AR]*.5, SC_2 ;SHIFT OVER ; 6477 =0 U 2230, 2230,3447,0505,4174,4007,0630,2000,0060,0000 ; 6478 EDISP1: [BR]_[BR]*.5, STEP SC, J/EDISP1 U 2231, 0661,3333,0005,4174,4003,5701,0000,0000,0000 ; 6479 READ [BR], 3T, DISP/DP ;LOOK AT HIGH 3 BITS ; 6480 =0001 ;(0) OPERATE GROUP ; 6481 [AR]-#, #/5, 4T, ; SEE IF 0-4 U 0661, 2232,1553,0300,4374,4007,0532,4000,0000,0005 ; 6482 SKIP DP18, J/EDOPR ; 6483 ;(1) MESSAGE BYTE ; 6484 READ [BRX], SKIP DP0, U 0663, 2250,3333,0006,4174,4007,0520,0000,0000,0000 ; 6485 J/EDMSG ; 6486 ;(2) UNDEFINED U 0665, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6487 J/EDNOP ; 6488 ;(3) UNDEFINED U 0667, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6489 J/EDNOP ; 6490 ;(4) UNDEFINED U 0671, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6491 J/EDNOP ; 6492 ;(5) SKIP IF M SET ; 6493 TL [BRX], #/100000, U 0673, 2254,4553,0600,4374,4007,0321,0000,0010,0000 ; 6494 J/EDSKP ; 6495 ;(6) SKIP IF N SET ; 6496 TL [BRX], #/200000, U 0675, 2254,4553,0600,4374,4007,0321,0000,0020,0000 ; 6497 J/EDSKP ; 6498 ;(7) SKIP ALWAYS U 0677, 2254,4443,0000,4174,4007,0700,0000,0000,0000 ; 6499 J/EDSKP ; 6500 ; 6501 .TOC "EXTEND -- EDIT -- DECODE OPERATE GROUP" ; 6502 ; 6503 ;HERE FOR OPERATE GROUP. SKIP IF IN RANGE ; 6504 =0 U 2232, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6505 EDOPR: J/EDNOP ;OUT OF RANGE U 2233, 0710,3333,0003,4174,4003,5701,0000,0000,0000 ; 6506 READ [AR], 3T, DISP/DP ;DISPATCH ON TYPE U 0710, 3404,0111,0701,4174,4007,0700,0000,0000,0000 ; 6507 =1000 [PC]_[PC]+1, J/EDSTOP ;(0) STOP EDIT ; 6508 STATE_[EDIT-SRC], ;(1) SELECT SOURCE BYTE U 0711, 2240,3771,0013,4370,4007,0700,0000,0000,0011 ; 6509 J/EDSEL ; 6510 READ [BRX], SKIP DP0, ;(2) START SIGNIFICANCE U 0712, 0006,3333,0006,4174,4007,0520,0000,0000,0000 ; 6511 J/EDSSIG ; 6512 [BRX]_[BRX].AND.#, ;(3) FIELD SEPERATOR ; 6513 #/77777, HOLD RIGHT, U 0713, 3423,4551,0606,4374,0007,0700,0000,0007,7777 ; 6514 J/EDNOP U 0714, 0715,3771,0005,1276,6007,0701,0000,0000,1443 ; 6515 [BR]_AC[MARK] ;(4) EXCHANGE MARK AND DEST ; 6516 VMA_[BR], START READ, U 0715, 2236,3443,0500,4174,4007,0700,0200,0004,0012 ; 6517 J/EDEXMD ; 6518 = ; 6519 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 177 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- EDIT -- STOP EDIT ; 6520 .TOC "EXTEND -- EDIT -- STOP EDIT" ; 6521 ; 6522 ;HERE TO END AN EDIT OPERATION. PC IS SET TO SKIP IF NORMAL END ; 6523 ; OR NON-SKIP IF ABORT ; 6524 EDSTOP: [BR]_.NOT.[BRX], ;AD WILL NOT DO D.AND.NOT.A U 3404, 3405,7441,0605,4174,4007,0700,1000,0071,0010 ; 6525 FE_S#, S#/10 ;PRESET FE U 3405, 3406,3441,0603,4174,4007,0701,1000,0043,0000 ; 6526 [AR]_[BRX], 3T, FE_FE+P ;MOVE POINTER, UPBATE PBN ; 6527 [BR].AND.#, 3T, ;WAS OLD NUMBER 3? U 3406, 2234,4553,0500,4374,4007,0321,0000,0003,0000 ; 6528 #/030000, SKIP ADL.EQ.0 ; .. ; 6529 =0 U 2234, 1515,3770,0303,4334,4017,0700,0000,0041,0000 ; 6530 EDSTP1: [AR]_P, J/STAC ;NO--ALL DONE ; 6531 [AR]_[AR]+1, ;YES--BUMP WORD # ; 6532 FE_FE.AND.S#, S#/0700, ;KEEP ONLY FLAG BITS U 2235, 2234,0111,0703,4174,4007,0700,1000,0051,0700 ; 6533 J/EDSTP1 ;GO STOP EDIT ; 6534 ; 6535 .TOC "EXTEND -- EDIT -- START SIGNIFICANCE" ; 6536 ; 6537 ;HERE WITH DST POINTER IN AR ; 6538 =110 U 0006, 3412,4443,0000,4174,4007,0700,0010,0000,0000 ; 6539 EDSSIG: CALL [EDFLT] ;STORE FLT CHAR U 0007, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6540 J/EDNOP ;DO NEXT PATTERN BYTE ; 6541 ; 6542 .TOC "EXTEND -- EDIT -- EXCHANGE MARK AND DESTINATION" ; 6543 ; 6544 ;HERE WITH ADDRESS OF MARK POINTER IN BR ; 6545 =0 ; 6546 EDEXMD: Q_AC[DSTP], ;GET DEST POINTER U 2236, 3660,3772,0000,1275,5007,0701,0010,0000,1444 ; 6547 CALL [LOADAR] ;GO PUT MARK IN AR U 2237, 3407,4443,0000,4174,4007,0700,0200,0003,0002 ; 6548 START WRITE ;START WRITE. SEPERATE STEP TO AVOID ; 6549 ; PROBLEM ON DPM5 U 3407, 3410,3223,0000,4174,4007,0701,0200,0000,0002 ; 6550 MEM WRITE, MEM_Q ;PUT OLD DEST IN MARK U 3410, 3423,3440,0303,1174,4007,0700,0400,0000,1444 ; 6551 AC[DSTP]_[AR], J/EDNOP ;PUT BACK DEST POINTER ; 6552 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 178 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- EDIT -- PROCESS SOURCE BYTE ; 6553 .TOC "EXTEND -- EDIT -- PROCESS SOURCE BYTE" ; 6554 ; 6555 =0* ; 6556 EDSEL: [AR]_AC[SRCP], ;PICK UP SRC POINTER U 2240, 2275,3771,0003,1276,6007,0701,0010,0000,1441 ; 6557 CALL [GETSRC] ;GET SOURCE BYTE U 2242, 0700,3447,0303,7174,4007,0700,0000,0000,0241 ; 6558 [AR]_[AR]*.5, WORK[E1] ;PREPARE TO TRANSLATE ; 6559 =000 [AR]_[AR]+WORK[E1], ;GO TRANSLATE BY HALFWORDS U 0700, 3443,0551,0303,7274,4007,0700,0010,0000,0241 ; 6560 2T, CALL [TRNAR] ; .. ; 6561 =010 ; 6562 EDFILL: READ [AR], ;(2) NO SIGNIFICANCE, GO FILL ; 6563 SKIP AD.EQ.0, ; SEE IF ANY FILLER U 0702, 2244,3333,0003,4174,4007,0621,0000,0000,0000 ; 6564 J/EDFIL1 ; GO TO IT ; 6565 STATE_[EDIT-SRC], ;(3) SIG START, DO FLOAT CHAR U 0703, 0246,3771,0013,4370,4007,0700,0000,0000,0011 ; 6566 J/EDSFLT U 0704, 3404,4443,0000,4174,4007,0700,0000,0000,0000 ; 6567 =100 J/EDSTOP ;(4) ABORT ; 6568 =101 ; 6569 EDSPUT: STATE_[EDIT-S+D], ;(5) NORMAL, STORE AT DST U 0705, 3450,3771,0013,4370,4007,0700,0010,0000,0013 ; 6570 CALL [PUTDST] ; .. ; 6571 =111 U 0707, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6572 J/EDNOP ;(7) BYTE STORED ; 6573 = ; 6574 ; 6575 ;HERE TO COMPLETE STORING FILL ; 6576 =0 U 2244, 0705,4443,0000,4174,4007,0700,0000,0000,0000 ; 6577 EDFIL1: J/EDSPUT ;STORE FILLER U 2245, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6578 J/EDNOP ;NO FILLER TO STORE ; 6579 ; 6580 ;HERE TO DO FLOAT BYTE ; 6581 =110 ; 6582 EDSFLT: WORK[FSIG]_[ARX], ;SAVE SIG CHAR U 0246, 3412,3333,0004,7174,4007,0700,0410,0000,0246 ; 6583 CALL [EDFLT] ;STORE FLOAT CHAR U 0247, 3411,3771,0003,7274,4007,0701,0000,0000,0246 ; 6584 [AR]_WORK[FSIG] ;RESTORE CHAR ; 6585 [AR]_[AR].AND.# CLR LH, ;JUST KEEP THE BYTE IN CASE ; 6586 #/77777, ; DEST BYTE .GT. 15 BITS U 3411, 0705,4251,0303,4374,4007,0700,0000,0007,7777 ; 6587 J/EDSPUT ;GO STORE CHAR WHICH STARTED THIS ALL ; 6588 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 179 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- EDIT -- PROCESS SOURCE BYTE ; 6589 ;SUBRUTINE TO PROCESS FLOAT CHAR ; 6590 ;CALL WITH: ; 6591 ; AR/ POINTER TO STORE @ MARK ; 6592 ;RETURN 7 WITH FLOAT STORED U 3412, 3413,3771,0005,1276,6007,0701,0000,0000,1443 ; 6593 EDFLT: [BR]_AC[MARK] ;ADDRESS OF MARK POINTER U 3413, 3414,3443,0500,4174,4007,0700,0200,0003,0012 ; 6594 VMA_[BR], START WRITE ;READY TO STORE U 3414, 3415,3771,0005,1276,6007,0701,0000,0000,1444 ; 6595 [BR]_AC[DSTP] ;GET DST POINTER U 3415, 2246,3333,0005,4175,5007,0701,0200,0000,0002 ; 6596 MEM WRITE, MEM_[BR] ;STORE POINTER ; 6597 =0 [AR]_0 XWD [2], ;FETCH FLOAT CHAR U 2246, 3417,4751,1203,4374,4007,0700,0010,0000,0002 ; 6598 CALL [EDBYTE] ;GET TBL BYTE ; 6599 MEM READ, [AR]_MEM, ;GET FLOAT CHAR U 2247, 0740,3771,0003,4365,5007,0621,0200,0000,0002 ; 6600 SKIP AD.EQ.0 ;SEE IF NULL ; 6601 =000 ; 6602 [FLG]_[FLG].OR.#, ;REMEMBER TO BACKUP DST POINTER ; 6603 STATE/EDIT-DST, ; WILL ALSO BACKUP SRC IF CALLED ; 6604 HOLD LEFT, ; FROM SELECT U 0740, 3450,3551,1313,4370,4007,0700,0010,0000,0012 ; 6605 CALL [PUTDST] ; STORE FLOAT ; 6606 =001 [BRX]_[BRX].OR.#, #/400000, U 0741, 3416,3551,0606,4374,0007,0700,0000,0040,0000 ; 6607 HOLD RIGHT, J/EDFLT1 ;NULL ; 6608 =110 [BRX]_[BRX].OR.#, #/400000, U 0746, 3416,3551,0606,4374,0007,0700,0000,0040,0000 ; 6609 HOLD RIGHT, J/EDFLT1 ;MARK STORED ; 6610 = ; 6611 EDFLT1: AC_[BRX], ;SAVE FLAGS SO WE DON'T ; 6612 ;TRY TO DO THIS AGAIN IF ; 6613 ;NEXT STORE PAGE FAILS U 3416, 0007,3440,0606,0174,4004,1700,0400,0000,0000 ; 6614 RETURN [7] ;AND RETURN ; 6615 ; 6616 .TOC "EXTEND -- EDIT -- MESSAGE BYTE" ; 6617 ; 6618 ;HERE WITH SKIP ON S ; 6619 =0 ; 6620 EDMSG: [AR]_WORK[FILL], ;GET FILL BYTE ; 6621 SKIP AD.EQ.0, 4T, ;SEE IF NULL U 2250, 0760,3771,0003,7274,4007,0622,0000,0000,0244 ; 6622 J/EDMSG1 ;GO STORE ; 6623 [AR]_[AR].AND.# CLR LH, ;GET OFFSET INTO TABLE U 2251, 2252,4251,0303,4374,4007,0700,0000,0000,0077 ; 6624 #/77 ; 6625 =0 [AR]_[AR]+1, WORK[E0], ;PLUS 1 U 2252, 3417,0111,0703,7174,4007,0700,0010,0000,0240 ; 6626 CALL [EDBYTE] ;GET TBL BYTE U 2253, 0760,3771,0003,4365,5007,0700,0200,0000,0002 ; 6627 MEM READ, [AR]_MEM ;FROM MEMORY ; 6628 =000 ; 6629 EDMSG1: STATE_[EDIT-DST], ;WHAT TO DO ON PAGE FAILS U 0760, 3450,3771,0013,4370,4007,0700,0010,0000,0012 ; 6630 CALL [PUTDST] ;STORE MESSAGE BYTE U 0761, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6631 =001 J/EDNOP ;NULL FILLER U 0766, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6632 =110 J/EDNOP ;NEXT BYTE ; 6633 = ; 6634 U 3417, 3420,0551,0303,7274,4007,0701,0000,0000,0240 ; 6635 EDBYTE: [AR]_[AR]+WORK[E0] ;GET OFFSET INTO TABLE ; 6636 VMA_[AR], START READ, ;START MEMORY CYCLE U 3420, 0001,3443,0300,4174,4004,1700,0200,0004,0012 ; 6637 RETURN [1] ;RETURN TO CALLER ; 6638 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 180 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- EDIT -- SKIP ; 6639 .TOC "EXTEND -- EDIT -- SKIP" ; 6640 ; 6641 =0 ; 6642 ;HERE TO SKIP ALWAYS ; 6643 EDSKP: [AR]_[AR].AND.#, #/77, ;JUST KEEP SKIP DISTANCE U 2254, 3421,4551,0303,4374,4007,0700,0000,0000,0077 ; 6644 J/EDSKP1 ;CONTINUE BELOW ; 6645 ;HERE IF WE DO NOT WANT TO SKIP U 2255, 3423,4443,0000,4174,4007,0700,0000,0000,0000 ; 6646 J/EDNOP U 3421, 3422,0115,0703,4174,4007,0700,0000,0000,0000 ; 6647 EDSKP1: [AR]_([AR]+1)*2 ;GIVE 1 EXTRA SKIP ; 6648 READ [AR], SCAD/A*2, ;PUT THE ADJUSTMENT ; 6649 SCADA/BYTE5, 3T, LOAD SC, ; THE SC U 3422, 3424,3333,0003,4174,4007,0701,2000,0007,0000 ; 6650 J/EDNOP1 ;JOIN MAIN LOOP ; 6651 ; 6652 ; 6653 .TOC "EXTEND -- EDIT -- ADVANCE PATTERN POINTER" ; 6654 U 3423, 3424,4443,0000,4174,4007,0700,2000,0071,0000 ; 6655 EDNOP: SC_0 ;NO SKIP U 3424, 3425,3333,0006,4174,4007,0701,1000,0073,0000 ; 6656 EDNOP1: READ [BRX], 3T, FE_P ;PUT PBN IN FE U 3425, 3426,4443,0000,4174,4007,0700,1000,0051,0030 ; 6657 FE_FE.AND.S#, S#/30 ;JUST BYTE # U 3426, 3427,4443,0000,4174,4007,0700,1000,0040,0000 ; 6658 FE_FE+SC ;ADD IN ANY SKIP DISTANCE U 3427, 3430,4443,0000,4174,4007,0700,1000,0041,0010 ; 6659 FE_FE+S#, S#/10 ;BUMP PBN ; 6660 [AR]_FE, ;GET NUMBER OF WORDS U 3430, 3431,3777,0003,4334,4057,0700,2000,0041,0000 ; 6661 LOAD SC ;PUT MSB WHERE IT CAN BE TESTED ; 6662 ; QUICKLY ; 6663 [AR]_[AR].AND.# CLR LH, ;KEEP ONLY 1 COPY U 3431, 2256,4251,0303,4374,4007,0630,0000,0000,0170 ; 6664 #/170, SKIP/SC ; .. ; 6665 =0 ; 6666 EDN1A: [AR]_[AR]*.5, SC_0, U 2256, 2260,3447,0303,4174,4007,0700,2000,0071,0000 ; 6667 J/EDNOP2 ;READY TO SHIFT OFF BYTE WITHIN ; 6668 ; WORD ; 6669 [AR]_[AR].OR.#, #/200, ;GET THE SIGN BIT OF THE FE ; 6670 HOLD LEFT, ; INTO THE AR. ONLY HAPPENS ON U 2257, 2256,3551,0303,4370,4007,0700,0000,0000,0200 ; 6671 J/EDN1A ; SKP 76 OR SKP 77 ; 6672 =0 U 2260, 2260,3447,0303,4174,4007,0630,2000,0060,0000 ; 6673 EDNOP2: [AR]_[AR]*.5, STEP SC, J/EDNOP2 ; 6674 [BRX]_[BRX]+[AR], ;UPDATE WORD ADDRESS U 2261, 3432,0111,0306,4170,4007,0700,0000,0000,0000 ; 6675 HOLD LEFT U 3432, 3433,3770,0303,4334,4017,0700,0000,0041,0000 ; 6676 [AR]_P ;PUT PBN BACK IN BRX ; 6677 [BRX]_[BRX].AND.#, ;JUST KEEP FLAGS ; 6678 #/700000, ; .. U 3433, 3434,4551,0606,4374,0007,0700,0000,0070,0000 ; 6679 HOLD RIGHT ; 6680 [AR]_[AR].AND.#, ;JUST KEEP PBN U 3434, 3435,4551,0303,4374,4007,0700,0000,0003,0000 ; 6681 #/030000 ; 6682 [BRX]_[BRX].OR.[AR], ;FINAL ANSWER U 3435, 3436,3111,0306,4174,0007,0700,0000,0000,0000 ; 6683 HOLD RIGHT U 3436, 2115,3440,0606,0174,4007,0700,0400,0000,0000 ; 6684 AC_[BRX], J/EDITLP ;DO NEXT FUNCTION ; 6685 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 181 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND SUBROUTINES -- FILL OUT DESTINATION ; 6686 .TOC "EXTEND SUBROUTINES -- FILL OUT DESTINATION" ; 6687 ; 6688 ;CALL WITH ; 6689 ; AC[DLEN]/ NEGATIVE NUMBER OF BYTES LEFT IN DEST ; 6690 ; FILL/ FILL BYTE ; 6691 ; RETURN [2] WITH FILLERS STORED ; 6692 ; ; 6693 ;NOTE: THIS ROUTINE NEED NOT TEST FOR INTERRUPTS ON EACH BYTE ; 6694 ; BECAUSE EVERY BYTE STORE DOES A MEMORY READ. ; 6695 ; ; 6696 =01* ; 6697 MOVF1: [AR]_WORK[FILL], 2T, ;GET FILL BYTE U 0332, 3450,3771,0003,7274,4007,0700,0010,0000,0244 ; 6698 CALL [PUTDST] ;PLACE IN DEST U 0336, 3437,3771,0003,1276,6007,0701,0000,0000,1443 ; 6699 [AR]_AC[DLEN] ;AMOUNT LEFT ; 6700 AC[DLEN]_[AR]+1, 3T, ;STORE UPDATED LEN U 3437, 2262,0113,0703,1174,4007,0521,0400,0000,1443 ; 6701 SKIP DP0 ; AND SEE IF DONE U 2262, 0002,4443,0000,4174,4004,1700,0000,0000,0000 ; 6702 =0 RETURN [2] ;DONE U 2263, 0332,4443,0000,7174,4007,0700,0000,0000,0244 ; 6703 MOVFIL: WORK[FILL], J/MOVF1 ;DO ANOTHER BYTE ; 6704 ;ENTERING HERE SAVES 150NS ; 6705 ; PER BYTE BUT COSTS 300NS ; 6706 ; PER FIELD MOVED. I ASSUME (BUT DO ; 6707 ; NOT KNOW) THAT THIS SPEEDS ; 6708 ; THINGS UP. ; 6709 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 182 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND SUBROUTINES -- GET MODIFIED SOURCE BYTE ; 6710 .TOC"EXTEND SUBROUTINES -- GET MODIFIED SOURCE BYTE" ; 6711 ; 6712 ;CALL WITH: ; 6713 ;SLEN = MINUS LENGTH OF STRING ; 6714 ;MSK = MASK FOR BYTE SIZE (1 IF BIT MUST BE ZERO) ; 6715 ;E1 = EFFECTIVE ADDRESS OF OPERATION WORD (SIGN EXTENDED IF OFFSET) ; 6716 ; [AR]_WORK[SLEN]+1, CALL [SRCMOD] ; 6717 ;RETURNS: ; 6718 ; 1 LENGTH EXHAUSTED ; 6719 ; 2 (EDIT ONLY) NO SIGNIFICANCE ; 6720 ; 3 (EDIT ONLY) SIGNIFICANCE START: ; 6721 ; 4 ABORT: OUT OF RANGE OR TRANSLATE FAILURE ; 6722 ; 5 NORMAL: BYTE IN AR ; 6723 ; ; 6724 ;DROM B SET AS FOLLOWS: ; 6725 ; 0 TRANSLATE ; 6726 ; 1 OFFSET ; 6727 ; 2 EDIT ; 6728 ; 4 CVTDBT ; 6729 =00 ; 6730 SRCMOD: WORK[SLEN]_[AR], ;PUT BACK SOURCE LENGTH ; 6731 SKIP DP0, ;SEE IF DONE U 1074, 2274,3333,0003,7174,4007,0520,0410,0000,0242 ; 6732 CALL [GSRC] ;GET A SOURCE BYTE U 1075, 0001,4221,0013,4170,4004,1700,0000,0000,0000 ; 6733 END STATE, RETURN [1] ;DONE U 1076, 0716,4443,0000,7174,4003,7700,0000,0000,0241 ; 6734 WORK[E1], B DISP ;OFFSET OR TRANSLATE? ; 6735 = U 0716, 3442,3447,0303,4174,4007,0700,0000,0000,0000 ; 6736 =1110 [AR]_[AR]*.5, J/XLATE ;TRANSLATE U 0717, 3440,3770,0303,7174,0007,0700,0000,0000,0241 ; 6737 FIX [AR] SIGN, WORK[E1] ;IF WE ARE PROCESSING FULL WORD ; 6738 ; BYTES, AND THEY ARE NEGATIVE, ; 6739 ; AND THE OFFSET IS POSITIVE THEN ; 6740 ; WE HAVE TO MAKE BITS -1 AND -2 ; 6741 ; COPIES OF THE SIGN BIT. U 3440, 3441,0551,0303,7274,4007,0700,0000,0000,0241 ; 6742 [AR]_[AR]+WORK[E1], 2T ;OFFSET ; 6743 [AR].AND.WORK[MSK], ;VALID BYTE? ; 6744 SKIP AD.EQ.0, 4T, ;SKIP IF OK U 3441, 0004,4553,0300,7274,4004,1622,0000,0000,0243 ; 6745 RETURN [4] ;RETURN 4 IF BAD, 5 IF OK ; 6746 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 183 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND SUBROUTINES -- TRANSLATE ; 6747 .TOC "EXTEND SUBROUTINES -- TRANSLATE" ; 6748 ; 6749 ;HERE WITH BYTE IN AR 1-36. FETCH TABLE ENTRY. U 3442, 3443,0551,0303,7274,4007,0701,0000,0000,0241 ; 6750 XLATE: [AR]_[AR]+WORK[E1] ;COMPUTE ADDRESS ; 6751 TRNAR: READ [AR], LOAD VMA, ;FETCH WORD U 3443, 2264,3333,0003,4174,4007,0700,0200,0004,0012 ; 6752 START READ ; .. ; 6753 =0 [AR]_[AR]*2, ;GET BACK LSB ; 6754 ;BIT 36 IS NOT PRESERVED ; 6755 ; BY PAGE FAILS U 2264, 3661,3445,0303,4174,4007,0700,0010,0000,0000 ; 6756 CALL [LOADARX] ;PUT ENTRY IN ARX U 2265, 2266,4553,0300,4374,4007,0331,0000,0000,0001 ; 6757 TR [AR], #/1 ;WHICH HALF? ; 6758 =0 ; 6759 XLATE1: [AR]_[ARX], 3T, ;RH -- COPY TO AR ; 6760 DISP/DP LEFT, ;DISPATCH ON CODE U 2266, 0721,3441,0403,4174,4003,1701,0000,0000,0000 ; 6761 J/TRNFNC ;DISPATCH TABLE ; 6762 [ARX]_[ARX] SWAP, ;LH -- FLIP AROUND U 2267, 2266,3770,0404,4344,4007,0700,0000,0000,0000 ; 6763 J/XLATE1 ;START SHIFT ; 6764 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 184 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND SUBROUTINES -- TRANSLATE ; 6765 ;HERE ON TRANSLATE OPERATION TO PERFORM FUNCTIONS REQUIRED BY ; 6766 ; THE 3 HIGH ORDER BITS OF THE TRANSLATE FUNCTION HALFWORD. WE ; 6767 ; DISPATCH ON FUNCTION AND HAVE: ; 6768 ; BRX/ FLAGS ; 6769 ; ARX/ TABLE ENTRY IN RH ; 6770 ; ; 6771 =0001 ; 6772 ;(0) NOP ; 6773 TRNFNC: READ [BRX], SKIP DP0, ;S FLAG ALREADY SET? U 0721, 2270,3333,0006,4174,4007,0520,0000,0000,0000 ; 6774 J/TRNRET ; .. ; 6775 ;(1) ABORT U 0723, 0004,4443,0000,4174,4004,1700,0000,0000,0000 ; 6776 RETURN [4] ; 6777 ;(2) CLEAR M FLAG ; 6778 [BRX]_[BRX].AND.NOT.#, ; 6779 #/100000, HOLD RIGHT, U 0725, 0721,5551,0606,4374,0007,0700,0000,0010,0000 ; 6780 J/TRNFNC ; 6781 ;(3) SET M FLAG ; 6782 [BRX]_[BRX].OR.#, ; 6783 #/100000, HOLD RIGHT, U 0727, 0721,3551,0606,4374,0007,0700,0000,0010,0000 ; 6784 J/TRNFNC ; 6785 ;(4) SET N FLAG ; 6786 TRNSIG: [BRX]_[BRX].OR.#, ; 6787 #/200000, HOLD RIGHT, U 0731, 0721,3551,0606,4374,0007,0700,0000,0020,0000 ; 6788 J/TRNFNC ; 6789 ;(5) SET N FLAG THEN ABORT ; 6790 [BRX]_[BRX].OR.#, ; 6791 #/200000, HOLD RIGHT, U 0733, 0004,3551,0606,4374,0004,1700,0000,0020,0000 ; 6792 RETURN [4] ; 6793 ;(6) CLEAR M THEN SET N ; 6794 [BRX]_[BRX].AND.NOT.#, ; 6795 #/100000, HOLD RIGHT, U 0735, 0731,5551,0606,4374,0007,0700,0000,0010,0000 ; 6796 J/TRNSIG ; 6797 ;(7) SET N AND M ; 6798 [BRX]_[BRX].OR.#, ; 6799 #/300000, HOLD RIGHT, U 0737, 0721,3551,0606,4374,0007,0700,0000,0030,0000 ; 6800 J/TRNFNC ; 6801 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 185 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND SUBROUTINES -- TRANSLATE ; 6802 ;HERE TO COMPLETE A TRANSLATE ; 6803 ; 6804 =0 ; 6805 TRNRET: READ [ARX], SKIP DP18, ;S-FLAG IS ZERO ; 6806 B DISP, SKIP DP18, ;SEE IF EDIT OR SIG START U 2270, 0754,3333,0004,4174,4003,7530,0000,0000,0000 ; 6807 J/TRNSS ; .. ; 6808 TRNSS1: [AR]_[ARX].AND.# CLR LH, ;S IS SET, JUST RETURN BYTE U 2271, 0005,4251,0403,4374,4004,1700,0000,0007,7777 ; 6809 #/77777, RETURN [5] ; .. ; 6810 ; 6811 =1100 ; 6812 TRNSS: [AR]_AC[DLEN], ;NO SIG ON MOVE OR D2B U 0754, 0533,3771,0003,1276,6003,7701,0000,0000,1443 ; 6813 B DISP, J/TRNNS1 ;SEE IF D2B ; 6814 [BRX]_[BRX].OR.#, ;SIG START ON MOVE OR D2B ; 6815 #/400000, HOLD RIGHT, U 0755, 2271,3551,0606,4374,0007,0700,0000,0040,0000 ; 6816 J/TRNSS1 ;RETURN BYTE ; 6817 [AR]_WORK[FILL], ;EDIT--NO SIG RETURN FILL U 0756, 0002,3771,0003,7274,4004,1701,0000,0000,0244 ; 6818 RETURN [2] ; .. ; 6819 [AR]_AC[DSTP], ;EDIT--START OF SIG U 0757, 0003,3771,0003,1276,6004,1701,0000,0000,1444 ; 6820 RETURN [3] ; .. ; 6821 ; 6822 =1011 U 0533, 3444,1111,0703,4174,4007,0700,4000,0000,0000 ; 6823 TRNNS1: [AR]_[AR]-1, J/TRNNS2 ;COMPENSATE FOR IGNORING SRC ; 6824 [AR]_WORK[SLEN]+1, ;DEC TO BIN HAS NO DEST LENGTH U 0537, 1074,0551,0703,7274,4007,0701,0000,0000,0242 ; 6825 J/SRCMOD ;JUST UPDATE SRC LENTH ; 6826 TRNNS2: AC[DLEN]_[AR] TEST, ;PUT BACK DLEN AND U 3444, 2272,3770,0303,1174,4007,0520,0400,0000,1443 ; 6827 SKIP DP0 ; SEE WHICH IS NOW SHORTER ; 6828 =0 [AR]_WORK[SLEN], ;DEST IS SHORTER. DO NOT CHANGE U 2272, 1074,3771,0003,7274,4007,0701,0000,0000,0242 ; 6829 J/SRCMOD ; AMOUNT LEFT ; 6830 [AR]_WORK[SLEN]+1, ;GO LOOK AT NEXT BYTE U 2273, 1074,0551,0703,7274,4007,0701,0000,0000,0242 ; 6831 J/SRCMOD ; 6832 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 186 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND SUBROUTINES -- GET UNMODIFIED SOURCE BYTE ; 6833 .TOC "EXTEND SUBROUTINES -- GET UNMODIFIED SOURCE BYTE" ; 6834 ; 6835 ;CALL: ; 6836 ; GSRC WITH SKIP ON SOURCE LENGTH ; 6837 ; GETSRC IF LENGHT IS OK ; 6838 ;WITH: ; 6839 ; AC1/ SOURCE BYTE POINTER ; 6840 ;RETURNS: ; 6841 ; 1 IF LENGTH RAN OUT ; 6842 ; 2 IF OK (BYTE IN AR) ; 6843 ; ; 6844 =0 ; 6845 GSRC: [AR]_AC[DLEN], ;LENGTH RAN OUT U 2274, 0001,3771,0003,1276,6004,1701,0000,0000,1443 ; 6846 RETURN [1] ;RESTORE AR AND RETURN U 2275, 3445,3771,0003,1276,6007,0701,0000,0000,1441 ; 6847 GETSRC: [AR]_AC[SRCP] ;GET SRC PTR ; 6848 IBP DP, IBP SCAD, ;UPDATE BYTE POINTER U 3445, 0231,3770,0305,4334,4016,7701,0000,0033,6000 ; 6849 SCAD DISP, 3T ;SEE IF OFLOW U 0231, 3447,3441,0503,4174,4007,0700,0000,0000,0000 ; 6850 =01 [AR]_[BR], J/GSRC1 ;NO OFLOW U 0233, 3446,3770,0503,4334,4017,0700,0000,0032,6000 ; 6851 SET P TO 36-S ;RESET P U 3446, 3447,0111,0703,4170,4007,0700,0000,0000,0000 ; 6852 [AR]_[AR]+1, HOLD LEFT ;BUMP Y ; 6853 U 3447, 2276,3440,0303,1174,4007,0700,0400,0000,1441 ; 6854 GSRC1: AC[SRCP]_[AR] ;STORE UPDATED POINTER ; 6855 =0 READ [AR], LOAD BYTE EA,;SETUP TO FIGURE OUT U 2276, 3076,3333,0003,4174,4217,0701,1010,0073,0500 ; 6856 FE_P, 3T, CALL [BYTEAS] ; EFFECTIVE ADDRESS ; 6857 READ [AR], ;LOOK AT POINTER ; 6858 BYTE DISP, ;SEE IF 7 BIT ; 6859 FE_FE.AND.S#, S#/0770, ;MASK OUT P FIELD U 2277, 0340,3333,0003,4174,4006,5701,1000,0051,0770 ; 6860 J/LDB1 ;GO GET THE BYTE ; 6861 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 187 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND SUBROUTINES -- STORE BYTE IN DESTINATION STRING ; 6862 .TOC "EXTEND SUBROUTINES -- STORE BYTE IN DESTINATION STRING" ; 6863 ; 6864 ;CALL WITH: ; 6865 ; AR/ BYTE TO STORE ; 6866 ; AC4/ DESTINATION BYTE POINTER ; 6867 ;RETURNS: ; 6868 ; AR & AC4/ UPDATED BYTE POINTER ; 6869 ; ARX/ BYTE TO STORE ; 6870 ; BR/ WORD TO MERGE WITH ; 6871 ; 6 ALWAYS ; 6872 ; U 3450, 2300,3441,0304,4174,4007,0700,0000,0000,0000 ; 6873 PUTDST: [ARX]_[AR] ;SAVE BYTE ; 6874 =0 [AR]_AC[DSTP], ;GET DEST POINTER U 2300, 3451,3771,0003,1276,6007,0701,0010,0000,1444 ; 6875 CALL [IDST] ;BUMP DEST POINTER ; 6876 AD/A+B, A/ARX, B/ARX, ;SHIFT 7-BIT BYTE TO ; 6877 SCAD/A, 3T, ; NATURAL PLACE, AND PUT U 2301, 2241,0113,0404,4174,4007,0701,1000,0077,0000 ; 6878 SCADA/BYTE5, LOAD FE ; INTO FE ; 6879 =0* READ [AR], BYTE DISP, ;GO PUT BYTE IN MEMORY U 2241, 0360,3333,0003,4174,4006,5701,0010,0000,0000 ; 6880 CALL [DPB1] ; .. U 2243, 0006,4443,0000,4174,4004,1700,0000,0000,0000 ; 6881 RETURN [6] ;ALL DONE ; 6882 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 188 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND SUBROUTINES -- UPDATE DEST STRING POINTERS ; 6883 .TOC "EXTEND SUBROUTINES -- UPDATE DEST STRING POINTERS" ; 6884 ; 6885 ; 6886 ;SUBROUTINE TO BUMP DST POINTERS ; 6887 ;CALL WITH: ; 6888 ; AR/ AC[DSTP] ; 6889 ; RETURN 1 WITH UPDATED POINTER STORED ; 6890 ; U 3451, 2304,3770,0305,4334,4016,7701,0000,0033,6000 ; 6891 IDST: IBP DP, IBP SCAD, SCAD DISP, 3T U 2304, 3453,3441,0503,4174,4217,0700,0000,0000,0600 ; 6892 =0* [AR]_[BR], LOAD DST EA, J/IDSTX U 2306, 3452,3770,0503,4334,4017,0700,0000,0032,6000 ; 6893 SET P TO 36-S U 3452, 3453,0111,0703,4170,4217,0700,0000,0000,0600 ; 6894 [AR]_[AR]+1, HOLD LEFT, LOAD DST EA ; 6895 IDSTX: AC[DSTP]_[AR], 3T, ;STORE PTR BACK U 3453, 0230,3440,0303,1174,4006,6701,1400,0073,1444 ; 6896 FE_P, DISP/EAMODE ;SAVE P FOR CMPDST ; 6897 =100* U 0230, 3101,0553,0300,2274,4007,0701,0200,0004,0712 ; 6898 DSTEA: VMA_[AR]+XR, START READ, PXCT BYTE DATA, 3T, J/BYTFET U 0232, 3101,3443,0300,4174,4007,0700,0200,0004,0712 ; 6899 VMA_[AR], START READ, PXCT BYTE DATA, J/BYTFET U 0234, 3454,0553,0300,2274,4007,0701,0200,0004,0612 ; 6900 VMA_[AR]+XR, START READ, PXCT/BIS-DST-EA, 3T, J/DSTIND U 0236, 3454,3443,0300,4174,4007,0700,0200,0004,0612 ; 6901 VMA_[AR], START READ, PXCT/BIS-DST-EA, J/DSTIND ; 6902 U 3454, 3455,3771,0003,4361,5217,0700,0200,0000,0602 ; 6903 DSTIND: MEM READ, [AR]_MEM, HOLD LEFT, LOAD DST EA U 3455, 0230,4443,0000,2174,4006,6700,0000,0000,0000 ; 6904 EA MODE DISP, J/DSTEA ; 6905 ; 6906 ; 6907 ;HERE TO TEST ILLEGAL BITS SET ; 6908 ;CALL WITH: ; 6909 ; SKIP IF ALL BITS LEGAL ; 6910 ; RETURN [4] IF OK, ELSE DO UUO ; 6911 ; ; 6912 3556: ;EXTEND OF 0 COMES HERE U 3556, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 6913 BITCHK: UUO U 3557, 0004,4443,0000,4174,4004,1700,0000,0000,0000 ; 6914 3557: RETURN [4] ; 6915 ; 6916 ;HERE TO PUT FILL IN [AR] AND WORK[FILL] ; 6917 GTFILL: MEM READ, ;WAIT FOR DATA U 3456, 3457,3771,0003,4365,5007,0700,0200,0000,0002 ; 6918 [AR]_MEM ;PLACE IN AR ; 6919 WORK[FILL]_[AR], ;SAVE FOR LATER U 3457, 0010,3333,0003,7174,4004,1700,0400,0000,0244 ; 6920 RETURN [10] ;RETURN TO CALLER ; 6921 ; 6922 ;SUBROUTINE TO CLEAR FLAGS IN AR ; 6923 CLRFLG: [AR]_[AR].AND.#, ;CLEAR FLAGS IN AR ; 6924 #/000777, ; .. U 3460, 0001,4551,0303,4374,0004,1700,0000,0000,0777 ; 6925 HOLD RIGHT, RETURN [1] ; 6926 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 189 ; EXTEND.MIC[7,3] 11:35 26-JULY-1984 EXTEND -- PAGE FAIL CLEANUP ; 6927 .TOC "EXTEND -- PAGE FAIL CLEANUP" ; 6928 ; 6929 ;BACK UP SOURCE POINTER ; 6930 =0 ; 6931 BACKS: [AR]_AC[SRCP], U 2302, 3473,3771,0003,1276,6007,0701,0010,0000,1441 ; 6932 CALL [BACKBP] ;BACKUP BP U 2303, 2700,3440,0505,1174,4007,0700,0400,0000,1441 ; 6933 AC[SRCP]_[BR], J/CLDISP ; 6934 U 3461, 3462,3771,0003,7274,4007,0701,0000,0000,0214 ; 6935 CMSDST: [AR]_WORK[SV.BRX] ;GET OLD SRC LEN U 3462, 2310,0113,0703,0174,4007,0701,0400,0000,0000 ; 6936 AC_[AR]+1, 3T ;BACK UP ; 6937 ;BACK UP DESTINATION POINTER ; 6938 =0 ; 6939 BACKD: [AR]_AC[DSTP], U 2310, 3473,3771,0003,1276,6007,0701,0010,0000,1444 ; 6940 CALL [BACKBP] U 2311, 2700,3440,0505,1174,4007,0700,0400,0000,1444 ; 6941 AC[DSTP]_[BR], J/CLDISP ; 6942 ; 6943 ;FAILURES DURING MOVE STRING (BACKUP LENGTHS) U 3463, 3464,1771,0003,7274,4007,0701,4000,0000,0242 ; 6944 STRPF: [AR]_-WORK[SLEN] ;GET AMOUNT LEFT ; 6945 STRPF0: [BR]_AC[DLEN], 4T, ;WHICH STRING IS LONGER? U 3464, 2312,3771,0005,1276,6007,0522,0000,0000,1443 ; 6946 SKIP DP0 ; 6947 =0 U 2312, 3466,3440,0303,1174,4007,0700,0400,0000,1443 ; 6948 STRPF1: AC[DLEN]_[AR], J/STPF1A ;SRC LONGER U 2313, 2314,3441,0304,4174,4007,0700,0000,0000,0000 ; 6949 [ARX]_[AR] ;COPY SRC LENGTH ; 6950 =0 [ARX]_[ARX].OR.WORK[SV.BRX], ;REBUILD FLAGS U 2314, 3671,3551,0404,7274,4007,0701,0010,0000,0214 ; 6951 CALL [AC_ARX] ;RESET AC]SLEN] U 2315, 3465,1111,0503,4174,4007,0700,4000,0000,0000 ; 6952 [AR]_[AR]-[BR] ;MAKE DEST LEN ; 6953 STRPF3: AC[DLEN]_[AR], ;PUT BACK DEST LEN U 3465, 2700,3440,0303,1174,4007,0700,0400,0000,1443 ; 6954 J/CLDISP ;DO NEXT CLEANUP ; 6955 U 3466, 3470,0111,0503,4174,4007,0700,0000,0000,0000 ; 6956 STPF1A: [AR]_[AR]+[BR], J/STRPF2 ; 6957 U 3467, 3470,1771,0003,7274,4007,0701,4000,0000,0242 ; 6958 PFDBIN: [AR]_-WORK[SLEN] ;RESTORE LENGTH U 3470, 3471,3551,0303,7274,4007,0701,0000,0000,0214 ; 6959 STRPF2: [AR]_[AR].OR.WORK[SV.BRX] U 3471, 2700,3440,0303,0174,4007,0700,0400,0000,0000 ; 6960 PFGAC0: AC_[AR], J/CLDISP ;PUT BACK SRC LEN AND FLAGS ; 6961 U 3472, 3464,7771,0003,7274,4007,0701,0000,0000,0242 ; 6962 STRPF4: [AR]_.NOT.WORK[SLEN], J/STRPF0 ; 6963 ; 6964 BACKBP: IBP DP, SCAD/A+B, SCADA/BYTE1, SCADB/SIZE, ;P_P+S U 3473, 0001,3770,0305,4334,4014,1700,0000,0043,6000 ; 6965 RETURN [1] ; 6966 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 190 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 TRAPS ; 6967 .TOC "TRAPS" ; 6968 U 3474, 3475,3741,0104,4074,4007,0700,0000,0000,0000 ; 6969 TRAP: [ARX]_PC WITH FLAGS ;SAVE THE PC WHICH CAUSED THE ; 6970 WORK[TRAPPC]_[ARX], ; TRAP U 3475, 2316,3333,0004,7174,4007,0340,0400,0000,0425 ; 6971 SKIP KERNEL ;SEE IF UBR OR EBR ; 6972 =0 [AR]_[AR]+[UBR], ;ADDRESS OF INSTRUCTION ; 6973 MEM READ, ;WAIT FOR PREFETCH TO GET INTO ; 6974 ; THE CACHE. MAY PAGE FAIL BUT ; 6975 ; THAT IS OK ; 6976 START READ, ;START FETCH ; 6977 VMA PHYSICAL, ;ABSOLUTE ADDRESSING U 2316, 3476,0111,1103,4364,4007,0700,0200,0024,1016 ; 6978 J/TRP1 ;JOIN COMMON CODE ; 6979 ; 6980 [AR]_[AR]+[EBR], ;WE COME HERE IN EXEC MODE ; 6981 MEM READ, ;WAIT FOR PREFETCH TO GET INTO ; 6982 ; THE CACHE. MAY PAGE FAIL BUT ; 6983 ; THAT IS OK ; 6984 START READ, ;START FETCH ; 6985 VMA PHYSICAL, ;ABSOLUTE ADDRESSING U 2317, 3476,0111,1003,4364,4007,0700,0200,0024,1016 ; 6986 J/TRP1 ;JOIN COMMON CODE ; 6987 ; 6988 TRP1: MEM READ, [HR]_MEM, ;PLACE INSTRUCTION IN HR U 3476, 3477,3771,0002,4365,5617,0700,0200,0000,0002 ; 6989 LOAD INST ;LOAD IR, XR, @ ; 6990 [HR].AND.#, ;TEST TO SEE IF THIS ; 6991 #/700000, 3T, ; IS A UUO U 3477, 2320,4553,0200,4374,4007,0321,0000,0070,0000 ; 6992 SKIP ADL.EQ.0 ; 6993 =0 CHANGE FLAGS, ;NOT A UUO ; 6994 HOLD USER/1, ;CLEAR TRAP FLAGS U 2320, 2716,4443,0000,4174,4467,0700,0000,0001,0000 ; 6995 J/XCT1 ;DO THE INSTRUCTION U 2321, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 6996 UUO ;DO THE UUO ; 6997 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 191 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES ; 6998 .TOC "IO -- INTERNAL DEVICES" ; 6999 ; 7000 .DCODE D 0700, 1200,1700,4100 ; 7001 700: IOT,AC DISP, J/GRP700 D 0701, 1200,1720,4100 ; 7002 IOT,AC DISP, J/GRP701 ; 7003 .UCODE ; 7004 U 1701, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7005 1701: UUO ;DATAI APR, U 1702, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7006 1702: UUO ;BLKO APR, U 1703, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7007 1703: UUO ;DATAO APR, U 1706, 3502,3771,0005,4304,4007,0701,0000,0000,0000 ; 7008 1706: [BR]_APR, J/APRSZ ;CONSZ APR, U 1707, 3500,3771,0005,4304,4007,0701,0000,0000,0000 ; 7009 1707: [BR]_APR, J/APRSO ;CONSO APR, ; 7010 1710: U 1710, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7011 RDERA: UUO ;BLKI PI, U 1711, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7012 1711: UUO ;DATAI PI, U 1712, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7013 1712: UUO ;BLKO PI, U 1713, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7014 1713: UUO ;DATAO PI, U 1716, 0136,3441,1405,4174,4007,0700,0000,0000,0000 ; 7015 1716: [BR]_[PI], J/CONSZ ;CONSZ PI, U 1717, 3501,3441,1405,4174,4007,0700,0000,0000,0000 ; 7016 1717: [BR]_[PI], J/CONSO ;CONSO PI, ; 7017 ; 7018 1720: U 1720, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7019 GRP701: UUO ;BLKI PAG, U 1726, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7020 1726: UUO ;CONSZ PAG, U 1727, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7021 1727: UUO ;CONSO PAG, ; 7022 ; 7023 ;680I AND CACHE SWEEP STUFF U 1730, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7024 1730: UUO U 1731, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7025 1731: UUO U 1732, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7026 1732: UUO U 1733, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7027 1733: UUO U 1734, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7028 1734: UUO U 1735, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7029 1735: UUO U 1736, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7030 1736: UUO U 1737, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7031 1737: UUO ; 7032 U 3500, 3501,4251,0505,4374,4007,0700,0000,0000,7770 ; 7033 APRSO: [BR]_[BR].AND.# CLR LH, #/7770 U 3501, 0260,4113,0305,4174,4007,0330,0000,0000,0000 ; 7034 CONSO: [BR].AND.[AR], SKIP ADR.EQ.0, J/SKIP ; 7035 U 3502, 0136,4251,0505,4374,4007,0700,0000,0000,7770 ; 7036 APRSZ: [BR]_[BR].AND.# CLR LH, #/7770 ; 7037 136: ;STANDARD LOCATION FOR VERSION INFO, ; 7038 ;ANY UWORD THAT HAS A FREE # FIELD CAN ; 7039 ;BE USED. ; 7040 CONSZ: [BR].AND.[AR], SKIP ADR.EQ.0, J/DONE, ; 7041 MICROCODE RELEASE(MAJOR)/UCR, ;MAJOR VERSION # U 0136, 1400,4113,0305,4174,4007,0330,0000,0000,0020 ; 7042 MICROCODE RELEASE(MINOR)/UCR ;MINOR VERSION # (FOR ID ONLY) ; 7043 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 192 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES ; 7044 1700: ; 7045 GRP700: ; 7046 APRID: [BR]_#, U 1700, 0137,3771,0005,4374,4007,0700,0000,0001,0001 ; 7047 #/4097. ; 7048 137: [BR]_#, ; 7049 MICROCODE OPTION(INHCST)/OPT, ; 7050 MICROCODE OPTION(NOCST)/OPT, ; 7051 MICROCODE OPTION(NONSTD)/OPT, ; 7052 MICROCODE OPTION(UBABLT)/OPT, ; 7053 MICROCODE OPTION(KIPAGE)/OPT, ; 7054 MICROCODE OPTION(KLPAGE)/OPT, ; 7055 MICROCODE VERSION/UCV, ; 7056 HOLD RIGHT, U 0137, 3613,3771,0005,4374,0007,0700,0000,0003,0130 ; 7057 J/RTNREG ; 7058 ; 7059 1704: U 1704, 3503,3771,0005,7274,4007,0701,0000,0000,0230 ; 7060 WRAPR: [BR]_WORK[APR] ; 7061 [BR]_[BR].AND.NOT.#, ;CLEAR THE OLD PIA U 3503, 3504,5551,0505,4370,4007,0700,0000,0000,0007 ; 7062 #/7, HOLD LEFT ; .. U 3504, 3505,4551,0304,4374,4007,0700,0000,0000,0007 ; 7063 [ARX]_[AR].AND.#, #/7 ;PUT NEW PIA IN ARX U 3505, 3506,3111,0405,4174,4007,0700,0000,0000,0000 ; 7064 [BR]_[BR].OR.[ARX] ;PUT NEW PIA IN BR ; 7065 [ARX]_[AR].AND.#, ;MASK THE DATA BITS U 3506, 3507,4551,0304,4374,4007,0700,0000,0000,7760 ; 7066 #/007760 ; DOWN TO ENABLES U 3507, 2322,4553,0300,4374,4007,0331,0000,0010,0000 ; 7067 TR [AR], #/100000 ;WANT TO ENABLE ANY? U 2322, 2323,3111,0405,4174,4007,0700,0000,0000,0000 ; 7068 =0 [BR]_[BR].OR.[ARX] ;YES--SET THEM U 2323, 2324,4553,0300,4374,4007,0331,0000,0004,0000 ; 7069 TR [AR], #/40000 ;WANT TO DISABLE ANY? U 2324, 2325,5111,0405,4174,4007,0700,0000,0000,0000 ; 7070 =0 [BR]_[BR].AND.NOT.[ARX] ;YES--CLEAR THEM U 2325, 3510,3771,0006,4304,4007,0701,0000,0000,0000 ; 7071 [BRX]_APR ;GET CURRENT STATUS U 3510, 2326,4553,0300,4374,4007,0331,0000,0002,0000 ; 7072 TR [AR], #/20000 ;WANT TO CLEAR FLAGS? U 2326, 2327,5111,0406,4174,4007,0700,0000,0000,0000 ; 7073 =0 [BRX]_[BRX].AND.NOT.[ARX] ;YES--CLEAR BITS U 2327, 2330,4553,0300,4374,4007,0331,0000,0001,0000 ; 7074 TR [AR], #/10000 ;WANT TO SET ANY FLAGS? U 2330, 2331,3111,0406,4174,4007,0700,0000,0000,0000 ; 7075 =0 [BRX]_[BRX].OR.[ARX] ;YES--SET FLAGS U 2331, 2332,4553,0300,4374,4007,0331,0000,0003,0000 ; 7076 TR [AR], #/30000 ;ANY CHANGE AT ALL? ; 7077 =0 READ [BRX], ;YES--LOAD NEW FLAGS U 2332, 3513,3333,0006,4174,4007,0700,0000,0000,0000 ; 7078 J/WRAPR2 ;TURN OFF INTERRUPT 8080 U 2333, 3511,3333,0005,4174,4007,0700,0000,0000,0000 ; 7079 WRAPR1: READ [BR] ;FIX DPM TIMING BUG ; 7080 READ [BR], ;ENABLE CONDITIONS U 3511, 3512,3333,0005,4174,4257,0700,0000,0000,0000 ; 7081 SET APR ENABLES ; 7082 WORK[APR]_[BR], ;SAVE FOR RDAPR U 3512, 1400,3333,0005,7174,4007,0700,0400,0000,0230 ; 7083 J/DONE ;ALL DONE ; 7084 ; 7085 WRAPR2: READ [BRX], ;LOAD NEW FLAGS U 3513, 3514,3333,0006,4174,4237,0700,0000,0000,0000 ; 7086 SPEC/APR FLAGS ; .. ; 7087 [BRX]_[BRX].AND.NOT.#, ;CLEAR INTERRUPT THE 8080 U 3514, 3515,5551,0606,4370,4007,0700,0000,0000,2000 ; 7088 #/002000, HOLD LEFT ; FLAG ; 7089 READ [BRX], ;LOAD NEW FLAGS ; 7090 SPEC/APR FLAGS, ; .. U 3515, 2333,3333,0006,4174,4237,0700,0000,0000,0000 ; 7091 J/WRAPR1 ;LOOP BACK ; 7092 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 193 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES ; 7093 1705: U 1705, 3516,3771,0005,7274,4007,0701,0000,0000,0230 ; 7094 RDAPR: [BR]_WORK[APR] ; 7095 [BR]_[BR] SWAP, ;PUT ENABLES IN BOTH U 3516, 3517,3770,0505,4344,0007,0700,0000,0000,0000 ; 7096 HOLD RIGHT ; HALVES ; 7097 [BR]_[BR].AND.#, ;SAVE ENABLES IN LH ; 7098 #/7760, ; U 3517, 3520,4551,0505,4374,0007,0700,0000,0000,7760 ; 7099 HOLD RIGHT ; 7100 [BR]_[BR].AND.#, ;SAVE PIA IN RH ; 7101 #/7, U 3520, 3521,4551,0505,4370,4007,0700,0000,0000,0007 ; 7102 HOLD LEFT U 3521, 3522,3771,0004,4304,4007,0701,0000,0000,0000 ; 7103 [ARX]_APR ;READ THE APR FLAGS ; 7104 [ARX]_[ARX].AND.# CLR LH, ;MASK OUT JUNK U 3522, 3523,4251,0404,4374,4007,0700,0000,0000,7770 ; 7105 #/007770 ;KEEP 8 FLAGS ; 7106 [BR]_[BR].OR.[ARX], ;MASH THE STUFF TOGETHER U 3523, 3613,3111,0405,4174,4007,0700,0000,0000,0000 ; 7107 J/RTNREG ;RETURN ; 7108 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 194 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- EBR & UBR ; 7109 .TOC "IO -- INTERNAL DEVICES -- EBR & UBR" ; 7110 ; 7111 ;UBR FORMAT: ; 7112 ;BITS 0 & 2 LOAD FLAGS (RETURNED ON RDUBR) ; 7113 ;BITS 3 - 5 ZERO ; 7114 ;BITS 6 -11 AC BLOCKS SELECTED - CUR,PREV ; 7115 ;BITS 16 -35 UPT PHYSICAL ADDRESS ; 7116 ; 7117 1723: ; 7118 WRUBR: VMA_[AR], ;LOAD E INTO VMA U 1723, 3524,3443,0300,4174,4007,0700,0200,0004,0012 ; 7119 START READ ;START MEMORY ; 7120 MEM READ, ;WAIT FOR DATA ; 7121 [AR]_MEM, 3T, ;PUT IT INTO THE AR U 3524, 2334,3771,0003,4365,5007,0521,0200,0000,0002 ; 7122 SKIP DP0 ;SEE IF WE WANT TO LOAD ; 7123 ; AC BLOCK NUMBERS ; 7124 ; 7125 =0 [AR]_[AR].AND.#, ;NO--CLEAR JUNK IN AR (ALL BUT LD UBR) ; 7126 #/100000, ; LEAVE ONLY LOAD UBR ; 7127 HOLD RIGHT, ; IN LEFT HALF ; 7128 SKIP ADL.EQ.0, 3T, ;SEE IF WE WANT TO LOAD UBR U 2334, 2336,4551,0303,4374,0007,0321,0000,0010,0000 ; 7129 J/ACBSET ;SKIP AROUND UBR LOAD ; 7130 ; 7131 ;HERE WHEN WE WANT TO LOAD AC BLOCK SELECTION ; 7132 [UBR]_[UBR].AND.#, ;MASK OUT THE UBR'S OLD ; 7133 #/770077, ; AC BLOCK NUMBERS U 2335, 3525,4551,1111,4374,0007,0700,0000,0077,0077 ; 7134 HOLD RIGHT ;IN THE LEFT HALF ; 7135 ; 7136 [AR]_[AR].AND.#, ;CLEAR ALL BUT NEW SELECTION ; 7137 #/507700, ;AND LOAD BITS U 3525, 3526,4551,0303,4374,0007,0700,0000,0050,7700 ; 7138 HOLD RIGHT ;IN AR LEFT ; 7139 ; 7140 [AR].AND.#, ;SEE IF WE WANT TO LOAD ; 7141 #/100000, 3T, ; UBR ALSO U 3526, 2336,4553,0300,4374,4007,0321,0000,0010,0000 ; 7142 SKIP ADL.EQ.0 ; 7143 ; 7144 ;HERE WITH AR LEFT = NEW AC BLOCKS OR ZERO, ; 7145 ;SKIP IF DON'T LOAD UBR ; 7146 =0 ; 7147 ACBSET: [BR]_[AR].AND.#, ;COPY UBR PAGE NUMBER ; 7148 #/3777, ; INTO BR U 2336, 3527,4551,0305,4374,4007,0700,0000,0000,3777 ; 7149 J/SETUBR ;GO LOAD UBR ; 7150 ; 7151 [UBR]_[UBR].OR.[AR], ;DO NOT LOAD UBR ; 7152 ; PUT AC BLOCK # IN ; 7153 HOLD RIGHT, ; THE LEFT HALF ; 7154 LOAD AC BLOCKS, ;LOAD HARDWARE U 2337, 1400,3111,0311,4174,0477,0700,0000,0000,0000 ; 7155 J/DONE ;ALL DONE ; 7156 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 195 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- EBR & UBR ; 7157 ;HERE WITH AR LEFT AS BEFORE, AR RIGHT = MASKED PAGE # ; 7158 SETUBR: [BR]_0, ;CLEAR BR LEFT ; 7159 HOLD RIGHT, ;BR IS 0,,PAGE # U 3527, 2340,4221,0005,4174,0007,0700,2000,0071,0007 ; 7160 SC_7 ;PUT THE COUNT IN SC ; 7161 =0 ; 7162 STUBRS: [BR]_[BR]*2, ;SHIFT BR OVER ; 7163 STEP SC, ; 9 PLACES U 2340, 2340,3445,0505,4174,4007,0630,2000,0060,0000 ; 7164 J/STUBRS ;PRODUCING UPT ADDRESS ; 7165 ; 7166 [UBR]_[UBR].AND.#, ;MASK OUT OLD UBR ; 7167 #/777774, ; BITS IN U 2341, 3530,4551,1111,4374,0007,0700,0000,0077,7774 ; 7168 HOLD RIGHT ; LEFT HALF ; 7169 ; 7170 [UBR]_0, ;CLEAR RIGHT HALF U 3530, 3531,4221,0011,4170,4007,0700,0000,0000,0000 ; 7171 HOLD LEFT ;UBR IS FLGS+ACBLK+0,,0 ; 7172 U 3531, 3532,3111,0511,4174,4007,0700,0000,0000,0000 ; 7173 [UBR]_[UBR].OR.[BR] ;PUT IN PAGE TABLE ADDRESS ; 7174 ; 7175 [UBR]_[UBR].OR.[AR], ;PUT IN AC BLOCK # ; 7176 HOLD RIGHT, ; IN LEFT HALF ; 7177 LOAD AC BLOCKS, ;TELL HARDWARE U 3532, 2406,3111,0311,4174,0477,0700,0000,0000,0000 ; 7178 J/SWEEP ;CLEAR CACHE ; 7179 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 196 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- EBR & UBR ; 7180 1724: U 1724, 2342,3445,0303,4174,4007,0700,2000,0071,0006 ; 7181 WREBR: [AR]_[AR]*2, SC_6 ;DO A SHIFT OVER 8 MORE ; 7182 =0 U 2342, 2342,3445,0303,4174,4007,0630,2000,0060,0000 ; 7183 WREBR1: [AR]_[AR]*2, STEP SC, J/WREBR1 ;SKIP WHEN = -1 ; 7184 .IF/FULL ;DO NOT ENABLE PAGING IN SMALL ; 7185 ; MICROCODE. U 2343, 3533,3771,0005,7274,4007,0701,0000,0000,0230 ; 7186 [BR]_WORK[APR] U 3533, 3534,4551,0505,4370,4007,0700,0000,0074,7777 ; 7187 [BR]_[BR].AND.#, #/747777, HOLD LEFT U 3534, 2344,4553,0300,4374,4007,0321,0000,0000,0020 ; 7188 [AR].AND.#, #/20, 3T, SKIP ADL.EQ.0 ;BIT 22 - TRAP ENABLE U 2344, 2345,3551,0505,4370,4007,0700,0000,0003,0000 ; 7189 =0 [BR]_[BR].OR.#, #/030000, HOLD LEFT ;SET - ALLOW TRAPS TO HAPPEN U 2345, 3535,3333,0005,4174,4257,0700,0000,0000,0000 ; 7190 READ [BR], SET APR ENABLES U 3535, 3536,3333,0005,7174,4007,0700,0400,0000,0230 ; 7191 WORK[APR]_[BR] ; 7192 .ENDIF/FULL ; 7193 ; 7194 .IF/KIPAGE ; 7195 .IF/KLPAGE U 3536, 3537,3441,0310,4174,4007,0700,0000,0000,0000 ; 7196 [EBR]_[AR] ;NOTE: SHIFTED LEFT 9 BITS U 3537, 2346,4553,1000,4374,4007,0321,0000,0000,0040 ; 7197 [EBR].AND.#, #/40, 3T, SKIP ADL.EQ.0 ;BIT 21 - KL PAGING ENABLE U 2346, 2406,3551,1010,4374,0007,0700,0000,0040,0000 ; 7198 =0 [EBR]_[EBR].OR.#, #/400000, HOLD RIGHT, J/SWEEP ;YES, SET INTERNAL FLAG U 2347, 2406,5551,1010,4374,0007,0700,0000,0040,0000 ; 7199 [EBR]_[EBR].AND.NOT.#, #/400000, HOLD RIGHT, J/SWEEP ;NO, CLR BIT 0 ; 7200 .ENDIF/KLPAGE ; 7201 .ENDIF/KIPAGE ; 7202 ;;7203 .IFNOT/KLPAGE ;MUST BE KI ONLY ;;7204 [EBR]_[AR],J/SWEEP ;SO INTERNAL FLAG ISN'T USED ; 7205 .ENDIF/KLPAGE ; 7206 ;;7207 .IFNOT/KIPAGE ;MUST BE KL ONLY ;;7208 [EBR]_[AR],J/SWEEP ;SO INTERNAL FLAG ISN'T USED ; 7209 .ENDIF/KIPAGE ; 7210 ; 7211 1725: U 1725, 2350,3447,1005,4174,4007,0700,2000,0071,0006 ; 7212 RDEBR: [BR]_[EBR]*.5, SC_6 ; 7213 =0 U 2350, 2350,3447,0505,4174,4007,0630,2000,0060,0000 ; 7214 RDEBR1: [BR]_[BR]*.5, STEP SC, J/RDEBR1 U 2351, 3540,4551,0505,4374,4007,0700,0000,0006,3777 ; 7215 [BR]_[BR].AND.#, #/63777 ;MASK TO JUST EBR ; 7216 [BR]_0, ;CLEAR LEFT HALF ; 7217 HOLD RIGHT, ; BITS U 3540, 3613,4221,0005,4174,0007,0700,0000,0000,0000 ; 7218 J/RTNREG ;RETURN ANSWER ; 7219 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 197 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- EBR & UBR ; 7220 1721: U 1721, 2352,4551,1105,4374,0007,0700,0000,0050,7700 ; 7221 RDUBR: [BR]_[UBR].AND.#,#/507700,HOLD RIGHT ;GET LOAD BITS AND AC BLOCKS U 2352, 2354,3447,1106,4174,4007,0700,2010,0071,0006 ; 7222 =0 [BRX]_[UBR]*.5, SC_6, CALL [GTPCW1] ;SET SC (9) START SHIFT,GET UBR ; 7223 VMA_[AR],START WRITE, ;START TO U 2353, 3614,3443,0300,4174,4007,0700,0200,0003,0012 ; 7224 J/RTNRG1 ;RETURN DATA ; 7225 ; 7226 U 3541, 3542,4551,1105,4374,0007,0700,0000,0050,7700 ; 7227 GETPCW: [BR]_[UBR].AND.#,#/507700,HOLD RIGHT ;GET LOAD BITS AND AC BLOCKS U 3542, 2354,3447,1106,4174,4007,0700,2000,0071,0006 ; 7228 [BRX]_[UBR]*.5, SC_6 ;SET SC (9) START SHIFT ; 7229 ; 7230 =0 U 2354, 2354,3447,0606,4174,4007,0630,2000,0060,0000 ; 7231 GTPCW1: [BRX]_[BRX]*.5, STEP SC, J/GTPCW1 ;SHIFT UBR ADDR TO PAGE # U 2355, 3543,4551,0606,4374,4007,0700,0000,0000,3777 ; 7232 [BRX]_[BRX].AND.#, #/3777 ;ONLY PAGE # U 3543, 0001,3441,0605,4170,4004,1700,0000,0000,0000 ; 7233 [BR]_[BRX], HOLD LEFT, RETURN [1] ;MOVE PAGE # TO RH OF RESULT ; 7234 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 198 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- KL PAGING REGISTERS ; 7235 .TOC "IO -- INTERNAL DEVICES -- KL PAGING REGISTERS" ; 7236 ; 7237 .DCODE D 0702, 1216,1760,4700 ; 7238 702: IOT,AC DISP, M, J/GRP702 ; 7239 .UCODE ; 7240 ; 7241 1760: ; 7242 GRP702: U 1760, 3613,3771,0005,7274,4007,0701,0000,0000,0215 ; 7243 RDSPB: [BR]_WORK[SBR], J/RTNREG ; 7244 1761: U 1761, 3613,3771,0005,7274,4007,0701,0000,0000,0216 ; 7245 RDCSB: [BR]_WORK[CBR], J/RTNREG ; 7246 1762: U 1762, 3613,3771,0005,7274,4007,0701,0000,0000,0220 ; 7247 RDPUR: [BR]_WORK[PUR], J/RTNREG ; 7248 1763: U 1763, 3613,3771,0005,7274,4007,0701,0000,0000,0217 ; 7249 RDCSTM: [BR]_WORK[CSTM], J/RTNREG ; 7250 1766: U 1766, 3613,3771,0005,7274,4007,0701,0000,0000,0227 ; 7251 RDHSB: [BR]_WORK[HSBADR], J/RTNREG U 1767, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7252 1767: UUO ; 7253 ; 7254 1770: U 1770, 3544,4443,0000,4174,4007,0703,0200,0006,0002 ; 7255 WRSPB: START READ,WRITE TEST,5T ;WAIT FOR (?) WRITE-TEST PF U 3544, 3545,3771,0003,4365,5007,0700,0200,0000,0002 ; 7256 MEM READ, [AR]_MEM U 3545, 1400,3333,0003,7174,4007,0700,0400,0000,0215 ; 7257 WORK[SBR]_[AR], J/DONE ; 7258 1771: U 1771, 3546,4443,0000,4174,4007,0703,0200,0006,0002 ; 7259 WRCSB: START READ,WRITE TEST,5T ;WAIT FOR (?) WRITE-TEST PF U 3546, 3547,3771,0003,4365,5007,0700,0200,0000,0002 ; 7260 MEM READ, [AR]_MEM U 3547, 1400,3333,0003,7174,4007,0700,0400,0000,0216 ; 7261 WORK[CBR]_[AR], J/DONE ; 7262 1772: U 1772, 3550,4443,0000,4174,4007,0703,0200,0006,0002 ; 7263 WRPUR: START READ,WRITE TEST,5T ;WAIT FOR (?) WRITE-TEST PF U 3550, 3551,3771,0003,4365,5007,0700,0200,0000,0002 ; 7264 MEM READ, [AR]_MEM U 3551, 1400,3333,0003,7174,4007,0700,0400,0000,0220 ; 7265 WORK[PUR]_[AR], J/DONE ; 7266 1773: U 1773, 3552,4443,0000,4174,4007,0703,0200,0006,0002 ; 7267 WRCSTM: START READ,WRITE TEST,5T ;WAIT FOR (?) WRITE-TEST PF U 3552, 3553,3771,0003,4365,5007,0700,0200,0000,0002 ; 7268 MEM READ, [AR]_MEM U 3553, 1400,3333,0003,7174,4007,0700,0400,0000,0217 ; 7269 WORK[CSTM]_[AR], J/DONE ; 7270 1776: U 1776, 3554,4443,0000,4174,4007,0703,0200,0006,0002 ; 7271 WRHSB: START READ,WRITE TEST,5T ;WAIT FOR (?) WRITE-TEST PF U 3554, 3555,3771,0003,4365,5007,0700,0200,0000,0002 ; 7272 MEM READ, [AR]_MEM U 3555, 1400,3333,0003,7174,4007,0700,0400,0000,0227 ; 7273 WORK[HSBADR]_[AR], J/DONE ; 7274 U 1777, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7275 1777: UUO ; 7276 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 199 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- TIMER CONTROL ; 7277 .TOC "IO -- INTERNAL DEVICES -- TIMER CONTROL" ; 7278 ; 7279 ; 7280 ;BEGIN [123] ; 7281 TICK: [AR]_WORK[TIME1], ;GET LOW WORD U 3560, 3561,3771,0003,7274,4117,0701,0000,0000,0301 ; 7282 SPEC/CLRCLK ;CLEAR CLOCK FLAG ; 7283 ;END [123] U 3561, 3562,4751,1205,4374,4007,0700,0000,0001,0000 ; 7284 TOCK: [BR]_0 XWD [10000] ;2^12 UNITS PER MS U 3562, 3563,0111,0503,4174,4007,0700,0000,0000,0000 ; 7285 [AR]_[AR]+[BR] ;INCREMENT THE TIMER U 3563, 2356,3770,0303,4174,0007,0520,0000,0000,0000 ; 7286 FIX [AR] SIGN, SKIP DP0 ;SEE IF IT OVERFLOWED ; 7287 =0 ; 7288 TOCK1: WORK[TIME1]_[AR], ;STORE THE NEW TIME U 2356, 3564,3333,0003,7174,4007,0700,0400,0000,0301 ; 7289 J/TOCK2 ;SKIP OVER THE OVERFLOW CODE U 2357, 2305,3771,0003,7274,4007,0701,0000,0000,0300 ; 7290 [AR]_WORK[TIME0] ;GET HIGH WORD ; 7291 =0* [AR]_[AR]+1, ;BUMP IT U 2305, 3572,0111,0703,4174,4007,0700,0010,0000,0000 ; 7292 CALL [WRTIM1] ;STORE BACK IN RAM ; 7293 [AR]_0, ;CAUSE LOW WORD WORD U 2307, 2356,4221,0003,4174,4007,0700,0000,0000,0000 ; 7294 J/TOCK1 ; TO GET STORED U 3564, 3565,3771,0003,7274,4007,0701,0000,0000,0303 ; 7295 TOCK2: [AR]_WORK[TTG] ; 7296 [AR]_[AR]-[BR], ;COUNT DOWN TIME TO GO U 3565, 2360,1111,0503,4174,4007,0421,4000,0000,0000 ; 7297 SKIP AD.LE.0 ;SEE IF IT TIMED OUT ; 7298 =0 ; 7299 TOCK3: WORK[TTG]_[AR], ;SAVE NEW TIME TO GO U 2360, 0002,3333,0003,7174,4004,1700,0400,0000,0303 ; 7300 RETURN [2] ;ALL DONE U 2361, 3566,3771,0003,7274,4007,0701,0000,0000,0302 ; 7301 [AR]_WORK[PERIOD] U 3566, 3567,3771,0005,4304,4007,0701,0000,0000,0000 ; 7302 [BR]_APR ;GET CURRENT FLAGS U 3567, 3570,3551,0505,4374,4007,0700,0000,0000,0040 ; 7303 [BR]_[BR].OR.#, #/40 ;SET TIMER INTERRUPT FLAG ; 7304 READ [BR], ;PLACE ON DP AND ; 7305 SPEC/APR FLAGS, ; LOAD INTO HARDWARE U 3570, 2360,3333,0005,4174,4237,0700,0000,0000,0000 ; 7306 J/TOCK3 ;ALL DONE ; 7307 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 200 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- WRTIME & RDTIME ; 7308 .TOC "IO -- INTERNAL DEVICES -- WRTIME & RDTIME" ; 7309 ; 7310 1774: U 1774, 3571,4443,0000,4174,4007,0700,0200,0004,0002 ; 7311 WRTIME: START READ ;FETCH WORD AT E ; 7312 MEM READ, ;WAIT FOR DATA U 3571, 1114,3771,0003,4365,5007,0700,0200,0000,0002 ; 7313 [AR]_MEM ;PUT WORD IN AR ; 7314 =00 VMA_[HR]+1, ;BUMP E ; 7315 START READ, ;START MEMORY U 1114, 3661,0111,0702,4170,4007,0700,0210,0004,0012 ; 7316 CALL [LOADARX] ;PUT DATA IN ARX ; 7317 [ARX]_[ARX].AND.#, ;CLEAR PART HELD IN ; 7318 #/770000, ; HARDWARE COUNTER U 1115, 3572,4551,0404,4370,4007,0700,0010,0077,0000 ; 7319 HOLD LEFT, CALL [WRTIM1] ; 7320 =11 WORK[TIME1]_[ARX], ;IN WORK SPACE U 1117, 1400,3333,0004,7174,4007,0700,0400,0000,0301 ; 7321 J/DONE ;NEXT INSTRUCTION ; 7322 = ; 7323 WRTIM1: WORK[TIME0]_[AR], ;SAVE THE NEW VALUE U 3572, 0002,3333,0003,7174,4004,1700,0400,0000,0300 ; 7324 RETURN [2] ; 7325 ; 7326 1764: U 1764, 3573,4451,1205,4324,4007,0700,0000,0000,0000 ; 7327 RDTIME: [BR]_TIME ;READ THE TIME U 3573, 3574,4451,1204,4324,4007,0700,0000,0000,0000 ; 7328 [ARX]_TIME ; AGAIN U 3574, 3575,4451,1206,4324,4007,0700,0000,0000,0000 ; 7329 [BRX]_TIME ; AGAIN ; 7330 [BR].XOR.[ARX], ;SEE IF STABLE U 3575, 2362,6113,0405,4174,4007,0621,0000,0000,0000 ; 7331 SKIP AD.EQ.0 ; .. U 2362, 2363,3441,0604,4174,4007,0700,0000,0000,0000 ; 7332 =0 [ARX]_[BRX] ;NO THEN NEXT TRY MUST BE OK U 2363, 3576,3771,0005,7274,4007,0701,0000,0000,0300 ; 7333 [BR]_WORK[TIME0] ; 7334 [ARX]_[ARX]+WORK[TIME1], ;COMBINE PARTS U 3576, 1120,0551,0404,7274,4007,0671,0000,0000,0301 ; 7335 SKIP/-1 MS ;SEE IF OVERFLOW HAPPENED ; 7336 =00 SPEC/CLRCLK, ;CLEAR CLOCK FLAG ; 7337 [AR]_WORK[TIME1], 2T, ;GET LOW WORD FOR TOCK U 1120, 3561,3771,0003,7274,4117,0700,0010,0000,0301 ; 7338 CALL [TOCK] ;UPDATE CLOCKS ; 7339 READ [HR], LOAD VMA, ;DID NOT OVERFLOW U 1121, 3577,3333,0002,4174,4007,0700,0200,0003,0012 ; 7340 START WRITE, J/RDTIM1 ;STORE ANSWER U 1122, 1764,4443,0000,4174,4007,0700,0000,0000,0000 ; 7341 J/RDTIME ;TRY AGAIN ; 7342 = U 3577, 3600,3333,0005,4175,5007,0701,0200,0000,0002 ; 7343 RDTIM1: MEM WRITE, MEM_[BR] U 3600, 3601,0111,0702,4170,4007,0700,0200,0003,0012 ; 7344 VMA_[HR]+1, LOAD VMA, START WRITE U 3601, 1400,3333,0004,4175,5007,0701,0200,0000,0002 ; 7345 MEM WRITE, MEM_[ARX], J/DONE ; 7346 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 201 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- WRINT & RDINT ; 7347 .TOC "IO -- INTERNAL DEVICES -- WRINT & RDINT" ; 7348 ; 7349 ; 7350 1775: U 1775, 3602,4443,0000,4174,4007,0700,0200,0004,0002 ; 7351 WRINT: START READ U 3602, 3603,3771,0003,4365,5007,0700,0200,0000,0002 ; 7352 MEM READ, [AR]_MEM U 3603, 3604,3333,0003,7174,4007,0700,0400,0000,0302 ; 7353 WORK[PERIOD]_[AR] ; 7354 WORK[TTG]_[AR], U 3604, 1400,3333,0003,7174,4007,0700,0400,0000,0303 ; 7355 J/DONE ; 7356 ; 7357 1765: ; 7358 RDINT: [BR]_WORK[PERIOD], U 1765, 3613,3771,0005,7274,4007,0701,0000,0000,0302 ; 7359 J/RTNREG ; 7360 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 202 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- RDPI & WRPI ; 7361 .TOC "IO -- INTERNAL DEVICES -- RDPI & WRPI" ; 7362 ; 7363 1715: U 1715, 3613,3441,1405,4174,4007,0700,0000,0000,0000 ; 7364 RDPI: [BR]_[PI], J/RTNREG ; 7365 ; 7366 1714: U 1714, 2364,4553,0300,4374,4007,0331,0000,0001,0000 ; 7367 WRPI: TR [AR], PI.CLR/1 U 2364, 2365,4221,0014,4174,4007,0700,0000,0000,0000 ; 7368 =0 [PI]_0 U 2365, 2366,4553,0300,4374,4007,0331,0000,0074,0000 ; 7369 TR [AR], PI.MBZ/17 U 2366, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7370 =0 UUO U 2367, 3605,4551,0305,4374,4007,0700,0000,0000,0177 ; 7371 [BR]_[AR].AND.#,#/177 U 3605, 3606,3770,0505,4344,0007,0700,0000,0000,0000 ; 7372 [BR]_[BR] SWAP, HOLD RIGHT U 3606, 2370,4553,0300,4374,4007,0331,0000,0002,0000 ; 7373 TR [AR], PI.DIR/1 U 2370, 2371,5111,0514,4174,0007,0700,0000,0000,0000 ; 7374 =0 [PI]_[PI].AND.NOT.[BR], HOLD RIGHT U 2371, 2372,4553,0300,4374,4007,0331,0000,0000,4000 ; 7375 TR [AR], PI.REQ/1 U 2372, 2373,3111,0514,4174,0007,0700,0000,0000,0000 ; 7376 =0 [PI]_[PI].OR.[BR], HOLD RIGHT U 2373, 2374,4553,0300,4374,4007,0331,0000,0000,0200 ; 7377 TR [AR], PI.TSN/1 U 2374, 2375,3551,1414,4370,4007,0700,0000,0000,0200 ; 7378 =0 [PI]_[PI].OR.#,PI.ON/1, HOLD LEFT U 2375, 2376,4553,0300,4374,4007,0331,0000,0000,0400 ; 7379 TR [AR], PI.TSF/1 U 2376, 2377,5551,1414,4370,4007,0700,0000,0000,0200 ; 7380 =0 [PI]_[PI].AND.NOT.#,PI.ON/1, HOLD LEFT U 2377, 2400,4553,0300,4374,4007,0331,0000,0000,2000 ; 7381 TR [AR], PI.TCN/1 U 2400, 2401,3111,0514,4170,4007,0700,0000,0000,0000 ; 7382 =0 [PI]_[PI].OR.[BR], HOLD LEFT U 2401, 0304,4553,0300,4374,4007,0331,0000,0000,1000 ; 7383 TR [AR], PI.TCF/1 U 0304, 0305,5111,0514,4170,4007,0700,0000,0000,0000 ; 7384 =0**0 [PI]_[PI].AND.NOT.[BR], HOLD LEFT U 0305, 3610,3770,1416,4344,4007,0700,0010,0000,0000 ; 7385 PIEXIT: CALL LOAD PI ; 7386 =1**1 U 0315, 0110,3443,0100,4174,4156,4700,0200,0014,0012 ; 7387 DONE ; 7388 = ; 7389 ; 7390 ;SUBROUTINE TO LOAD PI HARDWARE ; 7391 ;CALL WITH: ; 7392 ; CALL LOAD PI ; 7393 ;RETURNS 10 WITH PI HARDWARE LOADED ; 7394 ; U 3607, 3610,3770,1416,4344,4007,0700,0000,0000,0000 ; 7395 LOADPI: [T0]_[PI] SWAP ;PUT ACTIVE CHANS IN LH U 3610, 3611,2441,0716,4170,4007,0700,4000,0000,0000 ; 7396 LDPI2: [T0]_-1, HOLD LEFT ;DONT MASK RH U 3611, 3612,4111,1416,4174,4007,0700,0000,0000,0000 ; 7397 [T0]_[T0].AND.[PI] ;ONLY REQUEST CHANS THAT ARE ON ; 7398 .NOT.[T0], LOAD PI, ;RELOAD HARDWARE U 3612, 0010,7443,1600,4174,4434,1700,0000,0000,0000 ; 7399 RETURN [10] ;RETURN TO CALLER ; 7400 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 203 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- SUBROUTINES ; 7401 .TOC "IO -- INTERNAL DEVICES -- SUBROUTINES" ; 7402 ; 7403 ; 7404 ;HERE WITH SOMETHING IN BR STORE IT @AR U 3613, 3614,3443,0300,4174,4007,0700,0200,0003,0012 ; 7405 RTNREG: VMA_[AR], START WRITE U 3614, 1400,3333,0005,4175,5007,0701,0200,0000,0002 ; 7406 RTNRG1: MEM WRITE, MEM_[BR], J/DONE ; 7407 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 204 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- SUBROUTINES ; 7408 ;CACHE SWEEP ; 7409 ; 7410 1722: ; 7411 CLRPT: VMA_[AR], ;PUT CORRECT ADDRESS IN VMA U 1722, 3615,3443,0300,4174,4147,0700,0200,0000,0010 ; 7412 LOAD PAGE TABLE ;GET SET TO WRITE PAGE TABLE U 3615, 2402,4221,0003,4174,4007,0700,0000,0000,0000 ; 7413 [AR]_0 ;CLEAR ENTRY ; 7414 =0 [AR]_#,#/377377, ;INITIAL VMA VALUE U 2402, 3621,3771,0003,4374,4007,0700,0010,0037,7377 ; 7415 CALL [SSWEEP] ;LOAD THE SC ; 7416 [BR]_#, #/1001, ;CONSTANT TO KEEP ADDING U 2403, 3616,3771,0005,4374,4247,0700,0000,0000,1001 ; 7417 CLRCSH ;START TO CLEAR CACHE U 3616, 2404,3333,0003,4174,4247,0700,0000,0000,1000 ; 7418 READ [AR], CLRCSH ;FIRST THING TO CLEAR ; 7419 =0 ; 7420 CLRPTL: [AR]_[AR]-[BR], ;UPDATE AR (AND PUT ON DP) ; 7421 CLRCSH, ;SWEEP ON NEXT STEP ; 7422 STEP SC, ;SKIP IF WE ARE DONE U 2404, 2404,1111,0503,4174,4247,0630,6000,0060,1000 ; 7423 J/CLRPTL ;LOOP FOR ALL ENTRIES U 2405, 2411,3333,0003,4174,4007,0700,0000,0000,0000 ; 7424 READ [AR], J/ZAPPTA ;CLEAR LAST ENTRY ; 7425 ; 7426 =0 ; 7427 SWEEP: [AR]_#,#/377377, ;INITIAL VMA VALUE U 2406, 3621,3771,0003,4374,4007,0700,0010,0037,7377 ; 7428 CALL [SSWEEP] ;LOAD NUMBER OF STEPS INTO SC ; 7429 [BR]_#, #/1001, ;CONSTANT TO KEEP ADDING U 2407, 3617,3771,0005,4374,4347,0700,0000,0000,1001 ; 7430 SWEEP ;START SWEEP U 3617, 2410,3333,0003,4174,4347,0700,0000,0000,1000 ; 7431 READ [AR], SWEEP ;FIRST THING TO CLEAR ; 7432 =0 ; 7433 SWEEPL: [AR]_[AR]-[BR], ;UPDATE AR (AND PUT ON DP) ; 7434 SWEEP, ;SWEEP ON NEXT STEP ; 7435 STEP SC, ;SKIP IF WE ARE DONE U 2410, 2410,1111,0503,4174,4347,0630,6000,0060,1000 ; 7436 J/SWEEPL ;LOOP FOR ALL ENTRIES ; 7437 ;CLEAR LAST ENTRY AND U 2411, 3620,4223,0000,7174,4007,0700,0400,0000,0424 ; 7438 ZAPPTA: WORK[PTA.U]_0 ; FORGET PAGE TABLE ADDRESS ; 7439 WORK[PTA.E]_0, ;FORGET PAGE TABLE ADDRESS U 3620, 1400,4223,0000,7174,4007,0700,0400,0000,0423 ; 7440 J/DONE ;ALL DONE ; 7441 ; 7442 SSWEEP: SC_S#, S#/375, ;NUMBER OF STEPS U 3621, 0001,4443,0000,4174,4004,1700,2000,0071,0375 ; 7443 RETURN [1] ;RETURN ; 7444 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 205 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- SUBROUTINES ; 7445 ;WE COME HERE EITHER FROM NEXT INSTRUCTION DISPATCH OR PAGE FAIL ; 7446 ; LOGIC. IN ALL CASES, THE CURRENT INSTRUCTION IS CORRECTLY SETUP ; 7447 ; TO RESTART PROPERLY. ; 7448 ; 7449 ;FIRST SET THE CORRECT PI IN PROGRESS BIT ; 7450 ; [FLG]_[FLG].OR.#,FLG.PI/1, HOLD RIGHT, ; 7451 ; J/PI ;SET PI CYCLE AND PROCESS PI ; 7452 =1000 ; 7453 PI: AD/D, DBUS/PI NEW, ;LOOK AT NEW LEVEL ; 7454 DISP/DP LEFT, 3T, ;DISPATCH ON IT U 0770, 0770,3773,0000,4074,4003,1701,0000,0000,0000 ; 7455 J/PI ;GO TO 1 OF NEXT 7 PLACES U 0771, 3622,3551,1414,4370,4007,0700,0000,0004,0000 ; 7456 =1001 [PI]_[PI].OR.#, #/040000, HOLD LEFT, J/PIP1 U 0772, 3623,3551,1414,4370,4007,0700,0000,0002,0000 ; 7457 =1010 [PI]_[PI].OR.#, #/020000, HOLD LEFT, J/PIP2 U 0773, 3624,3551,1414,4370,4007,0700,0000,0001,0000 ; 7458 =1011 [PI]_[PI].OR.#, #/010000, HOLD LEFT, J/PIP3 U 0774, 3625,3551,1414,4370,4007,0700,0000,0000,4000 ; 7459 =1100 [PI]_[PI].OR.#, #/004000, HOLD LEFT, J/PIP4 U 0775, 3626,3551,1414,4370,4007,0700,0000,0000,2000 ; 7460 =1101 [PI]_[PI].OR.#, #/002000, HOLD LEFT, J/PIP5 U 0776, 3627,3551,1414,4370,4007,0700,0000,0000,1000 ; 7461 =1110 [PI]_[PI].OR.#, #/001000, HOLD LEFT, J/PIP6 U 0777, 3630,3551,1414,4370,4007,0700,0000,0000,0400 ; 7462 =1111 [PI]_[PI].OR.#, #/000400, HOLD LEFT, J/PIP7 U 3622, 3631,4751,1206,4374,4007,0700,0000,0000,0001 ; 7463 PIP1: [BRX]_0 XWD [1], J/PI10 ;REMEMBER WE ARE AT LEVEL 1 U 3623, 3631,4751,1206,4374,4007,0700,0000,0000,0002 ; 7464 PIP2: [BRX]_0 XWD [2], J/PI10 ;REMEMBER WE ARE AT LEVEL 2 U 3624, 3631,4751,1206,4374,4007,0700,0000,0000,0003 ; 7465 PIP3: [BRX]_0 XWD [3], J/PI10 ;REMEMBER WE ARE AT LEVEL 3 U 3625, 3631,4751,1206,4374,4007,0700,0000,0000,0004 ; 7466 PIP4: [BRX]_0 XWD [4], J/PI10 ;REMEMBER WE ARE AT LEVEL 4 U 3626, 3631,4751,1206,4374,4007,0700,0000,0000,0005 ; 7467 PIP5: [BRX]_0 XWD [5], J/PI10 ;REMEMBER WE ARE AT LEVEL 5 U 3627, 3631,4751,1206,4374,4007,0700,0000,0000,0006 ; 7468 PIP6: [BRX]_0 XWD [6], J/PI10 ;REMEMBER WE ARE AT LEVEL 6 U 3630, 3631,4751,1206,4374,4007,0700,0000,0000,0007 ; 7469 PIP7: [BRX]_0 XWD [7], J/PI10 ;REMEMBER WE ARE AT LEVEL 7 ; 7470 ; 7471 PI10: [AR]_[PI].AND.# CLR LH, ;TURN OFF PI SYSTEM U 3631, 3632,4251,1403,4374,4007,0700,0000,0007,7577 ; 7472 #/077577 ; TILL WE ARE DONE U 3632, 3633,7443,0300,4174,4437,0700,0000,0000,0000 ; 7473 .NOT.[AR], LOAD PI ; .. U 3633, 2412,4223,0000,4364,4277,0700,0200,0000,0010 ; 7474 ABORT MEM CYCLE ;NO MORE TRAPS ; 7475 =0 [AR]_VMA IO READ, ;SETUP TO READ WRU BITS ; 7476 WRU CYCLE/1, ; .. U 2412, 3666,4571,1203,4374,4007,0700,0010,0024,1300 ; 7477 CALL [STRTIO] ;START THE CYCLE ; 7478 MEM READ, ;WAIT FOR DATA ; 7479 [AR]_IO DATA, 3T, ;PUT DATA IN AR U 2413, 2414,3771,0003,4364,4007,0331,0200,0000,0002 ; 7480 SKIP ADR.EQ.0 ;SEE IF ANYONE THERE U 2414, 3642,4221,0004,4174,4007,0700,0000,0000,0000 ; 7481 =0 [ARX]_0, J/VECINT ;YES--VECTORED INTERRUPT U 2415, 3634,3445,0603,4174,4007,0700,0000,0000,0000 ; 7482 [AR]_[BRX]*2 ;N*2 ; 7483 [AR]_[AR]+#, #/40, 3T, ;2*N+40 U 3634, 3635,0551,0303,4370,4007,0701,0000,0000,0040 ; 7484 HOLD LEFT ; .. ; 7485 [AR]_[AR]+[EBR], ;ABSOULTE ADDRESS OF U 3635, 3636,0111,1003,4174,4007,0700,0000,0000,0000 ; 7486 J/PI40 ; INTERRUPT INSTRUCTION ; 7487 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 206 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- SUBROUTINES ; 7488 ;HERE WITH ABSOLUTE ADDRESS OF INTERRUPT INSTRUCTION IN [AR] U 3636, 3637,3443,0300,4174,4007,0700,0200,0024,1016 ; 7489 PI40: VMA_[AR], VMA PHYSICAL READ ;FETCH THE INSTRUCTION ; 7490 PI50: MEM READ, [AR]_MEM, LOAD VMA, ;FETCH INSTRUCTION U 3637, 3640,3771,0003,4365,5007,0701,0200,0020,0012 ; 7491 3T, FORCE EXEC ;E IS EXEC MODE U 3640, 2416,6553,0300,4374,4007,0321,0000,0025,4340 ; 7492 [AR].XOR.#, #/254340, 3T, SKIP ADL.EQ.0 U 2416, 2420,6553,0300,4374,4007,0321,0000,0026,4000 ; 7493 =0 [AR].XOR.#, #/264000, SKIP ADL.EQ.0, 3T, J/PIJSR U 2417, 3641,4521,1205,4074,4007,0700,0000,0000,0000 ; 7494 [BR]_FLAGS ;SAVE FLAGS ; 7495 AD/ZERO, LOAD FLAGS, U 3641, 0060,4223,0000,4174,4467,0700,0000,0000,0004 ; 7496 J/PIXPCW ;ENTER EXEC MODE AND ASSUME ; 7497 ; WE HAVE AN XPCW ; 7498 ;IF WE HALT HERE ON A VECTORED INTERRUPT, WE HAVE ; 7499 ; T0/ WHAT WE READ FROM BUS AS VECTOR ; 7500 ; ARX/ EPT+100+DEVICE ; 7501 ; BR/ ADDRESS OF ILLEGAL INSTRUCTION ; 7502 ; BRX/ VECTOR (MASKED AND SHIFTED) ; 7503 =0 U 2420, 0104,4751,1217,4374,4007,0700,0000,0000,0101 ; 7504 PIJSR: HALT [ILLII] ;NOT A JSR OR XPCW U 2421, 0470,4443,0000,4174,4007,0700,0200,0023,0002 ; 7505 START WRITE, FORCE EXEC ;PREPARE TO STORE OLD PC ; 7506 =0*0 [BR]_PC WITH FLAGS, ;OLD PC U 0470, 3667,3741,0105,4074,4007,0700,0010,0000,0000 ; 7507 CALL [STOBR] ;STORE OLD PC ; 7508 =1*0 [AR]_#, #/0, HOLD RIGHT, ;PREPARE TO CLEAR FLAGS U 0474, 3664,3771,0003,4374,0007,0700,0010,0000,0000 ; 7509 CALL [INCAR] ;BUMP POINTER ; 7510 =1*1 [PC]_[AR], LOAD FLAGS, ;NEW PC U 0475, 2714,3441,0301,4174,4467,0700,0000,0000,0004 ; 7511 J/PISET ;CLEAR PI CYCLE & START ; 7512 ; INTERRUPT PROGRAM ; 7513 = ; 7514 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 207 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 IO -- INTERNAL DEVICES -- SUBROUTINES ; 7515 ;HERE TO PROCESS A VECTORED INTERRUPT. AT THIS POINT: ; 7516 ; AR/ WRU BITS (BIT 18 FOR DEVICE 0) ; 7517 ; ARX/ 0 ; 7518 VECINT: [AR]_[AR]*2, ;SHIFT LEFT (UNSHIFTED ON DP) U 3642, 2422,3445,0303,4174,4007,0530,0000,0000,0000 ; 7519 SKIP DP18 ;ANYONE THERE? ; 7520 =0 [ARX]_[ARX]+[XWD1], ;NO--BUMP BOTH HALVES U 2422, 3642,0111,1504,4174,4007,0700,0000,0000,0000 ; 7521 J/VECINT ;KEEP LOOKING ; 7522 [AR]_VMA IO READ, ;SETUP FOR VECTOR CYCLE U 2423, 2424,4571,1203,4374,4007,0700,0000,0024,1240 ; 7523 VECTOR CYCLE/1 ; .. ; 7524 =0 [AR]_[AR].OR.[ARX], ;PUT IN UNIT NUMBER U 2424, 3666,3111,0403,4174,4007,0700,0010,0000,0000 ; 7525 CALL [STRTIO] ;START CYCLE ; 7526 MEM READ, ;WAIT FOR VECTOR (SEE DPM5) U 2425, 2426,3771,0016,4364,4007,0700,0200,0000,0002 ; 7527 [T0]_IO DATA ;GET VECTOR ; 7528 =0 [BR]_[EBR]+#, 3T, #/100, ;EPT+100 U 2426, 3663,0551,1005,4374,4007,0701,0010,0000,0100 ; 7529 CALL [CLARXL] ;CLEAR ARX LEFT ; 7530 [ARX]_[ARX]+[BR], ;EPT+100+DEVICE U 2427, 3643,0111,0504,4174,4007,0700,0200,0024,1016 ; 7531 VMA PHYSICAL READ ;FETCH WORD ; 7532 MEM READ, [BR]_MEM, 3T, ;GET POINTER U 3643, 2430,3771,0005,4365,5007,0331,0200,0000,0002 ; 7533 SKIP ADR.EQ.0 ;SEE IF NON-ZERO ; 7534 =0 [BRX]_([T0].AND.#)*.5, 3T, ;OK--MAKE VECTOR MOD 400 U 2430, 3644,4557,1606,4374,4007,0701,0000,0000,0774 ; 7535 #/774, J/VECIN1 ; AND SHIFT OVER U 2431, 0104,4751,1217,4374,4007,0700,0000,0000,0102 ; 7536 HALT [ILLINT] U 3644, 3645,3447,0606,4174,4007,0700,0000,0000,0000 ; 7537 VECIN1: [BRX]_[BRX]*.5 ;SHIFT 1 MORE PLACE ; 7538 [BR]_[BR]+[BRX], ;ADDRESS OF WORD TO USE ; 7539 LOAD VMA, FORCE EXEC, ;FORCE EXEC VIRTUAL ADDRESS U 3645, 3637,0111,0605,4174,4007,0700,0200,0024,0012 ; 7540 START READ, J/PI50 ;GO GET INSTRUCTION ; 7541 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 208 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 PRIORITY INTERRUPTS -- DISMISS SUBROUTINE ; 7542 .TOC "PRIORITY INTERRUPTS -- DISMISS SUBROUTINE" ; 7543 ; 7544 ;SUBROUTINE TO DISMISS THE HIGHEST PI IN PROGRESS ; 7545 ;RETURNS 4 ALWAYS ; 7546 ; 7547 ;DISMISS: ; 7548 ; TR [PI], #/077400 ;ANY PI IN PROGRESS? ; 7549 =0 U 2432, 3646,3771,0005,4374,4007,0700,0000,0004,0000 ; 7550 JEN1: [BR]_#, PI.IP1/1, J/DSMS1 ;YES--START LOOP U 2433, 0004,4443,0000,4174,4004,1700,0000,0000,0000 ; 7551 RETURN [4] ;NO--JUST RETURN ; 7552 U 3646, 2434,4113,0514,4174,4007,0330,0000,0000,0000 ; 7553 DSMS1: [PI].AND.[BR], SKIP ADR.EQ.0 U 2434, 0004,5111,0514,4170,4004,1700,0000,0000,0000 ; 7554 =0 [PI]_[PI].AND.NOT.[BR], HOLD LEFT, RETURN [4] U 2435, 3646,3447,0505,4174,4007,0700,0000,0000,0000 ; 7555 [BR]_[BR]*.5, J/DSMS1 ; 7556 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 209 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 EXTERNAL IO INSTRUCTIONS ; 7557 .TOC "EXTERNAL IO INSTRUCTIONS" ; 7558 ; 7559 .DCODE D 0710, 1210,1614,0100 ; 7560 710: IOT, WORD-TNE, J/TIOX D 0711, 1214,1614,0100 ; 7561 711: IOT, WORD-TNN, J/TIOX D 0720, 1200,1614,0100 ; 7562 720: IOT, TNE, J/TIOX D 0721, 1204,1614,0100 ; 7563 721: IOT, TNN, J/TIOX ; 7564 .UCODE ; 7565 ; 7566 1614: U 1614, 2436,4443,0000,4174,4007,0700,0010,0000,0000 ; 7567 TIOX: CALL [IORD] U 1617, 0014,4551,0305,0274,4003,7700,0000,0000,0000 ; 7568 1617: [BR]_[AR].AND.AC, TEST DISP ; 7569 ; 7570 .DCODE D 0712, 1210,1460,0100 ; 7571 712: IOT, B/10, J/RDIO D 0713, 1210,1461,0100 ; 7572 713: IOT, B/10, J/WRIO D 0722, 1200,1460,0100 ; 7573 722: IOT, B/0, J/RDIO D 0723, 1200,1461,0100 ; 7574 723: IOT, B/0, J/WRIO ; 7575 .UCODE ; 7576 ; 7577 1460: U 1460, 2436,4443,0000,4174,4007,0700,0010,0000,0000 ; 7578 RDIO: CALL [IORD] U 1463, 1400,3440,0303,0174,4007,0700,0400,0000,0000 ; 7579 1463: AC_[AR], J/DONE ; 7580 ; 7581 1461: U 1461, 2446,3771,0005,0276,6007,0700,0000,0000,0000 ; 7582 WRIO: [BR]_AC, J/IOWR ; 7583 ; 7584 .DCODE D 0714, 1210,1644,0100 ; 7585 714: IOT, B/10, J/BIXUB D 0715, 1214,1644,0100 ; 7586 715: IOT, B/14, J/BIXUB D 0724, 1200,1644,0100 ; 7587 724: IOT, B/0, J/BIXUB D 0725, 1204,1644,0100 ; 7588 725: IOT, B/4, J/BIXUB ; 7589 .UCODE ; 7590 ; 7591 1644: ; 7592 BIXUB: [BRX]_[AR], ;SAVE EFFECTIVE ADDRESS U 1644, 2436,3441,0306,4174,4007,0700,0010,0000,0000 ; 7593 CALL [IORD] ;GO GET THE DATA ; 7594 1647: [BR]_[AR], ;COPY DATA ITEM U 1647, 1013,3441,0305,4174,4003,7700,0000,0000,0000 ; 7595 B DISP ;SEE IF SET OR CLEAR ; 7596 =1011 [BR]_[BR].OR.AC, ;SET BITS U 1013, 3647,3551,0505,0274,4007,0700,0000,0000,0000 ; 7597 J/BIXUB1 ;GO DO WRITE ; 7598 [BR]_[BR].AND.NOT.AC, ;CLEAR BITS U 1017, 3647,5551,0505,0274,4007,0700,0000,0000,0000 ; 7599 J/BIXUB1 ;GO DO WRITE ; 7600 ; 7601 BIXUB1: [AR]_[BRX], ;RESTORE ADDRESS U 3647, 2446,3441,0603,4174,4007,0700,0000,0000,0000 ; 7602 J/IOWR ; 7603 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 210 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 EXTERNAL IO INSTRUCTIONS ; 7604 ;SUBROUTINE TO READ FROM AN IO DEVICE ; 7605 ;CALL WITH: ; 7606 ; SECTION 0 EFFECTIVE ADDRESS IN AR ; 7607 ; INSTRUCTION IN HR ; 7608 ;RETURN 3 WITH WORD OR BYTE IN AR ; 7609 ; ; 7610 =0 ; 7611 IORD: CLR IO BUSY, ;CLEAR BUSY U 2436, 2456,4443,0000,4174,4137,0700,0010,0000,0000 ; 7612 CALL [IOEA] ;COMPUTE IO EA U 2437, 0067,4443,0000,4174,4003,7700,0000,0000,0000 ; 7613 B DISP ; 7614 =10111 [BR]_VMA IO READ, ;BYTE MODE ; 7615 IO BYTE/1, ;SET BYTE FLAG U 0067, 2440,4571,1205,4374,4007,0700,0000,0024,1220 ; 7616 J/IORD1 ;GO DO C/A CYCLE U 0077, 2440,4571,1205,4374,4007,0700,0000,0024,1200 ; 7617 =11111 [BR]_VMA IO READ ;WORD MODE ; 7618 = ; 7619 =0 ; 7620 IORD1: VMA_[AR].OR.[BR] WITH FLAGS, U 2440, 3656,3113,0305,4174,4007,0701,0210,0000,0036 ; 7621 CALL [IOWAIT] ;WAIT FOR THINGS COMPLETE ; 7622 MEM READ, ;MAKE SURE REALLY READY ; 7623 [BR]_IO DATA, ;PUT DATA IN BR U 2441, 1027,3771,0005,4364,4003,7700,0200,0000,0002 ; 7624 B DISP ;SEE IF BYTE MODE U 1027, 2442,4553,0300,4374,4007,0331,0000,0000,0001 ; 7625 =0111 TR [AR], #/1, J/IORD2 ;BYTE MODE SEE IF ODD U 1037, 0003,3441,0503,4174,4004,1700,0000,0000,0000 ; 7626 [AR]_[BR], RETURN [3] ;ALL DONE ; 7627 ; 7628 ;HERE ON WORD MODE ; 7629 =0 ; 7630 IORD2: [BR]_[BR]*.5, SC_5, ;LEFT BYTE U 2442, 2444,3447,0505,4174,4007,0700,2000,0071,0005 ; 7631 J/IORD3 ;GO SHIFT IT ; 7632 [AR]_[BR].AND.#, ;MASK IT U 2443, 0003,4551,0503,4374,4004,1700,0000,0000,0377 ; 7633 #/377, RETURN [3] ;ALL DONE ; 7634 ; 7635 =0 ; 7636 IORD3: [BR]_[BR]*.5, ;SHIFT OVER U 2444, 2444,3447,0505,4174,4007,0630,2000,0060,0000 ; 7637 STEP SC, J/IORD3 ; .. ; 7638 [AR]_[BR].AND.#, ;MASK IT U 2445, 0003,4551,0503,4374,4004,1700,0000,0000,0377 ; 7639 #/377, RETURN [3] ;ALL DONE ; 7640 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 211 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 EXTERNAL IO INSTRUCTIONS ; 7641 ;ROUTINE TO WRITE TO AN IO DEVICE ; 7642 ;CALL WITH: ; 7643 ; SECTION 0 EFFECTIVE ADDRESS IN AR ; 7644 ; INSTRUCTION IN HR ; 7645 ; WORD OR BYTE IN BR ; 7646 ;RETURNS BACK TO USER ; 7647 ; ; 7648 =0 ; 7649 IOWR: CLR IO BUSY, ;CLEAR BUSY U 2446, 2456,4443,0000,4174,4137,0700,0010,0000,0000 ; 7650 CALL [IOEA] ;COMPUTE IO EA U 2447, 0227,4443,0000,4174,4003,7700,0000,0000,0000 ; 7651 B DISP U 0227, 2452,4553,0300,4374,4007,0331,0000,0000,0001 ; 7652 =10111 TR [AR], #/1, J/IOWR2 ;BYTE MODE U 0237, 3650,4571,1204,4374,4007,0700,0000,0021,1200 ; 7653 =11111 [ARX]_VMA IO WRITE ;SETUP FLAGS ; 7654 = U 3650, 2450,3113,0304,4174,4007,0701,0200,0000,0036 ; 7655 IOWR1: VMA_[AR].OR.[ARX] WITH FLAGS ; 7656 =0 MEM WRITE, MEM_[BR], ;SEND DATA U 2450, 3656,3333,0005,4175,5007,0701,0210,0000,0002 ; 7657 CALL [IOWAIT] ;WAIT FOR DATA U 2451, 0110,3443,0100,4174,4156,4700,0200,0014,0012 ; 7658 DONE ;RETURN ; 7659 ; 7660 ;HERE FOR BYTE MODE ; 7661 =0 ; 7662 IOWR2: [BR]_[BR]*2, SC_5, ;ODD--MOVE LEFT U 2452, 2454,3445,0505,4174,4007,0700,2000,0071,0005 ; 7663 J/IOWR3 ; .. ; 7664 [ARX]_VMA IO WRITE, ;SETUP FLAGS U 2453, 3650,4571,1204,4374,4007,0700,0000,0021,1220 ; 7665 IO BYTE/1, J/IOWR1 ; .. ; 7666 ; 7667 =0 ; 7668 IOWR3: [BR]_[BR]*2, STEP SC, ;SHIFT LEFT U 2454, 2454,3445,0505,4174,4007,0630,2000,0060,0000 ; 7669 J/IOWR3 ;KEEP SHIFTING ; 7670 [ARX]_VMA IO WRITE, ;SETUP FLAGS U 2455, 3650,4571,1204,4374,4007,0700,0000,0021,1220 ; 7671 IO BYTE/1, J/IOWR1 ; .. ; 7672 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 212 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 EXTERNAL IO INSTRUCTIONS ; 7673 ;HERE TO COMPUTE IO EFFECTIVE ADDRESS ; 7674 ;CALL WITH: ; 7675 ; SECTION 0 EFFECTIVE ADDRESS IN AR ; 7676 ; INSTRUCTION IN HR ; 7677 ;RETURN 1 WITH EA IN AR ; 7678 ; ; 7679 =0 ; 7680 IOEA: VMA_[PC]-1, ;GET INSTRUCTION ; 7681 START READ, ; .. U 2456, 3660,1113,0701,4170,4007,0700,4210,0004,0012 ; 7682 CALL [LOADAR] ;PUT WORD IN AR U 2457, 3651,7441,0306,4174,4007,0700,0000,0000,0000 ; 7683 [BRX]_.NOT.[AR] ;SEE IF IN RANGE 700-777 U 3651, 2460,4553,0600,4374,4007,0321,0000,0070,0000 ; 7684 TL [BRX], #/700000 ; .. ; 7685 =0 U 2460, 2462,4553,0200,4374,4007,0321,0000,0000,0020 ; 7686 IOEA1: TL [HR], #/20, J/IOEA2 ;INDIRECT? ; 7687 WORK[YSAVE]_[AR] CLR LH, ;DIRECT IO INSTRUCTION U 2461, 2460,4713,1203,7174,4007,0700,0400,0000,0422 ; 7688 J/IOEA1 ;SAVE Y FOR EA CALCULATION ; 7689 =0 ; 7690 IOEA2: [AR]_WORK[YSAVE], ;@--GET SAVED Y U 2462, 3652,3771,0003,7274,4007,0701,0000,0000,0422 ; 7691 J/IOEAI ;GET Y AND GO U 2463, 1055,4443,0000,2174,4006,6700,0000,0000,0000 ; 7692 EA MODE DISP ;WAS THERE INDEXING? ; 7693 =1101 [ARX]_XR, SKIP ADL.LE.0, ;SEE IF LOCAL OR GLOBAL INDEXING U 1055, 2466,3771,0004,2274,4007,0120,0000,0000,0000 ; 7694 2T, J/IOEAX ; .. ; 7695 [AR]_WORK[YSAVE], ;JUST PLAIN IO U 1057, 0001,3771,0003,7274,4124,1701,0000,0000,0422 ; 7696 CLR IO LATCH, RETURN [1] ; 7697 ; 7698 IOEAI: READ [HR], DBUS/DP, ;LOAD XR FLOPS IN CASE U 3652, 3653,3333,0002,4174,4217,0700,0000,0000,0000 ; 7699 LOAD INST EA ; THERE IS INDEXING U 3653, 2464,4553,0200,4374,4007,0321,0000,0000,0017 ; 7700 TL [HR], #/17 ;WAS THERE ALSO INDEXING U 2464, 2465,0551,0303,2270,4007,0701,0000,0000,0000 ; 7701 =0 [AR]_[AR]+XR, 3T, HOLD LEFT ;YES--ADD IN INDEX VALUE U 2465, 3654,3443,0300,4174,4007,0700,0200,0004,0012 ; 7702 VMA_[AR], START READ ;FETCH DATA WORD ; 7703 MEM READ, [AR]_MEM, ;GO GET DATA WORD U 3654, 0001,3771,0003,4365,5124,1700,0200,0000,0002 ; 7704 CLR IO LATCH, RETURN [1] ; 7705 ; 7706 =0 ; 7707 IOEAX: [AR]_[ARX]+WORK[YSAVE], ;GLOBAL INDEXING U 2466, 0001,0551,0403,7274,4124,1701,0000,0000,0422 ; 7708 CLR IO LATCH, RETURN [1] U 2467, 3655,0551,0403,7274,4007,0701,0000,0000,0422 ; 7709 [AR]_[ARX]+WORK[YSAVE] ;LOCAL INDEXING ; 7710 [AR]_0, HOLD RIGHT, U 3655, 0001,4221,0003,4174,0124,1700,0000,0000,0000 ; 7711 CLR IO LATCH, RETURN [1] ; 7712 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 213 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 EXTERNAL IO INSTRUCTIONS ; 7713 ;WAIT FOR IO TO COMPLETE ; 7714 ;RETURNS 1 OR PAGE FAILS ; 7715 ; ; 7716 IOWAIT: SC_S#, S#/200, ;DELAY ; 7717 [T0]_VMA, ;GET VMA U 3656, 1124,3771,0016,4354,4007,0650,2000,0071,0200 ; 7718 SKIP/-IO BUSY ;SEE IF BUSY YET ; 7719 =00 ; 7720 IOW1: CLR IO LATCH, ;WENT BUSY ; 7721 WORK[SV.VMA]_[T0], ;MAKE SURE SV.VMA IS SETUP U 1124, 3657,3333,0016,7174,4127,0700,0400,0000,0210 ; 7722 J/IOW2 ;WAIT FOR IT TO CLEAR ; 7723 SC_SC-1, SCAD DISP, 5T, ;SEE IF DONE YET ; 7724 SKIP/-IO BUSY, ; .. U 1125, 1124,4443,0000,4174,4006,7653,2000,0060,0000 ; 7725 J/IOW1 ;BACK TO LOOP ; 7726 CLR IO LATCH, ;WENT BUSY AND TIMEOUT ; 7727 WORK[SV.VMA]_[T0], ;MAKE SURE SV.VMA IS SETUP U 1126, 3657,3333,0016,7174,4127,0700,0400,0000,0210 ; 7728 J/IOW2 ; .. ; 7729 WORK[SV.VMA]_[T0], ;MAKE SURE SV.VMA IS SETUP U 1127, 2473,3333,0016,7174,4007,0700,0400,0000,0210 ; 7730 J/IOW5 ;GO TRAP ; 7731 ; 7732 IOW2: SC_S#, S#/777, ;GO TIME IO U 3657, 2470,4443,0000,4174,4007,0650,2000,0071,0777 ; 7733 SKIP/-IO BUSY ; .. ; 7734 =0 ; 7735 IOW3: CLR IO LATCH, ;TRY TO CLEAR LATCH U 2470, 2472,4443,0000,4174,4127,0630,2000,0060,0000 ; 7736 STEP SC, J/IOW4 ;STILL BUSY U 2471, 0001,4443,0000,4174,4004,1700,0000,0000,0000 ; 7737 RETURN [1] ;IDLE ; 7738 ; 7739 =0 ; 7740 IOW4: CLR IO LATCH, 5T, ;TRY TO CLEAR LATCH ; 7741 SKIP/-IO BUSY, ;SEE IF STILL BUSY U 2472, 2470,4443,0000,4174,4127,0653,0000,0000,0000 ; 7742 J/IOW3 ; .. U 2473, 1501,4571,1206,4374,4007,0700,0000,0020,0000 ; 7743 IOW5: [BRX]_[200000] XWD 0, J/HARD ; 7744 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 214 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 SMALL SUBROUTINES ; 7745 .TOC "SMALL SUBROUTINES" ; 7746 ; 7747 ;HERE ARE A COLLECTION ON 1-LINE SUBROUTINES ; 7748 LOADAR: MEM READ, [AR]_MEM, ;FROM MEMORY TO AR U 3660, 0001,3771,0003,4365,5004,1700,0200,0000,0002 ; 7749 RETURN [1] ;RETURN TO CALLER ; 7750 U 3661, 0001,3771,0004,4365,5004,1700,0200,0000,0002 ; 7751 LOADARX: MEM READ, [ARX]_MEM, RETURN [1] ; 7752 U 3662, 0001,3772,0000,4365,5004,1700,0200,0000,0002 ; 7753 LOADQ: MEM READ, Q_MEM, RETURN [1] ; 7754 U 3663, 0001,4221,0004,4174,0004,1700,0000,0000,0000 ; 7755 CLARXL: [ARX]_0, HOLD RIGHT, RETURN [1] ; 7756 U 3664, 0001,0111,0703,4174,4004,1700,0000,0000,0000 ; 7757 INCAR: [AR]_[AR]+1, RETURN [1] ; 7758 U 3665, 0001,3445,0505,4174,4004,1700,0000,0000,0000 ; 7759 SBRL: [BR]_[BR]*2, RETURN [1] ; 7760 U 3666, 0001,3443,0300,4174,4004,1701,0200,0000,0036 ; 7761 STRTIO: VMA_[AR] WITH FLAGS, RETURN [1] ; 7762 U 3667, 0004,3333,0005,4175,5004,1701,0200,0000,0002 ; 7763 STOBR: MEM WRITE, MEM_[BR], RETURN [4] ; 7764 U 3670, 0001,3333,0001,4175,5004,1701,0200,0000,0002 ; 7765 STOPC: MEM WRITE, MEM_[PC], RETURN [1] ; 7766 U 3671, 0001,3440,0404,0174,4004,1700,0400,0000,0000 ; 7767 AC_ARX: AC_[ARX], RETURN [1] ; 7768 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 215 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 UNDEFINED IO INSTRUCTIONS ; 7769 .TOC "UNDEFINED IO INSTRUCTIONS" ; 7770 ; 7771 .DCODE D 0703, 0003,1650,2100 ; 7772 703: I, B/3, J/IOT700 D 0706, 0006,1650,2100 ; 7773 706: I, B/6, J/IOT700 D 0707, 0007,1650,2100 ; 7774 I, B/7, J/IOT700 ; 7775 D 0716, 0006,1651,2100 ; 7776 716: I, B/6, J/IOT710 D 0717, 0007,1651,2100 ; 7777 I, B/7, J/IOT710 ; 7778 D 0726, 0006,1652,2100 ; 7779 726: I, B/6, J/IOT720 D 0727, 0007,1652,2100 ; 7780 I, B/7, J/IOT720 ; 7781 D 0730, 0000,1653,2100 ; 7782 730: I, B/0, J/IOT730 D 0731, 0001,1653,2100 ; 7783 I, B/1, J/IOT730 D 0732, 0002,1653,2100 ; 7784 I, B/2, J/IOT730 D 0733, 0003,1653,2100 ; 7785 I, B/3, J/IOT730 D 0734, 0004,1653,2100 ; 7786 I, B/4, J/IOT730 D 0735, 0005,1653,2100 ; 7787 I, B/5, J/IOT730 D 0736, 0006,1653,2100 ; 7788 I, B/6, J/IOT730 D 0737, 0007,1653,2100 ; 7789 I, B/7, J/IOT730 ; 7790 D 0740, 0000,1654,2100 ; 7791 740: I, B/0, J/IOT740 D 0741, 0001,1654,2100 ; 7792 I, B/1, J/IOT740 D 0742, 0002,1654,2100 ; 7793 I, B/2, J/IOT740 D 0743, 0003,1654,2100 ; 7794 I, B/3, J/IOT740 D 0744, 0004,1654,2100 ; 7795 I, B/4, J/IOT740 D 0745, 0005,1654,2100 ; 7796 I, B/5, J/IOT740 D 0746, 0006,1654,2100 ; 7797 I, B/6, J/IOT740 D 0747, 0007,1654,2100 ; 7798 I, B/7, J/IOT740 ; 7799 D 0750, 0000,1655,2100 ; 7800 750: I, B/0, J/IOT750 D 0751, 0001,1655,2100 ; 7801 I, B/1, J/IOT750 D 0752, 0002,1655,2100 ; 7802 I, B/2, J/IOT750 D 0753, 0003,1655,2100 ; 7803 I, B/3, J/IOT750 D 0754, 0004,1655,2100 ; 7804 I, B/4, J/IOT750 D 0755, 0005,1655,2100 ; 7805 I, B/5, J/IOT750 D 0756, 0006,1655,2100 ; 7806 I, B/6, J/IOT750 D 0757, 0007,1655,2100 ; 7807 I, B/7, J/IOT750 ; 7808 D 0760, 0000,1656,2100 ; 7809 760: I, B/0, J/IOT760 D 0761, 0001,1656,2100 ; 7810 I, B/1, J/IOT760 D 0762, 0002,1656,2100 ; 7811 I, B/2, J/IOT760 D 0763, 0003,1656,2100 ; 7812 I, B/3, J/IOT760 D 0764, 0004,1656,2100 ; 7813 I, B/4, J/IOT760 D 0765, 0005,1656,2100 ; 7814 I, B/5, J/IOT760 D 0766, 0006,1656,2100 ; 7815 I, B/6, J/IOT760 D 0767, 0007,1656,2100 ; 7816 I, B/7, J/IOT760 ; 7817 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 216 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 UNDEFINED IO INSTRUCTIONS D 0770, 0000,1657,2100 ; 7818 770: I, B/0, J/IOT770 D 0771, 0001,1657,2100 ; 7819 I, B/1, J/IOT770 D 0772, 0002,1657,2100 ; 7820 I, B/2, J/IOT770 D 0773, 0003,1657,2100 ; 7821 I, B/3, J/IOT770 D 0774, 0004,1657,2100 ; 7822 I, B/4, J/IOT770 D 0775, 0005,1657,2100 ; 7823 I, B/5, J/IOT770 D 0776, 0006,1657,2100 ; 7824 I, B/6, J/IOT770 D 0777, 0007,1657,2100 ; 7825 I, B/7, J/IOT770 ; 7826 .UCODE ; 7827 ; 7828 1650: U 1650, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7829 IOT700: UUO ; 7830 1651: ; 7831 IOT710: ; 7832 .IFNOT/UBABLT U 1651, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7833 UUO ;;7834 .IF/UBABLT ;;7835 J/BLTX ;GO TO COMMON CODE FOR UBABLT INSTRS ; 7836 .ENDIF/UBABLT ; 7837 1652: U 1652, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7838 IOT720: UUO ; 7839 1653: U 1653, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7840 IOT730: UUO ; 7841 1654: U 1654, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7842 IOT740: UUO ; 7843 1655: U 1655, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7844 IOT750: UUO ; 7845 1656: U 1656, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7846 IOT760: UUO ; 7847 1657: U 1657, 2737,4551,0202,4374,0007,0700,0000,0077,7740 ; 7848 IOT770: UUO ; 7849 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 217 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 UMOVE AND UMOVEM ; 7850 .TOC "UMOVE AND UMOVEM" ; 7851 ; 7852 .DCODE D 0704, 1200,1754,0100 ; 7853 704: IOT, J/UMOVE D 0705, 1200,1755,0100 ; 7854 IOT, J/UMOVEM ; 7855 .UCODE ; 7856 ; 7857 1754: ; 7858 UMOVE: VMA_[AR], ;LOAD VMA ; 7859 START READ, ;START MEMORY U 1754, 3672,3443,0300,4174,4207,0700,0200,0004,0012 ; 7860 SPEC/PREV ;FORCE PREVIOUS ; 7861 MEM READ, ;WAIT FOR MEMORY ; 7862 [AR]_MEM, ;PUT DATA IN AR U 3672, 1515,3771,0003,4365,5007,0700,0200,0000,0002 ; 7863 J/STAC ;GO PUT AR IN AC ; 7864 ; 7865 1755: ; 7866 UMOVEM: VMA_[AR], ;LOAD VMA ; 7867 START WRITE, ;START MEMORY U 1755, 3673,3443,0300,4174,4207,0700,0200,0003,0012 ; 7868 SPEC/PREV ;FORCE PREVIOUS ; 7869 [AR]_AC, ;FETCH AC U 3673, 1516,3771,0003,0276,6007,0700,0000,0000,0000 ; 7870 J/STMEM ;STORE IN MEMORY ; 7871 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 218 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 UMOVE AND UMOVEM ; 7872 ;HERE WITH HALT CODE IN THE T1 ; 7873 =010* ; 7874 HALTED: WORK[SV.ARX]_[ARX], ;SAVE TEMP REGISTER U 0104, 3676,3333,0004,7174,4007,0700,0410,0000,0212 ; 7875 CALL [SAVVMA] ;PUT VMA IN WORK[SV.VMA] ; 7876 =110* ABORT MEM CYCLE, ;ABORT CYCLE IN PROGRESS U 0114, 3675,4223,0000,4364,4277,0700,0210,0000,0010 ; 7877 CALL [WRTHSB] ;WRITE HALT STATUS BLOCK ; 7878 =111* U 0116, 3674,4221,0004,4174,4007,0700,0200,0021,1016 ; 7879 PWRON: [ARX]_0, VMA PHYSICAL WRITE ;STORE HALT CODE ; 7880 = U 3674, 2474,3333,0017,4175,5007,0701,0200,0000,0002 ; 7881 MEM WRITE, MEM_[T1] ; IN LOCATION 0 ; 7882 =0 NEXT [ARX] PHYSICAL WRITE, U 2474, 3670,0111,0704,4170,4007,0700,0210,0023,1016 ; 7883 CALL [STOPC] U 2475, 0005,4443,0000,4174,4107,0700,0000,0000,0074 ; 7884 H1: SET HALT, J/HALTLP ;TELL CONSOLE WE HAVE HALTED ; 7885 ; 7886 ; 7887 4: UNHALT, ;RESET CONSOLE U 0004, 2476,4443,0000,4174,4107,0640,0000,0000,0062 ; 7888 SKIP EXECUTE, J/CONT ;SEE IF CO OR EX ; 7889 5: U 0005, 0004,4443,0000,4174,4007,0660,0000,0000,0000 ; 7890 HALTLP: SKIP/-CONTINUE, J/4 ;WAIT FOR CONTINUE ; 7891 ; 7892 =0 ; 7893 CONT: VMA_[PC], ;LOAD PC INTO VMA ; 7894 FETCH, ;START READ U 2476, 0117,3443,0100,4174,4007,0700,0200,0014,0012 ; 7895 J/XCTGO ;DO THE INSTRUCTION U 2477, 2500,4571,1203,4374,4007,0700,0000,0024,1200 ; 7896 [AR]_VMA IO READ ;PUT FLAGS IN AR ; 7897 =0 [AR]_[AR].OR.#, ;PUT IN ADDRESS ; 7898 #/200000, HOLD LEFT, ; OF CSL REGISTER U 2500, 3666,3551,0303,4370,4007,0700,0010,0020,0000 ; 7899 CALL [STRTIO] ; 7900 CONT1: MEM READ, ;WAIT FOR DATA ; 7901 [HR]_MEM, ;PUT IN HR ; 7902 LOAD INST, ;LOAD IR, ETC. U 2501, 2716,3771,0002,4365,5617,0700,0200,0000,0002 ; 7903 J/XCT1 ;GO DO THE INSTRUCTION ; 7904 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 219 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 WRITE HALT STATUS BLOCK ; 7905 .TOC "WRITE HALT STATUS BLOCK" ; 7906 ; 7907 ;THE HALT STATUS BLOCK LOOKS LIKE: ; 7908 ; 7909 ; !=======================================================! ; 7910 ; !00! MAG ! ; 7911 ; !-------------------------------------------------------! ; 7912 ; !01! PC ! ; 7913 ; !-------------------------------------------------------! ; 7914 ; !02! HR ! ; 7915 ; !-------------------------------------------------------! ; 7916 ; !03! AR ! ; 7917 ; !-------------------------------------------------------! ; 7918 ; !04! ARX ! ; 7919 ; !-------------------------------------------------------! ; 7920 ; !05! BR ! ; 7921 ; !-------------------------------------------------------! ; 7922 ; !06! BRX ! ; 7923 ; !-------------------------------------------------------! ; 7924 ; !07! ONE ! ; 7925 ; !-------------------------------------------------------! ; 7926 ; !10! EBR ! ; 7927 ; !-------------------------------------------------------! ; 7928 ; !11! UBR ! ; 7929 ; !-------------------------------------------------------! ; 7930 ; !12! MASK ! ; 7931 ; !-------------------------------------------------------! ; 7932 ; !13! FLG ! ; 7933 ; !-------------------------------------------------------! ; 7934 ; !14! PI ! ; 7935 ; !-------------------------------------------------------! ; 7936 ; !15! XWD1 ! ; 7937 ; !-------------------------------------------------------! ; 7938 ; !16! T0 ! ; 7939 ; !-------------------------------------------------------! ; 7940 ; !17! T1 ! ; 7941 ; !=======================================================! ; 7942 ; ! VMA FLAGS ! VMA ! ; 7943 ; !=======================================================! ; 7944 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 220 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 WRITE HALT STATUS BLOCK ; 7945 ;START AT 1 TO DUMP 2901 REGISTERS INTO MAIN MEMORY ; 7946 1: WORK[SV.ARX]_[ARX], ;SAVE TEMP REGISTER U 0001, 3676,3333,0004,7174,4007,0700,0410,0000,0212 ; 7947 CALL [SAVVMA] ;WORK[SV.VMA]_VMA U 0011, 0024,3771,0004,7274,4007,0701,0000,0000,0227 ; 7948 11: [ARX]_WORK[HSBADR] U 0024, 3700,4223,0000,4364,4277,0700,0210,0000,0010 ; 7949 =10* ABORT MEM CYCLE, CALL [DUMP] U 0026, 2475,4443,0000,4174,4107,0700,0000,0000,0074 ; 7950 SET HALT, J/H1 ; 7951 ; 7952 ; 7953 WRTHSB: [ARX]_WORK[HSBADR], ;GET ADDRESS OF HSB U 3675, 2502,3771,0004,7274,4007,0422,0000,0000,0227 ; 7954 SKIP AD.LE.0, 4T ;SEE IF VALID ; 7955 =0 READ [MASK], LOAD PI, ;TURN OFF PI SYSTEM U 2502, 3700,3333,0012,4174,4437,0700,0000,0000,0000 ; 7956 J/DUMP ; AND GO TAKE DUMP ; 7957 [ARX]_WORK[SV.ARX], U 2503, 0002,3771,0004,7274,4004,1701,0000,0000,0212 ; 7958 RETURN [2] ;DO NOT DUMP ANYTHING ; 7959 U 3676, 3677,3771,0004,4354,4007,0700,0000,0000,0000 ; 7960 SAVVMA: [ARX]_VMA ; 7961 WORK[SV.VMA]_[ARX], U 3677, 0010,3333,0004,7174,4004,1700,0400,0000,0210 ; 7962 RETURN [10] ; 7963 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 221 ; INOUT.MIC[7,3] 13:32 7-JAN-1986 WRITE HALT STATUS BLOCK ; 7964 ;DUMP OUT THE 2901 U 3700, 2504,3333,0004,4174,4007,0700,0200,0021,1016 ; 7965 DUMP: READ [ARX], VMA PHYSICAL WRITE U 2504, 2746,3333,0000,4175,5007,0701,0210,0000,0002 ; 7966 =0* MEM WRITE, MEM_[MAG], CALL [NEXT] U 2506, 3701,3333,0001,4175,5007,0701,0200,0000,0002 ; 7967 MEM WRITE, MEM_[PC] U 3701, 2505,0111,0704,4170,4007,0700,0200,0023,1016 ; 7968 NEXT [ARX] PHYSICAL WRITE U 2505, 2746,3333,0002,4175,5007,0701,0210,0000,0002 ; 7969 =0* MEM WRITE, MEM_[HR], CALL [NEXT] U 2507, 2510,3333,0003,4175,5007,0701,0200,0000,0002 ; 7970 MEM WRITE, MEM_[AR] U 2510, 2746,3333,0003,7174,4007,0700,0410,0000,0211 ; 7971 =0* WORK[SV.AR]_[AR], CALL [NEXT] U 2512, 2511,3771,0003,7274,4007,0701,0000,0000,0212 ; 7972 [AR]_WORK[SV.ARX] U 2511, 2746,3333,0003,4175,5007,0701,0210,0000,0002 ; 7973 =0* MEM WRITE, MEM_[AR], CALL [NEXT] U 2513, 3702,3333,0005,4175,5007,0701,0200,0000,0002 ; 7974 MEM WRITE, MEM_[BR] U 3702, 2514,0111,0704,4170,4007,0700,0200,0023,1016 ; 7975 NEXT [ARX] PHYSICAL WRITE U 2514, 2746,3333,0006,4175,5007,0701,0210,0000,0002 ; 7976 =0* MEM WRITE, MEM_[BRX], CALL [NEXT] U 2516, 3703,3333,0007,4175,5007,0701,0200,0000,0002 ; 7977 MEM WRITE, MEM_[ONE] U 3703, 2515,0111,0704,4170,4007,0700,0200,0023,1016 ; 7978 NEXT [ARX] PHYSICAL WRITE U 2515, 2746,3333,0010,4175,5007,0701,0210,0000,0002 ; 7979 =0* MEM WRITE, MEM_[EBR], CALL [NEXT] U 2517, 3704,3333,0011,4175,5007,0701,0200,0000,0002 ; 7980 MEM WRITE, MEM_[UBR] U 3704, 2520,0111,0704,4170,4007,0700,0200,0023,1016 ; 7981 NEXT [ARX] PHYSICAL WRITE U 2520, 2746,3333,0012,4175,5007,0701,0210,0000,0002 ; 7982 =0* MEM WRITE, MEM_[MASK], CALL [NEXT] U 2522, 3705,3333,0013,4175,5007,0701,0200,0000,0002 ; 7983 MEM WRITE, MEM_[FLG] U 3705, 2521,0111,0704,4170,4007,0700,0200,0023,1016 ; 7984 NEXT [ARX] PHYSICAL WRITE U 2521, 2746,3333,0014,4175,5007,0701,0210,0000,0002 ; 7985 =0* MEM WRITE, MEM_[PI], CALL [NEXT] U 2523, 3706,3333,0015,4175,5007,0701,0200,0000,0002 ; 7986 MEM WRITE, MEM_[XWD1] U 3706, 2524,0111,0704,4170,4007,0700,0200,0023,1016 ; 7987 NEXT [ARX] PHYSICAL WRITE U 2524, 2746,3333,0016,4175,5007,0701,0210,0000,0002 ; 7988 =0* MEM WRITE, MEM_[T0], CALL [NEXT] U 2526, 2525,3333,0017,4175,5007,0701,0200,0000,0002 ; 7989 MEM WRITE, MEM_[T1] U 2525, 2746,3771,0003,7274,4007,0701,0010,0000,0210 ; 7990 =0* [AR]_WORK[SV.VMA], CALL [NEXT] U 2527, 3707,3333,0003,4175,5007,0701,0200,0000,0002 ; 7991 MEM WRITE, MEM_[AR] U 3707, 3710,3771,0003,7274,4007,0701,0000,0000,0211 ; 7992 HSBDON: [AR]_WORK[SV.AR] U 3710, 3711,3771,0004,7274,4007,0701,0000,0000,0210 ; 7993 [ARX]_WORK[SV.VMA] U 3711, 3712,3443,0400,4174,4007,0700,0200,0000,0010 ; 7994 VMA_[ARX] ; 7995 [ARX]_WORK[SV.ARX], U 3712, 0006,3771,0004,7274,4004,1701,0000,0000,0212 ; 7996 RETURN [6] ; 7997 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 222 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 WRITE HALT STATUS BLOCK ; 7998 .NOBIN ; 7999 .TOC "PAGE FAIL REFIL LOGIC" ; 8000 ; 8001 ;WHEN THE CPU CAN NOT COMPLETE A MEMORY REFERENCE BECAUSE THE PAGE ; 8002 ; TABLE DOES NOT CONTAIN VALID INFORMATION FOR THE VIRTUAL PAGE INVOLVED ; 8003 ; THE HARDWARE CALLS THIS ROUTINE TO RELOAD THE HARDWARE PAGE TABLE. ; 8004 ; ; 8005 ;THIS CODE WILL EITHER DO THE RELOAD OR GENERATE A PAGE FAIL FOR THE ; 8006 ; SOFTWARE. THE INFORMATION LOADED CONSISTS OF THE PHYSICAL PAGE NUMBER, ; 8007 ; THE CACHE ENABLE BIT AND THE WRITE ENABLE BIT. ; 8008 ; 8009 ;THIS LOGIC USES MANY VARIABLES. THEY ARE DESCRIBED BRIEFLY HERE: ; 8010 ; 8011 ;THING WHERE KEPT USE ; 8012 ;OLD VMA WORKSPACE WORD 210 SAVES VMA ; 8013 ;OLD AR WORKSPACE WORD 211 SAVES AR ; 8014 ;OLD ARX WORKSPACE WORD 212 SAVES ARX ; 8015 ;OLD BR WORKSPACE WORD 213 SAVES BR ; 8016 ;OLD BRX WORKSPACE WORD 214 SAVES BRX ; 8017 ;KL PAGING BIT EBR BIT 1 (IN 2901) INDICATES KL STYLE (TOPS-20) PAGING ; 8018 ; INSTEAD OF KI STYLE (TOPS-10 AND DIAGNOSTIC) ; 8019 ; MODE PAGING ; 8020 ;W BIT FLG BIT 4 PAGE CAN BE WRITTEN ; 8021 ;C BIT FLG BIT 6 DATA IN THIS PAGE MAY BE PUT ; 8022 ; INTO CACHE ; 8023 ;PI CYCLE FLG BIT 5 STORING OLD PC DURING PI ; 8024 ;MAP FLAG FLG BIT 18 MAP INSTRUCTION IN PROGRESS ; 8025 ;CLEANUP CODE FLG BITS 32-35 WHAT TO DO SO INSTRUCTION MAY BE ; 8026 ; RESTARTED ; 8027 ;SPT BASE WORKSPACE WORD 215 ADDRESS OF SHARED-POINTER-TABLE ; 8028 ;CST BASE WORKSPACE WORD 216 ADDRESS OF CORE-STATUS-TABLE ; 8029 ;CST MASK WORKSPACE WORD 217 BITS TO KEEP ON CST UPDATE ; 8030 ;CST DATA (PUR) WORKSPACE WORD 220 BITS TO SET ON CST UPDATE ; 8031 ;PAGE TABLE ADDRESS AR WHERE THIS PAGE TABLE IS LOCATED ; 8032 ;PHYSICAL PAGE # (PPN) AR RESULT OF THIS PROCESS ; 8033 ;CST ENTRY AR CORE STATUS TABLE ENTRY ; 8034 ;SPT ENTRY AR WORD FROM SPT ; 8035 ;PAGE TABLE ENTRY AR WORD FROM PT ; 8036 ;PAGE NUMBER BR INDEX INTO CURENT PAGE TABLE ; 8037 ;PAGE FAIL WORD BRX WHAT HAPPENED (ALSO MAP RESULT) ; 8038 ;;8039 .IF/INHCST ;;8040 SKIP NO CST "AD/D,DBUS/RAM,RAMADR/#,WORK/CBR,DT/4T,SKIP/ADEQ0" ; 8041 .ENDIF/INHCST ; 8042 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 223 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8043 ; ; 8044 ; ; 8045 ; ; 8046 ; KL10 PAGING - WORD FORMATS ; 8047 ; ; 8048 ;Section Pointer ; 8049 ; ; 8050 ;The section pointer is found in the user or exec section table. ; 8051 ;(Part of UPT or EPT.) ; 8052 ; ; 8053 ;Section pointer provides (via the SPT) the physical address of ; 8054 ;the PAGE TABLE for the given section. ; 8055 ; ; 8056 ; Code: 0 No-access (trap) ; 8057 ; 1 Immediate ; 8058 ; 2 Share ; 8059 ; 3 Indirect ; 8060 ; 4-7 Unused, reserved ; 8061 ; ; 8062 ; 0 1 2 3 4 5 6 18 35 ; 8063 ; +----+-+-+-+-+---------+-------------------------+ ; 8064 ; !CODE!P!W! !C!/////////! PAGE TABLE IDENTIFIER ! ; 8065 ; !010 ! ! ! ! !/////////! (SPT INDEX) ! ; 8066 ; +----+-+-+-+-+---------+-------------------------+ ; 8067 ; ; 8068 ; NORMAL SECTION POINTER (Code = 2) ; 8069 ; ; 8070 ; 0 2 3 4 5 6 9 18 35 ; 8071 ; +----+-+-+-+-+---+-----------+------------------------+ ; 8072 ; !CODE!P!W! !C!///!SECTION !SECTION TABLE IDENTIFIER! ; 8073 ; !011 ! ! ! ! !///!TABLE INDEX! (SPT INDEX) ! ; 8074 ; +----+-+-+-+-+---+-----------+------------------------+ ; 8075 ; ; 8076 ; INDIRECT SECTION POINTER (Code = 3) ; 8077 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 224 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8078 ;PAGE POINTERS ; 8079 ; ; 8080 ;FOUND IN PAGE TABLES ; 8081 ; ; 8082 ; 0 1 2 3 4 5 6 12 35 ; 8083 ; +----+-+-+-+-+----+------------------------------+ ; 8084 ; !CODE!P!W! !C!////! PHYSICAL ADDRESS OF PAGE ! ; 8085 ; !001 ! ! ! ! !////! ! ; 8086 ; +----+-+-+-+-+----+------------------------------+ ; 8087 ; ; 8088 ; IMMEDIATE POINTER (code field = 1) ; 8089 ; ; 8090 ; B12-35 give PHYSICAL ADDRESS OF PAGE ; 8091 ; if B12-17 >< 0, page not in core-trap ; 8092 ; if B12-17 = 0, B23-35 give CORE PAGE ; 8093 ; NUMBER of page, B18-22 MBZ ; 8094 ; ; 8095 ; ; 8096 ; ; 8097 ; ; 8098 ; ; 8099 ; 0 2 3 6 18 35 ; 8100 ; +-----+-------+---------+------------------------+ ; 8101 ; !CODE !SAME AS!/////////! SPT INDEX ! ; 8102 ; !010 ! IMMED.!/////////! ! ; 8103 ; +-----+-------+---------+------------------------+ ; 8104 ; ; 8105 ; SHARED POINTER (code field = 2) ; 8106 ; ; 8107 ; B18-35 Give SPT INDEX (SPTX). SPTX + SPT BASE ; 8108 ; ADDRESS = physical core address of word ; 8109 ; holding physical address of page. ; 8110 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 225 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8111 ; 0 1 2 3 6 9 17 18 35 ; 8112 ; +----+--------+---+-------+----------------------+ ; 8113 ; !CODE!SAME AS !///! PAGE ! PAGE TABLE IDENTIFIER! ; 8114 ; !011 ! IMMED. !///!NUMBER ! (SPT INDEX) ! ; 8115 ; +----+--------+---+-------+----------------------+ ; 8116 ; ; 8117 ; INDIRECT POINTER (code field = 3) ; 8118 ; ; 8119 ; This pointer type causes another pointer to be fetched ; 8120 ; and interpreted. The new pointer is found in word N ; 8121 ; (B9-17) of the page addressed by C(SPT + SPTX). ; 8122 ; ; 8123 ; ; 8124 ; ; 8125 ; SPT ENTRY ; 8126 ; ; 8127 ; Found in the SPT, i.e., when fetching C(SPT +SPTX) ; 8128 ; ; 8129 ; 12 35 ; 8130 ; +--------------------+---------------------------+ ; 8131 ; !////////////////////! PHYSICAL ADDRESS OF PAGE ! ; 8132 ; !////////////////////! OR PAGE TABLE ! ; 8133 ; +--------------------+---------------------------+ ; 8134 ; ; 8135 ; B12-35 Give PHYSICAL ADDRESS of page. ; 8136 ; ; 8137 ; The base address (physical core address) of the SPT ; 8138 ; resides in one AC of the reserved AC block. ; 8139 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 226 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8140 ;PHYSICAL STORAGE ADDRESS ; 8141 ; ; 8142 ;Found in B12-35 of IMMEDIATE POINTERS and SPT ENTRIES. ; 8143 ; ; 8144 ; 12 17 18 23 35 ; 8145 ; +---------+----+-----------------+ ; 8146 ; ! !MBZ ! CORE PAGE NUMBER! ; 8147 ; ! ! ! IF B12-17 = 0 ! ; 8148 ; +---------+----+-----------------+ ; 8149 ; ; 8150 ; If B12-17 = 0, then B23-35 are CORE PAGE NUMBER (i.e., ; 8151 ; B14-26 of physical core address) of page and B18-22 ; 8152 ; MBZ. If B12-17 >< 0, then address is not core and ; 8153 ; pager traps. ; 8154 ; ; 8155 ; ; 8156 ; ; 8157 ;CORE STATUS TABLE ENTRY ; 8158 ; ; 8159 ;Found when fetching C(CBR + CORE PAGENO) ; 8160 ; ; 8161 ; 0 5 32 34 35 ; 8162 ; +-------+-------------------------------+------+-+ ; 8163 ; ! CODE ! ! !M! ; 8164 ; +-------+-------------------------------+------+-+ ; 8165 ; ; 8166 ; B0-5 are code field: ; 8167 ; ; 8168 ; 0 - unavailable, trap ; 8169 ; ; 8170 ; 1-77 - available ; 8171 ; ; 8172 ; ; 8173 ; ; 8174 ; B32-34 reserved for future hardware specification. ; 8175 ; ; 8176 ; B35 is "modified" bit, set on any write ref to page. ; 8177 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 227 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8178 ;QUANTITIES IN HARDWARE REGISTERS ; 8179 ; ; 8180 ;SPT SPT Base Register ; 8181 ; ; 8182 ; 14 35 ; 8183 ; +--------------------------------+ ; 8184 ; ! PHYSICAL CORE WORD ADDRESS ! ; 8185 ; +--------------------------------+ ; 8186 ; ; 8187 ;CBR CST Base Register ; 8188 ; ; 8189 ; 14 35 ; 8190 ; +--------------------------------+ ; 8191 ; ! PHYSICAL CORE WORD ADDRESS ! ; 8192 ; +--------------------------------+ ; 8193 ; ; 8194 ;CSTMSK CST Update Mask ; 8195 ; ; 8196 ; 0 32 35 ; 8197 ; +------------------------------------------+---+-+ ; 8198 ; ! MASK !111!1! ; 8199 ; +------------------------------------------+---+-+ ; 8200 ; ; 8201 ; ANDed with CST word during update ; 8202 ; ; 8203 ;(B32-35 must be all 1's to preserve existing CST information) ; 8204 ; ; 8205 ;CSTDATA CST Update Data ; 8206 ; ; 8207 ; 0 32 34 35 ; 8208 ; +------------------------------------------+---+-+ ; 8209 ; ! DATA !000!0! ; 8210 ; +------------------------------------------+---+-+ ; 8211 ; ; 8212 ; IORed with CST word during update ; 8213 ; ; 8214 ;(B32-35 must be all 0's to preserve existing CST information) ; 8215 ; ; 8216 ;All unspecified bits and fields are reserved for future ; 8217 ;specification by DEC. ; 8218 ; ; 8219 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 228 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8220 .BIN ; 8221 ; 8222 .DCODE D 0257, 1215,1553,0100 ; 8223 257: IOT, AC, J/MAP ; 8224 .UCODE ; 8225 ; 8226 1553: ; 8227 MAP: [AR]_[AR].OR.#, ;ASSUME PHYSICAL REF ; 8228 #/160000, ;FAKE ANSWER U 1553, 3713,3551,0303,4374,0007,0700,0000,0016,0000 ; 8229 HOLD RIGHT ; .. U 3713, 3714,3771,0006,4354,4007,0700,0000,0000,0000 ; 8230 [BRX]_VMA ;PUT VMA AND FLAGS IN BRX ; 8231 [BRX]_[BRX].AND.#, ;JUST KEEP USER BIT U 3714, 3715,4551,0606,4374,0007,0700,0000,0040,0000 ; 8232 #/400000, HOLD RIGHT ; .. U 3715, 3716,3333,0006,7174,4007,0700,0400,0000,0210 ; 8233 WORK[SV.VMA]_[BRX] ;SAVE IN WORKSPACE U 3716, 3717,3771,0005,7274,4007,0701,0000,0000,0230 ; 8234 [BR]_WORK[APR] ;GET APR FLAGS U 3717, 2530,4553,0500,4374,4007,0331,0000,0003,0000 ; 8235 TR [BR], #/030000 ;PAGING ENABLED? U 2530, 3727,3771,0013,4370,4007,0700,0000,0040,0002 ; 8236 =0 STATE_[MAP], J/PFMAP ;YES--DO REAL MAP U 2531, 0100,3440,0303,0174,4156,4700,0400,0000,0000 ; 8237 AC_[AR], NEXT INST ;NO--RETURN VIRTUAL ADDRESS ; 8238 ;HARDWARE COMES HERE ON PAGE TABLE NOT VALID (OR INTERRUPT) WHEN ; 8239 ; STARTING A MEMORY REFERENCE. MICOWORD ADDRESS OF INSTRUCTION DOING ; 8240 ; MEM WAIT IS SAVED ON THE STACK. ; 8241 3777: ; 8242 PAGE-FAIL: U 3777, 3720,3333,0003,7174,4007,0700,0400,0000,0211 ; 8243 WORK[SV.AR]_[AR] U 3720, 3721,3333,0006,7174,4007,0700,0400,0000,0214 ; 8244 ITRAP: WORK[SV.BRX]_[BRX] U 3721, 3722,3771,0006,4354,4007,0700,0000,0000,0000 ; 8245 [BRX]_VMA U 3722, 3723,3333,0006,7174,4007,0700,0400,0000,0210 ; 8246 WORK[SV.VMA]_[BRX] ; 8247 WORK[SV.ARX]_[ARX], U 3723, 1060,3333,0004,7174,4007,0370,0400,0000,0212 ; 8248 SKIP IRPT ;SEE IF INTERRUPT (SAVE DISPATCH) ; 8249 =0000 ; 8250 PFD: DBM/PF DISP, DBUS/DBM, ;BRING CODE TO 2901'S ; 8251 AD/D, DEST/PASS, 4T, ;PUT ON DP 18-21 U 1060, 1060,3773,0000,4304,4003,1702,0000,0000,0000 ; 8252 DISP/DP LEFT, J/PFD ;DISPATCH ON IT ; 8253 =0001 ;(1) INTERRUPT U 1061, 1503,3333,0005,7174,4007,0700,0400,0000,0213 ; 8254 WORK[SV.BR]_[BR], J/PFPI1 ; 8255 =0011 ;(3) BAD DATA FROM MEMORY ; 8256 [BRX]_IO DATA, ;GET THE BAD DATA ; 8257 AD PARITY OK/0, ; DO NOT LOOK AT PARITY U 1063, 3724,3771,0006,4374,4007,0700,0000,0000,0000 ; 8258 J/BADDATA ;SAVE IN AC BLK 7 ; 8259 =0101 ;(5) NXM ERROR U 1065, 1501,4571,1206,4374,4007,0700,0000,0037,0000 ; 8260 [BRX]_[370000] XWD 0, J/HARD ; 8261 =0111 ;(7) NXM & BAD DATA U 1067, 1501,4571,1206,4374,4007,0700,0000,0037,0000 ; 8262 [BRX]_[370000] XWD 0, J/HARD ; 8263 =1000 ;(10) WRITE VIOLATION U 1070, 3727,3333,0005,7174,4007,0700,0400,0000,0213 ; 8264 WORK[SV.BR]_[BR], J/PFMAP ; 8265 =1001 ;[123] (11) 1 ms timer and movsrj U 1071, 1503,3333,0005,7174,4007,0700,0400,0000,0213 ; 8266 WORK[SV.BR]_[BR], J/PFPI1 ; 8267 =1010 ;(12) PAGE NOT VALID U 1072, 3727,3333,0005,7174,4007,0700,0400,0000,0213 ; 8268 WORK[SV.BR]_[BR], J/PFMAP ; 8269 =1011 ;(13) EXEC/USER MISMATCH U 1073, 3727,3333,0005,7174,4007,0700,0400,0000,0213 ; 8270 WORK[SV.BR]_[BR], J/PFMAP ; 8271 = ; 8272 ; 8273 BADDATA: U 3724, 3725,3333,0006,7174,4007,0700,0400,0000,0160 ; 8274 WORK[BADW0]_[BRX] ;SAVE BAD WORD U 3725, 3726,3333,0006,7174,4007,0700,0400,0000,0161 ; 8275 WORK[BADW1]_[BRX] ;AGAIN ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 228-1 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC U 3726, 1501,4571,1206,4374,4007,0700,0000,0036,0000 ; 8276 [BRX]_[360000] XWD 0, J/HARD ; 8277 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 229 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8278 ;WE HAVE SAVED AR, ARX, BR AND BRX. WE MERGE IN HERE FROM MAP ; 8279 ; INSTRUCTION, SAVE THE VMA AND START THE PAGE FAIL WORD. U 3727, 3730,4223,0000,4364,4277,0700,0200,0000,0010 ; 8280 PFMAP: ABORT MEM CYCLE ;CLEAR PAGE FAIL ; 8281 [FLG]_[FLG].OR.#, ;PRESET W AND C TO 1 ; 8282 FLG.W/1, FLG.C/1, ;BITS INVOLVED U 3730, 3731,3551,1313,4374,0007,0700,0000,0002,4000 ; 8283 HOLD RIGHT ;LEAVE RH ALONE U 3731, 2532,4553,0600,4374,4007,0321,0000,0002,0000 ; 8284 TL [BRX], WRITE TEST/1 ;IS THIS A WRITE TEST? ; 8285 =0 [BRX]_[BRX].OR.#, ; 8286 #/10000, U 2532, 2533,3551,0606,4374,0007,0700,0000,0001,0000 ; 8287 HOLD RIGHT ;YES--TURN INTO WRITE REF ; 8288 [BRX]_[BRX].AND.#, ;START PAGE FAIL WORD ; 8289 #/411000, ;SAVE 3 INTERESTING BITS U 2533, 3732,4551,0606,4374,0007,0700,0000,0041,1000 ; 8290 HOLD RIGHT ;SAVE VIRTUAL ADDRESS ; 8291 ;USER ADDR (400000) ; 8292 ;WRITE REF (010000) ; 8293 ;PAGED REF (001000) ; 8294 [BRX]_[BRX].XOR.#, ;FIX BIT 8 U 3732, 3733,6551,0606,4374,0007,0700,0000,0000,1000 ; 8295 #/1000, HOLD RIGHT ; 8296 [BR]_[BRX], ;COPY VIRTUAL ADDRESS U 3733, 2534,3441,0605,4174,4007,0700,2000,0071,0007 ; 8297 SC_7 ;PREPARE TO SHIFT 9 PLACES ; 8298 =0 ; 8299 PF25: [BR]_[BR]*.5, ;RIGHT ADJUST PAGE # ; 8300 STEP SC, ;COUNT SHIFT STEPS U 2534, 2534,3447,0505,4174,4007,0630,2000,0060,0000 ; 8301 J/PF25 ;LOOP FOR 9 ; 8302 [BR]_[BR].AND.# CLR LH, ;MASK TO 9 BITS U 2535, 3734,4251,0505,4374,4007,0700,0000,0000,0777 ; 8303 #/777 ; .. ; 8304 .IF/KLPAGE ; 8305 .IF/KIPAGE ; 8306 TL [EBR], ;KI MODE REFILL? U 3734, 2536,4553,1000,4374,4007,0321,0000,0000,0040 ; 8307 #/40 ;FLAG BIT ; 8308 =0 ; 8309 .ENDIF/KIPAGE ; 8310 READ [BRX], ;USER REF? (KL MODE) ; 8311 SKIP DP0, ; .. U 2536, 2540,3333,0006,4174,4007,0520,0000,0000,0000 ; 8312 J/PF30 ;CONTINUE AT PF30 ; 8313 .ENDIF/KLPAGE ; 8314 .IF/KIPAGE ; 8315 [ARX]_[BR]*.5, ;KI10 MODE REFILL U 2537, 3774,3447,0504,4174,4007,0700,0000,0000,0000 ; 8316 J/KIFILL ;GO HANDLE EASY CASE ; 8317 .ENDIF/KIPAGE ; 8318 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 230 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8319 .IF/KLPAGE ; 8320 ;HERE IN TOPS-20 MODE ; 8321 ;PICK UP CORRECT SECTION POINTER ; 8322 =0 ; 8323 PF30: [ARX]_WORK[PTA.E], ;EXEC MODE ; 8324 SKIP AD.EQ.0, 4T, ;SEE IF VALID U 2540, 2544,3771,0004,7274,4007,0622,0000,0000,0423 ; 8325 J/PF35 ;CONTINUE BELOW ; 8326 [ARX]_WORK[PTA.U], ;USER MODE U 2541, 2542,3771,0004,7274,4007,0622,0000,0000,0424 ; 8327 SKIP AD.EQ.0, 4T ;SEE IF VALID ; 8328 =0 VMA_[ARX]+[BR], ;POINTER VALID ; 8329 VMA PHYSICAL READ, ;START MEMORY U 2542, 1130,0113,0405,4174,4007,0700,0200,0024,1016 ; 8330 J/PF77 ;CONTINUE BELOW ; 8331 [AR]_[UBR]+#, 3T, ;USER MODE ; 8332 #/540, ;OFFSET TO UPT U 2543, 3735,0551,1103,4374,4007,0701,0000,0000,0540 ; 8333 J/PF40 ;GO GET POINTER ; 8334 ; 8335 =0 ; 8336 PF35: VMA_[ARX]+[BR], ;POINTER VALID ; 8337 VMA PHYSICAL READ, ;START MEMORY U 2544, 1130,0113,0405,4174,4007,0700,0200,0024,1016 ; 8338 J/PF77 ;CONTINUE BELOW ; 8339 [AR]_[EBR]+#, 3T, ;EXEC MODE U 2545, 3735,0551,1003,4374,4007,0701,0000,0000,0540 ; 8340 #/540 ;OFFSET TO EPT ; 8341 PF40: VMA_[AR], ;LOAD THE VMA ; 8342 START READ, ;START THE MEMORY CRANKING U 3735, 3736,3443,0300,4174,4007,0700,0200,0024,1016 ; 8343 VMA PHYSICAL ;ABSOLUTE ADDRESS ; 8344 MEM READ, ;WAIT FOR MEMORY U 3736, 1000,3771,0003,4365,5007,0700,0200,0000,0002 ; 8345 [AR]_MEM ;POINT POINTER IN AR ; 8346 ;LOOK AT SECTION POINTER AND DISPATCH ON TYPE ; 8347 =000 ; 8348 PF45: SC_7, ;FETCH SECTION 0 POINTER U 1000, 3767,4443,0000,4174,4007,0700,2010,0071,0007 ; 8349 CALL [SETPTR] ;FIGURE OUT POINTER TYPE ; 8350 SECIMM: TL [AR], ;IMMEDIATE POINTER ; 8351 #/77, ;TEST FOR 12-17 = 0 U 1001, 2552,4553,0300,4374,4007,0321,0000,0000,0077 ; 8352 J/PF50 ;CONTINUE AT PF50 ; 8353 [AR]_[AR]+WORK[SBR], ;SHARED SECTION U 1002, 2550,0551,0303,7274,4007,0701,0000,0000,0215 ; 8354 J/SECSHR ;GO FETCH POINTER FROM SPT ; 8355 [AR]_[AR]+WORK[SBR], ;INDIRECT SECTION POINTER U 1003, 3772,0551,0303,7274,4007,0701,0010,0000,0215 ; 8356 CALL [RDPT] ;GO FETCH SPT ENTRY ; 8357 =111 TL [AR], ;12 TO 17 = 0? U 1007, 2546,4553,0300,4374,4007,0321,0000,0000,0077 ; 8358 #/77 ; .. ; 8359 = U 2546, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8360 =0 PAGE FAIL TRAP ;NO ; 8361 [AR]_[AR]*2, ;FIRST SHIFT U 2547, 0602,3445,0303,4174,4007,0630,2000,0060,0000 ; 8362 STEP SC ;SC WAS LOADED AT PF45 ; 8363 =0*0 ; 8364 PF60: [AR]_[AR]*2, ;CONVERT TO ADDRESS OF ; 8365 STEP SC, ; SECTION TABLE U 0602, 0602,3445,0303,4174,4007,0630,2000,0060,0000 ; 8366 J/PF60 U 0603, 3772,4443,0000,4174,4007,0700,0010,0000,0000 ; 8367 CALL [RDPT] ;READ SECTION TABLE U 0607, 1000,4443,0000,4174,4007,0700,0000,0000,0000 ; 8368 =1*1 J/PF45 ;TRY AGAIN ; 8369 = ; 8370 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 231 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8371 ;STILL .IF/KLPAGE ; 8372 ;HERE FOR SHARED SECTION. AR GETS THE ADDRESS OF PAGE TABLE ; 8373 =0** U 2550, 3772,4443,0000,4174,4007,0700,0010,0000,0000 ; 8374 SECSHR: CALL [RDPT] ;READ WORD FROM SPT U 2554, 2552,4553,0300,4374,4007,0321,0000,0000,0077 ; 8375 TL [AR], #/77 ;TEST FOR BITS 12-17 = 0 ; 8376 ; 8377 ;HERE WITH ADDRESS OF PAGE TABLE IN AR AND SKIP ON ; 8378 ; BITS 12 THRU 17 EQUAL TO ZERO ; 8379 =0 U 2552, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8380 PF50: PAGE FAIL TRAP ;BITS 12-17 .NE. 0 ; 8381 [ARX]_[AR].AND.# CLR LH, ;PAGE NUMBER OF PAGE TABLE U 2553, 2555,4251,0304,4374,4007,0700,0000,0000,3777 ; 8382 #/3777 ;11 BIT PHYSICAL PAGE # ; 8383 .IFNOT/NOCST ; 8384 =0* [AR]_[ARX], ;COPY ADDRESS U 2555, 2622,3441,0403,4174,4007,0700,0010,0000,0000 ; 8385 CALL [UPCST] ;UPDATE CST0 U 2557, 2560,3551,0303,7274,4007,0701,0000,0000,0220 ; 8386 PF70: [AR]_[AR].OR.WORK[PUR] ;PUT IN NEW AGE AND ; 8387 ; USE BITS ; 8388 .IFNOT/INHCST ; 8389 =0** START NO TEST WRITE, ;START MEMORY WRITE U 2560, 3075,4443,0000,4174,4007,0700,0210,0001,0002 ; 8390 CALL [IBPX] ;GO STORE IN MEMORY ; 8391 .ENDIF/INHCST ;;8392 .IF/INHCST ;;8393 =0** SKIP NO CST, ;SEE IF A CST ;;8394 CALL [WRCST] ;AND GO WRITE IN MEMORY ; 8395 .ENDIF/INHCST U 2564, 2562,4443,0000,4174,4007,0700,2000,0071,0007 ; 8396 SC_7 ;THIS CAN BE BUMMED ; 8397 =0 ; 8398 PF75: [ARX]_[ARX]*2, ;CONVERT PAGE NUMBER TO ; 8399 STEP SC, ; PAGE ADDRESS U 2562, 2562,3445,0404,4174,4007,0630,2000,0060,0000 ; 8400 J/PF75 ;LOOP OVER 9 STEPS ; 8401 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 232 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8402 ;STILL .IF/KLPAGE ; 8403 ;WE NOW HAVE THE ADDRESS OF THE PAGE TABLE ENTRY. GO ; 8404 ; READ IT AND START ANALYSIS ; 8405 ; 8406 ;IF WE ARE HERE FOR THE FIRST TIME FOR THE USER OR EXEC SAVE THE ; 8407 ; ADDRESS OF THE PAGE TABLE IN PTA.E OR PTA.U SO THAT WE DO NOT ; 8408 ; HAVE TO DO THE SECTION LOOKUP EVERY TIME. U 2563, 1040,3333,0006,4174,4007,0520,0000,0000,0000 ; 8409 READ [BRX], SKIP DP0 ;USER OR EXEC REF? ; 8410 =000 [AR]_WORK[PTA.E], ;EXEC MODE ; 8411 SKIP AD.EQ.0, 4T, ;SEE IF SET YET U 1040, 2642,3771,0003,7274,4007,0622,0010,0000,0423 ; 8412 CALL [SHDREM] ;SHOULD WE REMEMBER PTR ; 8413 [AR]_WORK[PTA.U], ;USER MODE ; 8414 SKIP AD.EQ.0, 4T, ;SEE IF SET YET U 1041, 2642,3771,0003,7274,4007,0622,0010,0000,0424 ; 8415 CALL [SHDREM] ;SHOULD WE REMEMBER PTR ; 8416 WORK[PTA.E]_[ARX], ;SAVE FOR EXEC U 1042, 1047,3333,0004,7174,4007,0700,0400,0000,0423 ; 8417 J/PF76 ;CONTINUE BELOW ; 8418 WORK[PTA.U]_[ARX], ;SAVE FOR USER U 1043, 1047,3333,0004,7174,4007,0700,0400,0000,0424 ; 8419 J/PF76 ;CONTINUE BELOW ; 8420 =111 ; 8421 PF76: VMA_[ARX]+[BR], ;READ PAGE POINTER ; 8422 START READ, U 1047, 1130,0113,0405,4174,4007,0700,0200,0024,1016 ; 8423 VMA PHYSICAL ; 8424 = ; 8425 =00 ; 8426 PF77: MEM READ, ;START ANALYSIS OF POINTER ; 8427 [AR]_MEM, U 1130, 3767,3771,0003,4365,5007,0700,0210,0000,0002 ; 8428 CALL [SETPTR] ; 8429 PTRIMM: TL [AR], ;IMMEDIATE POINTER ; 8430 #/77, ;CHECK FOR BITS 0-5 U 1131, 1134,4553,0300,4374,4007,0321,0000,0000,0077 ; 8431 J/PF80 ;GO TO PF80 ; 8432 [AR]_[AR]+WORK[SBR], ;SHARED POINTER U 1132, 2561,0551,0303,7274,4007,0701,0000,0000,0215 ; 8433 J/PTRSHR ;GO TO READ SPT ; 8434 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 233 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8435 ;STILL .IF/KLPAGE ; 8436 ;INDIRECT POINTER. CHANGE PAGE # AND LOOK FOR PAGE TABLE ; 8437 PTRIND: [BR]_[AR] SWAP, ;PUT IN RIGHT HALF U 1133, 2566,3770,0305,4344,4007,0670,0000,0000,0000 ; 8438 SKIP/-1 MS ;DID CLOCK GO OFF ; 8439 =0 WORK[SV.AR1]_[AR], ;YES--UPDATE CLOCK U 2566, 2600,3333,0003,7174,4007,0700,0400,0000,0426 ; 8440 J/PFTICK ; .. ; 8441 [BR]_[BR].AND.# CLR LH, ;UPDATE PAGE # AND RESTART ; 8442 #/777, ;MASK FOR PAGE # U 2567, 2570,4251,0505,4374,4007,0370,0000,0000,0777 ; 8443 SKIP IRPT ;SEE IF THIS IS A LOOP ; 8444 =0 [AR]_[AR].AND.#, ;CHANGE INDIRECT POINTER ; 8445 #/277000, ; INTO SHARE POINTER ; 8446 HOLD RIGHT, ; .. U 2570, 1000,4551,0303,4374,0007,0700,0000,0027,7000 ; 8447 J/PF45 ;GO BACK AND TRY AGAIN U 2571, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8448 PAGE FAIL TRAP ;POINTER LOOP ; 8449 ; 8450 =0** U 2561, 3772,4443,0000,4174,4007,0700,0010,0000,0000 ; 8451 PTRSHR: CALL [RDPT] ;GO LOOK AT POINTER ; 8452 TL [AR], ;BITS 12-17 .EQ. 0? U 2565, 1134,4553,0300,4374,4007,0321,0000,0000,0077 ; 8453 #/77 ; 8454 ; 8455 ;HERE WITH FINAL POINTER. SKIP IF 12-17 NOT EQUAL TO ZERO ; 8456 .IFNOT/NOCST ; 8457 =00 U 1134, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8458 PF80: PAGE FAIL TRAP ;NO--TAKE A TRAP ; 8459 [ARX]_[AR].AND.# CLR LH, ;SAVE PHYSICAL PAGE # ; 8460 #/3777, ;MASK TO 13 BITS U 1135, 2622,4251,0304,4374,4007,0700,0010,0000,3777 ; 8461 CALL [UPCST] ;UPDATE CST0 ; 8462 =11 ;;8463 .IF/NOCST ;;8464 =0 ;;8465 PF80: PAGE FAIL TRAP ;NO--TAKE A TRAP ; 8466 .ENDIF/NOCST ; 8467 ; 8468 ;HERE WE HAVE CST ENTRY IN AR, PAGE FAIL WORD IN BRX. GO LOOK ; 8469 ; AT WRITABLE AND WRITTEN BITS ; 8470 PF90: [BRX]_[BRX].OR.#, ;TRANSLATION IS VALID U 1137, 3737,3551,0606,4374,0007,0700,0000,0010,0000 ; 8471 #/100000, HOLD RIGHT ; .. U 3737, 2572,4553,1300,4374,4007,0321,0000,0002,0000 ; 8472 TL [FLG], FLG.W/1 ;IS THIS PAGE WRITABLE? ; 8473 =0 [BRX]_[BRX].OR.#, ;YES--INDICATE THAT IN PFW ; 8474 #/020000, U 2572, 3745,3551,0606,4374,4007,0700,0000,0002,0000 ; 8475 J/PF100 ;NOT WRITE VIOLATION ; 8476 TL [BRX], ;IS THIS A WRITE REF? U 2573, 2574,4553,0600,4374,4007,0321,0000,0003,0000 ; 8477 WRITE TEST/1, WRITE CYCLE/1 U 2574, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8478 =0 PAGE FAIL TRAP ;WRITE VIOLATION ; 8479 PF107: ; 8480 .IFNOT/NOCST ; 8481 [AR]_[AR].OR.WORK[PUR], ;PUT IN NEW AGE U 2575, 2603,3551,0303,7274,4007,0701,0000,0000,0220 ; 8482 J/PF110 ;GO TO STORE CST ENTRY ; 8483 .ENDIF/NOCST ;;8484 .IF/NOCST ;;8485 PFDONE: TR [FLG], ;;8486 #/400000, ;;8487 J/PF140 ; 8488 .ENDIF/NOCST ; 8489 ; 8490 =0* ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 233-1 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8491 PFTICK: [AR]_WORK[TIME1], ;UPDATE TIMER U 2600, 3561,3771,0003,7274,4117,0701,0010,0000,0301 ; 8492 SPEC/CLRCLK, CALL [TOCK] ; 8493 [AR]_WORK[SV.AR1], ;RESTORE AR U 2602, 1133,3771,0003,7274,4007,0701,0000,0000,0426 ; 8494 J/PTRIND ;GO TRY AGAIN ; 8495 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 234 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8496 ;STILL .IF/KLPAGE ; 8497 ;HERE IF PAGE IS WRITABLE U 3745, 2576,4553,0600,4374,4007,0321,0000,0001,0000 ; 8498 PF100: TL [BRX], WRITE CYCLE/1 ;IS THIS A WRITE REF? ; 8499 =0 [AR]_[AR].OR.#, ;YES--SET WRITTEN BIT ; 8500 #/1, ; 8501 HOLD LEFT, U 2576, 2604,3551,0303,4370,4007,0700,0000,0000,0001 ; 8502 J/PF105 ; 8503 TR [AR], ;NOT WRITE, ALREADY WRITTEN? U 2577, 2604,4553,0300,4374,4007,0331,0000,0000,0001 ; 8504 #/1 ; 8505 =0 ; 8506 PF105: [BRX]_[BRX].OR.#, ;WRITTEN SET BIT ; 8507 #/040000, ;MARK PAGE AS ; 8508 HOLD RIGHT, ;WRITABLE U 2604, 2575,3551,0606,4374,0007,0700,0000,0004,0000 ; 8509 J/PF107 ;STORE CST WORD ; 8510 [FLG]_[FLG].AND.NOT.#, ;NOT WRITTEN, CAUSE TRAP ON ; 8511 FLG.W/1, ; WRITE ATTEMPT ; 8512 HOLD RIGHT, ;ONLY CLEAR LH U 2605, 2575,5551,1313,4374,0007,0700,0000,0002,0000 ; 8513 J/PF107 ; 8514 .IFNOT/NOCST ; 8515 =0** ; 8516 PF110: ; 8517 .IFNOT/INHCST ; 8518 START NO TEST WRITE, U 2603, 3075,4443,0000,4174,4007,0700,0210,0001,0002 ; 8519 CALL [IBPX] ;STORE CST ENTRY ; 8520 .ENDIF/INHCST ;;8521 .IF/INHCST ;;8522 SKIP NO CST, ;;8523 CALL [WRCST] ; 8524 .ENDIF/INHCST ; 8525 ; 8526 .ENDIF/KLPAGE ; 8527 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 235 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8528 ; 8529 ;HERE WHEN WE HAVE FIGURED OUT PHYSICAL ADDRESS (IN ARX) AND FLAGS ; 8530 ; (IN BRX) RELOAD PAGE TABLE. ; 8531 PFDONE: TR [FLG], ;MAP INSTRUCTION? U 2607, 2610,4553,1300,4374,4007,0331,0000,0040,0000 ; 8532 #/400000 ; 8533 .ENDIF/NOCST ; 8534 =0 ; 8535 PF140: [AR]_[ARX], ;GET PHYSCIAL PAGE # ; 8536 SC_7, ;PREPARE TO CONVERT TO U 2610, 2612,3441,0403,4174,4007,0700,2000,0071,0007 ; 8537 J/PF130 ; WORD ADDRESS ; 8538 [AR]_WORK[SV.VMA], ;RESTORE VMA U 2611, 3753,3771,0003,7274,4007,0701,0000,0000,0210 ; 8539 J/PF120 ; 8540 =0 ; 8541 PF130: [AR]_[AR]*2, ;CONVERT TO WORD # ; 8542 STEP SC, U 2612, 2612,3445,0303,4174,4007,0630,2000,0060,0000 ; 8543 J/PF130 ; 8544 [AR]_[AR].AND.#, ;JUST ADDRESS BITS ; 8545 #/3, U 2613, 3746,4551,0303,4374,0007,0700,0000,0000,0003 ; 8546 HOLD RIGHT U 3746, 3747,4221,0013,4170,4007,0700,0000,0000,0000 ; 8547 END MAP ;CLEAR MAP FLAGS ; 8548 [BRX]_[BRX].OR.#, ;TURN ON THE TRANSLATION ; 8549 #/100000, ; VALID BIT U 3747, 3750,3551,0606,4374,0007,0700,0000,0010,0000 ; 8550 HOLD RIGHT ; IN LEFT HALF ONLY U 3750, 2614,4553,1300,4374,4007,0321,0000,0000,4000 ; 8551 TL [FLG], FLG.C/1 ;CACHE BIT SET? ; 8552 =0 [BRX]_[BRX].OR.#, ;YES--SET IN MAP WORD U 2614, 2615,3551,0606,4374,0007,0700,0000,0000,2000 ; 8553 #/002000, HOLD RIGHT ; .. ; 8554 [BRX]_[BRX].AND.#, ;PRESERVE WORD # U 2615, 3752,4551,0606,4370,4007,0700,0000,0000,0777 ; 8555 #/777, HOLD LEFT ; IN PAGE FAIL WORD ; 8556 [AR]_[AR].OR.[BRX], ;COMPLETE MAP INSTRUCTION U 3752, 1500,3111,0603,4174,4003,7700,0200,0003,0001 ; 8557 EXIT ; 8558 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 236 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC U 3753, 3755,3441,0305,4174,4007,0700,0000,0000,0000 ; 8559 PF120: [BR]_[AR] ;COPY PAGE FAIL WORD ; 8560 [BR]_[AR].AND.NOT.#, ;CLEAR BITS WHICH START A CYCLE ; 8561 READ CYCLE/1, ; .. ; 8562 WRITE CYCLE/1, ; .. ; 8563 WRITE TEST/1, ; .. U 3755, 3756,5551,0305,4374,0007,0700,0000,0007,0000 ; 8564 HOLD RIGHT ;JUST DO LEFT HALF ; 8565 VMA_[BR], 3T, ;RESTORE VMA U 3756, 3757,3443,0500,4174,4007,0701,0200,0000,0030 ; 8566 DP FUNC/1 ;SET USER ACCORDING TO WHAT IT WAS ; 8567 [ARX]_[ARX].AND.# CLR LH, ;JUST KEEP PAGE # U 3757, 3760,4251,0404,4374,4007,0700,0000,0000,3777 ; 8568 #/3777 ; .. U 3760, 3761,3551,0406,4374,4007,0700,0000,0040,0000 ; 8569 [BRX]_[ARX].OR.#, #/400000 ;SET VALID BITS U 3761, 2616,4553,1300,4374,4007,0321,0000,0002,0000 ; 8570 TL [FLG], FLG.W/1 ;WANT WRITE SET? U 2616, 2617,3551,0606,4374,4007,0700,0000,0004,0000 ; 8571 =0 [BRX]_[BRX].OR.#, #/040000 ;SET WRITE BIT ; 8572 TL [FLG], FLG.C/1, ;WANT CACHE SET? U 2617, 2620,4553,1300,4374,4147,0321,0000,0000,4000 ; 8573 LOAD PAGE TABLE ;LOAD PAGE TABLE ON NEXT ; 8574 ; MICRO INSTRUCTION ; 8575 =0 [BRX]_[BRX].OR.#, ;SET CACHE BIT U 2620, 3762,3551,0606,4374,4007,0700,0000,0002,0000 ; 8576 #/020000, J/PF125 ;CACHE BIT U 2621, 3762,3333,0006,4174,4007,0700,0000,0000,0000 ; 8577 READ [BRX] ;LOAD PAGE TABLE U 3762, 3763,3771,0004,7274,4007,0701,0000,0000,0212 ; 8578 PF125: [ARX]_WORK[SV.ARX] U 3763, 3764,3771,0005,7274,4007,0701,0000,0000,0213 ; 8579 [BR]_WORK[SV.BR] U 3764, 3765,3771,0006,7274,4007,0701,0000,0000,0214 ; 8580 [BRX]_WORK[SV.BRX] ; 8581 VMA_[AR], ;MAKE MEM REQUEST ; 8582 DP FUNC/1, 3T, ;FROM DATA PATH U 3765, 3766,3443,0300,4174,4007,0701,0200,0000,0032 ; 8583 WAIT/1 ;WAIT FOR PREVIOUS CYCLE TO ; 8584 ; COMPLETE. (NEED THIS TO ; 8585 ; START ANOTHER CYCLE) ; 8586 [AR]_WORK[SV.AR], U 3766, 0000,3771,0003,7274,4004,1701,0000,0000,0211 ; 8587 RETURN [0] ; 8588 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 237 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8589 .IF/KLPAGE ; 8590 .IFNOT/NOCST ; 8591 ;SUBROUTINE TO START CST UPDATE ; 8592 ;CALL WITH: ; 8593 ; AR/ PHYSICAL PAGE NUMBER ; 8594 ;RETURN 2 WITH ENTRY IN AR, PAGE FAIL IF AGE TOO SMALL ; 8595 .IFNOT/INHCST ; 8596 =0** ; 8597 UPCST: [AR]_[AR]+WORK[CBR], ;ADDRESS OF CST0 ENTRY U 2622, 3772,0551,0303,7274,4007,0701,0010,0000,0216 ; 8598 CALL [RDPT] ;READ OLD VALUE ; 8599 TL [AR], ;0 - 5 = 0? U 2626, 2624,4553,0300,4374,4007,0321,0000,0077,0000 ; 8600 #/770000 ; .. ; 8601 =0 [AR]_[AR].AND.WORK[CSTM], ;CLEAR AGE FIELD U 2624, 0002,4551,0303,7274,4004,1701,0000,0000,0217 ; 8602 RETURN [2] ;AGE IS NOT ZERO U 2625, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8603 PAGE FAIL TRAP ;AGE TOO SMALL ; 8604 .ENDIF/INHCST ;;8605 .IF/INHCST ;;8606 UPCST: SKIP NO CST ;SEE IF A CST IS PRESENT ;;8607 =0*0 [AR]_[AR]+WORK[CBR], ;YES, ADDRESS OF CST0 ENTRY ;;8608 CALL [RDPT] ;READ OLD VALUE ;;8609 [AR]_0,RETURN [2] ;NO CST, RETURN ;;8610 TL [AR], ;CHECK AGE FIELD ;;8611 #/770000 ;;8612 = ;;8613 =0 [AR]_[AR].AND.WORK[CSTM], ;CLEAR AGE FIELD ;;8614 RETURN [2] ;AGE IS NOT ZERO ;;8615 PAGE FAIL TRAP ;AGE TOO SMALL ;;8616 ;;8617 =0 ;;8618 WRCST: START NO TEST WRITE, ;;8619 J/IBPX ;;8620 RETURN [4] ; 8621 .ENDIF/INHCST ; 8622 .ENDIF/NOCST ; 8623 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 238 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8624 ;STILL .IF/KLPAGE ; 8625 ;SUBROUTINE TO LOOK AT PAGE POINTER ; 8626 ;CALL WITH POINTER IN AR ; 8627 ;RETURNS 1 IF TYPE 1 ; 8628 ;RETURNS 2 IF TYPE 2 ; 8629 ;RETURNS 3 IF TYPE 3 ; 8630 ;GOES TO PFT IF TYPE 0 OR 4 THRU 7 ; 8631 SETPTR: [ARX]_[AR].OR.#, ;AND C AND W BITS U 3767, 3770,3551,0304,4374,4007,0700,0000,0075,3777 ; 8632 #/753777 ; OF ALL POINTERS ; 8633 [FLG]_[FLG].AND.[ARX], ; .. U 3770, 3771,4111,0413,4174,0007,0700,0000,0000,0000 ; 8634 HOLD RIGHT ;KEEP IN LH OF FLG ; 8635 READ [AR], ;TYPE 4,5,6 OR 7? U 3771, 2630,3333,0003,4174,4007,0520,0000,0000,0000 ; 8636 SKIP DP0 ; .. ; 8637 =0 TL [AR], ;HERE WE TEST FOR TYPE ; 8638 #/300000, ; ZERO POINTER U 2630, 2632,4553,0300,4374,4007,0321,0000,0030,0000 ; 8639 J/STPTR1 ;CHECK AT STPTR1 U 2631, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8640 PAGE FAIL TRAP ;BAD TYPE ; 8641 =0 ; 8642 STPTR1: TL [AR], ;NOT ZERO ; 8643 #/100000, ;SEPERATE TYPE 2 U 2632, 2634,4553,0300,4374,4007,0321,0000,0010,0000 ; 8644 J/STPTR2 ; .. U 2633, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8645 PAGE FAIL TRAP ;TYPE 0 ; 8646 ; 8647 =0 ; 8648 STPTR2: TL [AR], ;SEPERATE TYPE 1 ; 8649 #/200000, ; AND 3 U 2634, 2636,4553,0300,4374,4007,0321,0000,0020,0000 ; 8650 J/STPTR3 ; .. U 2635, 0002,4443,0000,4174,4004,1700,0000,0000,0000 ; 8651 RETURN [2] ;TYPE 2 ; 8652 ; 8653 =0 U 2636, 0003,4443,0000,4174,4004,1700,0000,0000,0000 ; 8654 STPTR3: RETURN [3] ;TYPE 3 U 2637, 0001,4443,0000,4174,4004,1700,0000,0000,0000 ; 8655 RETURN [1] ;TYPE 1 ; 8656 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 239 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8657 ;STILL .IF/KLPAGE ; 8658 ;SUBROUTINE TO FETCH A PAGE POINTER OR CST ENTRY ; 8659 ;CALL WITH ADDRESS IN AR ; 8660 ;RETURN 4 WITH WORD IN AR ; 8661 ; ; 8662 RDPT: VMA_[AR], ;LOAD THE VMA ; 8663 START READ, ;START MEM CYCLE ; 8664 VMA PHYSICAL, ;ABSOLUTE ADDRESS U 3772, 2640,3443,0300,4174,4007,0370,0200,0024,1016 ; 8665 SKIP IRPT ;CHECK FOR INTERRUPTS ; 8666 =0 MEM READ, ;NO INTERRUPTS ; 8667 [AR]_MEM, ;PUT THE DATA INTO AR U 2640, 0004,3771,0003,4365,5004,1700,0200,0000,0002 ; 8668 RETURN [4] ;AND RETURN U 2641, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8669 PAGE FAIL TRAP ;INTERRUPT ; 8670 ; 8671 ; 8672 ;SUBROUTINE TO SEE IF WE SHOULD REMEMBER AN EXEC SECTION PTR ; 8673 ;CALL WITH SKIP ON ADR.EQ.0 ; 8674 ;RETURNS 2 IF WE SHOULD STORE AND 7 IF WE SHOULD NOT ; 8675 ; ; 8676 =0 U 2642, 0007,4443,0000,4174,4004,1700,0000,0000,0000 ; 8677 SHDREM: RETURN [7] ;INDIRECT PTR U 2643, 3773,7441,1303,4174,4007,0700,0000,0000,0000 ; 8678 [AR]_.NOT.[FLG] ;FLIP BITS U 3773, 2644,4553,0300,4374,4007,0321,0000,0002,4000 ; 8679 TL [AR], FLG.W/1, FLG.C/1 ;BOTH BITS SET U 2644, 0007,4443,0000,4174,4004,1700,0000,0000,0000 ; 8680 =0 RETURN [7] ;NO--DON'T STORE U 2645, 0002,4443,0000,4174,4004,1700,0000,0000,0000 ; 8681 RETURN [2] ;STORE ; 8682 ; 8683 .ENDIF/KLPAGE ; 8684 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 240 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8685 .IF/KIPAGE ; 8686 ;HERE IN KI10 MODE ; 8687 ;BR CONTAINS PAGE # AND ARX CONTAINS PAGE #/2 ; 8688 ; 8689 KIFILL: READ [BRX], ;USER REF? U 3774, 2646,3333,0006,4174,4007,0520,0000,0000,0000 ; 8690 SKIP DP0 ; .. ; 8691 =0 [BR]-#, ;EXEC--LESS THAN 340? ; 8692 #/340, ; .. ; 8693 SKIP DP18, 4T, ; .. U 2646, 2650,1553,0500,4374,4007,0532,4000,0000,0340 ; 8694 J/KIF10 ;FOLLOW EXEC PATH ; 8695 KIUPT: [ARX]_[ARX]+[UBR], ;POINTER TO PAGE MAP ENTRY ; 8696 LOAD VMA, ;PUT ADDRESS IN VMA ; 8697 VMA PHYSICAL, ;ABSOLUTE ADDRESS ; 8698 START READ, ;FETCH UPT WORD U 2647, 3775,0111,1104,4174,4007,0700,0200,0024,1016 ; 8699 J/KIF30 ;JOIN COMMON CODE ; 8700 =0 ; 8701 KIF10: [BR]-#, ;EXEC ADDRESS .GE. 340 ; 8702 #/400, ; SEE IF .GT. 400 ; 8703 SKIP DP18, 4T, ; .. U 2650, 2652,1553,0500,4374,4007,0532,4000,0000,0400 ; 8704 J/KIEPT ;LOOK AT KIF20 ; 8705 [ARX]_[ARX]+#, 3T, ;EXEC ADDRESS .LT. 340 ; 8706 #/600, ;IN EBR+600 U 2651, 2652,0551,0404,4374,4007,0701,0000,0000,0600 ; 8707 J/KIEPT ;JOIN COMMON CODE ; 8708 ; 8709 =0 ; 8710 KIEPT: [ARX]_[ARX]+[EBR], ;ADD OFFSET TO ; 8711 LOAD VMA, ; EPT ; 8712 START READ, ;START FETCH ; 8713 VMA PHYSICAL, ;ABSOLUTE ADDRESS U 2652, 3775,0111,1004,4174,4007,0700,0200,0024,1016 ; 8714 J/KIF30 ;GO GET POINTER ; 8715 [ARX]_[ARX]+#, ;PER PROCESS PAGE ; 8716 #/220, 3T, ; IS IN UPT + 400 U 2653, 2647,0551,0404,4374,4007,0701,0000,0000,0220 ; 8717 J/KIUPT ;JOIN COMMON CODE ; 8718 KIF30: MEM READ, ;WAIT FOR DATA U 3775, 3776,3771,0004,4365,5007,0700,0200,0000,0002 ; 8719 [ARX]_MEM ;PLACE IT IN ARX ; 8720 TR [BR], ;SEE IF EVEN OR ODD U 3776, 2654,4553,0500,4374,4007,0331,0000,0000,0001 ; 8721 #/1 ; .. ; 8722 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 241 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8723 ;STILL .IF/KIPAGE ; 8724 =0 ; 8725 KIF40: READ [ARX], ;ODD ; 8726 SKIP DP18, ;SEE IF VALID U 2654, 2656,3333,0004,4174,4007,0530,0000,0000,0000 ; 8727 J/KIF50 ;JOIN COMMON CODE ; 8728 [ARX]_[ARX] SWAP, ;EVEN--FLIP AROUND U 2655, 2654,3770,0404,4344,4007,0700,0000,0000,0000 ; 8729 J/KIF40 ; AND CONTINUE ; 8730 ; 8731 .ENDIF/KIPAGE ; 8732 =0 U 2656, 2672,4553,1300,4374,4007,0321,0000,0001,0000 ; 8733 KIF50: PAGE FAIL TRAP ; 8734 ;AT THIS POINT WE HAVE THE PAGE MAP ENTRY IN RH OF AR ; 8735 [FLG]_[FLG].AND.NOT.#, ;CLEAR W AND C U 2657, 1435,5551,1313,4374,4007,0700,0000,0002,4000 ; 8736 FLG.W/1, FLG.C/1 ; FLAGS U 1435, 2660,4553,0400,4374,4007,0331,0000,0002,0000 ; 8737 TR [ARX], #/020000 ;CACHE ENABLED? ; 8738 =0 [FLG]_[FLG].OR.#, ;SET CACHE BITS U 2660, 2661,3551,1313,4374,0007,0700,0000,0000,4000 ; 8739 FLG.C/1, HOLD RIGHT ; .. U 2661, 2662,4553,0400,4374,4007,0331,0000,0004,0000 ; 8740 TR [ARX], #/040000 ;DO NOT CACHE ; 8741 ;SEE IF CACHE BIT SET ; 8742 =0 [BRX]_[BRX].OR.#, ;COPY BITS TO BRX ; 8743 #/020000, U 2662, 2663,3551,0606,4374,0007,0700,0000,0002,0000 ; 8744 HOLD RIGHT ; 8745 TR [ARX], ; .. U 2663, 2664,4553,0400,4374,4007,0331,0000,0010,0000 ; 8746 #/100000 ; 8747 =0 [FLG]_[FLG].OR.#, ;SAVE W ; 8748 FLG.W/1, ; .. ; 8749 HOLD RIGHT, ; .. U 2664, 1500,3551,1313,4374,0007,0700,0000,0002,0000 ; 8750 J/KIF90 ;ALL DONE ; 8751 TL [BRX], ;W=0, WRITE REF? U 2665, 2666,4553,0600,4374,4007,0321,0000,0001,0000 ; 8752 WRITE CYCLE/1 ; 8753 =0 ; 8754 KIF80: [BRX]_[BRX].OR.#, ;WRITE FAILURE ; 8755 #/100000, HOLD RIGHT, ;INDICATE THAT ACCESS WAS ON U 2666, 2656,3551,0606,4374,0007,0700,0000,0010,0000 ; 8756 J/KIF50 ;GO PAGE FAIL U 2667, 2607,4443,0000,4174,4007,0700,0000,0000,0000 ; 8757 J/PFDONE ;ALL DONE ; 8758 ; 8759 KIF90: [BRX]_[BRX].OR.#, ;PAGE IS WRITABLE ; 8760 #/40000, ;TURN ON IN BRX U 1500, 2607,3551,0606,4374,4007,0700,0000,0004,0000 ; 8761 J/PFDONE ;ALL SET ; 8762 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 242 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8763 ;HERE ON HARD PAGE FAILURES U 1501, 2670,3333,0005,7174,4007,0700,0400,0000,0213 ; 8764 HARD: WORK[SV.BR]_[BR] ;SAVE BR (CLEANUP MAY NEED IT) ; 8765 =0 [BR]_VMA, ;BUILD PAGE FAIL WORD U 2670, 1510,3771,0005,4354,4007,0700,0010,0000,0000 ; 8766 CALL [ABORT] ;CLEAR ERROR ; 8767 [BR]_[BR].AND.#, ;SAVE THE FLAGS ; 8768 #/401237, ; .. U 2671, 1502,4551,0505,4374,0007,0700,0000,0040,1237 ; 8769 HOLD RIGHT ; .. ; 8770 [BRX]_[BRX].OR.[BR], ;COMPLETE PAGE FAIL WORD U 1502, 2656,3111,0506,4174,4007,0700,0000,0000,0000 ; 8771 J/KIF50 ;GO TRAP ; 8772 U 1503, 1140,4443,0000,4174,4007,0370,0000,0000,0000 ; 8773 PFPI1: SKIP IRPT ;TIMER TRAP? ; 8774 =00 ; 8775 [AR]_WORK[TIME1], ;YES--GET LOW WORD ; 8776 SPEC/CLRCLK, ;CLEAR CLOCK FLAG U 1140, 3561,3771,0003,7274,4117,0701,0010,0000,0301 ; 8777 CALL [TOCK] ;DO THE UPDATE U 1141, 2673,4443,0000,4174,4007,0700,0000,0000,0000 ; 8778 J/PFT1 ;EXTERNAL INTERRUPT U 1142, 1507,4223,0000,4364,4277,0700,0200,0000,0010 ; 8779 ABORT MEM CYCLE ;CLEAR 1MS FLAGS ; 8780 = ; 8781 PFPI2: [AR]_WORK[SV.VMA], ;RESTORE VMA U 1507, 3762,3771,0003,7274,4007,0701,0000,0000,0210 ; 8782 J/PF125 ; 8783 ; 8784 U 1510, 0001,4223,0000,4364,4274,1700,0200,0000,0010 ; 8785 ABORT: ABORT MEM CYCLE, RETURN [1] ; 8786 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 243 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8787 ;HERE ON PAGE FAIL TRAP ; 8788 =0 U 2672, 0104,4751,1217,4374,4007,0700,0000,0000,0100 ; 8789 PFT: HALT [IOPF] ;IO PAGE FAILURE ; 8790 PFT1: [AR]_WORK[SV.VMA], U 2673, 2674,3771,0003,7274,4007,0611,0000,0000,0210 ; 8791 SKIP/TRAP CYCLE ;SEE IF TRAP CYCLE ; 8792 =0 TL [AR], FETCH/1, ;IS THIS AN INSTRUCTION FETCH U 2674, 2676,4553,0300,4374,4007,0321,0000,0010,0000 ; 8793 J/PFT1A ;GO LOOK BELOW U 2675, 1511,3771,0003,7274,4007,0701,0000,0000,0425 ; 8794 [AR]_WORK[TRAPPC] ;RESTORE PC U 1511, 2700,3333,0003,4174,4467,0700,0000,0000,0004 ; 8795 READ [AR], LOAD FLAGS, J/CLDISP ; 8796 =0 U 2676, 1100,4443,0000,4174,4007,0700,0000,0000,0000 ; 8797 PFT1A: J/CLEANED ;YES--NO PC TO BACK UP U 2677, 2700,1111,0701,4170,4007,0700,4000,0000,0000 ; 8798 FIXPC: [PC]_[PC]-1, HOLD LEFT ;DATA FAILURE--BACKUP PC ; 8799 =0 U 2700, 1100,3333,0013,4174,4003,5701,0000,0000,0000 ; 8800 CLDISP: CLEANUP DISP ;GO CLEANUP AFTER PAGE FAIL ; 8801 =0000 ; 8802 CLEANUP: ; 8803 CLEANED: ;(0) NORMAL CASE ; 8804 END STATE, SKIP IRPT, ;NO MORE CLEANUP NEEDED U 1100, 2702,4221,0013,4170,4007,0370,0000,0000,0000 ; 8805 J/PFT2 ;HANDLE PAGE FAIL OR INTERRUPT ; 8806 [AR]_WORK[SV.ARX], ;(1) BLT U 1101, 3167,3771,0003,7274,4007,0701,0000,0000,0212 ; 8807 J/BLT-CLEANUP ; 8808 [PC]_[PC]+1, ;(2) MAP U 1102, 1562,0111,0701,4174,4007,0700,0000,0000,0000 ; 8809 J/MAPDON ; 8810 STATE_[EDIT-SRC], ;(3) SRC IN STRING MOVE U 1103, 3463,3771,0013,4370,4007,0700,0000,0000,0011 ; 8811 J/STRPF ; 8812 STATE_[EDIT-DST], ;(4) DST IN STRING MOVE U 1104, 3463,3771,0013,4370,4007,0700,0000,0000,0012 ; 8813 J/STRPF ; 8814 STATE_[SRC], ;(5) SRC+DST IN STRING MOVE U 1105, 2310,3771,0013,4370,4007,0700,0000,0000,0003 ; 8815 J/BACKD ; 8816 STATE_[EDIT-DST], ;(6) FILL IN MOVSRJ U 1106, 3472,3771,0013,4370,4007,0700,0000,0000,0012 ; 8817 J/STRPF4 ; 8818 STATE_[EDIT-SRC], ;(7) DEC TO BIN U 1107, 3467,3771,0013,4370,4007,0700,0000,0000,0011 ; 8819 J/PFDBIN ; 8820 STATE_[EDIT-SRC], ;(10) SRC+DST IN COMP U 1110, 3461,3771,0013,4370,4007,0700,0000,0000,0011 ; 8821 J/CMSDST U 1111, 2302,4221,0013,4170,4007,0700,0000,0000,0000 ; 8822 END STATE, J/BACKS ;(11) EDIT SRC FAIL U 1112, 2310,4221,0013,4170,4007,0700,0000,0000,0000 ; 8823 END STATE, J/BACKD ;(12) EDIT DST FAIL ; 8824 STATE_[EDIT-SRC], ;(13) SRC+DST IN EDIT U 1113, 2310,3771,0013,4370,4007,0700,0000,0000,0011 ; 8825 J/BACKD ; 8826 = ; 8827 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 244 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8828 =0 ; 8829 PFT2: [AR]_[UBR]+#, ;PREPARE TO STORE PFW ; 8830 #/500, 3T, U 2702, 1512,0551,1103,4374,4007,0701,0000,0000,0500 ; 8831 J/PFT10 U 2703, 0770,3551,1313,4374,0007,0700,0000,0001,0000 ; 8832 PFT3: TAKE INTERRUPT ;PROCESS INTERRUPT ; 8833 PFT10: VMA_[AR], ;WHERE TO STORE PFW U 1512, 2704,3443,0300,4174,4007,0700,0200,0021,1016 ; 8834 VMA PHYSICAL WRITE ; 8835 =0 MEM WRITE, ;STORE PFW ; 8836 MEM_[BRX], U 2704, 1564,3333,0006,4175,5007,0701,0210,0000,0002 ; 8837 CALL [NEXTAR] ;ADVANCE POINTER TO ; 8838 ;PREPARE TO STORE PC ; 8839 .IF/KLPAGE ; 8840 .IF/KIPAGE U 2705, 2706,4553,1000,4374,4007,0321,0000,0040,0000 ; 8841 TL [EBR], #/400000 ;KL PAGING? ; 8842 =0 ; 8843 .ENDIF/KIPAGE U 2706, 2712,4521,1205,4074,4007,0700,0000,0000,0000 ; 8844 [BR]_FLAGS,J/EAPF ;YES--DO EXTENDED THING ; 8845 .ENDIF/KLPAGE ; 8846 ; 8847 .IF/KIPAGE U 2707, 1513,3741,0105,4074,4007,0700,0000,0000,0000 ; 8848 [BR]_PC WITH FLAGS ;GET OLD PC ; 8849 MEM WRITE, ;STORE OLD PC ; 8850 MEM_[BR], U 1513, 1563,3333,0005,4175,5007,0701,0200,0000,0002 ; 8851 J/EAPF1 ; 8852 .ENDIF/KIPAGE ; 8853 ; 8854 MAPDON: END STATE, ;CLEAR MAP BIT U 1562, 2710,4221,0013,4170,4007,0370,0000,0000,0000 ; 8855 SKIP IRPT ;ANY INTERRUPT? ; 8856 =0 [AR]_[BRX], ;RETURN PAGE FAIL WORD U 2710, 1500,3441,0603,4174,4003,7700,0200,0003,0001 ; 8857 EXIT U 2711, 2703,1111,0701,4174,4007,0700,4000,0000,0000 ; 8858 [PC]_[PC]-1, J/PFT3 ;INTERRUPTED OUT OF MAP ; 8859 ; RETRY INSTRUCTION ; 8860 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 245 ; PAGEF.MIC[7,3] 12:15 10-APR-1985 PAGE FAIL REFIL LOGIC ; 8861 ; 8862 .IF/KLPAGE ; 8863 =0 ; 8864 EAPF: MEM WRITE, MEM_[BR], ;STORE FLAGS U 2712, 1564,3333,0005,4175,5007,0701,0210,0000,0002 ; 8865 CALL [NEXTAR] ;STORE PC WORD U 2713, 1563,3333,0001,4175,5007,0701,0200,0000,0002 ; 8866 MEM WRITE, MEM_[PC] ; .. ; 8867 .ENDIF/KLPAGE ; 8868 ; 8869 EAPF1: [AR]_[AR]+1, ; 8870 VMA PHYSICAL READ, U 1563, 2743,0111,0703,4174,4007,0700,0200,0024,1016 ; 8871 J/GOEXEC ; 8872 U 1564, 0001,0111,0703,4170,4004,1700,0200,0023,1016 ; 8873 NEXTAR: NEXT [AR] PHYSICAL WRITE, RETURN [1] ; 8874 ; Number of microwords used: ; D words= 512 ; U words= 2024, Highest= 2047 END ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 246 ; Cross Reference Listing (U) A 633 # AR 637 # 2391 2429 2459 2460 2523 2571 2579 2718 2720 2723 2726 2729 2732 2816 2826 2841 2858 2868 2878 2888 2919 2929 2939 2974 2986 2993 2997 3007 3008 3010 3012 3013 3021 3044 3045 3271 3276 3278 3290 3293 3296 3301 3302 3372 3389 3391 3456 3459 3527 3528 3534 3554 3581 3596 3632 3643 3655 3709 3732 3737 3772 3816 3820 3829 3831 3992 3997 4027 4062 4076 4092 4103 4106 4109 4123 4150 4151 4156 4173 4189 4209 4321 4330 4335 4345 4351 4370 4374 4392 4420 4424 4426 4427 4446 4478 4481 4484 4498 4523 4540 4541 4546 4551 4559 4561 4563 4634 4644 4646 4651 4652 4697 4702 4712 4716 4754 4758 4762 4766 4942 4955 5040 5043 5055 5058 5064 5070 5105 5180 5183 5285 5291 5295 5296 5326 5332 5351 5357 5358 5359 5360 5369 5374 5394 5395 5407 5409 5418 5419 5439 5444 5445 5451 5486 5490 5492 5495 5498 5502 5504 5506 5508 5509 5510 5511 5517 5519 5520 5529 5534 5550 5576 5584 5589 5591 5635 5648 5667 5676 5680 5695 5709 5711 5713 5719 5746 5753 5756 5768 5771 5779 5781 5785 5790 5792 5808 5813 5816 5838 5841 5842 5846 5964 5968 5972 5979 5990 5999 6014 6034 6038 6051 6054 6080 6164 6171 6188 6210 6224 6251 6262 6263 6264 6277 6311 6341 6352 6390 6405 6433 6438 6467 6468 6469 6470 6472 6473 6476 6481 6530 6551 6558 6559 6585 6623 6635 6636 6643 6663 6666 6669 6673 6674 6676 6680 6682 6736 6737 6742 6743 6750 6753 6757 6826 6848 6854 6873 6891 6895 6898 6899 6900 6901 6923 6948 6949 6953 6959 6960 6964 7034 7040 7063 7065 7067 7069 7072 7074 7076 7118 7125 7136 7140 7147 7151 7175 7181 7183 7188 7196 7223 7286 7367 7369 7371 7373 7375 7377 7379 7381 7383 7405 7411 7473 7483 7489 7492 7493 7510 7518 7568 7579 7592 7594 7620 7625 7652 7655 7683 7701 7702 7761 7858 7866 7897 8227 8237 8341 8350 8353 8355 8357 8361 8364 8375 8381 8386 8429 8432 8437 8444 8452 8459 8481 8499 8503 8541 8544 8559 8560 8581 8597 8599 8601 8631 8637 8642 8648 8662 8679 8792 8833 ARX 638 # 2491 2773 2774 3712 3714 3727 3756 4089 4101 4110 4111 4128 4131 4133 4155 4175 4191 4211 4214 4234 4363 4391 4443 4469 4470 4549 4641 4642 4650 4719 4909 4916 4917 4945 4948 4969 5099 5121 5293 5331 5363 5549 5570 5573 5633 5650 5672 5692 5712 5717 5763 5802 5809 6052 6093 6100 6134 6168 6218 6227 6237 6246 6269 6270 6278 6310 6314 6391 6428 6436 6440 6442 6759 6762 6808 6876 6950 7064 7068 7070 7073 7075 7104 7106 7317 7330 7334 7524 7707 7709 7767 7994 8328 8336 8384 8398 8421 8535 8567 8569 8633 8705 8715 8728 8737 8740 8745 BR 639 # 2190 2387 2422 2424 2428 2909 3040 3073 3074 3077 3078 3079 3080 3095 3098 3101 3104 3108 3111 3113 3145 3146 3149 3150 3431 3434 3437 3440 3443 3446 3449 3452 3777 3782 3810 3837 3846 3847 3994 3999 4097 4229 4394 4396 4404 4408 4471 4474 4548 4552 4553 4554 4557 4562 4593 4735 4737 4796 4797 4798 4799 4800 4807 4816 4820 4829 4890 4891 4892 4893 4894 4915 4958 4964 5067 5107 5109 5119 5124 5292 5299 5300 5304 5305 5361 5364 5398 5449 5532 5556 5558 5568 5582 5661 5679 5682 5918 5930 5931 5933 5934 5961 5970 6015 6020 6045 6048 6139 6204 6207 6208 6221 6229 6235 6358 6368 6379 6388 6392 6410 6463 6478 6516 6527 6594 6850 6851 6892 6893 6933 6941 6952 6956 7033 7036 7061 7095 7097 7100 7162 7173 7187 7189 7214 7215 7285 7296 7303 7372 7374 7376 7382 7384 7420 7433 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 247 ; Cross Reference Listing 7530 7553 7554 7555 7596 7598 7626 7630 7632 7636 7638 7662 7668 7759 8235 8299 8302 8315 8441 8565 8691 8701 8720 8767 8770 BRX 640 # 4125 4153 4159 4230 4253 4273 4277 4281 4285 4291 4295 4299 4303 4380 4433 4473 4585 4588 4599 5046 5098 5127 5135 5142 5166 5324 5325 5327 5366 5371 5561 5578 5644 5658 5659 5701 5922 6021 6091 6102 6103 6127 6176 6184 6265 6294 6307 6316 6321 6329 6331 6340 6346 6351 6363 6402 6404 6422 6431 6458 6460 6462 6493 6496 6512 6524 6526 6606 6608 6611 6677 6684 6778 6782 6786 6790 6794 6798 6814 7087 7231 7232 7233 7332 7482 7537 7538 7601 7684 8231 8284 8285 8288 8294 8296 8470 8473 8476 8498 8506 8548 8552 8554 8556 8571 8575 8742 8751 8754 8759 8856 EBR 642 # 6980 7197 7198 7199 7212 7485 7528 8306 8339 8710 8841 FLG 645 # 3623 5513 5614 5615 5622 5749 5752 5755 5758 5818 5825 5826 6602 8281 8360 8380 8448 8458 8472 8478 8510 8531 8551 8570 8572 8603 8640 8645 8669 8678 8733 8735 8738 8747 8832 HR 636 # 2291 2297 2303 2309 2318 2322 2331 2336 2437 2785 2790 3531 3540 3543 3545 3546 3547 3566 3570 3580 3585 3588 3608 3629 3642 3924 3926 3928 3930 3932 3934 3936 3938 3944 3964 4042 5920 6913 6990 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7252 7275 7370 7686 7700 7829 7833 7838 7840 7842 7844 7846 7848 MAG 634 # 2426 4135 4138 4157 4160 4161 4174 4180 4182 4216 4218 4220 4398 4416 4438 4442 4445 4486 4488 4489 4616 4621 4626 4632 4633 5552 5643 5698 5724 5759 5794 5798 5800 MASK 644 # 2152 2153 2154 2157 2160 2193 2204 2240 2244 2247 2250 2259 2262 2265 2268 2519 2742 2763 2970 3018 3582 3630 3644 3665 3948 3965 3988 3991 4036 4096 4232 4266 4400 4411 4439 4564 4776 4896 4907 5454 5514 5587 5637 5727 5796 5885 5887 5889 5891 5893 5895 5897 5899 5901 6136 6138 6160 6275 6597 7284 7327 7328 7329 7463 7464 7465 7466 7467 7468 7469 7475 7494 7504 7522 7536 7614 7617 7653 7664 7670 7687 7743 7896 8260 8262 8276 8789 8844 ONE 641 # 2182 2186 2231 2233 2278 2365 2416 2419 2949 3340 3406 3422 3489 3503 3529 3538 3541 3616 3634 3637 3984 4031 4047 4326 4741 5038 5106 5147 5149 5154 5171 5172 5441 5453 5528 5677 5835 5956 5997 6030 6036 6057 6075 6085 6104 6105 6140 6141 6183 6247 6252 6315 6327 6334 6354 6361 6366 6375 6385 6389 6393 6394 6430 6444 6455 6507 6531 6625 6647 6700 6823 6824 6830 6852 6894 6936 7291 7314 7344 7396 7680 7757 7882 7968 7975 7978 7981 7984 7987 8798 8808 8858 8869 8873 PC 635 # 2230 2234 2252 2345 2407 2432 3328 3455 3460 3691 3808 3814 3834 4020 4221 4223 4698 4707 6969 7387 7506 7658 7893 8848 PI 646 # 3594 3595 3609 7015 7016 7364 7378 7380 7385 7395 7397 7456 7457 7458 7459 7460 7461 7462 7471 T0 648 # 4201 4205 4441 4452 4459 4462 4464 4465 5569 5577 5603 5605 5606 5607 5610 5618 5621 5623 5663 5729 5737 5738 6359 6426 7398 7534 T1 649 # 4418 4558 5593 5678 5681 5700 5710 UBR 643 # 3950 3990 6972 7132 7166 7221 7222 7227 7228 8331 8695 8829 XWD1 647 # 3511 3681 7520 (D) A 1317 # ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 248 ; Cross Reference Listing DBLAC 1321 # 2777 DFP 1327 # 5539 5540 5628 5689 DREAD 1320 # 2768 2769 4084 4085 4168 4386 DSHIFT 1323 # 2959 2960 FP 1325 # 5265 5266 5267 5268 5270 5271 5273 5274 5275 5276 5278 5279 5310 5311 5312 5314 5316 5317 5339 5340 5341 5343 5345 5346 5424 5425 FPI 1324 # 5269 5277 5315 5344 IOT 1328 # 7001 7002 7238 7560 7561 7562 7563 7571 7572 7573 7574 7585 7586 7587 7588 7853 7854 8223 RD-PF 1326 # 2549 2554 2559 2564 2602 2607 2612 2617 2622 2627 2632 2637 2644 2649 2654 2659 2664 2669 2674 2679 2809 2819 2829 2834 2851 2861 2871 2881 2901 2912 2922 2932 4055 4069 4117 4142 4309 4314 READ 1318 # 2552 2557 2562 2567 2586 2604 2605 2609 2610 2615 2620 2625 2630 2635 2640 2646 2647 2651 2652 2657 2662 2667 2672 2677 2682 2811 2812 2821 2822 2831 2832 2836 2837 2844 2853 2854 2863 2864 2873 2874 2883 2884 2903 2904 2914 2915 2924 2925 2934 2935 3188 3189 3190 3191 3192 3193 3204 3205 3206 3207 3208 3209 3210 3211 3222 3223 3224 3225 3226 3227 3228 3229 3239 3240 3241 3242 3243 3244 3245 3246 3361 3362 3363 3364 3365 3366 3367 3368 3378 3379 3380 3381 3382 3383 3384 3385 3395 3396 3397 3398 3399 3400 3401 3402 3411 3412 3413 3414 3415 3416 3417 3418 3649 4057 4058 4071 4072 4119 4120 4144 4145 4311 4312 4316 4317 4687 4688 4689 4690 4691 5389 SHIFT 1322 # 2954 2955 2956 WRITE 1319 # 2551 2556 2561 2566 2614 2619 2624 2629 2634 2639 2656 2661 2666 2671 2676 2681 2778 2846 2847 (U) ACALU 1215 # AC+N 1217 # 2175 2176 2183 2373 2385 2491 2774 2783 3024 3045 3089 3119 4089 4101 4180 4182 4184 4192 4194 4201 4203 4215 4216 4217 4218 4219 4220 4332 4416 4438 4442 4445 4459 4460 4462 4465 4484 4486 4488 4489 4615 4616 4619 4620 4621 4624 4625 4626 4632 4633 5552 5643 5696 5698 5704 5763 5771 5809 5816 5960 5968 5978 5981 6011 6014 6027 6034 6041 6051 6089 6099 6119 6134 6151 6166 6168 6194 6197 6199 6206 6207 6208 6210 6216 6218 6221 6227 6229 6257 6259 6260 6264 6271 6272 6273 6277 6278 6285 6287 6292 6298 6314 6325 6337 6346 6352 6363 6366 6368 6372 6385 6391 6392 6515 6546 6551 6556 6593 6595 6699 6700 6812 6819 6826 6845 6847 6854 6874 6895 6931 6933 6939 6941 6945 6948 6953 B 1216 # (D) ACDISP 1348 # 3518 7001 7002 7238 (U) ACN 1218 # 2373 2385 2491 2774 2783 3024 3045 3089 3119 4089 4101 4180 4182 4184 4192 4194 4201 4203 4215 4216 4217 4218 4219 4220 4332 4416 4438 4442 4445 4459 4460 4462 4465 4484 4486 4488 4489 4615 4616 4619 4620 4621 4624 4625 4626 4632 4633 5552 5643 5696 5698 5704 5763 5771 5809 5816 6298 6314 6325 6372 6391 BIN0 1225 # 2175 6194 6216 6221 6229 6260 6271 6272 6273 6277 6285 BIN1 1226 # 2176 2183 6166 6168 6197 6199 6206 6207 6208 6210 6218 6227 6257 6259 6264 6278 6287 DLEN 1222 # 5960 5968 5981 6011 6014 6041 6051 6089 6099 6134 6292 6337 6346 6352 6363 6366 6368 6385 6392 6699 6700 6812 6826 6845 6945 6948 6953 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 249 ; Cross Reference Listing DSTP 1223 # 5978 6151 6546 6551 6595 6819 6874 6895 6939 6941 MARK 1224 # 6515 6593 SRCLEN 1220 # SRCP 1221 # 6027 6034 6119 6556 6847 6854 6931 6933 (U) AD 530 # 2157 2160 2193 2204 2240 2244 2247 2250 2259 2262 2265 2268 2322 2519 2740 2742 2761 2763 3582 3665 3948 3988 4036 4400 4411 5885 5887 5889 5891 5893 5895 5897 5899 5901 5931 6160 6275 6597 7284 7327 7328 7329 7463 7464 7465 7466 7467 7468 7469 7475 7504 7522 7536 7614 7617 7653 7664 7670 7687 7743 7896 8260 8262 8276 8789 A 559 # 2152 2154 2230 2234 2252 2297 2309 2336 2345 2387 2428 2429 2432 2491 2523 2774 2790 2974 2986 2993 2997 3007 3008 3010 3012 3013 3021 3040 3045 3073 3074 3077 3078 3079 3080 3095 3098 3101 3104 3108 3111 3145 3146 3149 3150 3302 3328 3391 3431 3443 3455 3456 3459 3460 3527 3528 3534 3554 3570 3581 3596 3632 3643 3655 3709 3712 3714 3732 3737 3810 3816 3829 3834 3847 4123 4125 4128 4150 4151 4153 4155 4173 4175 4189 4191 4209 4211 4223 4229 4230 4232 4253 4266 4321 4330 4345 4351 4380 4392 4394 4396 4408 4420 4424 4439 4443 4446 4459 4465 4469 4478 4498 4546 4551 4552 4553 4558 4559 4561 4563 4634 4698 4707 4712 4719 4735 4758 4766 4820 4896 4909 4945 4964 4969 5043 5046 5064 5099 5119 5127 5135 5183 5291 5292 5293 5304 5326 5327 5331 5332 5351 5359 5361 5366 5369 5374 5407 5409 5439 5441 5444 5445 5451 5486 5490 5492 5498 5506 5508 5509 5510 5528 5529 5534 5561 5568 5569 5573 5576 5577 5584 5589 5591 5603 5605 5606 5607 5610 5618 5621 5623 5633 5635 5637 5644 5648 5650 5661 5667 5672 5676 5677 5680 5692 5695 5717 5727 5729 5737 5738 5746 5753 5756 5768 5771 5785 5790 5792 5813 5816 5838 5846 5934 5979 5999 6014 6034 6045 6051 6080 6091 6127 6134 6168 6207 6227 6229 6264 6277 6278 6314 6340 6346 6351 6352 6359 6363 6368 6390 6391 6392 6426 6460 6469 6472 6476 6478 6516 6526 6551 6558 6594 6611 6636 6666 6673 6684 6736 6753 6759 6850 6854 6873 6892 6895 6899 6901 6933 6941 6948 6949 6953 6960 7015 7016 7118 7162 7181 7183 7196 7212 7214 7222 7223 7228 7231 7233 7332 7364 7387 7405 7411 7482 7489 7510 7518 7537 7555 7579 7592 7594 7601 7626 7630 7636 7658 7662 7668 7702 7759 7761 7767 7858 7866 7893 7994 8237 8296 8299 8315 8341 8361 8364 8384 8398 8535 8541 8559 8565 8581 8662 8833 8856 A+B 532 # 2182 2186 2231 2233 2278 2365 2416 2419 2785 3113 3340 3406 3616 3634 3637 3777 3782 3950 3984 3990 4031 4047 4201 4205 4234 4290 4294 4374 4470 4471 4474 4484 4557 4562 4588 4592 4598 4741 5147 5149 5154 5171 5172 5305 5449 5453 5532 5582 5663 5956 6020 6052 6057 6075 6104 6105 6210 6224 6235 6237 6247 6315 6327 6334 6354 6375 6389 6444 6455 6463 6507 6531 6625 6647 6674 6700 6852 6876 6894 6936 6956 6972 6980 7285 7291 7314 7344 7485 7520 7530 7538 7757 7882 7968 7975 7978 7981 7984 7987 8328 8336 8421 8695 8710 8808 8869 8873 A+Q 531 # 4441 4452 4473 5106 5570 5578 5679 5682 5835 A-.25 543 # A-B-.25 548 # 4370 4426 4427 5105 5124 5142 5166 5363 5371 5719 5968 6103 6139 6358 A-D-.25 544 # 6188 6428 6433 6481 8691 8701 A-Q-.25 547 # A.AND.B 564 # 4159 4174 4391 4462 4915 5514 5763 5796 5798 5809 5990 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 250 ; Cross Reference Listing 6136 7034 7040 7397 7553 8633 A.AND.Q 563 # 4157 4398 4442 4486 4488 4564 4616 4621 4626 4632 4633 4829 4907 4916 5759 5794 A.EQV.B 591 # A.EQV.Q 590 # 4135 4138 4160 4161 4216 4218 4220 4489 A.OR.B 556 # 2909 4097 4917 5070 5922 6021 6054 6093 6251 6682 7064 7068 7075 7106 7151 7173 7175 7376 7382 7524 7620 7655 8556 8770 A.OR.Q 555 # 5593 A.XOR.B 583 # 5800 7330 A.XOR.Q 582 # B 558 # 2162 2170 2172 2173 2176 2178 2185 2187 2378 2398 2497 2529 2535 2540 2543 2574 2593 2738 2745 2752 2759 2789 3070 3086 3142 3287 3331 3334 3337 3343 3346 3349 3408 3562 3610 3621 3661 3697 3703 3742 3748 3819 3954 3958 3968 3972 3974 3980 4002 4008 4019 4023 4039 4046 4127 4272 4276 4298 4302 4333 4339 4353 4358 4360 4365 4432 4434 4451 4467 4476 4537 4544 4565 4695 4704 4708 4723 4726 4742 4823 4889 4897 4905 4954 4967 4987 5019 5026 5290 5294 5377 5379 5411 5415 5448 5488 5507 5575 5674 5683 5732 5750 5788 5924 5927 5940 5942 5943 5973 5985 6019 6035 6061 6062 6063 6078 6120 6123 6125 6129 6142 6153 6161 6169 6300 6302 6345 6364 6377 6381 6383 6432 6439 6465 6479 6484 6506 6510 6562 6582 6596 6648 6656 6730 6751 6773 6805 6855 6857 6879 6919 6970 7077 7079 7080 7082 7085 7089 7190 7191 7257 7261 7265 7269 7273 7288 7299 7304 7320 7323 7339 7343 7345 7353 7354 7406 7418 7424 7431 7656 7698 7721 7727 7729 7763 7765 7874 7881 7946 7955 7961 7965 7966 7967 7969 7970 7971 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 8233 8243 8244 8246 8247 8254 8264 8266 8268 8270 8274 8275 8310 8409 8416 8418 8439 8577 8635 8689 8725 8764 8795 8800 8836 8850 8864 8866 B-.25 542 # B-A-.25 540 # 3422 3529 3538 3541 4280 4284 4554 4585 6015 6036 6140 6141 6252 6341 6393 6430 6823 6952 7296 7420 7433 7680 8798 8858 D 562 # 2151 2155 2180 2181 2183 2221 2271 2341 2355 2359 2364 2368 2372 2373 2385 2386 2391 2396 2407 2413 2571 2590 2691 2693 2718 2720 2723 2724 2726 2729 2730 2732 2747 2749 2754 2756 2783 2967 2984 2990 3002 3005 3043 3089 3092 3271 3276 3389 3434 3437 3440 3446 3449 3452 3475 3551 3558 3575 3590 3595 3615 3619 3680 3691 3719 3725 3752 3761 3772 3774 3808 3814 3831 3832 3845 3846 3850 3964 4007 4020 4109 4124 4133 4152 4156 4194 4199 4214 4217 4219 4221 4322 4331 4332 4414 4543 4697 4702 4716 4718 4722 4737 4770 4796 4797 4798 4799 4800 4816 4890 4891 4892 4893 4894 4942 4951 4958 4972 4974 4978 4982 4984 4988 5017 5022 5045 5058 5060 5098 5107 5111 5118 5162 5180 5181 5288 5321 5353 5417 5495 5511 5553 5563 5655 5706 5841 5917 5936 5945 5960 5963 5977 5978 5981 6003 6006 6011 6027 6028 6038 6048 6065 6066 6067 6068 6076 6082 6090 6099 6101 6119 6121 6128 6132 6145 6147 6151 6163 6166 6175 6194 6197 6199 6206 6216 6257 6259 6260 6265 6292 6297 6298 6299 6311 6320 6325 6337 6343 6353 6356 6357 6372 6384 6386 6387 6405 6408 6457 6462 6467 6468 6508 6515 6530 6546 6556 6565 6569 6584 6593 6595 6599 6620 6627 6629 6660 6676 6697 6699 6737 6762 6812 6817 6819 6826 6828 6845 6847 6848 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 251 ; Cross Reference Listing 6851 6874 6891 6893 6903 6918 6931 6935 6939 6945 6964 6969 6988 7008 7009 7046 7048 7060 7071 7094 7095 7103 7121 7186 7243 7245 7247 7249 7251 7256 7260 7264 7268 7272 7281 7286 7290 7295 7301 7302 7313 7333 7337 7352 7358 7372 7385 7395 7414 7416 7427 7429 7453 7479 7490 7506 7508 7527 7532 7550 7582 7623 7690 7693 7695 7703 7717 7748 7751 7753 7862 7869 7901 7948 7953 7957 7960 7972 7990 7992 7993 7995 8230 8234 8236 8245 8251 8256 8323 8326 8345 8410 8413 8427 8437 8491 8493 8538 8578 8579 8580 8586 8667 8719 8728 8765 8775 8781 8790 8794 8806 8810 8812 8814 8816 8818 8820 8824 8848 D+A 536 # 2291 2303 2318 2331 3489 3511 3566 3681 3727 3756 3820 3837 4062 4089 4092 4754 4762 5040 5109 5121 5930 5933 5997 6030 6085 6183 6208 6218 6221 6361 6379 6422 6431 6438 6440 6559 6635 6742 6750 6824 6830 6898 6900 7334 7483 7528 7701 7707 7709 8331 8339 8353 8355 8432 8597 8705 8715 8829 D+Q 537 # 4990 4998 5029 5048 D-.25 554 # D-A-.25 552 # 3372 3503 4076 4101 4103 4106 5055 6366 6385 D-Q-.25 553 # D.AND.A 571 # 2424 2426 2437 2459 2773 2816 2939 2970 3018 3278 3301 3531 3540 3543 3545 3546 3547 3580 3585 3588 3594 3608 3609 3629 3630 3642 3644 3924 3926 3928 3930 3932 3934 3936 3938 3944 3965 3991 3992 3997 4042 4110 4180 4182 4363 4416 4438 4445 4641 4776 4948 4955 5067 5295 5299 5324 5357 5394 5398 5418 5513 5552 5643 5678 5681 5698 5749 5752 5755 5758 5818 5918 5920 5961 5964 6100 6102 6138 6164 6171 6184 6204 6246 6262 6269 6294 6310 6329 6388 6402 6404 6436 6442 6458 6470 6473 6493 6496 6512 6527 6643 6677 6680 6743 6757 6913 6923 6990 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7063 7065 7067 7069 7072 7074 7076 7097 7100 7125 7132 7136 7140 7147 7166 7187 7188 7197 7215 7221 7227 7232 7252 7275 7317 7367 7369 7370 7371 7373 7375 7377 7379 7381 7383 7494 7534 7568 7625 7632 7638 7652 7684 7686 7700 7829 7833 7838 7840 7842 7844 7846 7848 8231 8235 8284 8288 8306 8350 8357 8360 8375 8380 8429 8444 8448 8452 8458 8472 8476 8478 8498 8503 8531 8544 8551 8554 8570 8572 8599 8601 8603 8637 8640 8642 8645 8648 8669 8679 8720 8733 8737 8740 8745 8751 8767 8792 8841 8844 D.AND.Q 572 # 3115 4516 5329 5638 D.EQV.A 595 # 2888 D.EQV.Q 596 # D.OR.A 560 # 2153 2422 2460 2868 3296 3994 3999 4111 4464 4549 5296 5300 5325 5358 5419 5558 5614 5615 5622 5659 5711 5825 6176 6263 6307 6316 6321 6331 6602 6606 6608 6669 6782 6786 6790 6798 6814 6950 6959 7189 7198 7303 7378 7456 7457 7458 7459 7460 7461 7462 7596 7897 8227 8281 8285 8386 8470 8473 8481 8499 8506 8548 8552 8569 8571 8575 8631 8738 8742 8747 8754 8759 8832 D.OR.Q 561 # 3117 4401 D.XOR.A 587 # 2190 2858 3293 4418 7492 7493 8294 D.XOR.Q 588 # Q 557 # 3119 4129 4137 4184 4192 4192 4203 4215 4357 4412 4429 4435 4440 4444 4450 4458 4977 5139 5165 5376 5381 5452 5494 5518 5612 5619 5639 5651 5662 5721 5723 5767 5812 6109 6148 6550 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 252 ; Cross Reference Listing Q-.25 541 # Q-A-.25 539 # 4433 5038 Q-D-.25 545 # 4981 ZERO 568 # 2163 2163 2165 2168 2175 2177 2179 2196 2218 2402 2806 2983 3024 3044 3273 3611 3975 4228 4254 4324 4460 4538 4805 4818 4824 4825 4828 4900 4901 4904 4960 5103 5145 5169 5302 5373 5384 5396 5400 5402 5403 5416 5429 5521 5694 5722 5761 5777 5805 5986 5988 6022 6041 6089 6094 6106 6117 6146 6267 6285 6287 6305 6339 6395 6399 6403 6406 6461 6585 6623 6663 6733 6808 7033 7036 7104 7158 7170 7216 7293 7368 7413 7438 7439 7471 7474 7481 7495 7710 7755 7876 7879 7949 8280 8302 8381 8441 8459 8547 8567 8779 8785 8804 8822 8823 8854 -A-.25 551 # 2579 2949 4326 4404 4481 4523 4541 4548 4642 4646 4650 4652 5285 5360 5364 5395 5504 5520 5549 5550 5701 5712 5713 5781 5802 5808 6270 6394 7396 -B-.25 550 # 5702 -D-.25 546 # 4455 4615 4620 4625 4630 6001 6273 6944 6958 -Q-.25 549 # 4403 4454 4480 4521 4522 4539 5382 5487 5489 5491 5493 5776 .NOT.A 594 # 2841 2878 2919 2929 3290 4096 4335 4540 4644 4651 5454 5502 5517 5519 5700 5710 5779 5970 5972 6524 7398 7473 7683 8678 .NOT.A.AND.B 575 # 4131 5587 7070 7073 7374 7384 7554 .NOT.A.AND.Q 574 # 5724 .NOT.B 593 # 5807 6179 .NOT.D 597 # 2898 2908 4619 4624 4629 6018 6046 6050 6186 6190 6272 6962 .NOT.D.AND.A 579 # 2826 3623 4027 5556 5658 5709 5826 6410 6778 6794 7061 7087 7199 7380 7598 8510 8560 8735 .NOT.D.AND.Q 580 # .NOT.Q 592 # 4914 5775 5989 0+A 535 # 5842 0+B 534 # 0+D 538 # 0+Q 533 # 5588 5735 (U) AD PARITY OK 707 # 2183 2359 2372 2373 2590 2691 2693 2724 2730 2783 2967 2970 2984 3018 3475 3719 3752 3774 3832 3845 4152 4194 4331 4722 5118 5288 5321 5353 5417 5563 5960 5963 5978 5981 6011 6027 6099 6101 6119 6151 6163 6166 6194 6197 6199 6206 6216 6257 6259 6260 6292 6297 6298 6299 6320 6325 6337 6372 6457 6515 6556 6593 6595 6699 6812 6819 6845 6847 6874 6931 6939 6945 7582 7869 8257 (U) ADFLGS 1111 # 2580 3406 3422 3489 3503 4063 4077 4094 4104 4107 4234 4645 4647 (U) AREAD 1145 # 2323 (U) B 653 # AR 657 # 2160 2162 2177 2240 2244 2247 2259 2262 2265 2322 2355 2359 2364 2372 2378 2391 2396 2398 2407 2416 2416 2419 2419 2428 2429 2459 2460 2497 2523 2529 2535 2540 2543 2571 2574 2579 2691 2693 2718 2720 2723 2724 2726 2729 2730 2732 2738 2740 2742 2745 2747 2749 2752 2754 2756 2759 2761 2763 2806 2816 2826 2841 2858 2868 2878 2888 2898 2909 2909 2919 2929 2939 2949 2967 2970 2974 2984 2986 2990 2993 2997 3002 3005 3007 3008 3010 3012 3013 3043 3044 3045 3070 3086 3142 3271 3276 3290 3293 3296 3301 3302 3331 3334 3337 3343 3346 3349 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 253 ; Cross Reference Listing 3372 3389 3391 3406 3406 3408 3422 3616 3616 3634 3637 3637 3644 3772 3777 3782 3832 3964 3965 3972 3991 4007 4008 4020 4023 4027 4036 4039 4047 4062 4076 4092 4097 4097 4103 4106 4109 4129 4135 4137 4138 4155 4156 4173 4221 4324 4326 4331 4333 4358 4380 4414 4420 4424 4467 4471 4471 4474 4474 4478 4481 4484 4498 4523 4537 4540 4541 4546 4551 4554 4557 4559 4561 4562 4562 4563 4593 4629 4630 4634 4644 4646 4651 4652 4695 4704 4708 4712 4723 4726 4735 4737 4741 4741 4742 4770 4808 4823 4825 4828 4829 4889 4890 4891 4892 4893 4894 4897 4905 4914 4915 4915 4917 4917 4972 4974 4984 4987 4988 5017 5026 5040 5050 5055 5058 5060 5064 5142 5166 5180 5181 5183 5285 5292 5294 5295 5296 5305 5305 5331 5332 5353 5357 5358 5369 5374 5376 5377 5379 5381 5382 5407 5409 5411 5415 5417 5418 5419 5439 5444 5445 5448 5449 5449 5451 5453 5453 5486 5488 5490 5492 5495 5498 5502 5504 5506 5507 5508 5509 5510 5511 5514 5514 5517 5519 5520 5529 5532 5532 5534 5550 5577 5582 5582 5584 5589 5591 5635 5672 5676 5680 5683 5706 5709 5711 5713 5737 5738 5746 5750 5753 5756 5768 5771 5779 5781 5785 5788 5790 5792 5807 5813 5816 5838 5841 5842 5846 5885 5887 5889 5891 5893 5895 5897 5899 5901 5927 5956 5956 5963 5970 5972 5973 5988 5989 5997 6001 6014 6015 6015 6018 6020 6020 6021 6021 6027 6034 6035 6045 6046 6048 6050 6051 6052 6052 6057 6057 6065 6104 6104 6105 6106 6119 6125 6132 6136 6136 6139 6139 6142 6146 6151 6153 6160 6161 6163 6171 6179 6183 6186 6190 6259 6262 6263 6264 6272 6273 6277 6297 6299 6302 6311 6320 6337 6351 6352 6353 6354 6354 6359 6377 6379 6381 6386 6390 6403 6405 6406 6408 6430 6433 6438 6444 6444 6455 6467 6468 6469 6470 6472 6473 6506 6526 6530 6531 6531 6551 6556 6558 6559 6562 6584 6585 6597 6599 6620 6623 6625 6625 6627 6635 6643 6647 6647 6648 6660 6663 6666 6669 6673 6676 6680 6697 6699 6700 6730 6736 6737 6742 6750 6751 6753 6759 6808 6812 6817 6819 6823 6824 6826 6828 6830 6845 6847 6850 6851 6852 6852 6854 6855 6857 6874 6879 6892 6893 6894 6894 6895 6903 6918 6919 6923 6931 6935 6936 6939 6944 6948 6952 6952 6953 6956 6956 6958 6959 6960 6962 6972 6972 6980 6980 7121 7125 7136 7181 7183 7256 7257 7260 7261 7264 7265 7268 7269 7272 7273 7281 7285 7285 7286 7288 7290 7291 7291 7293 7295 7296 7296 7299 7301 7313 7323 7337 7352 7353 7354 7413 7414 7418 7420 7420 7424 7427 7431 7433 7433 7471 7475 7479 7482 7483 7485 7485 7490 7508 7518 7522 7524 7524 7579 7601 7626 7632 7638 7687 7690 7695 7701 7703 7707 7709 7710 7748 7757 7757 7862 7869 7896 7897 7970 7971 7972 7973 7990 7991 7992 8227 8237 8243 8331 8339 8345 8353 8355 8361 8364 8384 8386 8410 8413 8427 8432 8439 8444 8481 8491 8493 8499 8535 8538 8541 8544 8556 8556 8586 8597 8601 8635 8667 8678 8775 8781 8790 8794 8795 8806 8829 8856 8869 8869 8873 ARX 658 # 2183 2187 2368 2373 2402 2426 2491 2773 2774 2783 2789 3681 3712 3714 3719 3727 3752 3756 3831 3834 3948 3950 3950 3958 3968 3984 4031 4089 4101 4110 4111 4127 4128 4133 4157 4160 4161 4174 4174 4182 4192 4205 4205 4211 4214 4228 4234 4254 4273 4277 4281 4285 4291 4295 4299 4303 4345 4357 4363 4429 4435 4444 4538 4543 4549 4565 4585 4585 4588 4588 4599 4641 4642 4650 4718 4722 4909 4916 4942 4945 4948 4951 4954 5098 5147 5147 5172 5291 5359 5360 5371 5549 5651 5663 5663 5698 5721 5796 5796 5798 5798 5800 5800 5802 5835 5979 5981 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 254 ; Cross Reference Listing 5999 6030 6036 6062 6067 6075 6075 6078 6080 6085 6099 6103 6123 6129 6134 6140 6166 6168 6197 6218 6224 6224 6227 6237 6237 6246 6257 6269 6270 6275 6278 6298 6300 6310 6314 6315 6315 6325 6343 6372 6383 6387 6389 6389 6391 6428 6436 6440 6442 6582 6762 6805 6873 6876 6949 6950 6969 6970 7063 7065 7103 7104 7317 7320 7328 7332 7334 7345 7481 7520 7520 7530 7530 7653 7655 7664 7670 7693 7751 7755 7767 7874 7879 7882 7946 7948 7953 7957 7960 7961 7965 7968 7975 7978 7981 7984 7987 7993 7995 8247 8315 8323 8326 8381 8398 8416 8418 8459 8567 8578 8631 8695 8695 8705 8710 8710 8715 8719 8725 8728 BR 659 # 2185 2386 2387 2413 2422 2424 2590 2593 2908 3018 3040 3073 3074 3077 3078 3079 3080 3092 3095 3098 3101 3104 3108 3111 3113 3145 3146 3149 3150 3273 3278 3287 3431 3434 3437 3440 3443 3446 3449 3452 3475 3489 3503 3511 3615 3621 3630 3680 3691 3697 3703 3725 3742 3748 3774 3808 3810 3814 3819 3829 3845 3846 3850 3988 3990 3990 3994 3999 4002 4096 4175 4321 4330 4339 4353 4360 4365 4370 4374 4392 4394 4396 4404 4408 4426 4427 4544 4548 4552 4553 4697 4702 4716 4776 4796 4797 4798 4799 4800 4816 4818 4820 4955 4958 4960 4964 4967 4982 4992 5019 5031 5067 5070 5106 5107 5109 5119 5121 5288 5290 5293 5299 5300 5304 5351 5395 5441 5454 5528 5553 5556 5558 5569 5639 5677 5695 5702 5719 5917 5922 5922 5924 5930 5931 5933 5936 5940 5942 5943 5945 5960 5968 5978 5985 6011 6019 6038 6061 6066 6138 6194 6199 6206 6207 6208 6210 6216 6221 6229 6235 6235 6247 6247 6260 6339 6340 6341 6341 6361 6364 6366 6368 6375 6375 6385 6392 6394 6410 6462 6463 6465 6476 6478 6479 6515 6524 6593 6595 6596 6848 6891 6933 6941 6945 6964 7008 7009 7015 7016 7033 7034 7036 7040 7046 7048 7060 7061 7064 7064 7068 7068 7070 7070 7079 7080 7082 7094 7095 7097 7100 7106 7106 7147 7158 7162 7186 7187 7189 7190 7191 7212 7214 7215 7216 7221 7227 7233 7243 7245 7247 7249 7251 7284 7302 7303 7304 7327 7330 7333 7343 7358 7364 7371 7372 7406 7416 7429 7494 7506 7528 7532 7538 7538 7550 7555 7568 7582 7594 7596 7598 7614 7617 7620 7623 7630 7636 7656 7662 7668 7759 7763 7974 8234 8254 8264 8266 8268 8270 8296 8299 8302 8328 8336 8421 8437 8441 8559 8560 8579 8764 8765 8767 8844 8848 8850 8864 BRX 660 # 2181 2182 2182 4123 4125 4152 4153 4180 4199 4230 4253 4351 4412 4470 5043 5046 5103 5105 5118 5124 5149 5154 5171 5171 5321 5324 5325 5327 5361 5363 5364 5366 5552 5643 5644 5655 5658 5659 5692 5701 5920 5964 6054 6063 6068 6091 6093 6101 6120 6127 6141 6164 6169 6176 6251 6251 6265 6292 6294 6305 6307 6316 6321 6327 6327 6331 6334 6334 6345 6346 6363 6393 6457 6484 6510 6512 6606 6608 6611 6656 6674 6674 6677 6682 6682 6684 6773 6778 6782 6786 6790 6794 6798 6814 7071 7073 7073 7075 7075 7077 7085 7087 7089 7222 7228 7231 7232 7329 7463 7464 7465 7466 7467 7468 7469 7534 7537 7592 7683 7743 7976 8230 8231 8233 8244 8245 8246 8256 8260 8262 8274 8275 8276 8285 8288 8294 8310 8409 8470 8473 8506 8548 8552 8554 8569 8571 8575 8577 8580 8689 8742 8754 8759 8770 8770 8836 EBR 662 # 2165 3954 7196 7198 7199 7979 FLG 665 # 2168 2170 2172 2173 3623 5111 5145 5169 5521 5614 5615 5622 5761 5777 5805 5825 5826 5977 6003 6006 6022 6028 6076 6082 6090 6094 6117 6121 6128 6147 6175 6267 6357 6384 6395 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 255 ; Cross Reference Listing 6399 6461 6508 6565 6569 6602 6629 6733 7983 8236 8281 8510 8547 8633 8633 8735 8738 8747 8800 8804 8810 8812 8814 8816 8818 8820 8822 8823 8824 8832 8854 HR 656 # 2180 2186 2186 2271 2303 2318 2331 2341 2365 2437 3531 3540 3543 3545 3546 3547 3551 3562 3566 3575 3580 3585 3588 3590 3608 3629 3642 3655 3661 3665 3924 3926 3928 3930 3932 3934 3936 3938 3944 3975 3980 4019 4042 4046 4607 6913 6988 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7252 7275 7314 7339 7344 7370 7698 7829 7833 7838 7840 7842 7844 7846 7848 7901 7969 MAG 654 # 2154 4232 4266 4391 4439 4462 4896 4901 4904 5637 5727 5763 5809 7966 MASK 664 # 2151 2152 2153 3610 4131 5990 7955 7982 ONE 661 # 2157 2176 2178 2785 6358 7977 PC 655 # 2218 2231 2233 2278 2291 2297 3021 3340 3456 3459 3527 3528 3529 3538 3541 3554 3581 3596 3619 3709 3761 3820 3837 3974 6252 6507 6507 7510 7680 7765 7967 8798 8808 8808 8858 8866 PI 666 # 2196 7368 7374 7374 7376 7376 7378 7380 7382 7382 7384 7384 7456 7457 7458 7459 7460 7461 7462 7553 7554 7554 7985 T0 668 # 3595 4151 4159 4191 4194 4201 4440 4446 4450 4452 4454 4459 4464 4465 5563 5568 5575 5576 5603 5605 5606 5607 5610 5618 5621 5623 5650 5723 5729 6356 6422 6431 6432 7385 7395 7396 7397 7397 7527 7717 7721 7727 7729 7988 T1 669 # 2193 2204 2221 2250 2268 2519 3582 4400 4411 4418 4432 4434 4451 4476 4558 5587 5587 5612 5619 5662 5674 5694 5700 5710 5732 6426 6439 7504 7536 7881 7989 8789 UBR 663 # 2163 7132 7151 7151 7166 7170 7173 7173 7175 7175 7980 XWD1 667 # 2155 7986 (D) B 1330 # 3179 3180 3181 3182 3183 3184 3188 3189 3190 3191 3192 3193 3195 3196 3197 3198 3199 3200 3201 3202 3204 3205 3206 3207 3208 3209 3210 3211 3213 3214 3215 3216 3217 3218 3219 3220 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3239 3240 3241 3242 3243 3244 3245 3246 3352 3353 3354 3355 3356 3357 3358 3359 3361 3362 3363 3364 3365 3366 3367 3368 3378 3379 3380 3381 3382 3383 3384 3385 3395 3396 3397 3398 3399 3400 3401 3402 3411 3412 3413 3414 3415 3416 3417 3418 3464 3465 3466 3467 3468 3469 3470 3471 3478 3479 3480 3481 3482 3483 3484 3485 3492 3493 3494 3495 3496 3497 3498 3499 3506 3507 3671 3672 3673 3768 3857 3858 3859 3860 3861 3862 3863 3864 3914 3915 3916 3917 3918 3919 5854 5855 5856 5857 5858 5859 5860 5862 5863 5864 5865 5867 5868 5869 5870 5875 5876 5877 5878 5879 7560 7561 7562 7563 7571 7572 7573 7574 7585 7586 7587 7588 7772 7773 7774 7776 7777 7779 7780 7782 7783 7784 7785 7786 7787 7788 7789 7791 7792 7793 7794 7795 7796 7797 7798 7800 7801 7802 7803 7804 7805 7806 7807 7809 7810 7811 7812 7813 7814 7815 7816 7818 7819 7820 7821 7822 7823 7824 7825 AC 1334 # 2549 2550 2554 2555 2559 2560 2564 2565 2586 2602 2603 2607 2608 2612 2613 2617 2618 2622 2623 2627 2628 2632 2633 2637 2638 2644 2645 2649 2650 2654 2655 2659 2660 2664 2665 2669 2670 2674 2675 2679 2680 2769 2799 2800 2809 2810 2819 2820 2829 2830 2834 2835 2851 2852 2861 2862 2871 2872 2881 2882 2891 2892 2901 2902 2912 2913 2922 2923 2932 2933 2942 2943 4055 4056 4069 4070 4117 4118 4687 8223 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 256 ; Cross Reference Listing BOTH 1336 # 2802 2812 2822 2832 2837 2854 2864 2874 2884 2894 2904 2915 2925 2935 2945 4058 4072 4120 DBLAC 1332 # 2768 4084 4085 4142 4143 4168 4309 4310 4314 4315 4386 5628 5689 DBLB 1333 # 4145 4312 4317 MEM 1335 # 2551 2556 2561 2566 2604 2609 2614 2619 2624 2629 2634 2639 2646 2651 2656 2661 2666 2671 2676 2681 2801 2811 2821 2831 2836 2846 2847 2853 2863 2873 2883 2893 2903 2914 2924 2934 2944 4057 4071 4119 4144 4311 4316 7238 SELF 1331 # 2552 2557 2562 2567 2605 2610 2615 2620 2625 2630 2635 2640 2647 2652 2657 2662 2667 2672 2677 2682 (U) BWRITE 1154 # 2571 2577 2691 2693 2726 2732 2740 2742 2761 2763 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 4063 4077 4129 4135 4158 4160 5449 5453 5499 5521 8557 8857 (U) BYTE 813 # BYTE1 814 # 4697 4702 4716 4737 4890 6038 6048 6530 6676 6848 6851 6891 6893 6964 BYTE2 815 # 4891 BYTE3 816 # 4892 BYTE4 817 # 4893 BYTE5 818 # 3043 4796 4797 4798 4799 4800 4894 6660 (U) CALL 965 # 2158 2184 2196 2401 2773 2783 3553 3592 3594 3595 3609 3633 3636 3833 3836 3951 3967 3972 3976 3982 3985 4019 4021 4126 4154 4181 4190 4200 4210 4233 4343 4364 4419 4425 4439 4443 4449 4495 4519 4697 4702 4706 4711 4716 4725 4728 4976 4986 5020 5047 5102 5118 5120 5328 5370 5373 5378 5380 5488 5490 5492 5507 5508 5509 5568 5576 5604 5644 5649 5661 5668 5675 5694 5718 5722 5726 5751 5754 5757 5789 5791 5793 5799 5919 5959 5962 5966 5998 6004 6029 6053 6064 6079 6083 6090 6100 6102 6108 6122 6131 6152 6167 6170 6183 6198 6209 6217 6220 6223 6226 6234 6239 6266 6301 6310 6326 6338 6365 6376 6384 6401 6427 6456 6459 6464 6539 6547 6557 6560 6570 6583 6598 6605 6626 6630 6698 6732 6756 6856 6875 6880 6932 6940 6951 7222 7292 7316 7319 7338 7385 7415 7428 7477 7507 7509 7525 7529 7567 7578 7593 7612 7621 7650 7657 7682 7875 7877 7883 7899 7947 7949 7966 7969 7971 7973 7976 7979 7982 7985 7988 7990 8349 8356 8367 8374 8385 8390 8412 8415 8428 8451 8461 8492 8519 8598 8766 8777 8837 8865 (U) CHKL 718 # 2271 2341 2355 2364 2368 2385 2396 2407 2413 2426 2497 2529 2535 2540 2543 2593 2789 3089 3408 3551 3575 3590 3615 3619 3680 3697 3703 3725 3742 3748 3761 3819 3850 3972 3974 3980 4007 4019 4023 4046 4124 4217 4219 4322 4332 4416 4438 4445 4742 4770 4776 4897 5162 5917 5936 6356 6546 6596 6599 6627 6903 6918 6988 7121 7256 7260 7264 7268 7272 7313 7343 7345 7352 7406 7490 7532 7656 7703 7748 7751 7753 7763 7765 7862 7881 7901 7966 7967 7969 7970 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 8345 8427 8667 8719 8836 8850 8864 8866 (U) CHKR 725 # 2271 2341 2355 2364 2368 2385 2396 2407 2413 2426 2497 2529 2535 2540 2543 2593 2789 3089 3408 3551 3575 3590 3615 3619 3680 3697 3703 3725 3742 3748 3761 3819 3850 3972 3974 3980 4007 4019 4023 4046 4124 4217 4219 4322 4332 4416 4438 4445 4742 4770 4776 4897 5162 5917 5936 6356 6546 6596 6599 6627 6903 6918 6988 7121 7256 7260 7264 7268 7272 7313 7343 7345 7352 7406 7490 7532 7656 7703 7748 7751 7753 7763 7765 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 257 ; Cross Reference Listing 7862 7881 7901 7966 7967 7969 7970 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 8345 8427 8667 8719 8836 8850 8864 8866 (U) CLKL 714 # 2231 2233 2278 2291 2292 2298 2303 2318 2319 2331 2342 2365 2693 2724 2732 2754 2756 3340 3456 3459 3527 3528 3529 3538 3541 3554 3566 3596 3620 3634 3762 3821 3835 3839 3984 3996 4001 4031 4047 4098 4741 4771 4980 5039 5062 5111 5123 5145 5149 5154 5169 5172 5182 5330 5593 5930 5933 5936 5977 6003 6006 6022 6028 6057 6076 6082 6090 6094 6105 6117 6121 6128 6147 6175 6252 6267 6305 6340 6357 6384 6395 6399 6455 6461 6508 6565 6569 6604 6629 6670 6675 6733 6852 6894 6903 7062 7088 7102 7171 7187 7189 7233 7314 7319 7344 7378 7380 7382 7384 7396 7456 7457 7458 7459 7460 7461 7462 7484 7554 7680 7701 7701 7882 7898 7968 7975 7978 7981 7984 7987 8236 8501 8547 8555 8798 8804 8810 8812 8814 8816 8818 8820 8822 8823 8824 8854 8873 (U) CLKR 721 # 2422 2424 2437 2459 2460 2691 2726 2730 2747 2749 2773 3116 3118 3389 3531 3540 3543 3545 3546 3547 3580 3585 3588 3608 3629 3642 3773 3924 3926 3928 3930 3932 3934 3936 3938 3946 3966 3976 4028 4044 4109 4110 4111 4133 4156 4363 4402 4464 4518 4641 4818 4953 4961 5024 5069 5104 5108 5295 5296 5299 5300 5324 5325 5357 5358 5418 5419 5495 5511 5614 5615 5622 5638 5760 5795 5825 5826 5841 5923 5945 6172 6177 6246 6262 6263 6269 6308 6310 6317 6323 6332 6351 6403 6406 6411 6436 6442 6513 6607 6609 6679 6683 6737 6779 6783 6787 6791 6795 6799 6815 6913 6925 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7056 7096 7099 7127 7134 7138 7153 7159 7168 7176 7198 7199 7217 7221 7227 7252 7275 7286 7370 7372 7374 7376 7508 7710 7755 7829 7833 7838 7840 7842 7844 7846 7848 8229 8232 8283 8287 8290 8295 8446 8471 8508 8512 8546 8550 8553 8564 8634 8739 8744 8749 8755 8769 8832 (U) CLRFPD 1083 # 3692 3809 3815 4212 4712 4729 6395 (D) COND FUNC 1353 # 2551 2552 2556 2557 2561 2562 2566 2567 2604 2605 2609 2610 2614 2615 2619 2620 2624 2625 2629 2630 2634 2635 2639 2640 2646 2647 2651 2652 2656 2657 2661 2662 2666 2667 2671 2672 2676 2677 2681 2682 2801 2802 2811 2812 2821 2822 2831 2832 2836 2837 2846 2847 2853 2854 2863 2864 2873 2874 2883 2884 2893 2894 2903 2904 2914 2915 2924 2925 2934 2935 2944 2945 4057 4058 4071 4072 4119 4120 4144 4145 4311 4312 4316 4317 5266 5267 5270 5271 5274 5275 5278 5279 5311 5312 5316 5317 5340 5341 5345 5346 7238 (U) CRY38 948 # 2579 2949 3372 3422 3503 3529 3538 3541 4076 4093 4101 4106 4280 4284 4326 4370 4403 4426 4427 4433 4454 4480 4521 4522 4523 4539 4541 4548 4554 4585 4615 4620 4625 4630 4642 4646 4650 4652 4981 5038 5055 5105 5124 5142 5166 5285 5360 5363 5364 5371 5382 5395 5487 5489 5491 5493 5504 5520 5549 5588 5701 5712 5719 5735 5776 5781 5802 5808 5842 5968 6001 6015 6036 6103 6139 6140 6141 6188 6252 6270 6273 6341 6358 6366 6385 6393 6394 6428 6430 6433 6481 6823 6944 6952 6958 7296 7396 7420 7433 7680 8691 8701 8798 8858 (U) DBM 693 # APR FLAGS 696 # 7008 7009 7071 7103 7302 BYTES 697 # DP 699 # 3043 4697 4702 4716 4737 4796 4797 4798 4799 4800 4890 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 258 ; Cross Reference Listing 4891 4892 4893 4894 6038 6048 6530 6660 6676 6848 6851 6891 6893 6964 DP SWAP 700 # 2391 2571 2718 2720 2723 2726 2729 2732 3271 3276 3595 3772 3831 3846 3964 4816 4942 4958 5058 5098 5107 5180 6405 6462 6467 6468 6762 7095 7372 7385 7395 8437 8728 EXP 698 # 5495 5511 5841 7327 7328 7329 MEM 702 # 2163 2270 2341 2354 2363 2367 2395 2406 2412 2425 3550 3574 3589 3611 3615 3619 3679 3724 3761 3849 4006 4769 4775 5161 5917 5936 6356 6599 6627 6903 6917 6973 6981 6988 7120 7256 7260 7264 7268 7272 7312 7352 7474 7478 7490 7526 7532 7622 7703 7748 7751 7753 7861 7876 7900 7949 8280 8344 8426 8666 8718 8779 8785 PF DISP 695 # 8250 SCAD DIAG 694 # VMA 701 # 7717 7960 8230 8245 8765 # 703 # 2151 2153 2155 2157 2160 2180 2181 2190 2193 2204 2221 2240 2244 2247 2250 2259 2262 2265 2268 2422 2424 2437 2459 2460 2519 2747 2749 2754 2756 2773 3044 3115 3117 3531 3540 3543 3545 3546 3547 3580 3582 3585 3588 3594 3608 3609 3623 3629 3642 3727 3756 3820 3837 3924 3926 3928 3930 3932 3934 3936 3938 3944 3948 3988 3992 3994 3997 3999 4027 4036 4042 4110 4111 4363 4400 4401 4411 4418 4464 4516 4543 4549 4641 4806 4948 4951 4955 4974 4978 4984 4988 5017 5022 5055 5060 5067 5111 5121 5295 5296 5299 5300 5324 5325 5329 5357 5358 5394 5398 5418 5419 5513 5556 5558 5614 5615 5622 5638 5658 5659 5678 5681 5709 5711 5749 5752 5755 5758 5818 5825 5826 5885 5887 5889 5891 5893 5895 5897 5899 5901 5918 5920 5945 5961 5964 5977 6003 6006 6028 6076 6082 6090 6100 6102 6121 6128 6147 6160 6164 6171 6175 6176 6184 6188 6204 6246 6262 6263 6269 6275 6294 6307 6310 6316 6321 6329 6331 6357 6384 6388 6402 6404 6410 6422 6431 6436 6442 6458 6470 6473 6481 6493 6496 6508 6512 6527 6565 6569 6585 6597 6602 6606 6608 6623 6629 6643 6663 6669 6677 6680 6757 6778 6782 6786 6790 6794 6798 6808 6814 6913 6923 6990 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7033 7036 7046 7048 7061 7063 7065 7067 7069 7072 7074 7076 7087 7097 7100 7104 7125 7132 7136 7140 7147 7166 7187 7188 7189 7197 7198 7199 7215 7221 7227 7232 7252 7275 7284 7303 7317 7367 7369 7370 7371 7373 7375 7377 7378 7379 7380 7381 7383 7414 7416 7427 7429 7456 7457 7458 7459 7460 7461 7462 7463 7464 7465 7466 7467 7468 7469 7471 7475 7483 7492 7493 7504 7508 7522 7528 7534 7536 7550 7614 7617 7625 7632 7638 7652 7653 7664 7670 7684 7686 7700 7743 7829 7833 7838 7840 7842 7844 7846 7848 7896 7897 8227 8231 8235 8236 8260 8262 8276 8281 8284 8285 8288 8294 8302 8306 8331 8339 8350 8357 8360 8375 8380 8381 8429 8441 8444 8448 8452 8458 8459 8470 8472 8473 8476 8478 8498 8499 8503 8506 8510 8531 8544 8548 8551 8552 8554 8560 8567 8569 8570 8571 8572 8575 8599 8603 8631 8637 8640 8642 8645 8648 8669 8679 8691 8701 8705 8715 8720 8733 8735 8737 8738 8740 8742 8745 8747 8751 8754 8759 8767 8789 8792 8810 8812 8814 8816 8818 8820 8824 8829 8832 8841 (U) DBUS 684 # DBM 690 # 2151 2153 2155 2157 2160 2163 2180 2181 2190 2193 2204 2221 2240 2244 2247 2250 2259 2262 2265 2268 2270 2271 2341 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 259 ; Cross Reference Listing 2341 2354 2355 2363 2364 2367 2368 2391 2395 2396 2406 2407 2412 2413 2422 2424 2425 2426 2437 2459 2460 2519 2571 2718 2720 2723 2726 2729 2732 2747 2749 2754 2756 2773 3043 3044 3115 3117 3271 3276 3531 3540 3543 3545 3546 3547 3550 3551 3574 3575 3580 3582 3585 3588 3589 3590 3594 3595 3608 3609 3611 3615 3615 3619 3619 3623 3629 3642 3679 3680 3724 3725 3727 3756 3761 3761 3772 3820 3831 3837 3846 3849 3850 3924 3926 3928 3930 3932 3934 3936 3938 3944 3948 3964 3988 3992 3994 3997 3999 4006 4007 4027 4036 4042 4110 4111 4363 4400 4401 4411 4418 4464 4516 4543 4549 4641 4697 4702 4716 4737 4769 4770 4775 4776 4796 4797 4798 4799 4800 4806 4816 4890 4891 4892 4893 4894 4942 4948 4951 4955 4958 4974 4978 4984 4988 5017 5022 5055 5058 5060 5067 5098 5107 5111 5121 5161 5162 5180 5295 5296 5299 5300 5324 5325 5329 5357 5358 5394 5398 5418 5419 5495 5511 5513 5556 5558 5614 5615 5622 5638 5658 5659 5678 5681 5709 5711 5749 5752 5755 5758 5818 5825 5826 5841 5885 5887 5889 5891 5893 5895 5897 5899 5901 5917 5917 5918 5920 5936 5936 5945 5961 5964 5977 6003 6006 6028 6038 6048 6076 6082 6090 6100 6102 6121 6128 6147 6160 6164 6171 6175 6176 6184 6188 6204 6246 6262 6263 6269 6275 6294 6307 6310 6316 6321 6329 6331 6356 6356 6357 6384 6388 6402 6404 6405 6410 6422 6431 6436 6442 6458 6462 6467 6468 6470 6473 6481 6493 6496 6508 6512 6527 6530 6565 6569 6585 6597 6599 6599 6602 6606 6608 6623 6627 6627 6629 6643 6660 6663 6669 6676 6677 6680 6757 6762 6778 6782 6786 6790 6794 6798 6808 6814 6848 6851 6891 6893 6903 6903 6913 6917 6918 6923 6964 6973 6981 6988 6988 6990 6996 7005 7006 7007 7008 7009 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7033 7036 7046 7048 7061 7063 7065 7067 7069 7071 7072 7074 7076 7087 7095 7097 7100 7103 7104 7120 7121 7125 7132 7136 7140 7147 7166 7187 7188 7189 7197 7198 7199 7215 7221 7227 7232 7252 7256 7256 7260 7260 7264 7264 7268 7268 7272 7272 7275 7284 7302 7303 7312 7313 7317 7327 7328 7329 7352 7352 7367 7369 7370 7371 7372 7373 7375 7377 7378 7379 7380 7381 7383 7385 7395 7414 7416 7427 7429 7456 7457 7458 7459 7460 7461 7462 7463 7464 7465 7466 7467 7468 7469 7471 7474 7475 7478 7479 7483 7490 7490 7492 7493 7504 7508 7522 7526 7527 7528 7532 7532 7534 7536 7550 7614 7617 7622 7623 7625 7632 7638 7652 7653 7664 7670 7684 7686 7700 7703 7703 7717 7743 7748 7748 7751 7751 7753 7753 7829 7833 7838 7840 7842 7844 7846 7848 7861 7862 7876 7896 7897 7900 7901 7949 7960 8227 8230 8231 8235 8236 8245 8250 8256 8260 8262 8276 8280 8281 8284 8285 8288 8294 8302 8306 8331 8339 8344 8345 8350 8357 8360 8375 8380 8381 8426 8427 8429 8437 8441 8444 8448 8452 8458 8459 8470 8472 8473 8476 8478 8498 8499 8503 8506 8510 8531 8544 8548 8551 8552 8554 8560 8567 8569 8570 8571 8572 8575 8599 8603 8631 8637 8640 8642 8645 8648 8666 8667 8669 8679 8691 8701 8705 8715 8718 8719 8720 8728 8733 8735 8737 8738 8740 8742 8745 8747 8751 8754 8759 8765 8767 8779 8785 8789 8792 8810 8812 8814 8816 8818 8820 8824 8829 8832 8841 DP 688 # 2175 2176 2491 2497 2523 2529 2535 2540 2543 2593 2774 2789 3024 3045 3080 3113 3119 3302 3389 3391 3408 3431 3434 3434 3437 3437 3440 3440 3443 3446 3446 3449 3449 3452 3452 3656 3697 3703 3712 3714 3742 3748 3777 3782 3810 3819 3972 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 260 ; Cross Reference Listing 3974 3980 4019 4023 4046 4109 4133 4156 4184 4192 4201 4203 4214 4214 4215 4216 4218 4220 4442 4458 4459 4460 4462 4465 4484 4486 4489 4616 4621 4626 4632 4633 4634 4712 4742 4897 5070 5119 5139 5165 5183 5445 5451 5763 5771 5807 5808 5809 5816 5968 6014 6034 6041 6051 6054 6089 6091 6093 6127 6134 6168 6210 6227 6229 6264 6265 6265 6277 6278 6285 6287 6311 6311 6314 6346 6352 6363 6368 6390 6391 6392 6550 6551 6596 6611 6684 6700 6737 6826 6826 6854 6895 6933 6941 6948 6953 6960 7286 7343 7345 7406 7579 7656 7698 7763 7765 7767 7881 7966 7967 7969 7970 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 8237 8800 8836 8850 8864 8866 PC FLAGS 685 # 3630 3644 3691 3808 3814 3965 3991 4020 4221 6969 7494 7506 8844 8848 PI NEW 686 # 7453 RAM 689 # 2183 2291 2303 2318 2331 2359 2372 2373 2385 2386 2590 2691 2693 2724 2730 2783 2816 2826 2858 2868 2888 2898 2908 2939 2967 2970 2984 2990 3002 3005 3018 3089 3092 3278 3293 3296 3301 3372 3475 3489 3503 3511 3558 3566 3681 3719 3752 3774 3832 3845 4062 4076 4089 4092 4101 4103 4106 4124 4152 4180 4182 4194 4199 4217 4219 4322 4331 4332 4414 4416 4438 4445 4455 4615 4619 4620 4624 4625 4629 4630 4718 4722 4754 4762 4972 4981 4982 4994 4998 5033 5040 5045 5053 5109 5118 5181 5288 5321 5353 5417 5552 5553 5563 5643 5655 5698 5706 5930 5933 5960 5963 5978 5981 5997 6001 6011 6018 6027 6030 6046 6050 6065 6066 6067 6068 6085 6099 6101 6119 6132 6138 6145 6151 6163 6166 6183 6186 6190 6194 6197 6199 6206 6208 6216 6218 6221 6257 6259 6260 6272 6273 6292 6297 6298 6299 6320 6325 6337 6343 6353 6361 6366 6372 6379 6385 6386 6387 6408 6428 6433 6438 6440 6457 6515 6546 6556 6559 6584 6593 6595 6620 6635 6697 6699 6742 6743 6750 6812 6817 6819 6824 6828 6830 6845 6847 6874 6898 6900 6931 6935 6939 6944 6945 6950 6958 6959 6962 7060 7094 7186 7243 7245 7247 7249 7251 7281 7290 7295 7301 7333 7334 7337 7358 7568 7582 7596 7598 7690 7693 7695 7701 7707 7709 7869 7948 7953 7957 7972 7990 7992 7993 7995 8234 8323 8326 8353 8355 8386 8410 8413 8432 8481 8491 8493 8538 8578 8579 8580 8586 8597 8601 8775 8781 8790 8794 8806 (U) DEST 619 # A 620 # 2391 2407 2491 2523 2571 2718 2720 2723 2726 2729 2732 2774 3045 3080 3271 3276 3302 3389 3391 3431 3434 3437 3440 3443 3446 3449 3452 3595 3712 3714 3772 3810 3831 3846 3964 4109 4133 4156 4214 4459 4465 4634 4697 4702 4712 4716 4737 4796 4797 4798 4799 4800 4816 4890 4891 4892 4893 4894 4942 4958 5058 5098 5107 5119 5180 5183 5445 5451 5495 5511 5771 5816 5841 6014 6034 6038 6048 6051 6091 6127 6134 6168 6227 6229 6264 6265 6277 6278 6311 6314 6346 6352 6363 6368 6390 6391 6392 6405 6462 6467 6468 6530 6551 6611 6676 6684 6737 6762 6826 6848 6851 6854 6891 6893 6895 6933 6941 6948 6953 6960 6964 7095 7286 7372 7385 7395 7579 7767 8237 8437 8728 AD 622 # 2151 2153 2155 2157 2160 2163 2165 2168 2177 2180 2181 2182 2183 2186 2193 2196 2204 2218 2221 2231 2233 2240 2244 2247 2250 2259 2262 2265 2268 2271 2278 2291 2297 2303 2318 2322 2331 2341 2355 2359 2364 2365 2368 2372 2373 2396 2402 2413 2416 2419 2422 2424 2437 2459 2460 2519 2579 2590 2691 2693 2724 2730 2740 2742 2747 2749 2754 2756 2761 2763 2773 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 261 ; Cross Reference Listing 2783 2806 2816 2826 2841 2858 2868 2878 2888 2898 2908 2909 2919 2929 2939 2949 2967 2970 2984 3018 3021 3044 3273 3278 3290 3293 3296 3301 3340 3372 3406 3422 3456 3459 3475 3489 3503 3511 3527 3528 3531 3540 3543 3545 3546 3547 3551 3554 3566 3575 3580 3581 3582 3585 3588 3590 3596 3608 3615 3616 3619 3623 3629 3630 3634 3637 3642 3644 3655 3680 3681 3691 3709 3719 3725 3727 3752 3756 3761 3774 3808 3814 3820 3829 3832 3834 3837 3845 3850 3924 3926 3928 3930 3932 3934 3936 3938 3944 3948 3950 3965 3975 3984 3988 3990 3991 3994 3999 4007 4020 4027 4031 4036 4042 4047 4062 4076 4089 4092 4096 4097 4101 4103 4106 4110 4111 4123 4129 4135 4137 4138 4151 4152 4157 4160 4161 4175 4191 4205 4221 4228 4321 4324 4326 4330 4331 4345 4351 4357 4363 4380 4400 4411 4412 4418 4429 4435 4444 4452 4464 4471 4474 4523 4538 4540 4541 4543 4548 4549 4562 4629 4630 4641 4642 4644 4646 4650 4651 4652 4722 4735 4741 4770 4776 4818 4829 4914 4915 4916 4917 4951 4960 4972 4974 4982 4984 4988 4991 5017 5030 5040 5043 5049 5060 5067 5103 5106 5109 5111 5118 5121 5145 5147 5149 5154 5169 5171 5172 5181 5285 5288 5291 5292 5293 5295 5296 5299 5300 5305 5321 5324 5325 5331 5351 5353 5357 5358 5359 5360 5395 5417 5418 5419 5449 5453 5454 5502 5504 5514 5517 5519 5520 5521 5532 5549 5550 5563 5568 5569 5576 5577 5587 5612 5614 5615 5619 5622 5639 5650 5662 5663 5692 5694 5695 5700 5701 5702 5710 5721 5723 5737 5738 5761 5777 5779 5781 5796 5798 5800 5802 5805 5825 5826 5842 5885 5887 5889 5891 5893 5895 5897 5899 5901 5917 5920 5922 5930 5931 5933 5936 5945 5956 5960 5963 5964 5970 5972 5977 5978 5979 5981 5989 5997 5999 6001 6003 6006 6011 6015 6018 6020 6021 6022 6027 6028 6030 6036 6045 6046 6050 6052 6057 6065 6066 6067 6068 6075 6076 6080 6082 6085 6090 6094 6099 6101 6104 6105 6106 6117 6119 6121 6128 6132 6136 6138 6139 6140 6141 6146 6147 6151 6160 6163 6164 6166 6171 6175 6176 6183 6186 6190 6194 6197 6199 6208 6216 6218 6221 6224 6235 6237 6246 6247 6251 6252 6257 6259 6260 6262 6263 6267 6269 6270 6272 6273 6275 6292 6294 6297 6298 6299 6305 6307 6310 6315 6316 6320 6321 6325 6327 6331 6334 6337 6339 6340 6341 6343 6351 6353 6354 6356 6357 6359 6361 6366 6372 6375 6379 6384 6385 6386 6387 6389 6393 6394 6395 6399 6403 6406 6408 6410 6422 6426 6428 6430 6431 6433 6436 6438 6440 6442 6444 6455 6457 6461 6470 6473 6507 6508 6512 6515 6524 6526 6531 6556 6559 6565 6569 6584 6585 6593 6595 6597 6599 6602 6606 6608 6620 6623 6625 6627 6629 6635 6643 6663 6669 6674 6677 6680 6682 6697 6699 6733 6742 6750 6759 6778 6782 6786 6790 6794 6798 6808 6812 6814 6817 6819 6823 6824 6828 6830 6845 6847 6850 6852 6873 6874 6892 6894 6903 6913 6918 6923 6931 6935 6939 6944 6945 6949 6950 6952 6956 6958 6959 6962 6969 6972 6980 6988 6996 7005 7006 7007 7008 7009 7011 7012 7013 7014 7015 7016 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7033 7036 7046 7048 7060 7061 7063 7064 7065 7068 7070 7071 7073 7075 7087 7094 7097 7100 7103 7104 7106 7121 7125 7132 7136 7147 7151 7158 7166 7170 7173 7175 7186 7187 7189 7196 7198 7199 7215 7216 7221 7227 7232 7233 7243 7245 7247 7249 7251 7252 7256 7260 7264 7268 7272 7275 7281 7284 7285 7290 7291 7293 7295 7296 7301 7302 7303 7313 7314 7317 7327 7328 7329 7332 7333 7334 7337 7344 7352 7358 7364 7368 7370 7371 7374 7376 7378 7380 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 262 ; Cross Reference Listing 7382 7384 7396 7397 7413 7414 7416 7420 7427 7429 7433 7456 7457 7458 7459 7460 7461 7462 7463 7464 7465 7466 7467 7468 7469 7471 7475 7479 7481 7483 7485 7490 7494 7504 7506 7508 7510 7520 7522 7524 7527 7528 7530 7532 7536 7538 7550 7554 7568 7582 7592 7594 7596 7598 7601 7614 7617 7623 7626 7632 7638 7653 7664 7670 7683 7690 7693 7695 7701 7703 7707 7709 7710 7717 7743 7748 7751 7755 7757 7829 7833 7838 7840 7842 7844 7846 7848 7862 7869 7879 7882 7896 7897 7901 7948 7953 7957 7960 7968 7972 7975 7978 7981 7984 7987 7990 7992 7993 7995 8227 8230 8231 8234 8236 8245 8256 8260 8262 8276 8281 8285 8288 8294 8296 8302 8323 8326 8331 8339 8345 8353 8355 8381 8384 8386 8410 8413 8427 8432 8441 8444 8459 8470 8473 8481 8491 8493 8499 8506 8510 8535 8538 8544 8547 8548 8552 8554 8556 8559 8560 8567 8569 8571 8575 8578 8579 8580 8586 8597 8601 8631 8633 8667 8678 8695 8705 8710 8715 8719 8735 8738 8742 8747 8754 8759 8765 8767 8770 8775 8781 8789 8790 8794 8798 8804 8806 8808 8810 8812 8814 8816 8818 8820 8822 8823 8824 8829 8832 8844 8848 8854 8856 8858 8869 8873 AD*.5 629 # 2154 2426 2428 2429 2986 2990 3002 3005 3007 3008 3012 3043 3095 3098 4173 4174 4180 4182 4192 4194 4199 4230 4392 4414 4420 4551 4552 4553 4559 4809 4820 4896 4945 4948 4955 4964 5366 5374 5376 5381 5382 5441 5490 5492 5508 5509 5528 5529 5534 5552 5553 5556 5558 5643 5644 5651 5655 5658 5659 5677 5698 5706 5709 5711 5835 5846 6469 6472 6476 6478 6558 6660 6666 6673 6736 7212 7214 7222 7228 7231 7534 7537 7555 7630 7636 8299 8315 AD*2 627 # 2152 2974 2997 3010 3013 3040 4128 4155 4211 4454 4594 4718 5055 5064 5361 5364 5369 5444 6206 6207 6463 6647 6753 7162 7181 7183 7482 7518 7662 7668 7759 8361 8364 8398 8541 PASS 624 # 2162 2170 2172 2173 2176 2178 2179 2185 2187 2230 2234 2252 2309 2336 2345 2432 2497 2529 2535 2540 2543 2593 2789 2790 3113 3328 3408 3455 3460 3534 3570 3632 3643 3665 3697 3703 3732 3737 3742 3748 3777 3782 3816 3819 3847 3972 3974 3980 4019 4023 4046 4131 4159 4201 4216 4218 4220 4223 4398 4442 4462 4484 4486 4489 4616 4621 4626 4632 4633 4695 4698 4707 4742 4758 4766 4897 4954 4967 4977 4987 5019 5099 5127 5135 5763 5807 5808 5809 5927 5934 5940 5943 5968 5973 5990 6035 6061 6062 6063 6078 6109 6125 6148 6161 6179 6210 6300 6302 6358 6364 6377 6383 6460 6516 6582 6594 6596 6636 6700 6730 6899 6901 6919 6936 6970 7034 7040 7082 7118 7191 7223 7257 7261 7265 7269 7273 7288 7299 7320 7323 7330 7343 7345 7353 7354 7387 7405 7406 7411 7438 7439 7489 7553 7620 7655 7656 7658 7687 7702 7721 7727 7729 7761 7763 7765 7858 7866 7874 7881 7893 7946 7961 7966 7967 7969 7970 7971 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 7994 8233 8243 8244 8246 8247 8251 8254 8264 8266 8268 8270 8274 8275 8328 8336 8341 8416 8418 8421 8439 8565 8581 8662 8764 8833 8836 8850 8864 8866 Q_AD 623 # 2385 2983 3089 3115 3117 4124 4150 4189 4209 4217 4219 4229 4322 4332 4391 4401 4403 4416 4438 4441 4443 4445 4456 4469 4470 4473 4480 4488 4516 4521 4522 4539 4564 4615 4619 4620 4624 4625 4824 4900 4907 4969 4978 4981 4998 5022 5038 5045 5105 5162 5302 5326 5329 5373 5384 5396 5400 5402 5403 5416 5429 5487 5489 5491 5493 5561 5570 5573 5578 5588 5593 5633 5638 5648 5661 5667 5679 5682 5712 5717 5722 5724 5735 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 263 ; Cross Reference Listing 5759 5775 5776 5794 5986 6145 6546 7753 Q_Q*.5 628 # 2386 2387 3073 3092 3101 3145 4125 4153 4232 4253 4254 4266 4273 4281 4291 4299 4394 4396 4404 4408 4424 4439 4446 4498 4546 5046 5304 5327 5332 5407 5409 5439 5582 5607 5610 5618 5621 5623 5637 5672 5713 5727 5753 5756 5790 5792 5838 Q_Q*2 626 # 2993 3074 3077 3078 3079 3104 3108 3111 3146 3149 3150 4277 4285 4295 4303 4440 4450 4478 4481 4554 4557 4558 4561 4563 4585 4588 4600 4605 4825 4828 4901 4904 4909 5486 5498 5506 5510 5584 5589 5591 5603 5605 5606 5635 5676 5680 5729 5746 5768 5785 5813 5988 (U) DISP 858 # 4566 ADISP 865 # AREAD 861 # 2323 BDISP 866 # 2571 2577 2691 2693 2726 2732 2740 2742 2761 2763 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 3273 3279 3372 3391 3392 3475 3489 3503 3513 3698 3705 3743 4063 4077 4129 4135 4158 4160 5441 5449 5453 5499 5511 5521 5528 5932 5974 6118 6173 6380 6734 6806 6813 7568 7595 7613 7624 7651 8557 8857 BYTE 871 # 4710 4727 6155 6858 6879 CONSOLE 859 # DP 864 # 4432 4434 4451 4476 6479 6506 8800 DP LEFT 862 # 6465 6760 7454 8252 DROM 860 # 2356 2360 2369 2374 2382 2403 2409 2433 2438 5941 5944 EAMODE 872 # 2281 2347 3556 4749 4752 5928 6896 6904 7692 MUL 868 # 4273 4281 4291 4299 5585 5611 5613 5730 NICOND 870 # 2230 2231 2233 2234 2294 2300 2524 3045 3091 3119 3328 3340 3431 3455 3456 3459 3460 3527 3528 3554 3596 3713 3789 3796 4223 4487 4490 4698 5445 5451 5810 7387 7658 8237 NORM 863 # 5305 5334 5411 5486 5488 5498 5502 5504 5506 5507 5510 5532 5683 5737 5738 5748 5750 5770 5780 5782 5787 5788 5815 5844 PAGE FAIL 869 # RETURN 867 # 2459 2460 3561 3565 4029 4032 4235 4278 4286 4296 4304 4498 4520 4521 4523 4607 4634 4736 4738 4742 4777 4810 4829 4897 5111 5531 5533 5534 5623 5818 5825 5826 5841 6230 6240 6245 6248 6286 6287 6437 6443 6614 6637 6702 6733 6745 6776 6792 6809 6818 6820 6846 6881 6914 6920 6925 6965 7233 7300 7324 7399 7443 7551 7554 7626 7633 7639 7696 7704 7708 7711 7737 7749 7751 7753 7755 7757 7759 7761 7763 7765 7767 7958 7962 7996 8587 8602 8651 8654 8655 8668 8677 8680 8681 8785 8873 SCAD0 873 # 4697 4702 4716 4792 5288 5431 5433 5986 5988 6039 6849 6891 7723 (U) DIVIDE 959 # 4557 4558 4602 4606 (U) DONT CACHE 1129 # (U) DP FUNC 1146 # 7620 7655 7761 8566 8582 (U) DT 928 # 2T 931 # 3T 932 # 2183 2373 2385 2386 2496 2528 2534 2539 2542 2592 2783 2789 2990 3002 3005 3019 3089 3092 3334 3337 3346 3349 3408 3437 3440 3449 3452 3594 3594 3609 3609 3696 3702 3741 3747 3818 3971 3973 3979 3992 3997 4018 4022 4045 4089 4101 4127 4132 4194 4199 4217 4219 4332 4334 4336 4340 4354 4393 4399 4414 4416 4428 4438 4445 4458 4539 4615 4617 4619 4620 4622 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 264 ; Cross Reference Listing 4624 4625 4627 4643 4650 4697 4702 4710 4716 4718 4727 4742 4897 4968 4972 4981 4982 4997 5027 5040 5045 5109 5138 5164 5181 5305 5334 5351 5371 5377 5379 5411 5452 5486 5488 5494 5498 5502 5504 5506 5507 5510 5513 5518 5532 5553 5655 5674 5678 5681 5683 5695 5706 5725 5737 5738 5748 5749 5750 5752 5755 5758 5767 5770 5776 5780 5782 5787 5788 5812 5815 5818 5836 5844 5918 5960 5961 5978 5981 5997 6001 6011 6018 6027 6030 6046 6050 6065 6066 6067 6068 6085 6099 6100 6102 6119 6132 6138 6142 6145 6151 6155 6166 6183 6184 6186 6190 6194 6195 6197 6199 6204 6206 6208 6216 6218 6221 6257 6259 6260 6271 6272 6273 6274 6292 6298 6325 6329 6337 6342 6343 6353 6361 6366 6372 6379 6385 6386 6387 6388 6402 6404 6408 6458 6493 6496 6515 6546 6550 6556 6559 6563 6584 6593 6595 6596 6600 6620 6621 6635 6697 6699 6742 6743 6744 6750 6757 6812 6817 6819 6824 6828 6830 6845 6847 6858 6874 6879 6931 6935 6939 6944 6945 6950 6958 6959 6962 7008 7009 7060 7067 7069 7071 7072 7074 7076 7094 7103 7186 7243 7245 7247 7249 7251 7281 7290 7295 7297 7301 7302 7331 7333 7334 7337 7343 7345 7358 7367 7369 7373 7375 7377 7379 7381 7383 7406 7620 7625 7652 7655 7656 7684 7686 7690 7693 7695 7700 7707 7709 7761 7763 7765 7881 7948 7953 7954 7957 7966 7967 7969 7970 7972 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7990 7991 7992 7993 7995 8234 8235 8284 8306 8323 8324 8326 8327 8350 8353 8355 8357 8360 8375 8380 8386 8410 8411 8413 8414 8429 8432 8448 8452 8458 8472 8476 8478 8481 8491 8493 8498 8503 8531 8538 8551 8570 8572 8578 8579 8580 8586 8597 8599 8601 8603 8637 8640 8642 8645 8648 8669 8679 8720 8733 8737 8740 8745 8751 8775 8781 8790 8792 8794 8806 8835 8841 8849 8864 8866 4T 933 # 5T 934 # (U) EXT ADR 1152 # 3960 3970 3984 4004 4031 6977 6985 7489 7531 7620 7655 7761 7879 7882 7965 7968 7975 7978 7981 7984 7987 8329 8337 8343 8423 8664 8697 8713 8834 8870 8873 (U) FETCH 1118 # 2230 2231 2233 2234 2253 2279 2293 2299 2346 2407 2432 3022 3328 3340 3455 3456 3459 3460 3527 3528 3554 3596 3711 4223 4698 4707 7387 7658 7894 8792 (D) FL-B 1341 # AC 1342 # 5265 5268 5269 5273 5276 5277 5310 5314 5315 5339 5343 5344 5389 5390 5424 5425 BOTH 1344 # 5267 5271 5275 5279 5312 5317 5341 5346 MEM 1343 # 5266 5270 5274 5278 5311 5316 5340 5345 (U) FLG.C 1307 # 8282 8551 8572 8679 8736 8739 (U) FLG.PI 1306 # 3624 8360 8380 8448 8458 8478 8603 8640 8645 8669 8733 8832 (U) FLG.SN 1308 # 5513 5614 5615 5622 5749 5752 5755 5758 5818 5825 5826 (U) FLG.W 1305 # 8282 8472 8511 8570 8679 8736 8748 (U) FMWRITE 954 # 2162 2170 2172 2173 2175 2176 2178 2179 2185 2187 2491 2523 2774 3024 3045 3080 3113 3119 3302 3391 3431 3434 3437 3440 3443 3446 3449 3452 3665 3712 3714 3777 3782 3810 4184 4192 4201 4203 4214 4215 4216 4218 4220 4442 4458 4459 4460 4462 4465 4484 4486 4489 4616 4621 4626 4632 4633 4634 4695 4712 4954 4967 4977 4987 5019 5070 5119 5183 5445 5451 5763 5771 5807 5808 5809 5816 5927 5940 5943 5968 5973 5990 6014 6034 6035 6041 6051 6054 6061 6062 6063 6078 6089 6091 6093 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 265 ; Cross Reference Listing 6109 6125 6127 6134 6148 6161 6168 6179 6210 6227 6229 6264 6265 6277 6278 6285 6287 6300 6302 6311 6314 6346 6352 6358 6363 6364 6368 6377 6383 6390 6391 6392 6551 6582 6611 6684 6700 6730 6826 6854 6895 6919 6933 6936 6941 6948 6953 6960 6970 7082 7191 7257 7261 7265 7269 7273 7288 7299 7320 7323 7353 7354 7438 7439 7579 7687 7721 7727 7729 7767 7874 7946 7961 7971 8233 8237 8243 8244 8246 8247 8254 8264 8266 8268 8270 8274 8275 8416 8418 8439 8764 (U) FORCE EXEC 1116 # 3960 3970 3984 4004 4031 6977 6985 7475 7489 7491 7505 7522 7531 7539 7614 7617 7653 7664 7670 7879 7882 7896 7965 7968 7975 7978 7981 7984 7987 8329 8337 8343 8423 8664 8697 8713 8834 8870 8873 (U) FORCE USER 1115 # 3960 3970 3984 4004 4031 6977 6985 7475 7489 7522 7531 7614 7617 7653 7664 7670 7879 7882 7896 7965 7968 7975 7978 7981 7984 7987 8329 8337 8343 8423 8664 8697 8713 8834 8870 8873 (U) GENL 716 # 2231 2233 2278 2291 2292 2298 2303 2318 2319 2331 2342 2365 2693 2724 2732 2754 2756 3340 3456 3459 3527 3528 3529 3538 3541 3554 3566 3596 3620 3634 3762 3821 3835 3839 3984 3996 4001 4031 4047 4098 4741 4771 4980 5039 5062 5111 5123 5145 5149 5154 5169 5172 5182 5330 5593 5930 5933 5936 5977 6003 6006 6022 6028 6057 6076 6082 6090 6094 6105 6117 6121 6128 6147 6175 6252 6267 6305 6340 6357 6384 6395 6399 6455 6461 6508 6565 6569 6604 6629 6670 6675 6733 6852 6894 6903 7062 7088 7102 7171 7187 7189 7233 7314 7319 7344 7378 7380 7382 7384 7396 7456 7457 7458 7459 7460 7461 7462 7484 7554 7680 7701 7701 7882 7898 7968 7975 7978 7981 7984 7987 8236 8501 8547 8555 8798 8804 8810 8812 8814 8816 8818 8820 8822 8823 8824 8854 8873 (U) GENR 723 # 2422 2424 2437 2459 2460 2691 2726 2730 2747 2749 2773 3116 3118 3389 3531 3540 3543 3545 3546 3547 3580 3585 3588 3608 3629 3642 3773 3924 3926 3928 3930 3932 3934 3936 3938 3946 3966 3976 4028 4044 4109 4110 4111 4133 4156 4363 4402 4464 4518 4641 4818 4953 4961 5024 5069 5104 5108 5295 5296 5299 5300 5324 5325 5357 5358 5418 5419 5495 5511 5614 5615 5622 5638 5760 5795 5825 5826 5841 5923 5945 6172 6177 6246 6262 6263 6269 6308 6310 6317 6323 6332 6351 6403 6406 6411 6436 6442 6513 6607 6609 6679 6683 6737 6779 6783 6787 6791 6795 6799 6815 6913 6925 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7056 7096 7099 7127 7134 7138 7153 7159 7168 7176 7198 7199 7217 7221 7227 7252 7275 7286 7370 7372 7374 7376 7508 7710 7755 7829 7833 7838 7840 7842 7844 7846 7848 8229 8232 8283 8287 8290 8295 8446 8471 8508 8512 8546 8550 8553 8564 8634 8739 8744 8749 8755 8769 8832 (U) HALT 1284 # BW14 1294 # 2519 CSL 1288 # 2250 2268 HALT 1287 # 3582 ILLII 1291 # 7504 ILLINT 1292 # 7536 IOPF 1290 # 8789 MULERR 1296 # 2193 NICOND 5 1295 # POWER 1286 # 2221 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 266 ; Cross Reference Listing (U) HOLD USER 1085 # 2219 2580 3406 3422 3489 3503 3560 3564 3600 3622 3692 3704 3760 3790 3794 3809 3815 4010 4063 4077 4094 4104 4107 4137 4138 4162 4212 4224 4234 4237 4344 4379 4410 4496 4645 4647 4712 4729 4751 5003 5355 5367 5432 5720 6394 6395 6994 (D) I 1349 # 2550 2555 2560 2565 2603 2608 2613 2618 2623 2628 2633 2638 2645 2650 2655 2660 2665 2670 2675 2680 2799 2800 2801 2802 2810 2820 2830 2835 2845 2852 2862 2872 2882 2891 2892 2893 2894 2902 2913 2923 2933 2942 2943 2944 2945 2957 2958 3177 3178 3179 3180 3181 3182 3183 3184 3186 3187 3195 3196 3197 3198 3199 3200 3201 3202 3213 3214 3215 3216 3217 3218 3219 3220 3230 3231 3232 3233 3234 3235 3236 3237 3352 3353 3354 3355 3356 3357 3358 3359 3464 3465 3466 3467 3468 3469 3470 3471 3478 3479 3480 3481 3482 3483 3484 3485 3492 3493 3494 3495 3496 3497 3498 3499 3506 3507 3518 3520 3671 3672 3673 3674 3768 3801 3802 3803 3804 3857 3858 3859 3860 3861 3862 3863 3864 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3903 3904 3905 3906 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 4056 4070 4118 4143 4310 4315 5114 5390 5854 5855 5856 5857 5858 5859 5860 5862 5863 5864 5865 5867 5868 5869 5870 5872 5873 5874 5875 5876 5877 5878 5879 5913 7772 7773 7774 7776 7777 7779 7780 7782 7783 7784 7785 7786 7787 7788 7789 7791 7792 7793 7794 7795 7796 7797 7798 7800 7801 7802 7803 7804 7805 7806 7807 7809 7810 7811 7812 7813 7814 7815 7816 7818 7819 7820 7821 7822 7823 7824 7825 (U) I.CO3 1180 # (U) I.CO4 1181 # (U) I.CO5 1182 # (U) I.CO6 1183 # (U) I.CO7 1184 # (U) IO BYTE 1165 # 7615 7665 7671 (U) IO CYCLE 1159 # 7475 7522 7614 7617 7653 7664 7670 7896 (U) J 521 # 2323 2356 2360 2369 2374 2382 2403 2409 2433 2438 2459 2460 3561 3565 4029 4032 4235 4278 4286 4296 4304 4498 4520 4521 4523 4567 4607 4634 4736 4738 4742 4777 4810 4829 4897 5111 5531 5533 5534 5623 5818 5825 5826 5841 5941 5944 6230 6240 6245 6248 6286 6287 6437 6443 6614 6637 6702 6733 6745 6776 6792 6809 6818 6820 6846 6881 6914 6920 6925 6965 7233 7300 7324 7399 7443 7551 7554 7626 7633 7639 7696 7704 7708 7711 7737 7749 7751 7753 7755 7757 7759 7761 7763 7765 7767 7890 7958 7962 7996 8587 8602 8651 8654 8655 8668 8677 8680 8681 8785 8873 ABORT 8785 # 3951 8766 ACBSET 7147 # 7129 AC_ARX 7767 # 3836 6951 ADD 4062 # 4055 4056 4057 4058 ADDCRY 6245 # 6220 6226 6239 ADJBP 4942 # 4696 ADJBP0 4945 # 4947 ADJBP1 4964 # 4966 ADJBP2 4974 # 4971 ADJBP3 5017 # 5002 ADJBP4 5029 # 5041 ADJBP5 5043 # 5037 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 267 ; Cross Reference Listing ADJBP6 5064 # 5066 ADJSP 3772 # 3768 ADJSP1 3789 # 3781 ADJSP2 3794 # 3786 AND 2816 # 2809 2810 2811 2812 2841 ANDCA 2826 # 2819 2820 2821 2822 2878 ANDCB 2878 # 2871 2872 2873 2874 ANDCM 2841 # 2834 2835 2836 2837 AOBJ 3511 # 3506 3507 AOJ 3489 # 3478 3479 3480 3481 3482 3483 3484 3485 AOS 3406 # 3395 3396 3397 3398 3399 3400 3401 3402 APRID 7046 # APRSO 7033 # 7009 APRSZ 7036 # 7008 ARSIGN 2459 # 2401 ASH 2983 # 2954 ASHC 3086 # 2958 ASHC1 3092 # 3090 ASHCL 3108 # 3097 3110 ASHCQ1 3119 # 3080 3116 ASHCR 3101 # 3103 ASHCX 3113 # 3105 ASHL 2993 # 2993 ASHL0 2990 # 2983 ASHR 2986 # 2972 ASHX 2997 # 3010 ASHXX 3010 # 3015 BACKBP 6964 # 6932 6940 BACKD 6939 # 8815 8823 8825 BACKS 6931 # 8822 BADDATA 8273 # 8258 BDABT 6408 # 6344 BDCFLG 6410 # 6389 BDEC 6292 # BDEC0 6298 # 6296 BDEC1 6305 # 6314 BDEC2 6310 # 6318 BDEC3 6320 # 6306 6328 BDEC4 6325 # 6320 BDEC5 6337 # 6323 6333 BDECLP 6375 # 6394 BDFILL 6359 # 6368 BDSET 6383 # 6403 6406 BDSUB 6422 # 6326 6376 BDSUB1 6426 # 6423 BDSUB2 6442 # 6445 BDTBL 6399 # 6382 BITCHK 6913 # 5919 5962 6100 6102 6459 BIXUB 7592 # 7585 7586 7587 7588 BIXUB1 7601 # 7597 7599 BLT 5118 # 5114 BLT-CLEANUP 5179 # 8807 BLTCLR 5138 # 5153 BLTGOT 5166 # 5141 BLTGO 5164 # 5130 5158 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 268 ; Cross Reference Listing BLTLP 5161 # 5176 BLTLP1 5127 # 5163 BOTH 2331 # BWRITE 2470 # 2571 2577 2691 2693 2726 2732 2740 2742 2761 2763 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 4063 4077 4129 4135 4158 4160 8557 8857 BYTEAS 4749 # 4773 6856 BYTEA 4751 # 4706 4725 BYTEA0 4754 # 4750 BYTFET 4775 # 4757 4761 6898 6899 BYTIND 4769 # 4765 CAIM 3372 # 3353 3354 3355 3356 3357 3358 3359 3361 3362 3363 3364 3365 3366 3367 3368 CHKSN 5818 # 5799 CLARXL 7755 # 5102 7529 CLARX0 6436 # 4645 4647 4651 4652 6167 6301 6427 CLDISP 8800 # 6933 6941 6954 6960 8795 CLEANED 8803 # 5184 8797 CLEANUP 8802 # 8800 CLRB1 6287 # 6285 CLRBIN 6285 # 6170 6266 CLRFLG 6923 # 5966 6338 CLRPTL 7420 # 7423 CLRPT 7411 # CLRSN 5826 # 5604 5694 CMPDST 6151 # 6131 CMS 6099 # CMS2 6140 # 6110 CMS3 6116 # 6142 6146 CMS4 6119 # CMS5 6145 # 6124 CMS6 6131 # 6148 CMS7 6136 # 6133 CMS8 6147 # 6145 CMSDST 6935 # 8821 COM0 4634 # 4629 4630 COM0A 4629 # 4633 COM1 4633 # 4624 COM1A 4624 # 4632 COM2 4632 # 4619 COM2A 4619 # CONSO 7034 # 7016 CONSZ 7040 # 7015 CONT 7893 # 7888 CONT1 7900 # 4050 CPYSGN 4109 # 4095 4105 DAC 2491 # 2498 2768 6408 DADD 4089 # 4084 DADD1 4092 # 4098 DBABT 6251 # 6187 6191 DBDN1 6264 # 6262 DBDONE 6259 # 6253 6278 DBFAST 6204 # 6200 DBIN 6160 # DBIN1 6175 # 6178 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 269 ; Cross Reference Listing DBIN2 6179 # 6175 DBINLP 6183 # 6201 6211 DBLDBL 6235 # 6223 6234 DBLDIV 4585 # 4439 4449 5722 5726 DBLMUL 4229 # 4200 DBLNEG 4641 # 2783 DBLNGA 4642 # 2773 DBLNG1 4650 # 4364 6310 DBNEG 6269 # 6258 DBSLOW 6216 # 2184 6198 DBSLO 6197 # 6205 DBXIT 6257 # 6185 DDIV 4391 # 4386 DDIV1 4408 # 4395 4399 DDIV2 4411 # 4409 DDIV3A 4416 # 4421 DDIV3 4412 # 4406 DDIV4 4424 # 4417 DDIV5A 4438 # 4429 DDIV5B 4462 # 4453 DDIV5C 4464 # 4459 DDIV5 4432 # 4428 DDIV6 4467 # 4460 4462 DDIV7 4469 # DDIV8A 4478 # DDIV8 4476 # 4469 DDIV9 4484 # 4479 DDIVS 4498 # 4425 4443 5718 DFAD 5552 # 5539 DFADJ 5603 # 5568 5576 DFADJ1 5610 # 5611 DFADJ2 5612 # DFADJ3 5618 # 5614 5618 DFADJ4 5619 # 5615 DFADJ5 5621 # 5613 5622 DFADJ6 5623 # 5621 DFAS1 5561 # 5557 5559 DFAS2 5568 # 5562 DFAS3 5573 # 5564 DFAS5 5582 # 5570 5578 DFAS6 5587 # 5588 DFAS7 5589 # 5587 DFDV 5692 # 5689 DFDV1 5698 # 5705 DFDV2 5706 # 5699 DFDV3 5717 # 5709 DFDV4A 5732 # 5735 DFDV4B 5737 # 5734 DFDV4 5719 # 5715 DFMP 5633 # 5628 DFMP1 5635 # 5636 DFMP2 5661 # 5658 DFPR1 2424 # 2418 DFPR2 2425 # 2423 DFSB 5549 # 5540 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 270 ; Cross Reference Listing DIV 4330 # 4314 4315 4316 4317 DIV1 4339 # 4325 4327 4381 DIV2 4342 # 4355 DIVA 4351 # 4337 DIVB 4357 # 4352 DIVC 4370 # 4362 4367 DIVHI 4592 # 4586 4589 4603 DIVIDE 4557 # 4557 DIVSET 4551 # 4547 DIVSGN 4537 # 4519 5373 DIVSUB 4516 # 4343 4976 4986 5020 DMLINT 4237 # 4202 DMOVNM 2783 # 2778 DMOVN 2773 # 2769 DMOVN1 2785 # 2777 DMTRAP 4221 # 4215 DMUL 4173 # 4168 DMUL1 4194 # 4183 DMUL2 4199 # 4193 DMULGO 4228 # 4181 DNEG 5775 # 5749 5752 5755 5758 DNEG1 5777 # 5775 DNEG2 5779 # 5776 DNN1 5805 # 5801 DNN2 5807 # 5803 DNNORM 5785 # 5738 5780 5782 5787 5815 DNNRM1 5812 # 5795 DNORM 5746 # 5684 5737 5748 5770 DNORM0 5683 # 5593 DNORM1 5767 # 5760 DNORM2 5809 # 5807 DOCVT 6297 # 6347 6363 DOCVT1 6372 # 6297 DOCVT2 6393 # 6373 DOCVT3 6390 # 6412 DONE 2230 # 2530 2544 2844 2845 3024 3177 3178 3186 3187 3287 3331 3334 3337 3352 3464 3715 3823 3840 4224 4729 5071 5146 5170 7040 7083 7155 7257 7261 7265 7269 7273 7321 7345 7355 7406 7440 7579 DPB 4718 # 4691 DPB1 4889 # 4728 6880 DPB7 4896 # 4890 4891 4892 4893 4894 4918 DPBSLO 4900 # 4889 DRND1 5841 # 5837 5845 5848 DROUND 5835 # 5751 5754 5757 5789 5791 5793 5839 DSMS1 7553 # 7550 7555 DSTEA 6898 # 6904 DSTIND 6903 # 6900 6901 DSUB 4101 # 4085 DUMP 7965 # 7949 7956 DVSUB1 4543 # 4540 DVSUB2 4544 # 4538 DVSUB3 4546 # 4550 EACALC 2285 # 2348 EAPF 8864 # 8844 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 271 ; Cross Reference Listing EAPF1 8869 # 8851 EDBYTE 6635 # 6598 6626 EDEXMD 6546 # 6517 EDFILL 6562 # EDFIL1 6577 # 6564 EDFLT 6593 # 6539 6583 EDFLT1 6611 # 6607 6609 EDISP 6476 # 6470 EDISP1 6478 # 6478 EDIT 6455 # EDITLP 6460 # 6684 EDMSG 6620 # 6485 EDMSG1 6629 # 6622 EDN1A 6666 # 6671 EDNOP 6655 # 6487 6489 6491 6505 6514 6540 6551 6572 6578 6631 6632 6646 EDNOP1 6656 # 6650 EDNOP2 6673 # 6667 6673 EDOPR 6505 # 6482 EDSEL 6556 # 6509 EDSFLT 6582 # 6566 EDSKP 6643 # 6494 6497 6499 EDSKP1 6647 # 6644 EDSPUT 6569 # 6577 6587 EDSSIG 6539 # 6511 EDSTOP 6524 # 6507 6567 EDSTP1 6530 # 6533 ENDSKP 6267 # 6091 EQV 2888 # 2881 2882 2883 2884 EXCH 2590 # 2586 EXTDSP 5931 # EXTEA 5930 # EXTEA0 5927 # 5925 EXTEA1 5928 # 5936 EXTEND 5917 # 5913 EXTEXT 5940 # 5932 5946 EXTIND 5936 # 5933 FAD 5288 # 5265 5266 5267 5268 5269 5270 5271 FAS1 5290 # FAS2 5299 # 5290 FAS3 5302 # 5295 5296 5299 5300 FAS4 5304 # 5304 FDV 5351 # 5339 5340 5341 5343 5344 5345 5346 FDV0 5357 # 5354 FDV1 5359 # 5357 FDV2 5360 # 5358 FDV3 5361 # 5359 5360 FDV4 5363 # 5364 FDV5 5366 # 5363 FDV6 5369 # 5366 FDV7 5373 # 5374 FDV8 5376 # FDV9 5384 # 5376 5381 5382 FETIND 2341 # 2306 2311 2333 FIX 5429 # 5424 5425 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 272 ; Cross Reference Listing FIX++ 4561 # 4562 FIX1++ 4563 # 4561 FIXL 5444 # 5434 5444 FIXPC 8798 # 4237 6424 FIXR 5439 # 5440 FIXT 5451 # 5448 FIXX 5448 # 5441 FIXX1 5449 # 5455 FL-BWRITE 2517 # 5449 5453 5499 5521 FLEX 5499 # 5495 FLTR 5394 # 5389 FLTR1A 5402 # 5399 FLTR1 5398 # 5395 FLTR2 5407 # 5400 5402 FLTR3 5409 # 5410 FMP 5321 # 5310 5311 5312 5314 5315 5316 5317 FMP1 5326 # 5324 5325 FP-LONG 3936 # 3914 3915 3916 3917 3918 3919 FPR0 2398 # 2392 FPR1 2402 # FSB 5285 # 5273 5274 5275 5276 5277 5278 5279 FSC 5415 # 5390 GETPCW 7227 # 3982 GETSRC 6847 # 6122 6557 GOEXEC 4006 # 8871 GRP700 7045 # 7001 GRP701 7019 # 7002 GRP702 7242 # 7238 GSRC 6845 # 6079 6732 GSRC1 6854 # 6850 GTFILL 6917 # 5959 6456 GTPCW1 7231 # 7222 7231 H1 7884 # 7950 HALT 3580 # 3532 HALTED 7874 # 2193 2250 2268 2519 3582 7504 7536 8789 HALTLP 7890 # 7884 HARD 8764 # 7743 8260 8262 8276 HLL 2693 # 2602 2603 2646 2718 HLLE 2759 # 2632 2633 2634 2635 HLLO 2763 # 2622 2623 2624 2625 HLLZ 2761 # 2612 2613 2614 2615 HLR 2720 # 2649 2650 HLRE 2752 # 2679 2680 2681 2682 HLRM 2729 # 2651 HLRO 2756 # 2669 2670 2671 2672 HLRS 2732 # 2652 HLRZ 2754 # 2659 2660 2661 2662 HRL 2718 # 2607 2608 HRLE 2745 # 2637 2638 2639 2640 HRLM 2723 # 2609 HRLO 2749 # 2627 2628 2629 2630 HRLS 2726 # 2610 HRLZ 2747 # 2617 2618 2619 2620 HRR 2691 # 2604 2644 2645 2720 HRRE 2738 # 2674 2675 2676 2677 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 273 ; Cross Reference Listing HRRO 2742 # 2664 2665 2666 2667 HRRZ 2740 # 2654 2655 2656 2657 HSBDON 7992 # IBP 4694 # 4687 IBPS 4735 # 4697 4702 4716 IBPX 4742 # 3833 4735 8390 8519 IDIV 4321 # 4309 4310 4311 4312 IDPB 4716 # 4690 IDST 6891 # 6152 6875 IDSTX 6895 # 6892 ILDB 4702 # 4688 IMUL 4123 # 4117 4118 4119 4120 IMUL1 4129 # 4346 IMUL2 4131 # 4128 IMUL3 4137 # 4134 INCAR 7757 # 6053 7509 INCPC 2278 # 2273 INDEX 2318 # INDRCT 2336 # IOEA 7680 # 7612 7650 IOEA1 7686 # 7688 IOEA2 7690 # 7686 IOEAI 7698 # 7691 IOEAX 7707 # 7694 IOR 2868 # 2861 2862 2863 2864 2929 IORD 7611 # 7567 7578 7593 IORD1 7620 # 7616 IORD2 7630 # 7625 IORD3 7636 # 7631 7637 IOT700 7829 # 7772 7773 7774 IOT710 7831 # 7776 7777 IOT720 7838 # 7779 7780 IOT730 7840 # 7782 7783 7784 7785 7786 7787 7788 7789 IOT740 7842 # 7791 7792 7793 7794 7795 7796 7797 7798 IOT750 7844 # 7800 7801 7802 7803 7804 7805 7806 7807 IOT760 7846 # 7809 7810 7811 7812 7813 7814 7815 7816 IOT770 7848 # 7818 7819 7820 7821 7822 7823 7824 7825 IOW1 7720 # 7725 IOW2 7732 # 7722 7728 IOW3 7735 # 7742 IOW4 7740 # 7736 IOW5 7743 # 7730 IOWAIT 7716 # 7621 7657 IOWR 7649 # 7582 7602 IOWR1 7655 # 7665 7671 IOWR2 7662 # 7652 IOWR3 7668 # 7663 7669 ITRAP 8244 # 6055 JEN 3588 # 3542 JEN1 7550 # 3594 3609 JEN2 3594 # 3586 JFCL 3600 # 3520 JFFO 3018 # 2957 JFFO1 3026 # 3023 JFFOL 3040 # 3042 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 274 ; Cross Reference Listing JMPA 3443 # 3851 JRA 3845 # 3804 JRST 3527 # 3468 3518 JRST0 3556 # 3553 3577 3592 JRST1 3574 # 3569 3573 JRST10 3585 # 3539 JRSTF 3550 # 3530 JSA 3829 # 3803 JSP 3808 # 3802 JSR 3814 # 3801 JSTAC 3709 # 3699 3706 3744 JSTAC1 3712 # 3763 JSYS 3930 # 3911 JUMP 3475 # 3465 3466 3467 3469 3470 3471 JUMP-TABLE 3428 # 3475 3489 3503 3513 JUMP- 3455 # 3434 3437 3440 3603 JUMPA 3459 # 3443 3446 3449 3452 3811 4012 KIEPT 8710 # 8704 8707 KIF10 8701 # 8694 KIF30 8718 # 8699 8714 KIF40 8725 # 8729 KIF50 8733 # 8727 8756 8771 KIF80 8754 # KIF90 8759 # 8750 KIFILL 8689 # 8316 KIMUUO 4018 # 3961 KIUPT 8695 # 8717 L-BDEC 5891 # 5864 5865 L-CMS 5885 # 5854 5855 5856 5858 5859 5860 L-DBIN 5889 # 5862 5863 L-EDIT 5887 # 5857 L-MVS 5893 # 5867 5868 5869 5870 L-SPARE-A 5897 # 5873 L-SPARE-B 5899 # 5874 L-SPARE-C 5901 # 5875 5876 5877 5878 5879 L-XBLT 5895 # 5872 LDB 4704 # 4689 LDB1 4791 # 4711 6155 6860 LDB7 4805 # 4796 4797 4798 4799 4800 LDBSH 4820 # 4815 LDBSWP 4814 # 4793 LDPI2 7396 # 3595 7385 LOADAR 7748 # 6401 6464 6547 7682 LOADARX 7751 # 6756 7316 LOADPI 7395 # 2196 LOADQ 7753 # 5120 6108 LSH 2967 # 2956 LSHC 3069 # 2960 LSHCL 3077 # 3069 3077 LSHCR 3073 # 3073 LSHCX 3079 # 3074 3146 3151 LSHL 2974 # 2969 LUUO 4036 # 3857 3858 3859 3860 3861 3862 3863 3864 LUUO1 4039 # 5885 5887 5889 5891 5893 5895 5897 5899 5901 MAP 8227 # 8223 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 275 ; Cross Reference Listing MAPDON 8854 # 8809 MOVE 2577 # 2551 2574 2581 2605 2647 2829 2830 2831 2832 2846 2847 4110 4111 4137 4138 4162 4972 MOVELP 5997 # 5977 6006 MOVF1 6697 # 6703 MOVFIL 6703 # 6029 6090 MOVLP0 6006 # 5991 MOVM 2574 # 2564 2566 2567 MOVN 2579 # 2559 2560 2561 2562 MOVPAT 6472 # 6467 6469 6472 MOVRJ 6027 # 5983 MOVS 2571 # 2554 2555 2556 2557 2724 2730 2747 2749 2754 2756 MOVSTX 6080 # MOVST0 6075 # 5980 MOVST1 6076 # 6031 6086 MOVST2 6089 # 6000 6081 MOVST3 6093 # 6089 MOVST4 6085 # 6042 MSKPAT 6473 # 6468 MUL 4150 # 4142 4143 4144 4145 MUL+ 4272 # 4256 4268 4274 4292 MUL- 4290 # 4282 4300 MULBY4 6234 # 6217 MULSB1 4254 # 5644 MULSUB 4253 # 4126 4154 5047 5328 MULTIPLY 4265 # 4233 5649 5661 5668 MUUO 3943 # 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 MVABT 6011 # 6002 MVABT1 6014 # 6016 MVABT2 6018 # 6014 MVEND 6021 # MVS 5956 # MVS1 5973 # 5971 MVSK2 6061 # 6035 MVSK3 6051 # 6047 MVSKP 6034 # 6027 6045 6058 6069 MVSKP1 6045 # 6040 MVSKP2 6057 # 6049 MVSO 5985 # 5978 MVSO1 5988 # 5988 NEXT 4031 # 3972 3976 4019 7966 7969 7971 7973 7976 7979 7982 7985 7988 7990 NEXTAR 8873 # 8837 8865 NICOND 2239 # 2524 3045 3091 3119 3431 3713 3789 3796 4487 4490 5445 5451 5810 8237 NICOND-FETCH 2258 # 2230 2231 2233 2234 2294 2300 3328 3340 3455 3456 3459 3460 3527 3528 3554 3596 4223 4698 7387 7658 NIDISP 3091 # 3791 3795 4344 4379 4410 4496 4713 5003 5355 5367 5432 5720 NODDIV 4495 # 4432 4434 NODIV 4379 # 4373 4377 NOMOD 2322 # NXTWRD 4741 # 4737 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 276 ; Cross Reference Listing ORCA 2908 # 2901 2902 2903 2904 ORCB 2939 # 2932 2933 2934 2935 ORCM 2929 # 2922 2923 2924 2925 PAGE-FAIL 8242 # PF100 8498 # 8475 PF105 8506 # 8502 PF107 8479 # 8509 8513 PF110 8516 # 8482 PF120 8559 # 8539 PF125 8578 # 8576 8782 PF130 8541 # 8537 8543 PF140 8535 # PF25 8299 # 8301 PF30 8323 # 8312 PF35 8336 # 8325 PF40 8341 # 8333 PF45 8348 # 8368 8447 PF50 8380 # 8352 PF60 8364 # 8366 PF70 8386 # PF75 8398 # 8400 PF76 8421 # 8417 8419 PF77 8426 # 8330 8338 PF80 8458 # 8431 PF90 8470 # PFD 8250 # 8252 PFDBIN 6958 # 8819 PFDONE 8531 # 8757 8761 PFGAC0 6960 # PFMAP 8280 # 8236 8264 8268 8270 PFPI1 8773 # 8254 8266 PFPI2 8781 # PFT 8789 # 8360 8380 8448 8458 8478 8603 8640 8645 8669 8733 PFT1 8790 # 8778 PFT10 8833 # 8831 PFT1A 8797 # 8793 PFT2 8829 # 8805 PFT3 8832 # 8858 PFTICK 8491 # 8440 PI 7453 # 7455 8832 PI10 7471 # 7463 7464 7465 7466 7467 7468 7469 PI40 7489 # 7486 PI50 7490 # 7540 PIEXIT 7385 # 3624 PIJSR 7504 # 7493 PIP1 7463 # 7456 PIP2 7464 # 7457 PIP3 7465 # 7458 PIP4 7466 # 7459 PIP5 7467 # 7460 PIP6 7468 # 7461 PIP7 7469 # 7462 PISET 3623 # 7511 PIXPCW 3632 # 7496 POP 3719 # 3673 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 277 ; Cross Reference Listing POPJ 3752 # 3674 POPX1 3747 # 3735 PTRIMM 8429 # PTRIND 8437 # 8494 PTRSHR 8451 # 8433 PUSH 3679 # 3672 PUSH1 3681 # 3693 PUSHJ 3691 # 3671 PUTDST 6873 # 6004 6083 6365 6384 6570 6605 6630 6698 PWRON 7879 # 2222 QDNEG 4615 # 4419 4495 QMULT 4232 # 4190 4210 RDAPR 7094 # RDCSB 7245 # RDCSTM 7249 # RDEBR 7212 # RDEBR1 7214 # 7214 RDERA 7011 # RDHSB 7251 # RDINT 7358 # RDIO 7578 # 7571 7573 RDPI 7364 # RDPT 8662 # 8356 8367 8374 8451 8598 RDPUR 7247 # RDSPB 7243 # RDTIME 7327 # 7341 RDTIM1 7343 # 7340 RDUBR 7221 # ROT 3002 # 2955 ROTC 3141 # 2959 ROTCL 3149 # 3141 3149 ROTCR 3145 # 3145 ROTL 3012 # 3004 RTNREG 7405 # 7057 7107 7218 7243 7245 7247 7249 7251 7359 7364 RTNRG1 7406 # 7224 SAVVMA 7960 # 7875 7947 SBRL 7759 # 5370 6209 SECIMM 8350 # SECSHR 8374 # 8354 SETBLT 5098 # 5118 SETCA 2898 # 2891 2892 2893 2894 SETCM 2919 # 2912 2913 2914 2915 2939 SETO 2949 # 2942 2943 2944 2945 SETPDL 3704 # 3749 SETPTR 8631 # 8349 8428 SETSN 5825 # 5378 5380 5675 SETUBR 7158 # 7149 SETZ 2806 # 2799 2800 2801 2802 SFM 3642 # 3544 SHDREM 8677 # 8412 8415 SHIFT 2378 # 2388 SKIP 2233 # 3343 3346 3349 6267 6395 7034 SKIP-COMP-TABLE 3325 # 3372 3391 3392 6118 SKIPE 3334 # 6094 SKIPS 3389 # 3378 3379 3380 3381 3382 3383 3384 3385 3408 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 278 ; Cross Reference Listing SNNEG 5502 # 5487 5489 5491 5493 SNNORM 5506 # 5502 5504 5506 5510 SNNOT 5517 # 5513 SNNOT1 5520 # 5515 SNNOT2 5521 # 5517 5519 5520 SNORM 5486 # 5305 5334 5411 5486 5498 SNORM0 5411 # 5384 5396 5403 5418 5419 SNORM1 5498 # 5494 SOJ 3503 # 3492 3493 3494 3495 3496 3497 3498 3499 SOS 3422 # 3411 3412 3413 3414 3415 3416 3417 3418 SRCMOD 6730 # 5998 6183 6825 6829 6831 SRND1 5531 # 5528 SROUND 5528 # 5488 5490 5492 5507 5508 5509 5529 SSWEEP 7442 # 7415 7428 STAC 2523 # 2492 2536 2541 2549 2550 2565 2594 2774 2975 2988 2997 5764 5771 5816 6022 6530 7863 STAC34 6277 # 6272 STBOTH 2534 # STBTH1 2539 # 2487 STDBTH 2496 # STMAC 3696 # 3688 STMEM 2528 # 7870 STOBR 7763 # 3633 3985 7507 STOPC 7765 # 3636 7883 STORE 2542 # 2794 3644 STPF1A 6956 # 6948 STPTR1 8642 # 8639 STPTR2 8648 # 8644 STPTR3 8654 # 8650 STRPF 6944 # 8811 8813 STRPF0 6945 # 6962 STRPF1 6948 # STRPF2 6959 # 6956 STRPF3 6953 # STRPF4 6962 # 8817 STRTIO 7761 # 7477 7525 7899 STSELF 2486 # 2552 STUBRS 7162 # 7164 SUB 4076 # 4069 4070 4071 4072 SWEEPL 7433 # 7436 SWEEP 7427 # 7178 7198 7199 TDONE 3302 # 3293 3296 TDX 3273 # 3181 3190 3195 3199 3204 3208 3213 3217 3222 3226 3230 3234 3239 3243 TDXX 3278 # 3179 3183 3188 3192 3197 3201 3206 3210 3215 3219 3224 3228 3232 3236 3241 3245 TENLP 2182 # 2189 TEST-TABLE 3284 # 3273 3279 7568 TICK 7281 # 6064 TIOX 7567 # 7560 7561 7562 7563 TOCK 7284 # 7338 8492 8777 TOCK1 7288 # 7294 TOCK2 7295 # 7289 TOCK3 7299 # 7306 TRAP 6969 # 2243 2246 2249 2261 2264 2267 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 279 ; Cross Reference Listing TRNAR 6751 # 6560 TRNFNC 6773 # 6761 6780 6784 6788 6800 TRNNS1 6823 # 6813 TRNNS2 6826 # 6823 TRNRET 6805 # 6774 TRNSIG 6786 # 6796 TRNSS 6812 # 6807 TRNSS1 6808 # 6816 TRP1 6988 # 6978 6986 TSX 3271 # 3182 3191 3196 3200 3205 3209 3214 3218 3223 3227 3231 3235 3240 3244 TSXX 3276 # 3180 3184 3189 3193 3198 3202 3207 3211 3216 3220 3225 3229 3233 3237 3242 3246 TXXX 3287 # 3302 TXZX 3301 # 3290 UMOVEM 7866 # 7854 UMOVE 7858 # 7853 UPCST 8597 # 8385 8461 UUO 3942 # 3903 3910 UUO101 3924 # 3904 UUO102 3926 # 3905 UUO103 3928 # 3906 UUO106 3932 # 3912 UUO107 3934 # 3913 UUO247 3938 # 3920 UUOFLG 4027 # 3967 4021 UUOGO 3948 # 2437 3531 3540 3543 3545 3546 3547 3580 3585 3588 3608 3629 3642 3924 3926 3928 3930 3932 3934 3936 3938 6913 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7252 7275 7370 7829 7833 7838 7840 7842 7844 7846 7848 UUOPCW 3979 # 4024 VECINT 7518 # 7481 7521 VECIN1 7537 # 7535 WRAPR 7060 # WRAPR1 7079 # 7091 WRAPR2 7085 # 7078 WRCSB 7259 # WRCSTM 7267 # WREBR 7181 # WREBR1 7183 # 7183 WRHSB 7271 # WRINT 7351 # WRIO 7582 # 7572 7574 WRPI 7367 # WRPUR 7263 # WRSPB 7255 # WRTHSB 7953 # 7877 WRTIME 7311 # WRTIM1 7323 # 7292 7319 WRUBR 7118 # XCT 3653 # 3649 XCT1 3665 # 3659 6995 7903 XCT1A 3655 # 3663 XCT2 2345 # 3666 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 280 ; Cross Reference Listing XCTGO 2270 # 2254 7895 XJEN 3608 # 3536 XJRSTF 3615 # 3535 3638 XJRSTF0 3534 # 3612 XLATE 6750 # 6736 XLATE1 6759 # 6763 XOR 2858 # 2851 2852 2853 2854 XOS 3407 # 3422 XPCW 3629 # 3537 ZAPPTA 7438 # 7424 (D) J 1346 # (U) JFCLFLG 1105 # 3600 (U) LD FLAGS 1109 # 2220 3559 3563 3621 4009 7495 7510 8795 (U) LD PCU 1097 # 4011 (U) LDVMA 1148 # 2163 2182 2186 2230 2230 2231 2233 2234 2234 2252 2278 2293 2299 2305 2309 2332 2336 2345 2365 2407 2417 2420 2432 2786 2790 2791 3022 3328 3328 3340 3455 3455 3456 3459 3460 3460 3527 3528 3529 3534 3538 3541 3554 3567 3570 3596 3611 3617 3632 3634 3634 3643 3683 3710 3720 3732 3737 3753 3816 3847 3959 3960 3960 3969 3970 3970 3984 3984 4003 4004 4031 4031 4040 4047 4048 4223 4223 4698 4698 4707 4754 4758 4762 4766 5099 5127 5135 5149 5150 5154 5155 5172 5173 5931 5933 5934 5957 6105 6354 6381 6426 6432 6439 6455 6460 6516 6594 6636 6751 6898 6899 6900 6901 6977 6985 7118 7223 7314 7339 7344 7344 7387 7387 7405 7411 7474 7489 7489 7489 7490 7531 7531 7539 7620 7655 7658 7658 7680 7702 7761 7858 7866 7876 7879 7879 7882 7882 7893 7949 7965 7965 7968 7968 7975 7975 7978 7978 7981 7981 7984 7984 7987 7987 7994 8280 8328 8329 8329 8336 8337 8337 8341 8343 8421 8423 8565 8581 8662 8664 8696 8697 8711 8713 8779 8785 8833 8834 8834 8870 8870 8873 8873 (U) LOADFE 952 # 2381 2399 2414 2968 2971 2975 2985 2987 3003 3006 3009 3014 3026 3041 3087 4705 4709 4721 4814 4819 4821 4823 4826 4889 4902 4905 4906 4908 4910 5294 5322 5331 5333 5353 5359 5360 5374 5396 5400 5402 5403 5417 5486 5490 5492 5498 5506 5508 5509 5510 5529 5534 5575 5590 5592 5656 5673 5684 5707 5733 5747 5754 5757 5769 5786 5791 5793 5814 5839 5847 5985 5986 5988 6154 6525 6526 6532 6656 6657 6658 6659 6856 6859 6878 6896 (U) LOADSC 950 # 2177 2187 2380 2399 2414 2430 2991 2993 3069 3070 3071 3073 3077 3087 3096 3099 3103 3110 3141 3142 3143 3145 3149 4124 4152 4189 4209 4229 4255 4267 4273 4281 4291 4299 4342 4439 4447 4554 4557 4597 4943 4946 4959 4965 4970 4983 4999 5044 5059 5065 5288 5292 5293 5302 5304 5326 5373 5407 5410 5415 5433 5434 5435 5437 5440 5444 5554 5564 5574 5608 5611 5618 5633 5636 5644 5648 5651 5661 5667 5722 5723 6299 6328 6467 6469 6472 6476 6478 6649 6655 6661 6666 6673 7160 7163 7181 7183 7212 7214 7222 7228 7231 7422 7435 7442 7630 7637 7662 7668 7716 7723 7732 7736 8297 8300 8348 8362 8365 8396 8399 8536 8542 (U) LSRC 602 # (U) MACRO% ABORT MEM CYCLE 2001 # 2163 3611 7474 7876 7949 8280 8779 8785 AC 1851 # 4123 4150 4321 4412 5351 5416 5557 5559 AC[] 1852 # 4488 5696 5704 6207 6271 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 281 ; Cross Reference Listing AC[]_Q 1753 # 3119 4184 4192 4203 4215 AC[]_Q.AND.[] 1742 # 4442 4486 4616 4621 4626 4632 4633 AC[]_[] 1729 # 2491 2774 3045 4459 4465 5771 5816 6014 6034 6051 6134 6168 6227 6229 6264 6277 6278 6314 6346 6352 6363 6368 6391 6392 6551 6854 6895 6933 6941 6948 6953 AC[]_[] TEST 1730 # 6826 AC[]_[] VIA AD 1727 # AC[]_[]*2 1732 # 4201 AC[]_[]+1 1731 # 6700 AC[]_[]+Q 1737 # AC[]_[]+[] 1739 # 4484 6210 AC[]_[]-[] 1738 # 5968 AC[]_[].AND.[] 1741 # 4462 5763 5809 AC[]_[].EQV.Q 1743 # 4216 4218 4220 4489 AC[]_-Q 1749 # AC[]_-[] 1744 # AC[]_.NOT.[] 1747 # AC[]_0 1751 # 2175 3024 4460 6041 6089 6285 6287 AC[]_1 1752 # 2176 AC_-[] 1745 # 5808 AC_.NOT.[] 1748 # 5807 AC_Q 1750 # 4458 AC_[] 1733 # 2523 3080 3302 3391 3431 3443 3712 3714 3810 4634 4712 5119 5183 5445 5451 6091 6127 6390 6611 6684 6960 7579 7767 8237 AC_[] TEST 1734 # 3434 3437 3440 3446 3449 3452 4214 6265 6311 AC_[] VIA AD 1728 # AC_[]+1 1735 # 6936 AC_[]+Q 1736 # AC_[]+[] 1740 # 3113 3777 3782 AC_[].OR.[] 1746 # 5070 6054 6093 AD FLAGS 2029 # 2580 3406 3422 3489 3503 4063 4077 4094 4104 4107 4234 4645 4647 AD FLAGS EXIT 2077 # 4063 4077 AD PARITY 1955 # 2183 2359 2372 2373 2590 2691 2693 2724 2730 2783 2967 2970 2984 3018 3475 3719 3752 3774 3832 3845 4152 4194 4331 4722 5118 5288 5321 5353 5417 5563 5960 5963 5978 5981 6011 6027 6099 6101 6119 6151 6163 6166 6194 6197 6199 6206 6216 6257 6259 6260 6292 6297 6298 6299 6320 6325 6337 6372 6457 6515 6556 6593 6595 6699 6812 6819 6845 6847 6874 6931 6939 6945 7582 7869 ADD .25 1986 # 2579 2949 3372 3422 3503 3529 3538 3541 4076 4093 4101 4106 4280 4284 4326 4370 4403 4426 4427 4433 4454 4480 4521 4522 4523 4539 4541 4548 4554 4585 4615 4620 4625 4630 4642 4646 4650 4652 4981 5038 5055 5105 5124 5142 5166 5285 5360 5363 5364 5371 5382 5395 5487 5489 5491 5493 5504 5520 5549 5588 5701 5712 5719 5735 5776 5781 5802 5808 5842 5968 6001 6015 6036 6103 6139 6140 6141 6188 6252 6270 6273 6341 6358 6366 6385 6393 6394 6428 6430 6433 6481 6823 6944 6952 6958 7296 7396 7420 7433 7680 8691 8701 8798 8858 ADL PARITY 1948 # ADR PARITY 1952 # AREAD 2072 # 2323 ASH 1963 # 2427 2987 ASH AROV 2014 # 2993 3109 3112 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 282 ; Cross Reference Listing ASH36 LEFT 2980 # 2993 ASHC 1968 # 2993 3102 3105 3109 3112 4273 4281 4291 4299 4405 4409 4478 4482 4498 5304 5407 5409 5439 5583 5585 5589 5591 5607 5611 5618 5621 5623 5635 5676 5680 5715 5729 5747 5753 5756 5769 5786 5790 5792 5814 5839 B DISP 2073 # 2571 2577 2691 2693 2726 2732 2740 2742 2761 2763 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 3273 3279 3372 3391 3392 3475 3489 3503 3513 3698 3705 3743 4063 4077 4129 4135 4158 4160 5441 5449 5453 5499 5511 5521 5528 5932 5974 6118 6173 6380 6734 6806 6813 7568 7595 7613 7624 7651 8557 8857 BAD PARITY 1957 # BASIC DIV STEP 4533 # 4554 4557 BWRITE DISP 2074 # 2571 2577 2691 2693 2726 2732 2740 2742 2761 2763 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 4063 4077 4129 4135 4158 4160 8557 8857 BYTE DISP 2091 # 4710 4727 6155 6858 6879 BYTE STEP 4682 # 5986 5988 CALL IBP 4676 # 4697 4702 4716 CALL LOAD PI 2097 # 3595 7385 CALL [] 1987 # 2184 2196 2401 2773 2783 3553 3592 3594 3595 3609 3633 3636 3833 3836 3951 3967 3972 3976 3982 3985 4019 4021 4126 4154 4181 4190 4200 4210 4233 4343 4364 4419 4425 4439 4443 4449 4495 4519 4697 4702 4706 4711 4716 4725 4728 4976 4986 5020 5047 5102 5118 5120 5328 5370 5373 5378 5380 5488 5490 5492 5507 5508 5509 5568 5576 5604 5644 5649 5661 5668 5675 5694 5718 5722 5726 5751 5754 5757 5789 5791 5793 5799 5919 5959 5962 5966 5998 6004 6029 6053 6064 6079 6083 6090 6100 6102 6108 6122 6131 6152 6167 6170 6183 6198 6209 6217 6220 6223 6226 6234 6239 6266 6301 6310 6326 6338 6365 6376 6384 6401 6427 6456 6459 6464 6539 6547 6557 6560 6570 6583 6598 6605 6626 6630 6698 6732 6756 6856 6875 6880 6932 6940 6951 7222 7292 7316 7319 7338 7385 7415 7428 7477 7507 7509 7525 7529 7567 7578 7593 7612 7621 7650 7657 7682 7875 7877 7883 7899 7947 7949 7966 7969 7971 7973 7976 7979 7982 7985 7988 7990 8349 8356 8367 8374 8385 8390 8412 8415 8428 8451 8461 8492 8519 8598 8766 8777 8837 8865 CHANGE FLAGS 2007 # 2219 2220 2580 3406 3422 3489 3503 3559 3560 3563 3564 3600 3621 3622 3692 3704 3760 3790 3794 3809 3815 4009 4010 4011 4063 4077 4094 4104 4107 4137 4138 4162 4212 4224 4234 4237 4344 4379 4410 4496 4645 4647 4712 4729 4751 5003 5355 5367 5432 5720 6394 6395 6993 7495 7510 8795 CHK PARITY 1956 # 2271 2341 2355 2364 2368 2385 2396 2407 2413 2426 2497 2529 2535 2540 2543 2593 2789 3089 3408 3551 3575 3590 3615 3619 3680 3697 3703 3725 3742 3748 3761 3819 3850 3972 3974 3980 4007 4019 4023 4046 4124 4217 4219 4322 4332 4416 4438 4445 4742 4770 4776 4897 5162 5917 5936 6356 6546 6596 6599 6627 6903 6918 6988 7121 7256 7260 7264 7268 7272 7313 7343 7345 7352 7406 7490 7532 7656 7703 7748 7751 7753 7763 7765 7862 7881 7901 7966 7967 7969 7970 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 8345 8427 8667 8719 8836 8850 8864 8866 CHK PARITY L 1949 # CHK PARITY R 1953 # CLEANUP DISP 2099 # 8800 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 283 ; Cross Reference Listing CLEAR ARX0 1705 # 2773 4641 6269 6310 6436 6442 CLEAR CONTINUE 1996 # CLEAR EXECUTE 1997 # CLEAR RUN 1998 # CLEAR []0 1704 # 2773 4363 4641 6246 6262 6269 6310 6436 6442 CLR FPD 2016 # 3692 3809 3815 4212 4712 4729 6395 CLR IO BUSY 2002 # 7611 7649 CLR IO LATCH 2003 # 7696 7704 7708 7711 7720 7726 7735 7740 CLRCSH 1993 # 7417 7418 7421 DFADJ 5600 # 5611 DISMISS 2096 # 3594 3609 DIV 1971 # 4554 4557 4558 4605 5486 5498 5506 5510 5603 5605 5606 DIV DISP 2090 # DIV STEP 4534 # 4557 DONE 2082 # 2230 2234 3328 3455 3460 4223 4698 7387 7658 DPB SCAD 4885 # 4890 4891 4892 4893 4894 EA MODE DISP 2071 # 2281 2347 3556 4749 4752 5928 6904 7692 END BLT 2039 # 5145 5169 END MAP 2040 # 8547 END STATE 2037 # 5145 5169 6022 6094 6117 6267 6395 6399 6461 6733 8547 8804 8822 8823 8854 EXIT 2076 # 2571 2577 2691 2693 2726 2732 2740 2742 2761 2763 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 4129 4135 4158 4160 8557 8857 EXP TEST 2028 # 5495 5511 5841 FETCH 1808 # 2230 2231 2233 2234 2253 2293 2299 2407 2432 3022 3328 3340 3455 3456 3459 3460 3527 3528 3554 3596 3711 4223 4698 4707 7387 7658 7894 FE_-1 1928 # FE_-12. 1926 # 3026 FE_-2 1925 # FE_-FE 1912 # 4814 4908 FE_-FE+200 1939 # 5359 5360 FE_-FE+S# 1915 # 4819 FE_-FE-1 1913 # 2968 3003 FE_-S-10 1922 # 4823 4889 FE_-S-20 1921 # FE_0 1927 # FE_EXP 1934 # 2399 2414 5294 5575 FE_FE+1 1929 # 2971 2985 3006 5374 5490 5492 5508 5509 5529 5534 5754 5757 5791 5793 5839 5847 FE_FE+10 1931 # 4821 4826 4902 4910 FE_FE+2 1930 # 5331 FE_FE+4 1933 # 3041 FE_FE+P 1937 # 6526 FE_FE+S# 1940 # 5673 5684 6659 FE_FE+SC 1916 # 6658 FE_FE-1 1932 # 5486 5498 5506 5510 5590 5592 5747 5769 5786 5814 FE_FE-19 1914 # FE_FE-200 1938 # 5333 FE_FE.AND.S# 1917 # 4709 4906 6154 6532 6657 6859 FE_P 1918 # 4705 4905 6656 6856 6896 FE_S 1919 # FE_S# 1923 # 3026 5396 5400 5402 5403 6525 FE_S#-FE 1924 # 5733 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 284 ; Cross Reference Listing FE_S+2 1920 # 5985 FE_SC+EXP 1935 # 5322 5417 5656 FE_SC-EXP 1936 # 5353 5707 FIRST DIV STEP 4535 # 4554 FIX [] SIGN 1718 # 3389 4109 4133 4156 6737 7286 FL NO DIVIDE 2032 # 5355 5367 5720 FL-EXIT 2078 # 5449 5453 5499 5521 FM WRITE 1725 # 2162 2170 2172 2173 2175 2176 2178 2179 2185 2187 2491 2523 2774 3024 3045 3080 3113 3119 3302 3391 3431 3434 3437 3440 3443 3446 3449 3452 3665 3712 3714 3777 3782 3810 4184 4192 4201 4203 4214 4215 4216 4218 4220 4442 4458 4459 4460 4462 4465 4484 4486 4489 4616 4621 4626 4632 4633 4634 4695 4712 4954 4967 4977 4987 5019 5070 5119 5183 5445 5451 5763 5771 5807 5808 5809 5816 5927 5940 5943 5968 5973 5990 6014 6034 6035 6041 6051 6054 6061 6062 6063 6078 6089 6091 6093 6109 6125 6127 6134 6148 6161 6168 6179 6210 6227 6229 6264 6265 6277 6278 6285 6287 6300 6302 6311 6314 6346 6352 6358 6363 6364 6368 6377 6383 6390 6391 6392 6551 6582 6611 6684 6700 6730 6826 6854 6895 6919 6933 6936 6941 6948 6953 6960 6970 7082 7191 7257 7261 7265 7269 7273 7288 7299 7320 7323 7353 7354 7438 7439 7579 7687 7721 7727 7729 7767 7874 7946 7961 7971 8233 8237 8243 8244 8246 8247 8254 8264 8266 8268 8270 8274 8275 8416 8418 8439 8764 FORCE EXEC 1788 # 7491 7505 7539 GEN 17-FE 1943 # 4791 GEN MSK [] 1721 # 4825 4828 4901 4904 5988 HALT [] 2098 # 2193 2250 2268 2519 3582 7504 7536 8789 HOLD LEFT 1947 # 2231 2233 2278 2291 2292 2298 2303 2318 2319 2331 2342 2365 2693 2724 2732 2754 2756 3340 3456 3459 3527 3528 3529 3538 3541 3554 3566 3596 3620 3634 3762 3821 3835 3839 3984 3996 4001 4031 4047 4098 4741 4771 4980 5039 5062 5111 5123 5145 5149 5154 5169 5172 5182 5330 5593 5930 5933 5936 5977 6003 6006 6022 6028 6057 6076 6082 6090 6094 6105 6117 6121 6128 6147 6175 6252 6267 6305 6340 6357 6384 6395 6399 6455 6461 6508 6565 6569 6604 6629 6670 6675 6733 6852 6894 6903 7062 7088 7102 7171 7187 7189 7233 7314 7319 7344 7378 7380 7382 7384 7396 7456 7457 7458 7459 7460 7461 7462 7484 7554 7680 7701 7701 7882 7898 7968 7975 7978 7981 7984 7987 8236 8501 8547 8555 8798 8804 8810 8812 8814 8816 8818 8820 8822 8823 8824 8854 8873 HOLD RIGHT 1951 # 2422 2424 2437 2459 2460 2691 2726 2730 2747 2749 2773 3116 3118 3389 3531 3540 3543 3545 3546 3547 3580 3585 3588 3608 3629 3642 3773 3924 3926 3928 3930 3932 3934 3936 3938 3946 3966 3976 4028 4044 4109 4110 4111 4133 4156 4363 4402 4464 4518 4641 4818 4953 4961 5024 5069 5104 5108 5295 5296 5299 5300 5324 5325 5357 5358 5418 5419 5495 5511 5614 5615 5622 5638 5760 5795 5825 5826 5841 5923 5945 6172 6177 6246 6262 6263 6269 6308 6310 6317 6323 6332 6351 6403 6406 6411 6436 6442 6513 6607 6609 6679 6683 6737 6779 6783 6787 6791 6795 6799 6815 6913 6925 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7056 7096 7099 7127 7134 7138 7153 7159 7168 7176 7198 7199 7217 7221 7227 7252 7275 7286 7370 7372 7374 7376 7508 7710 7755 7829 7833 7838 7840 7842 7844 7846 7848 8229 8232 8283 8287 8290 8295 8446 8471 8508 8512 8546 8550 8553 8564 8634 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 285 ; Cross Reference Listing 8739 8744 8749 8755 8769 8832 IBP DP 4673 # 4697 4702 4716 6038 6848 6891 6964 IBP SCAD 4674 # 4697 4702 4716 6038 6848 6891 IBP SPEC 4675 # 4697 4702 4716 INH CRY18 1959 # 3512 3682 3729 3758 3778 3783 5035 5110 INST DISP 2075 # 2356 2360 2369 2374 2382 2403 2409 2433 2438 INTERRUPT TRAP 2088 # JFCL FLAGS 2025 # 3600 JUMP DISP 2081 # 3475 3489 3503 3513 JUMPA 2083 # 3456 3459 3527 3528 3554 3596 LDB SCAD 4787 # 4796 4797 4798 4799 4800 LEAVE USER 2023 # 2219 4010 LOAD AC BLOCKS 1991 # 2165 7154 7177 LOAD BYTE EA 1982 # 4705 4724 4772 5924 5936 6855 LOAD DST EA 1985 # 6892 6894 6903 LOAD FE 1865 # 2381 2399 2414 2968 2971 2975 2985 2987 3003 3006 3009 3014 3026 3041 3087 4705 4709 4721 4814 4819 4821 4823 4826 4889 4902 4905 4906 4908 4910 5294 5322 5331 5333 5353 5359 5360 5374 5396 5400 5402 5403 5417 5486 5490 5492 5498 5506 5508 5509 5510 5529 5534 5575 5590 5592 5656 5673 5684 5707 5733 5747 5754 5757 5769 5786 5791 5793 5814 5839 5847 5985 5986 5988 6154 6525 6526 6532 6656 6657 6658 6659 6856 6859 6878 6896 LOAD FLAGS 2027 # 2220 3559 3563 3621 4009 7495 7510 8795 LOAD IND EA 1983 # 2343 LOAD INST 1980 # 2272 3657 6989 7902 LOAD INST EA 1981 # 3552 3576 3591 7699 LOAD IR 1976 # 5923 LOAD PAGE TABLE 1990 # 7412 8573 LOAD PCU 2021 # 4011 LOAD PI 1994 # 3610 7398 7473 7955 LOAD PXCT 1988 # 3662 LOAD SC 1864 # 2177 2187 2380 2399 2414 2430 2991 2993 3069 3070 3071 3073 3077 3087 3096 3099 3103 3110 3141 3142 3143 3145 3149 4124 4152 4189 4209 4229 4255 4267 4273 4281 4291 4299 4342 4439 4447 4554 4557 4597 4943 4946 4959 4965 4970 4983 4999 5044 5059 5065 5288 5292 5293 5302 5304 5326 5373 5407 5410 5415 5433 5434 5435 5437 5440 5444 5554 5564 5574 5608 5611 5618 5633 5636 5644 5648 5651 5661 5667 5722 5723 6299 6328 6467 6469 6472 6476 6478 6649 6655 6661 6666 6673 7160 7163 7181 7183 7212 7214 7222 7228 7231 7422 7435 7442 7630 7637 7662 7668 7716 7723 7732 7736 8297 8300 8348 8362 8365 8396 8399 8536 8542 LOAD SRC EA 1984 # LOAD VMA 1787 # 2163 2182 2186 2230 2230 2231 2233 2234 2234 2252 2278 2293 2299 2305 2309 2332 2336 2345 2365 2407 2417 2420 2432 2786 2790 2791 3022 3328 3328 3340 3455 3455 3456 3459 3460 3460 3527 3528 3529 3534 3538 3541 3554 3567 3570 3596 3611 3617 3632 3634 3634 3643 3683 3710 3720 3732 3737 3753 3816 3847 3959 3960 3960 3969 3970 3970 3984 3984 4003 4004 4031 4031 4040 4047 4048 4223 4223 4698 4698 4707 4754 4758 4762 4766 5099 5127 5135 5149 5150 5154 5155 5172 5173 5931 5933 5934 5957 6105 6354 6381 6426 6432 6439 6455 6460 6516 6594 6636 6751 6898 6899 6900 6901 6977 6985 7118 7223 7314 7339 7344 7344 7387 7387 7405 7411 7474 7489 7489 7489 7490 7531 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 286 ; Cross Reference Listing 7531 7539 7620 7655 7658 7658 7680 7702 7761 7858 7866 7876 7879 7879 7882 7882 7893 7949 7965 7965 7968 7968 7975 7975 7978 7978 7981 7981 7984 7984 7987 7987 7994 8280 8328 8329 8329 8336 8337 8337 8341 8343 8421 8423 8565 8581 8662 8664 8696 8697 8711 8713 8779 8785 8833 8834 8834 8870 8870 8873 8873 LSH 1964 # LSHC 1967 # 3073 3077 4586 4589 LUUO 2085 # 5885 5887 5889 5891 5893 5895 5897 5899 5901 MEM CYCLE 1784 # 2163 2182 2186 2230 2230 2230 2231 2231 2233 2233 2234 2234 2234 2252 2253 2270 2278 2293 2293 2299 2299 2304 2305 2309 2310 2332 2333 2336 2337 2341 2345 2354 2363 2365 2366 2367 2395 2406 2407 2407 2417 2418 2420 2421 2425 2432 2432 2496 2528 2534 2539 2542 2591 2592 2786 2787 2789 2790 2791 2793 3022 3022 3328 3328 3328 3340 3340 3407 3408 3455 3455 3455 3456 3456 3459 3459 3460 3460 3460 3527 3527 3528 3528 3529 3529 3534 3534 3538 3538 3541 3541 3550 3554 3554 3567 3568 3570 3571 3574 3589 3596 3596 3611 3615 3617 3618 3619 3632 3632 3634 3634 3635 3638 3643 3643 3679 3683 3684 3696 3702 3710 3711 3720 3721 3724 3732 3734 3737 3739 3741 3747 3753 3755 3761 3816 3817 3818 3830 3847 3848 3849 3959 3960 3960 3969 3970 3970 3971 3973 3979 3984 3984 3984 4003 4004 4005 4006 4018 4022 4031 4031 4031 4040 4041 4045 4047 4048 4049 4223 4223 4223 4698 4698 4698 4707 4707 4735 4741 4742 4754 4755 4758 4759 4762 4763 4766 4767 4769 4775 4896 4897 5099 5100 5127 5128 5135 5136 5138 5149 5150 5152 5154 5155 5157 5161 5164 5172 5173 5175 5917 5931 5933 5933 5934 5934 5936 5957 5958 6105 6105 6354 6355 6356 6381 6382 6426 6432 6439 6455 6455 6460 6460 6516 6516 6548 6550 6594 6594 6596 6599 6627 6636 6636 6751 6752 6898 6898 6899 6899 6900 6900 6901 6901 6903 6917 6973 6976 6977 6981 6984 6985 6988 7118 7119 7120 7223 7223 7255 7256 7259 7260 7263 7264 7267 7268 7271 7272 7311 7312 7314 7315 7339 7340 7343 7344 7344 7344 7345 7351 7352 7387 7387 7387 7405 7405 7406 7411 7474 7478 7489 7489 7489 7490 7490 7505 7526 7531 7531 7532 7539 7540 7620 7622 7655 7656 7658 7658 7658 7680 7681 7702 7702 7703 7748 7751 7753 7761 7763 7765 7858 7859 7861 7866 7867 7876 7879 7879 7881 7882 7882 7882 7893 7894 7900 7949 7965 7965 7966 7967 7968 7968 7968 7969 7970 7973 7974 7975 7975 7975 7976 7977 7978 7978 7978 7979 7980 7981 7981 7981 7982 7983 7984 7984 7984 7985 7986 7987 7987 7987 7988 7989 7991 7994 8280 8328 8329 8329 8336 8337 8337 8341 8342 8343 8344 8389 8421 8422 8423 8426 8518 8565 8581 8662 8663 8664 8666 8696 8697 8698 8711 8712 8713 8718 8779 8785 8833 8834 8834 8835 8849 8864 8866 8870 8870 8873 8873 8873 MEM READ 1812 # 2270 2341 2354 2363 2367 2395 2406 2425 3550 3574 3589 3615 3619 3679 3724 3761 3849 4006 4769 4775 5161 5917 5936 6356 6599 6627 6903 6917 6973 6981 6988 7120 7256 7260 7264 7268 7272 7312 7352 7478 7490 7526 7532 7622 7703 7748 7751 7753 7861 7900 8344 8426 8666 8718 MEM WAIT 1811 # 2270 2341 2354 2363 2367 2395 2406 2425 2496 2528 2534 2539 2542 2592 2789 3408 3550 3574 3589 3615 3619 3679 3696 3702 3724 3741 3747 3761 3818 3849 3971 3973 3979 4006 4018 4022 4045 4742 4769 4775 4897 5138 5161 5164 5917 5936 6356 6550 6596 6599 6627 6903 6917 6973 6981 6988 7120 7256 7260 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 287 ; Cross Reference Listing 7264 7268 7272 7312 7343 7345 7352 7406 7478 7490 7526 7532 7622 7656 7703 7748 7751 7753 7763 7765 7861 7881 7900 7966 7967 7969 7970 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 8344 8426 8666 8718 8835 8849 8864 8866 MEM WRITE 1813 # 2496 2528 2534 2539 2542 2592 2789 3408 3696 3702 3741 3747 3818 3971 3973 3979 4018 4022 4045 4742 4897 5138 5164 6550 6596 7343 7345 7406 7656 7763 7765 7881 7966 7967 7969 7970 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 8835 8849 8864 8866 MEM_Q 1820 # 5139 5165 6550 MEM_[] 1819 # 2497 2529 2535 2540 2543 2593 2789 3408 3697 3703 3742 3748 3819 3972 3974 3980 4019 4023 4046 4742 4897 6596 7343 7345 7406 7656 7763 7765 7881 7966 7967 7969 7970 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 8836 8850 8864 8866 MUL DISP 2089 # 4273 4281 4291 4299 5585 5611 5613 5730 MUL FINAL 4251 # 4277 4285 4295 4303 MUL STEP 4250 # 4273 4281 4291 4299 NEXT INST 2069 # 2524 3045 3091 3119 3431 3713 3789 3796 4487 4490 5445 5451 5810 8237 NEXT INST FETCH 2070 # 2230 2231 2233 2234 2294 2300 3328 3340 3455 3456 3459 3460 3527 3528 3554 3596 4223 4698 7387 7658 NEXT [] PHYSICAL WRI 1842 # 3984 4031 7882 7968 7975 7978 7981 7984 7987 8873 NO DIVIDE 2031 # 4344 4379 4410 4496 5003 NORM DISP 2095 # 5305 5334 5411 5486 5488 5498 5502 5504 5506 5507 5510 5532 5683 5737 5738 5748 5750 5770 5780 5782 5787 5788 5815 5844 ONES 1970 # 4825 4828 4901 4904 5988 PAGE FAIL TRAP 2086 # 8360 8380 8448 8458 8478 8603 8640 8645 8669 8733 PI DISP 2094 # PXCT BLT DEST 1796 # 5129 5137 5151 5156 PXCT BLT SRC 1800 # 5101 5174 PXCT BYTE DATA 1798 # 4756 4760 6898 6899 PXCT BYTE PTR EA 1797 # 4764 4768 PXCT DATA 1795 # 2323 2365 2417 2420 2788 2792 3733 3738 PXCT EA 1794 # 2332 2337 3572 PXCT EXTEND EA 1801 # 5933 5934 PXCT STACK WORD 1799 # 3685 3722 3754 Q-[] 1669 # 4433 Q.AND.NOT.[] 1670 # Q_# 1685 # 4978 5022 Q_-1 1677 # Q_-AC[] 1678 # 4615 4620 4625 Q_-Q 1679 # 4403 4480 4521 4522 4539 5487 5489 5491 5493 5776 Q_-[] 1676 # 5712 Q_.NOT.AC[] 1675 # 4619 4624 Q_.NOT.Q 1684 # 5775 Q_0 1686 # 2983 4824 4900 5302 5373 5384 5396 5400 5402 5403 5416 5429 5722 5986 Q_0 XWD [] 1687 # Q_AC 1680 # 4124 4322 Q_AC[] 1681 # 2385 3089 4217 4219 4332 6546 Q_AC[].AND.MASK 1682 # Q_AC[].AND.[] 1683 # 4416 4438 4445 Q_MEM 1830 # 5162 7753 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 288 ; Cross Reference Listing Q_Q*.5 1692 # 4232 4266 4439 5637 5727 Q_Q*2 1693 # Q_Q+.25 1688 # 5588 5735 Q_Q+1 1689 # Q_Q+AC 1691 # 4998 Q_Q+[] 1698 # 4441 4473 5570 5578 5679 5682 Q_Q-1 1690 # 5038 Q_Q-WORK[] 1777 # 4981 Q_Q.AND.# 1695 # 3115 4516 5329 5638 Q_Q.AND.NOT.[] 1697 # 5724 Q_Q.AND.[] 1696 # 4488 4907 Q_Q.OR.# 1694 # 3117 4401 Q_WORK[] 1759 # 5045 6145 Q_[] 1671 # 4150 4189 4209 4229 4443 4469 4969 5326 5561 5573 5633 5648 5661 5667 5717 Q_[]+[] 1673 # 4470 Q_[]-[] 1672 # 5105 Q_[].AND.Q 1699 # 4564 5759 5794 Q_[].AND.[] 1674 # 4391 Q_[].OR.Q 1700 # 5593 RAM_[] 1780 # 2185 2187 READ Q 1710 # 5452 5494 5518 5767 5812 READ XR 1708 # 3558 READ [] 1709 # 2378 2398 2574 2738 2745 2752 2759 3070 3086 3142 3287 3331 3334 3337 3343 3346 3349 3562 3610 3621 3661 3954 3958 3968 4002 4008 4039 4127 4333 4339 4353 4358 4360 4365 4432 4434 4451 4467 4476 4537 4544 4565 4704 4708 4723 4726 4823 4889 4905 5026 5290 5294 5377 5379 5411 5415 5448 5488 5507 5575 5674 5683 5732 5750 5788 5924 5942 5985 6019 6120 6123 6129 6142 6153 6169 6345 6381 6432 6439 6465 6479 6484 6506 6510 6562 6648 6656 6751 6773 6805 6855 6857 6879 7077 7079 7080 7085 7089 7190 7304 7339 7418 7424 7431 7698 7955 7965 8310 8409 8577 8635 8689 8725 8795 8800 RETURN [] 2093 # 2459 2460 3561 3565 4029 4032 4235 4278 4286 4296 4304 4498 4520 4521 4523 4607 4634 4736 4738 4742 4777 4810 4829 4897 5111 5531 5533 5534 5623 5818 5825 5826 5841 6230 6240 6245 6248 6286 6287 6437 6443 6614 6637 6702 6733 6745 6776 6792 6809 6818 6820 6846 6881 6914 6920 6925 6965 7233 7300 7324 7399 7443 7551 7554 7626 7633 7639 7696 7704 7708 7711 7737 7749 7751 7753 7755 7757 7759 7761 7763 7765 7767 7958 7962 7996 8587 8602 8651 8654 8655 8668 8677 8680 8681 8785 8873 ROT 1966 # 3009 3014 ROTC 1969 # 3145 3149 SCAD DISP 2092 # 4697 4702 4716 4792 5288 5431 5433 5986 5988 6039 6849 6891 7723 SC_-1 1909 # SC_-2 1910 # SC_-SHIFT 1873 # SC_-SHIFT-1 1874 # 3070 3142 SC_-SHIFT-2 1875 # SC_0 1908 # 6655 6666 SC_1 1907 # SC_11. 1898 # SC_14. 1897 # ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 289 ; Cross Reference Listing SC_19. 1896 # 2177 SC_2 1906 # 6476 SC_20. 1895 # 6299 SC_22. 1894 # SC_24. 1893 # SC_26. 1892 # 5722 SC_27. 1891 # 5326 5373 SC_28. 1890 # SC_3 1905 # 4959 SC_34. 1889 # 4342 4439 4447 4970 4983 4999 SC_35. 1888 # 4124 4152 4189 4209 4229 5044 5644 5648 5661 5667 5723 SC_36. 1887 # SC_4 1904 # SC_5 1903 # 7630 7662 SC_6 1902 # 5407 5633 6469 7181 7212 7222 7228 SC_7 1901 # 6467 7160 8297 8348 8396 8536 SC_8. 1900 # SC_9. 1899 # 4943 5059 SC_EXP 1880 # 2399 2414 5292 5564 SC_FE 1883 # 2430 5651 SC_FE+S# 1882 # 3096 5433 SC_S# 1884 # 2177 4124 4152 4189 4209 4229 4342 4439 4447 4943 4959 4970 4983 4999 5044 5059 5326 5373 5407 5633 5644 5648 5661 5667 5722 5723 6299 6467 6469 6476 6655 6666 7160 7181 7212 7222 7228 7442 7630 7662 7716 7732 8297 8348 8396 8536 SC_S#-FE 1881 # 3099 5435 SC_SC-1 1869 # 7723 SC_SC-EXP 1876 # SC_SC-EXP-1 1877 # 5288 5554 SC_SC-FE 1879 # SC_SC-FE-1 1878 # 5293 5574 SC_SHIFT 1870 # 3087 5415 SC_SHIFT-1 1871 # 2380 SC_SHIFT-2 1872 # SET APR ENABLES 2000 # 2168 7081 7190 SET AROV 2009 # 4137 4138 4162 4224 5432 SET FL NO DIVIDE 2012 # 5355 5367 5720 SET FOV 2010 # SET FPD 2015 # 4237 4751 6394 SET HALT 1995 # 7884 7950 SET NO DIVIDE 2011 # 4344 4379 4410 4496 5003 5355 5367 5720 SET PDL OV 2018 # 3704 3760 3790 3794 SET P TO 36-S 4678 # 4737 6048 6851 6893 SET TRAP1 2019 # SHIFT 1867 # 2975 2987 3009 3014 SKIP AC REF 2063 # SKIP AD.EQ.0 2047 # 3019 3334 3346 3437 3449 4127 4132 4334 4336 4340 4354 4399 4428 4458 4539 4617 4622 4627 4643 4650 4968 4997 5351 5377 5379 5452 5494 5518 5674 5725 5767 5812 6142 6195 6271 6274 6563 6600 6621 6744 7331 8324 8327 8411 8414 SKIP AD.LE.0 2048 # 3337 3349 3440 3452 4393 5027 5371 5695 6342 7297 7954 SKIP ADL.EQ.0 2059 # 2190 3992 3997 5394 5399 5513 5678 5681 5749 5752 5755 5758 5818 5918 5961 6100 6102 6184 6204 6388 6404 6458 6493 6496 6528 6992 7128 7142 7188 7197 7492 7493 7684 7686 7700 8284 8306 8350 8357 8360 8375 8380 8429 8448 8452 8458 8472 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 290 ; Cross Reference Listing 8476 8478 8498 8551 8570 8572 8599 8603 8637 8640 8642 8645 8648 8669 8679 8733 8751 8792 8841 SKIP ADL.LE.0 2050 # 7693 SKIP ADR.EQ.0 2060 # 3088 3594 3609 5125 6329 6402 6757 7034 7040 7067 7069 7072 7074 7076 7367 7369 7373 7375 7377 7379 7381 7383 7480 7533 7553 7625 7652 8235 8503 8531 8720 8737 8740 8745 SKIP CRY0 2055 # 3687 3730 3759 5363 5487 5489 5491 5493 SKIP CRY1 2056 # 4090 4102 5803 6219 6225 6238 6429 6440 SKIP CRY2 2057 # 5776 5836 SKIP DP0 2045 # 2400 2415 2574 2752 2759 3042 3114 3331 3343 3434 3446 3776 3779 3784 3955 4109 4134 4156 4159 4214 4222 4323 4359 4361 4366 4371 4375 4397 4414 4426 4433 4448 4467 4485 4537 4544 4559 5000 5144 5168 5290 5294 5323 5353 5361 5395 5417 5448 5555 5657 5704 5708 5719 5732 5969 5982 5999 6012 6019 6037 6079 6081 6103 6120 6123 6129 6169 6261 6266 6303 6312 6345 6362 6434 6484 6510 6701 6731 6773 6827 6946 7122 7286 8311 8409 8636 8690 SKIP DP18 2046 # 2379 2738 2745 5942 6189 6393 6482 6805 6806 7519 8693 8703 8726 SKIP EXECUTE 2064 # 7888 SKIP FPD 2052 # 4176 4697 4702 4716 6293 SKIP IF AC0 2044 # 2486 3390 4694 SKIP IO LEGAL 2054 # 2436 3539 3542 SKIP IRPT 2061 # 5148 6039 8248 8443 8665 8773 8804 8855 SKIP JFCL 2058 # 3601 SKIP KERNEL 2053 # 3532 3536 3537 3544 3653 6971 SKIP -1MS 2062 # 6034 SKIP-COMP DISP 2080 # 3372 3391 3392 6118 SPEC MEM READ 1814 # 2412 SPEC MEM WRITE 1815 # START NO TEST WRITE 1807 # 8389 8518 START READ 1805 # 2230 2231 2233 2234 2253 2293 2299 2304 2310 2333 2337 2366 2407 2418 2421 2432 3022 3328 3340 3455 3456 3459 3460 3527 3528 3529 3534 3538 3541 3554 3568 3571 3596 3618 3638 3711 3721 3755 3848 4005 4049 4223 4698 4707 4755 4759 4763 4767 5100 5175 5933 5934 5958 6105 6355 6382 6455 6460 6516 6636 6752 6898 6899 6900 6901 6976 6984 7119 7255 7259 7263 7267 7271 7311 7315 7351 7387 7540 7658 7681 7702 7859 7894 8342 8422 8663 8698 8712 START WRITE 1806 # 2591 2787 2793 3407 3632 3635 3643 3684 3734 3739 3817 3830 3984 4031 4041 4735 4741 4896 5128 5136 5152 5157 6548 6594 7223 7340 7344 7405 7505 7867 7882 7968 7975 7978 7981 7984 7987 8873 STATE_[] 2036 # 5111 5977 6003 6006 6028 6076 6082 6090 6121 6128 6147 6175 6357 6384 6508 6565 6569 6629 8236 8810 8812 8814 8816 8818 8820 8824 STEP SC 1866 # 2187 2991 2993 3069 3071 3073 3077 3103 3110 3141 3143 3145 3149 4255 4267 4273 4281 4291 4299 4554 4557 4597 4946 4965 5065 5302 5304 5410 5434 5437 5440 5444 5608 5611 5618 5636 6328 6472 6478 6673 7163 7183 7214 7231 7422 7435 7637 7668 7736 8300 8362 8365 8399 8542 SWEEP 1992 # 7430 7431 7434 TAKE INTERRUPT 2087 # 8832 TEST DISP 2079 # 3273 3279 7568 TL [] 1714 # 3992 3997 5513 5678 5681 5749 5752 5755 5758 5818 5918 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 291 ; Cross Reference Listing 5961 6100 6102 6184 6204 6388 6404 6458 6493 6496 7684 7686 7700 8284 8306 8350 8357 8360 8375 8380 8429 8448 8452 8458 8472 8476 8478 8498 8551 8570 8572 8599 8603 8637 8640 8642 8645 8648 8669 8679 8733 8751 8792 8841 TR [] 1713 # 3594 3609 6329 6402 6757 7067 7069 7072 7074 7076 7367 7369 7373 7375 7377 7379 7381 7383 7625 7652 8235 8503 8531 8720 8737 8740 8745 TURN OFF PXCT 1989 # 2242 2245 2248 2260 2263 2266 2280 TXXX TEST 2065 # 3287 UNHALT 1999 # 7887 UPDATE USER 2022 # 3560 3564 3622 UUO 2084 # 2437 3531 3540 3543 3545 3546 3547 3580 3585 3588 3608 3629 3642 3924 3926 3928 3930 3932 3934 3936 3938 6913 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7252 7275 7370 7829 7833 7838 7840 7842 7844 7846 7848 VMA 1854 # VMA EXTENDED 1792 # VMA PHYSICAL 1789 # 3960 3970 3984 4004 4031 6977 6985 7489 7531 7879 7882 7965 7968 7975 7978 7981 7984 7987 8329 8337 8343 8423 8664 8697 8713 8834 8870 8873 VMA PHYSICAL READ 1791 # 7489 7531 8329 8337 8870 VMA PHYSICAL WRITE 1790 # 3960 3970 7879 7965 8834 VMA_[] 1834 # 2230 2234 2252 2309 2336 2345 2432 2790 3328 3455 3460 3534 3570 3632 3643 3732 3737 3816 3847 4223 4698 4707 4758 4766 5099 5127 5135 5934 6460 6516 6594 6636 6899 6901 7118 7223 7387 7405 7411 7489 7658 7702 7858 7866 7893 7994 8341 8565 8581 8662 8833 VMA_[] WITH FLAGS 1835 # 7761 VMA_[]+1 1837 # 2231 2233 2278 2365 3340 3634 4047 5149 5154 5172 6105 6455 7314 7344 VMA_[]+XR 1839 # 4754 4762 6898 6900 VMA_[]+[] 1840 # 8328 8336 8421 VMA_[]-1 1838 # 3529 3538 3541 7680 VMA_[].OR.[] WITH FL 1836 # 7620 7655 WORK[] 1855 # 6137 6359 6558 6625 6703 6734 6737 WORK[]_.NOT.[] 1765 # 6179 WORK[]_0 1760 # 2179 7438 7439 WORK[]_1 1761 # 2178 WORK[]_Q 1758 # 4977 6109 6148 WORK[]_[] 1762 # 2162 2170 2172 2173 4695 4954 4967 4987 5019 5927 5940 5943 5973 6035 6061 6062 6063 6078 6125 6161 6300 6302 6364 6377 6383 6582 6730 6919 6970 7082 7191 7257 7261 7265 7269 7273 7288 7299 7320 7323 7353 7354 7721 7727 7729 7874 7946 7961 7971 8233 8243 8244 8246 8247 8254 8264 8266 8268 8270 8274 8275 8416 8418 8439 8764 WORK[]_[] CLR LH 1763 # 3665 7687 WORK[]_[]-1 1764 # 6358 WORK[]_[].AND.[] 1766 # 5990 WRITE TEST 1804 # 2591 2787 2793 3407 3632 3635 3643 3684 3734 3739 3817 3830 3984 4031 4041 4735 4741 4896 5128 5136 5152 5157 6548 6594 7223 7255 7259 7263 7267 7271 7340 7344 7405 7505 7867 7882 7968 7975 7978 7981 7984 7987 8873 XR 1853 # [] LEFT_-1 1655 # 2742 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 292 ; Cross Reference Listing [] LEFT_0 1653 # 2740 [] RIGHT_-1 1656 # 2763 [] RIGHT_0 1654 # 2761 []+[] 1520 # 2785 4234 4374 []-# 1522 # 6188 6481 8691 8701 []-[] 1521 # 4370 4426 4427 5124 5142 5166 5363 5371 5719 6103 [].AND.# 1523 # 5394 5398 6527 6990 7140 7188 7197 [].AND.NOT.WORK[] 1767 # [].AND.NOT.[] 1526 # 4131 [].AND.Q 1524 # 4398 [].AND.WORK[] 1768 # 6743 [].AND.[] 1525 # 4159 7034 7040 7553 [].OR.[] 1527 # [].XOR.# 1528 # 2190 7492 7493 [].XOR.[] 1529 # 7330 []_# 1531 # 2151 2155 2180 2181 2221 2747 2749 2754 2756 4543 4951 4974 4984 4988 5017 5060 5111 5945 5977 6003 6006 6028 6076 6082 6090 6121 6128 6147 6175 6357 6384 6508 6565 6569 6629 7046 7048 7414 7416 7427 7429 7508 7550 8236 8810 8812 8814 8816 8818 8820 8824 []_#-[] 1530 # []_(#-[])*2 1617 # 5055 []_(-[])*.5 1618 # []_(-[]-.25)*.5 LONG 1619 # 4404 5713 []_(-[]-.25)*2 LONG 1620 # 4481 []_(AC[].AND.[])*.5 1615 # 4180 4182 5552 5643 5698 []_(MEM.AND.[])*.5 1829 # 2426 []_(Q+1)*.5 1616 # 5835 []_([]+#)*2 1630 # []_([]+1)*2 1631 # 6647 []_([]+[])*.5 LONG 1632 # 5582 []_([]+[])*2 LONG 1633 # 4588 []_([]+[]+.25)*.5 LO 1636 # []_([]-[])*.5 LONG 1634 # []_([]-[])*2 LONG 1635 # 4585 []_([].AND.#)*.5 1622 # 4948 4955 7534 []_([].AND.#)*2 1623 # []_([].AND.NOT.#)*.5 1624 # []_([].AND.NOT.#)*2 1625 # []_([].AND.[])*.5 1626 # 4174 []_([].AND.[])*2 1627 # []_([].OR.#)*.5 1628 # []_([].OR.#)*2 1629 # []_+SIGN 1659 # 2424 2459 5295 5299 5324 5357 5418 []_+SIGN*.5 1664 # 5556 5658 5709 []_-1 1532 # 4326 6394 7396 []_-2 1533 # []_-AC 1548 # 4630 []_-AC[] 1549 # 6273 []_-Q 1534 # []_-Q*.5 1536 # 5382 []_-Q*2 1535 # 4454 []_-SIGN 1660 # 2422 2460 5296 5300 5325 5358 5419 []_-SIGN*.5 1665 # 5558 5659 5711 []_-WORK[] 1775 # 6001 6944 6958 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 293 ; Cross Reference Listing []_-[] 1537 # 2579 2949 4523 4541 4548 4642 4646 4650 4652 5285 5360 5395 5504 5520 5549 5701 5781 5802 6270 []_-[]*2 1539 # 5364 []_-[]-.25 1538 # 5550 []_.NOT.AC[] 1541 # 6272 []_.NOT.AC 1540 # 2898 2908 4629 []_.NOT.Q 1542 # 4914 5989 []_.NOT.WORK[] 1774 # 6018 6046 6050 6186 6190 6962 []_.NOT.[] 1543 # 2841 2878 2919 2929 3290 4096 4540 4644 4651 5454 5502 5517 5519 5700 5710 5779 5970 5972 6524 7683 8678 []_0 1544 # 2163 2165 2168 2177 2196 2218 2402 2806 3273 3975 4228 4324 4538 4818 4960 5103 5145 5169 5521 5694 5761 5777 5805 6022 6094 6106 6117 6146 6267 6305 6339 6395 6399 6403 6406 6461 6733 7158 7170 7216 7293 7368 7413 7481 7710 7755 7879 8547 8804 8822 8823 8854 []_0 XWD [] 1546 # 2157 2160 2204 2240 2244 2247 2259 2262 2265 3948 3988 4036 4400 4411 5885 5887 5889 5891 5893 5895 5897 5899 5901 6597 7284 7463 7464 7465 7466 7467 7468 7469 []_0*.5 LONG 1545 # 4254 []_AC[] 1563 # 2183 2373 2783 5960 5978 5981 6011 6027 6099 6119 6151 6166 6194 6197 6199 6216 6257 6259 6260 6292 6298 6325 6337 6372 6515 6556 6593 6595 6699 6812 6819 6845 6847 6874 6931 6939 6945 []_AC[]*.5 1565 # 4194 []_AC[]*2 1564 # 6206 []_AC[]-1 1560 # 6366 6385 []_AC[]-[] 1559 # 4101 []_AC[].AND.[] 1561 # []_AC 1547 # 2359 2372 2590 2691 2693 2724 2730 2967 2984 3475 3719 3752 3774 3832 3845 4152 4331 4722 5118 5288 5321 5353 5417 5563 5963 6101 6163 6297 6299 6320 6457 7582 7869 []_AC*.5 1550 # 2990 3002 3005 4199 4414 5553 5655 5706 []_AC*.5 LONG 1551 # 2386 3092 []_AC*2 1552 # 4718 []_AC+1 1553 # 3489 []_AC+1000001 1554 # 3511 3681 []_AC+[] 1555 # 5109 []_AC-1 1556 # 3503 []_AC-[] 1557 # 3372 4076 4106 []_AC-[]-.25 1558 # 4103 []_AC.AND.MASK 1562 # 2970 3018 []_APR 1566 # 7008 7009 7071 7103 7302 []_CURRENT AC [] 1567 # []_EA 1570 # 2322 []_EA FROM [] 1568 # 5931 []_EXP 1571 # 5495 5511 5841 []_FE 1572 # 3043 6660 []_FLAGS 1573 # 3630 3644 3965 3991 7494 8844 []_IO DATA 1824 # 7479 7527 7623 8256 []_MEM 1825 # 2271 2341 2355 2364 2368 2396 2413 3551 3575 3590 3615 3619 3680 3725 3761 3850 4007 4770 5917 5936 6356 6599 6627 6903 6918 6988 7121 7256 7260 7264 7268 7272 7313 7352 7490 7532 7703 7748 7751 7862 7901 8345 8427 8667 8719 []_MEM THEN FETCH 1826 # 2407 []_MEM*.5 1827 # ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 294 ; Cross Reference Listing []_MEM.AND.MASK 1828 # 4776 []_P 1574 # 6530 6676 []_PC WITH FLAGS 1575 # 3691 3808 3814 4020 4221 6969 7506 8848 []_Q 1576 # 4129 4137 4357 4412 4429 4435 4444 5612 5619 5639 5662 5721 5723 []_Q*.5 1577 # 4192 5376 5381 5651 []_Q*2 1578 # []_Q*2 LONG 1579 # 4440 4450 []_Q+1 1580 # 5106 []_RAM 1581 # []_TIME 1582 # 7327 7328 7329 []_VMA 1583 # 7717 7960 8230 8245 8765 []_VMA FLAGS 1845 # 7475 7522 7614 7617 7653 7664 7670 7896 []_VMA IO READ 1846 # 7475 7522 7614 7617 7896 []_VMA IO WRITE 1847 # 7653 7664 7670 []_WORK[] 1773 # 4972 4982 5181 6065 6066 6067 6068 6132 6343 6353 6386 6387 6408 6584 6620 6697 6817 6828 6935 7060 7094 7186 7243 7245 7247 7249 7251 7281 7290 7295 7301 7333 7337 7358 7690 7695 7948 7953 7957 7972 7990 7992 7993 7995 8234 8323 8326 8410 8413 8491 8493 8538 8578 8579 8580 8586 8775 8781 8790 8794 8806 []_WORK[]+1 1776 # 5997 6030 6085 6183 6361 6824 6830 []_XR 1584 # 7693 []_[] 1585 # 2297 3021 3456 3459 3527 3528 3554 3581 3596 3655 3709 3829 3834 4123 4151 4175 4191 4321 4330 4345 4351 4380 4735 5043 5291 5292 5293 5331 5351 5359 5568 5569 5576 5577 5650 5692 5695 5737 5738 5979 5999 6045 6080 6340 6351 6359 6426 6526 6759 6850 6873 6892 6949 7015 7016 7196 7233 7332 7364 7510 7592 7594 7601 7626 8296 8384 8535 8559 8856 []_[] SWAP 1586 # 2391 2571 2718 2720 2723 2726 2729 2732 3271 3276 3595 3772 3831 3846 3964 4816 4942 4958 5058 5098 5107 5180 6405 6462 6467 6468 6762 7095 7372 7385 7395 8437 8728 []_[] XWD 0 1587 # 6160 6275 7743 8260 8262 8276 []_[]*.5 1588 # 2154 2428 2429 2986 3007 3008 3012 3095 3098 4173 4230 4392 4420 4551 4552 4553 4559 4820 4896 4945 4964 5366 5374 5441 5490 5492 5508 5509 5528 5529 5534 5644 5677 5846 6469 6472 6476 6478 6558 6666 6673 6736 7212 7214 7222 7228 7231 7537 7555 7630 7636 8299 8315 []_[]*.5 LONG 1589 # 2387 3073 3101 3145 4125 4153 4232 4253 4266 4394 4396 4408 4424 4439 4446 4498 4546 5046 5304 5327 5332 5407 5409 5439 5607 5610 5618 5621 5623 5637 5672 5727 5753 5756 5790 5792 5838 []_[]*2 1590 # 2152 2974 2997 3010 3013 3040 4128 4155 4211 5064 5361 5369 5444 6207 6753 7162 7181 7183 7482 7518 7662 7668 7759 8361 8364 8398 8541 []_[]*2 LONG 1591 # 2993 3074 3077 3078 3079 3104 3108 3111 3146 3149 3150 4478 4558 4561 4563 4909 5486 5498 5506 5510 5584 5589 5591 5603 5605 5606 5635 5676 5680 5729 5746 5768 5785 5813 []_[]*4 1592 # 6463 []_[]+# 1593 # 3727 3756 6422 6431 7483 7528 8331 8339 8705 8715 8829 []_[]+.25 1594 # 5842 []_[]+0 1595 # []_[]+1 1596 # 2182 2186 2416 2419 3406 3616 3637 4741 5147 5171 5453 5956 6057 6075 6104 6247 6315 6327 6334 6354 6375 6389 6444 6507 6531 6625 6852 6894 7291 7757 8808 8869 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 295 ; Cross Reference Listing []_[]+1000001 1597 # 3820 3837 5121 []_[]+AC 1598 # 4062 4092 []_[]+AC[] 1599 # 4089 6208 6218 6221 []_[]+Q 1600 # 4452 []_[]+RAM 1601 # 6438 6440 []_[]+WORK[] 1769 # 5040 6379 6559 6635 6742 6750 7334 7707 7709 8353 8355 8432 8597 []_[]+XR 1602 # 2291 2303 2318 2331 3566 5930 5933 7701 []_[]+[] 1603 # 3950 3990 4205 4471 4474 4562 5305 5449 5532 5663 6020 6052 6224 6235 6237 6674 6956 6972 6980 7285 7485 7520 7530 7538 8695 8710 []_[]+[]+.25 1604 # []_[]-# 1605 # []_[]-1 1606 # 3422 6036 6140 6141 6252 6393 6430 6823 8798 8858 []_[]-1000001 1607 # []_[]-AC 1608 # []_[]-RAM 1609 # 6428 6433 []_[]-WORK[] 1778 # []_[]-[] 1610 # 6015 6341 6952 7296 7420 7433 []_[]-[] REV 1611 # 6139 []_[].AND.AC 1637 # 2816 2939 3278 3301 7568 []_[].AND.NOT.# 1638 # 3623 4027 5826 6410 6778 6794 7061 7087 7199 7380 8510 8560 8735 []_[].AND.NOT.AC 1640 # 2826 7598 []_[].AND.NOT.WORK[] 1771 # []_[].AND.NOT.[] 1639 # 5587 7070 7073 7374 7384 7554 []_[].AND.Q 1641 # 4157 4829 4916 []_[].AND.WORK[] 1770 # 6138 8601 []_[].AND.[] 1642 # 4915 5514 5796 5798 6136 7397 8633 []_[].AND.# 1612 # 2424 2437 2459 3531 3540 3543 3545 3546 3547 3580 3585 3588 3608 3629 3642 3924 3926 3928 3930 3932 3934 3936 3938 3944 4042 4110 5067 5295 5299 5324 5357 5418 6171 6294 6470 6473 6512 6643 6677 6680 6913 6923 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7063 7065 7097 7100 7125 7132 7136 7147 7166 7187 7215 7221 7227 7232 7252 7275 7317 7370 7371 7632 7638 7829 7833 7838 7840 7842 7844 7846 7848 8231 8288 8444 8544 8554 8767 []_[].AND.# CLR LH 1613 # 3044 6585 6623 6663 6808 7033 7036 7104 7471 8302 8381 8441 8459 8567 []_[].AND.# CLR RH 1614 # 5920 5964 6164 []_[].EQV.AC 1643 # 2888 []_[].EQV.Q 1644 # 4135 4138 4160 4161 []_[].OR.# 1645 # 2153 2422 2460 3994 3999 4111 4464 4549 5296 5300 5325 5358 5419 5614 5615 5622 5825 6176 6263 6307 6316 6321 6331 6602 6606 6608 6669 6782 6786 6790 6798 6814 7189 7198 7303 7378 7456 7457 7458 7459 7460 7461 7462 7897 8227 8281 8285 8470 8473 8499 8506 8548 8552 8569 8571 8575 8631 8738 8742 8747 8754 8759 8832 []_[].OR.AC 1646 # 2868 3296 7596 []_[].OR.FLAGS 1647 # []_[].OR.WORK[] 1772 # 6950 6959 8386 8481 []_[].OR.[] 1648 # 2909 4097 4917 5922 6021 6251 6682 7064 7068 7075 7106 7151 7173 7175 7376 7382 7524 8556 8770 []_[].XOR.AC 1650 # 2858 3293 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 296 ; Cross Reference Listing []_[].XOR.[] 1651 # 5800 []_[].XOR.# 1649 # 4418 8294 .NOT.[] 1519 # 4335 7398 7473 2T 1857 # 4414 4427 5294 5564 6138 6208 6272 6560 6697 6742 7337 7694 3T 1858 # 2190 2415 2425 2580 3113 3287 3372 3406 3422 3512 3602 3686 3721 3729 3754 3758 3775 3780 3785 3822 3838 4063 4077 4180 4182 4201 4235 4372 4376 4426 4432 4433 4434 4451 4455 4476 4484 4565 4630 4647 4705 4720 4791 4809 4905 4949 4956 5036 5052 5056 5122 5124 5143 5167 5288 5322 5363 5394 5395 5398 5430 5433 5487 5489 5491 5493 5552 5553 5556 5558 5657 5658 5659 5703 5707 5709 5711 5719 5802 5808 5968 5986 5988 6036 6040 6103 6210 6224 6238 6270 6273 6358 6361 6393 6394 6422 6428 6431 6440 6465 6479 6506 6526 6527 6649 6656 6700 6759 6849 6856 6877 6891 6895 6898 6900 6936 6991 7121 7128 7141 7188 7197 7454 7479 7483 7491 7492 7493 7528 7532 7534 7701 8331 8339 8565 8582 8705 8716 8800 8830 4T 1859 # 3018 3489 3503 4089 4094 4101 4104 4106 4996 5001 5982 6012 6189 6194 6219 6260 6433 6481 6621 6744 6945 7954 8251 8324 8327 8411 8414 8693 8703 5T 1860 # 7255 7259 7263 7267 7271 7723 7740 7-BIT DPB 4886 # 4890 4891 4892 4893 4894 7-BIT LDB 4788 # 4796 4797 4798 4799 4800 (D) MACRO% AC 2126 # 2549 2550 2554 2555 2559 2560 2564 2565 2586 2602 2603 2607 2608 2612 2613 2617 2618 2622 2623 2627 2628 2632 2633 2637 2638 2644 2645 2649 2650 2654 2655 2659 2660 2664 2665 2669 2670 2674 2675 2679 2680 2769 2799 2800 2809 2810 2819 2820 2829 2830 2834 2835 2851 2852 2861 2862 2871 2872 2881 2882 2891 2892 2901 2902 2912 2913 2922 2923 2932 2933 2942 2943 4055 4056 4069 4070 4117 4118 4687 8223 AC DISP 2140 # 3518 7001 7002 7238 B 2128 # 2802 2812 2822 2832 2837 2854 2864 2874 2884 2894 2904 2915 2925 2935 2945 4058 4072 4120 DAC 2130 # 2768 4084 4085 4142 4143 4168 4309 4310 4314 4315 4386 5628 5689 DBL AC 2115 # 2777 DBL B 2131 # 4145 4312 4317 DBL FL-R 2121 # 5539 5540 5628 5689 DBL R 2114 # 2768 2769 4084 4085 4168 4386 FL-AC 2132 # 5265 5268 5269 5273 5276 5277 5310 5314 5315 5339 5343 5344 5389 5390 5424 5425 FL-BOTH 2134 # 5267 5271 5275 5279 5312 5317 5341 5346 FL-I 2120 # 5269 5277 5315 5344 FL-MEM 2133 # 5266 5270 5274 5278 5311 5316 5340 5345 FL-R 2118 # 5265 5268 5273 5276 5310 5314 5339 5343 5424 5425 FL-RW 2119 # 5266 5267 5270 5271 5274 5275 5278 5279 5311 5312 5316 5317 5340 5341 5345 5346 I 2106 # 2845 2957 3177 3178 3179 3180 3181 3182 3183 3184 3186 3187 3195 3196 3197 3198 3199 3200 3201 3202 3213 3214 3215 3216 3217 3218 3219 3220 3230 3231 3232 3233 3234 3235 3236 3237 3352 3353 3354 3355 3356 3357 3358 3359 3464 3465 3466 3467 3468 3469 3470 3471 3479 3480 3481 3482 3483 3484 3485 3493 3494 3495 3496 3497 3498 3499 3506 3507 3518 3520 3671 3673 3674 3801 3802 3803 3804 3857 3858 3859 3860 3861 3862 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 297 ; Cross Reference Listing 3863 3864 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3903 3904 3905 3906 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 5114 5390 5854 5855 5856 5857 5858 5859 5860 5862 5863 5864 5865 5867 5868 5869 5870 5872 5873 5874 5875 5876 5877 5878 5879 5913 7772 7773 7774 7776 7777 7779 7780 7782 7783 7784 7785 7786 7787 7788 7789 7791 7792 7793 7794 7795 7796 7797 7798 7800 7801 7802 7803 7804 7805 7806 7807 7809 7810 7811 7812 7813 7814 7815 7816 7818 7819 7820 7821 7822 7823 7824 7825 I-PF 2107 # 2550 2555 2560 2565 2603 2608 2613 2618 2623 2628 2633 2638 2645 2650 2655 2660 2665 2670 2675 2680 2799 2800 2810 2820 2830 2835 2852 2862 2872 2882 2891 2892 2902 2913 2923 2933 2942 2943 2958 3478 3492 3768 4056 4070 4118 4143 4310 4315 IOT 2122 # 7001 7002 7238 7560 7561 7562 7563 7571 7572 7573 7574 7585 7586 7587 7588 7853 7854 8223 IR 2113 # 3672 IW 2112 # 2801 2802 2893 2894 2944 2945 M 2127 # 2551 2556 2561 2566 2604 2609 2614 2619 2624 2629 2634 2639 2646 2651 2656 2661 2666 2671 2676 2681 2801 2811 2821 2831 2836 2846 2847 2853 2863 2873 2883 2893 2903 2914 2924 2934 2944 4057 4071 4119 4144 4311 4316 7238 R 2108 # 2586 2844 3188 3189 3190 3191 3192 3193 3204 3205 3206 3207 3208 3209 3210 3211 3222 3223 3224 3225 3226 3227 3228 3229 3239 3240 3241 3242 3243 3244 3245 3246 3361 3362 3363 3364 3365 3366 3367 3368 3378 3379 3380 3381 3382 3383 3384 3385 3649 4687 4688 4689 4690 4691 5389 R-PF 2109 # 2549 2554 2559 2564 2602 2607 2612 2617 2622 2627 2632 2637 2644 2649 2654 2659 2664 2669 2674 2679 2809 2819 2829 2834 2851 2861 2871 2881 2901 2912 2922 2932 4055 4069 4117 4142 4309 4314 ROUND 2135 # 5268 5269 5270 5271 5276 5277 5278 5279 5314 5315 5316 5317 5343 5344 5345 5346 5389 5425 RW 2111 # 2552 2557 2562 2567 2604 2605 2609 2610 2615 2620 2625 2630 2635 2640 2646 2647 2651 2652 2657 2662 2667 2672 2677 2682 2811 2812 2821 2822 2831 2832 2836 2837 2853 2854 2863 2864 2873 2874 2883 2884 2903 2904 2914 2915 2924 2925 2934 2935 3395 3396 3397 3398 3399 3400 3401 3402 3411 3412 3413 3414 3415 3416 3417 3418 4057 4058 4071 4072 4119 4120 4144 4145 4311 4312 4316 4317 S 2129 # 2552 2557 2562 2567 2605 2610 2615 2620 2625 2630 2635 2640 2647 2652 2657 2662 2667 2672 2677 2682 SH 2116 # 2954 2955 2956 SHC 2117 # 2959 2960 SJC- 3312 # 3352 3361 3378 3395 3411 3464 3478 3492 SJCA 3316 # 3356 3365 3382 3399 3415 3468 3482 3496 SJCE 3314 # 3354 3363 3380 3397 3413 3466 3480 3494 5855 SJCG 3319 # 3359 3368 3385 3402 3418 3471 3485 3499 5860 SJCGE 3317 # 3357 3366 3383 3400 3416 3469 3483 3497 3506 5858 SJCL 3313 # 3353 3362 3379 3396 3412 3465 3479 3493 3507 5854 SJCLE 3315 # 3355 3364 3381 3398 3414 3467 3481 3495 5856 SJCN 3318 # 3358 3367 3384 3401 3417 3470 3484 3498 5859 TC- 3168 # 3213 3214 3222 3223 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 298 ; Cross Reference Listing TCA 3170 # 3217 3218 3226 3227 TCE 3169 # 3215 3216 3224 3225 TCN 3171 # 3219 3220 3228 3229 TN- 3158 # TNA 3161 # 3181 3182 3190 3191 TNE 3159 # 3179 3180 3188 3189 7562 TNN 3162 # 3183 3184 3192 3193 7563 TO- 3172 # 3230 3231 3239 3240 TOA 3174 # 3234 3235 3243 3244 TOE 3173 # 3232 3233 3241 3242 TON 3175 # 3236 3237 3245 3246 TZ- 3164 # 3195 3196 3204 3205 TZA 3166 # 3199 3200 3208 3209 TZE 3165 # 3197 3198 3206 3207 TZN 3167 # 3201 3202 3210 3211 W 2110 # 2551 2556 2561 2566 2614 2619 2624 2629 2634 2639 2656 2661 2666 2671 2676 2681 2778 2846 2847 W TEST 2139 # 2586 4688 4690 WORD-TNE 3160 # 7560 WORD-TNN 3163 # 7561 (U) MEM 956 # 2163 2182 2186 2230 2230 2230 2231 2231 2233 2233 2234 2234 2234 2252 2253 2270 2278 2293 2293 2299 2299 2304 2305 2309 2310 2323 2332 2333 2336 2337 2341 2345 2354 2363 2365 2366 2367 2395 2406 2407 2407 2417 2418 2420 2421 2425 2432 2432 2496 2528 2534 2539 2542 2571 2577 2591 2592 2691 2693 2726 2732 2740 2742 2761 2763 2786 2787 2789 2790 2791 2793 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 3022 3022 3328 3328 3328 3340 3340 3407 3408 3455 3455 3455 3456 3456 3459 3459 3460 3460 3460 3527 3527 3528 3528 3529 3529 3534 3534 3538 3538 3541 3541 3550 3554 3554 3567 3568 3570 3571 3574 3589 3596 3596 3611 3615 3617 3618 3619 3632 3632 3634 3634 3635 3638 3643 3643 3679 3683 3684 3696 3702 3710 3711 3720 3721 3724 3732 3734 3737 3739 3741 3747 3753 3755 3761 3816 3817 3818 3830 3847 3848 3849 3959 3960 3960 3960 3969 3970 3970 3970 3971 3973 3979 3984 3984 3984 4003 4004 4005 4006 4018 4022 4031 4031 4031 4040 4041 4045 4047 4048 4049 4063 4077 4129 4135 4158 4160 4223 4223 4223 4698 4698 4698 4707 4707 4735 4741 4742 4754 4755 4758 4759 4762 4763 4766 4767 4769 4775 4896 4897 5099 5100 5127 5128 5135 5136 5138 5149 5150 5152 5154 5155 5157 5161 5164 5172 5173 5175 5449 5453 5499 5521 5917 5931 5933 5933 5934 5934 5936 5957 5958 6105 6105 6354 6355 6356 6381 6382 6426 6432 6439 6455 6455 6460 6460 6516 6516 6548 6550 6594 6594 6596 6599 6627 6636 6636 6751 6752 6898 6898 6899 6899 6900 6900 6901 6901 6903 6917 6973 6976 6977 6981 6984 6985 6988 7118 7119 7120 7223 7223 7255 7256 7259 7260 7263 7264 7267 7268 7271 7272 7311 7312 7314 7315 7339 7340 7343 7344 7344 7344 7345 7351 7352 7387 7387 7387 7405 7405 7406 7411 7474 7478 7489 7489 7489 7489 7490 7490 7505 7526 7531 7531 7531 7532 7539 7540 7620 7620 7622 7655 7655 7656 7658 7658 7658 7680 7681 7702 7702 7703 7748 7751 7753 7761 7761 7763 7765 7858 7859 7861 7866 7867 7876 7879 7879 7879 7881 7882 7882 7882 7893 7894 7900 7949 7965 7965 7965 7966 7967 7968 7968 7968 7969 7970 7973 7974 7975 7975 7975 7976 7977 7978 7978 7978 7979 7980 7981 7981 7981 7982 7983 7984 7984 7984 7985 7986 7987 7987 7987 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 299 ; Cross Reference Listing 7988 7989 7991 7994 8280 8328 8329 8329 8329 8336 8337 8337 8337 8341 8342 8343 8344 8389 8421 8422 8423 8426 8518 8557 8565 8581 8662 8663 8664 8666 8696 8697 8698 8711 8712 8713 8718 8779 8785 8833 8834 8834 8834 8835 8849 8857 8864 8866 8870 8870 8870 8873 8873 8873 (U) MICROCODE OPTION(INH@ 1236 # OPT 1240 # 7049 (U) MICROCODE OPTION(KIP@ 1260 # OPT 1262 # 7053 (U) MICROCODE OPTION(KLP` 1266 # OPT 1268 # 7054 (U) MICROCODE OPTION(NOC` 1242 # OPT 1246 # 7050 (U) MICROCODE OPTION(NON 1248 # OPT 1252 # 7051 (U) MICROCODE OPTION(UBA  1254 # OPT 1258 # 7052 (U) MICROCODE OPTIONS 1229 # (U) MICROCODE RELEASE(MA 1276 # UCR 1277 # 7041 (U) MICROCODE RELEASE(MI` 1279 # UCR 1280 # 7042 (U) MICROCODE VERSION 1273 # UCV 1274 # 7055 (D) MODE 1340 # (U) MULTI PREC 961 # 4405 4457 4472 4475 4482 4596 5550 5583 5703 5714 (U) MULTI SHIFT 963 # 2975 2987 3009 3014 4822 4827 4903 4911 (U) PHYSICAL 1130 # 3960 3970 3984 4004 4031 6977 6985 7417 7418 7421 7430 7431 7434 7475 7489 7522 7531 7614 7617 7653 7664 7670 7879 7882 7896 7965 7968 7975 7978 7981 7984 7987 8329 8337 8343 8423 8664 8697 8713 8834 8870 8873 (U) PI.CLR 1189 # 7367 (U) PI.CO1 1178 # (U) PI.CO2 1179 # (U) PI.DIR 1188 # 7373 (U) PI.IP1 1170 # 7550 (U) PI.IP2 1171 # (U) PI.IP3 1172 # (U) PI.IP4 1173 # (U) PI.IP5 1174 # (U) PI.IP6 1175 # (U) PI.IP7 1176 # (U) PI.MBZ 1187 # 7369 (U) PI.ON 1177 # 7378 7380 (U) PI.REQ 1190 # 7375 (U) PI.SC1 1195 # (U) PI.SC2 1196 # (U) PI.SC3 1197 # (U) PI.SC4 1198 # (U) PI.SC5 1199 # (U) PI.SC6 1200 # (U) PI.SC7 1201 # (U) PI.TCF 1192 # 7383 (U) PI.TCN 1191 # 7381 (U) PI.TSF 1193 # 7379 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 300 ; Cross Reference Listing (U) PI.TSN 1194 # 7377 (U) PI.ZER 1169 # (U) PXCT 1134 # BIS-DST-EA 1140 # 6892 6894 6900 6901 6903 BIS-SRC-EA 1138 # CURRENT 1135 # 2230 2231 2233 2234 2253 2293 2299 2407 2432 3022 3328 3340 3455 3456 3459 3460 3527 3528 3552 3554 3576 3591 3596 3711 4223 4698 4707 7387 7658 7699 7894 D1 1137 # 2323 2365 2417 2420 2788 2792 3733 3738 5129 5137 5151 5156 D2 1141 # 3685 3722 3754 4756 4760 5101 5174 6898 6899 E1 1136 # 2332 2337 2343 3572 3658 E2 1139 # 4705 4724 4764 4768 4772 5924 5933 5934 5936 6855 (U) RAMADR 673 # AC# 674 # 2359 2372 2386 2523 2590 2691 2693 2724 2730 2816 2826 2858 2868 2888 2898 2908 2939 2967 2970 2984 2990 3002 3005 3018 3080 3092 3113 3278 3293 3296 3301 3302 3372 3391 3431 3434 3437 3440 3443 3446 3449 3452 3475 3489 3503 3511 3681 3712 3714 3719 3752 3774 3777 3782 3810 3832 3845 4062 4076 4092 4103 4106 4123 4124 4150 4152 4199 4214 4321 4322 4331 4412 4414 4456 4458 4629 4630 4634 4712 4718 4722 4998 5070 5109 5118 5119 5183 5288 5321 5351 5353 5416 5417 5445 5451 5553 5557 5559 5563 5655 5706 5807 5808 5963 6054 6091 6093 6101 6127 6163 6265 6297 6299 6311 6320 6390 6457 6611 6684 6936 6960 7568 7579 7582 7596 7598 7767 7869 8237 AC*# 675 # 2175 2176 2183 2373 2385 2491 2774 2783 3024 3045 3089 3119 4089 4101 4180 4182 4184 4192 4194 4201 4203 4215 4216 4217 4218 4219 4220 4332 4416 4438 4442 4445 4459 4460 4462 4465 4484 4486 4488 4489 4615 4616 4619 4620 4621 4624 4625 4626 4632 4633 5552 5643 5696 5698 5704 5763 5771 5809 5816 5960 5968 5978 5981 6011 6014 6027 6034 6041 6051 6089 6099 6119 6134 6151 6166 6168 6194 6197 6199 6206 6207 6208 6210 6216 6218 6221 6227 6229 6257 6259 6260 6264 6271 6272 6273 6277 6278 6285 6287 6292 6298 6314 6325 6337 6346 6352 6363 6366 6368 6372 6385 6391 6392 6515 6546 6551 6556 6593 6595 6699 6700 6812 6819 6826 6845 6847 6854 6874 6895 6931 6933 6939 6941 6945 6948 6953 RAM 678 # 2185 2187 6428 6433 6438 6440 VMA 677 # 2163 2271 2341 2355 2364 2368 2396 2407 2413 2426 2497 2529 2535 2540 2543 2593 2789 3408 3551 3575 3590 3611 3615 3619 3680 3697 3703 3725 3742 3748 3761 3819 3850 3972 3974 3980 4007 4019 4023 4046 4742 4770 4776 4897 5139 5162 5165 5917 5936 6356 6550 6596 6599 6627 6903 6918 6988 7121 7256 7260 7264 7268 7272 7313 7343 7345 7352 7406 7474 7479 7490 7527 7532 7623 7656 7703 7748 7751 7753 7763 7765 7862 7876 7881 7901 7949 7966 7967 7969 7970 7973 7974 7976 7977 7979 7980 7982 7983 7985 7986 7988 7989 7991 8256 8280 8345 8427 8667 8719 8779 8785 8836 8850 8864 8866 XR# 676 # 2281 2291 2303 2318 2331 2347 3556 3558 3566 4749 4752 4754 4762 5928 5930 5933 6898 6900 6904 7692 7693 7701 # 679 # 2162 2170 2172 2173 2178 2179 3665 4695 4954 4967 4972 4977 4981 4982 4987 4993 5019 5032 5040 5045 5051 5181 5927 5940 5943 5973 5990 5997 6001 6018 6030 6035 6046 6050 6061 6062 6063 6065 6066 6067 6068 6078 6085 6109 6125 6132 6137 6138 6145 6148 6161 6179 6183 6186 6190 6300 6302 6343 6353 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 301 ; Cross Reference Listing 6358 6359 6361 6364 6377 6379 6383 6386 6387 6408 6558 6559 6582 6584 6620 6625 6635 6697 6703 6730 6734 6737 6742 6743 6750 6817 6824 6828 6830 6919 6935 6944 6950 6958 6959 6962 6970 7060 7082 7094 7186 7191 7243 7245 7247 7249 7251 7257 7261 7265 7269 7273 7281 7288 7290 7295 7299 7301 7320 7323 7333 7334 7337 7353 7354 7358 7438 7439 7687 7690 7695 7707 7709 7721 7727 7729 7874 7946 7948 7953 7957 7961 7971 7972 7990 7992 7993 7995 8233 8234 8243 8244 8246 8247 8254 8264 8266 8268 8270 8274 8275 8323 8326 8353 8355 8386 8410 8413 8416 8418 8432 8439 8481 8491 8493 8538 8578 8579 8580 8586 8597 8601 8764 8775 8781 8790 8794 8806 (D) READ 1351 # 2549 2550 2552 2554 2555 2557 2559 2560 2562 2564 2565 2567 2586 2602 2603 2604 2605 2607 2608 2609 2610 2612 2613 2615 2617 2618 2620 2622 2623 2625 2627 2628 2630 2632 2633 2635 2637 2638 2640 2644 2645 2646 2647 2649 2650 2651 2652 2654 2655 2657 2659 2660 2662 2664 2665 2667 2669 2670 2672 2674 2675 2677 2679 2680 2682 2768 2769 2799 2800 2809 2810 2811 2812 2819 2820 2821 2822 2829 2830 2831 2832 2834 2835 2836 2837 2844 2851 2852 2853 2854 2861 2862 2863 2864 2871 2872 2873 2874 2881 2882 2883 2884 2891 2892 2901 2902 2903 2904 2912 2913 2914 2915 2922 2923 2924 2925 2932 2933 2934 2935 2942 2943 2954 2955 2956 2958 2959 2960 3188 3189 3190 3191 3192 3193 3204 3205 3206 3207 3208 3209 3210 3211 3222 3223 3224 3225 3226 3227 3228 3229 3239 3240 3241 3242 3243 3244 3245 3246 3361 3362 3363 3364 3365 3366 3367 3368 3378 3379 3380 3381 3382 3383 3384 3385 3395 3396 3397 3398 3399 3400 3401 3402 3411 3412 3413 3414 3415 3416 3417 3418 3478 3492 3649 3672 3768 4055 4056 4057 4058 4069 4070 4071 4072 4084 4085 4117 4118 4119 4120 4142 4143 4144 4145 4168 4309 4310 4311 4312 4314 4315 4316 4317 4386 4687 4688 4689 4690 4691 5265 5266 5267 5268 5269 5270 5271 5273 5274 5275 5276 5277 5278 5279 5310 5311 5312 5314 5315 5316 5317 5339 5340 5341 5343 5344 5345 5346 5389 5424 5425 5539 5540 5628 5689 5913 (U) READ CYCLE 1122 # 2230 2231 2233 2234 2253 2293 2299 2304 2310 2333 2337 2366 2407 2418 2421 2432 3022 3328 3340 3455 3456 3459 3460 3527 3528 3529 3534 3538 3541 3554 3568 3571 3596 3618 3638 3711 3721 3755 3848 4005 4049 4223 4698 4707 4755 4759 4763 4767 5100 5175 5933 5934 5958 6105 6355 6382 6455 6460 6516 6636 6752 6898 6899 6900 6901 6976 6984 7119 7255 7259 7263 7267 7271 7311 7315 7351 7387 7475 7489 7522 7531 7540 7614 7617 7658 7681 7702 7859 7894 7896 8329 8337 8342 8422 8561 8663 8698 8712 8870 (D) ROUND 1339 # 5268 5269 5270 5271 5276 5277 5278 5279 5314 5315 5316 5317 5343 5344 5345 5346 5389 5425 (U) RSRC 607 # AB 609 # 3665 7687 AQ 608 # D0 615 # 2761 6160 6275 7475 7522 7614 7617 7653 7664 7670 7743 7896 8260 8262 8276 DA 613 # 2157 2160 2193 2204 2240 2244 2247 2250 2259 2262 2265 2268 2519 3044 3582 3948 3988 4036 4400 4411 4805 5885 5887 5889 5891 5893 5895 5897 5899 5901 6585 6597 6623 6663 6808 7033 7036 7104 7284 7327 7328 7329 7463 7464 7465 7466 7467 7468 7469 7471 7504 7536 8302 8381 8441 8459 8567 8789 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 302 ; Cross Reference Listing DQ 614 # 0A 612 # 2322 2763 3691 3808 3814 4020 4221 5556 5558 5658 5659 5709 5711 5931 6969 7506 8848 0B 611 # 2740 2742 0Q 610 # 3630 3644 3965 3991 5920 5964 6164 7494 8844 (U) S# 997 # 2177 2380 2399 2399 2414 2414 2430 2968 2971 2975 2985 2987 3003 3006 3009 3014 3026 3041 3043 3070 3087 3096 3099 3142 4124 4152 4189 4209 4229 4342 4439 4447 4709 4791 4814 4819 4821 4823 4826 4889 4890 4891 4892 4893 4894 4902 4906 4908 4910 4943 4959 4970 4983 4999 5044 5059 5292 5294 5326 5331 5333 5359 5360 5373 5374 5396 5400 5402 5403 5407 5415 5430 5433 5435 5486 5490 5492 5495 5498 5506 5508 5509 5510 5511 5529 5534 5564 5575 5590 5592 5633 5644 5648 5651 5661 5667 5673 5684 5722 5723 5733 5747 5754 5757 5769 5786 5791 5793 5814 5839 5841 5847 5985 5986 5988 6154 6299 6467 6469 6476 6525 6530 6532 6655 6657 6659 6660 6666 6676 6859 7160 7181 7212 7222 7228 7442 7630 7662 7716 7732 8297 8348 8396 8536 (U) SCAD 974 # A 982 # 2177 3026 4124 4152 4189 4209 4229 4342 4439 4447 4705 4719 4796 4797 4798 4799 4800 4905 4943 4959 4970 4983 4999 5044 5059 5326 5373 5396 5400 5402 5403 5407 5633 5644 5648 5661 5667 5722 5723 6299 6467 6469 6476 6525 6655 6656 6666 6856 6877 6896 7160 7181 7212 7222 7228 7442 7630 7662 7716 7732 8297 8348 8396 8536 A*2 975 # 6648 A+B 979 # 2380 2399 2399 2414 2414 2971 2975 2985 2987 3006 3009 3014 3041 3043 3087 3096 4821 4826 4890 4891 4892 4893 4894 4902 4910 5292 5294 5322 5331 5333 5374 5415 5417 5429 5433 5486 5490 5492 5495 5498 5506 5508 5509 5510 5511 5529 5534 5564 5575 5590 5592 5656 5673 5684 5747 5754 5757 5769 5786 5791 5793 5814 5839 5841 5847 5985 5986 5988 6526 6530 6658 6659 6660 6676 6964 A-1 981 # 2187 2991 2993 3069 3071 3073 3077 3103 3110 3141 3143 3145 3149 4255 4267 4273 4281 4291 4299 4554 4557 4597 4946 4965 5065 5302 5304 5410 5434 5437 5440 5444 5608 5611 5618 5636 6328 6472 6478 6673 7163 7183 7214 7231 7422 7435 7637 7668 7723 7736 8300 8362 8365 8399 8542 A-B 978 # 2968 3003 3070 3099 3142 4697 4702 4716 4737 4791 4814 4819 4823 4889 4908 5353 5359 5360 5435 5707 5733 6038 6048 6848 6851 6891 6893 A-B-1 977 # 5288 5293 5554 5574 A.AND.B 980 # 4709 4906 6154 6532 6657 6859 A.OR.B 976 # 2430 5651 (U) SCADA 983 # BYTE1 987 # 4697 4702 4705 4716 4796 4905 6038 6526 6656 6848 6856 6891 6896 6964 BYTE2 988 # 4797 BYTE3 989 # 4798 BYTE4 990 # 4799 BYTE5 991 # 4720 4800 6649 6878 PTR44 986 # 4737 6048 6851 6893 S# 985 # 2177 2380 2399 2399 2414 2414 2430 2968 2971 2975 2985 2987 3003 3006 3009 3014 3026 3041 3043 3070 3087 3096 3099 3142 4124 4152 4189 4209 4229 4342 4439 4447 4709 4791 4814 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 303 ; Cross Reference Listing 4819 4821 4823 4826 4889 4890 4891 4892 4893 4894 4902 4906 4908 4910 4943 4959 4970 4983 4999 5044 5059 5292 5294 5326 5331 5333 5359 5360 5373 5374 5396 5400 5402 5403 5407 5415 5429 5433 5435 5486 5490 5492 5495 5498 5506 5508 5509 5510 5511 5529 5534 5564 5575 5590 5592 5633 5644 5648 5651 5661 5667 5673 5684 5722 5723 5733 5747 5754 5757 5769 5786 5791 5793 5814 5839 5841 5847 5985 5986 5988 6154 6299 6467 6469 6476 6525 6530 6532 6655 6657 6659 6660 6666 6676 6859 7160 7181 7212 7222 7228 7442 7630 7662 7716 7732 8297 8348 8396 8536 SC 984 # 2187 2991 2993 3069 3071 3073 3077 3103 3110 3141 3143 3145 3149 4255 4267 4273 4281 4291 4299 4554 4557 4597 4946 4965 5065 5288 5293 5302 5304 5322 5353 5410 5417 5434 5437 5440 5444 5554 5574 5608 5611 5618 5636 5656 5707 6328 6472 6478 6658 6673 7163 7183 7214 7231 7422 7435 7637 7668 7723 7736 8300 8362 8365 8399 8542 (U) SCADB 992 # EXP 994 # 2399 2399 2414 2414 5288 5292 5294 5322 5353 5417 5554 5564 5575 5656 5707 FE 993 # 2430 2968 2971 2975 2985 2987 3003 3006 3009 3014 3041 3043 3096 3099 4709 4791 4814 4819 4821 4826 4890 4891 4892 4893 4894 4902 4906 4908 4910 5293 5331 5333 5359 5360 5374 5430 5433 5435 5486 5490 5492 5495 5498 5506 5508 5509 5510 5511 5529 5534 5574 5590 5592 5651 5673 5684 5733 5747 5754 5757 5769 5786 5791 5793 5814 5839 5841 5847 5986 5988 6154 6526 6530 6532 6657 6658 6659 6660 6676 6859 SHIFT 995 # 2380 3070 3087 3142 5415 SIZE 996 # 4697 4702 4716 4737 4823 4889 5985 6038 6048 6848 6851 6891 6893 6964 (U) SETFOV 1078 # 5355 5367 5720 (U) SETFPD 1084 # 4237 4751 6394 (U) SETNDV 1079 # 4344 4379 4410 4496 5003 5355 5367 5720 (U) SETOV 1076 # 4137 4138 4162 4224 4344 4379 4410 4496 5003 5355 5367 5432 5720 (U) SHSTYLE 821 # ASHC 826 # 2993 3102 3105 3109 3112 4273 4281 4291 4299 4405 4409 4478 4482 4498 5304 5407 5409 5439 5583 5585 5589 5591 5607 5611 5618 5621 5623 5635 5676 5680 5715 5729 5747 5753 5756 5769 5786 5790 5792 5814 5839 DIV 828 # 4554 4557 4558 4601 4605 5486 5498 5506 5510 5603 5605 5606 LSHC 827 # 3073 3077 4586 4589 NORM 822 # 2427 2987 4232 4266 4439 4595 5637 5727 ONES 824 # 4825 4828 4901 4904 5988 ROT 825 # 3009 3014 ROTC 829 # 3145 3149 ZERO 823 # (U) SKIP 899 # AC0 907 # 2486 3390 4694 ADEQ0 919 # 3019 3334 3346 3437 3449 4127 4132 4334 4336 4340 4354 4399 4428 4458 4539 4617 4622 4627 4643 4650 4968 4997 5351 5377 5379 5452 5494 5518 5674 5725 5767 5812 6142 6195 6271 6274 6563 6600 6621 6744 7331 8324 8327 8411 8414 ADLEQ0 903 # 2190 3992 3997 5394 5399 5513 5678 5681 5749 5752 5755 5758 5818 5918 5961 6100 6102 6184 6204 6388 6404 6458 6493 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 304 ; Cross Reference Listing 6496 6528 6992 7128 7142 7188 7197 7492 7493 7684 7686 7700 8284 8306 8350 8357 8360 8375 8380 8429 8448 8452 8458 8472 8476 8478 8498 8551 8570 8572 8599 8603 8637 8640 8642 8645 8648 8669 8679 8733 8751 8792 8841 ADREQ0 904 # 3088 3594 3609 5125 6329 6402 6757 7034 7040 7067 7069 7072 7074 7076 7367 7369 7373 7375 7377 7379 7381 7383 7480 7533 7553 7625 7652 8235 8503 8531 8720 8737 8740 8745 CRY0 902 # 3687 3730 3759 5363 5487 5489 5491 5493 CRY1 915 # 4090 4102 5803 6219 6225 6238 6429 6440 CRY2 910 # 5776 5836 DP0 911 # 2400 2415 2574 2752 2759 3042 3114 3331 3343 3434 3446 3776 3779 3784 3955 4109 4134 4156 4159 4214 4222 4323 4359 4361 4366 4371 4375 4397 4414 4426 4433 4448 4467 4485 4537 4544 4559 5000 5144 5168 5290 5294 5323 5353 5361 5395 5417 5448 5555 5657 5704 5708 5719 5732 5969 5982 5999 6012 6019 6037 6079 6081 6103 6120 6123 6129 6169 6261 6266 6303 6312 6345 6362 6434 6484 6510 6701 6731 6773 6827 6946 7122 7286 8311 8409 8636 8690 DP18 912 # 2379 2738 2745 5942 6189 6393 6482 6805 6806 7519 8693 8703 8726 EXECUTE 921 # 7888 FPD 906 # 4176 4697 4702 4716 6293 INT 908 # 5148 6039 8248 8443 8665 8773 8804 8855 IOLGL 900 # 2436 3539 3542 IOT 913 # JFCL 914 # 3601 KERNEL 905 # 3532 3536 3537 3544 3653 6971 LE 909 # 3337 3349 3440 3452 4393 5027 5371 5695 6342 7297 7954 LLE 901 # 7693 SC 920 # 2187 2991 2993 3069 3071 3073 3077 3094 3103 3110 3141 3143 3145 3149 4255 4267 4273 4281 4291 4299 4554 4557 4597 4946 4965 5065 5302 5304 5410 5434 5437 5440 5444 5557 5559 5608 5611 5618 5636 6328 6472 6478 6664 6673 7163 7183 7214 7231 7422 7435 7637 7668 7736 8300 8362 8365 8399 8542 TRAP CYCLE 917 # 8791 TXXX 916 # 3287 -1 MS 924 # 5140 6034 7335 8438 -CONTINUE 923 # 7890 -IO BUSY 922 # 7718 7724 7733 7741 (U) SPEC 785 # 2571 2577 2691 2693 2726 2732 2740 2742 2761 2763 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 4129 4135 4158 4160 8557 8857 APR EN 799 # 2168 7081 7190 APR FLAGS 797 # 7086 7090 7305 ASHOV 806 # 2993 3109 3112 CLR IO BUSY 789 # 7611 7649 CLR IO LATCH 788 # 7696 7704 7708 7711 7720 7726 7735 7740 CLRCLK 787 # 7282 7336 8492 8776 CLRCSH 798 # 7417 7418 7421 EXPTST 807 # 5495 5511 5841 FLAGS 808 # 2219 2220 2580 3406 3422 3489 3503 3559 3560 3563 3564 3600 3621 3622 3692 3704 3760 3790 3794 3809 3815 4009 4010 4011 4063 4077 4094 4104 4107 4137 4138 4162 4212 4224 4234 4237 4344 4379 4410 4496 4645 4647 4712 4729 4751 5003 5355 5367 5432 5720 6394 6395 6993 7495 7510 8795 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 305 ; Cross Reference Listing INHCRY18 803 # 3512 3682 3729 3758 3778 3783 5035 5110 LDACBLK 809 # 2165 7154 7177 LDINST 810 # 2272 3657 6989 7902 LDPAGE 790 # 7412 8573 LDPI 805 # 3610 7398 7473 7955 LDPXCT 792 # 3662 LOADIR 804 # 5923 LOADXR 795 # 2343 3552 3576 3591 4705 4724 4772 5924 5936 6855 6892 6894 6903 7699 MEMCLR 800 # 2163 3611 7474 7876 7949 8280 8779 8785 NICOND 791 # 2230 2231 2233 2234 2294 2300 2524 3045 3091 3119 3328 3340 3431 3455 3456 3459 3460 3527 3528 3554 3596 3713 3789 3796 4223 4487 4490 4698 5445 5451 5810 7387 7658 8237 PREV 794 # 7860 7868 PXCT OFF 802 # 2242 2245 2248 2260 2263 2266 2280 SWEEP 801 # 7430 7431 7434 WAIT 793 # 2412 # 786 # 7884 7887 7950 (U) STATE 1000 # BLT 1002 # 5111 COMP-DST 1009 # 6128 CVTDB 1008 # 6175 DST 1005 # 6090 DSTF 1007 # 6028 EDIT-DST 1011 # 6147 6357 6384 6603 6629 8812 8816 EDIT-S+D 1012 # 6569 EDIT-SRC 1010 # 6121 6508 6565 8810 8818 8820 8824 MAP 1003 # 8236 SIMPLE 1001 # SRC 1004 # 5977 6006 6076 8814 SRC+DST 1006 # 6003 6082 (U) SWITCH% FULL 394 1297 1299 2174 2194 2199 2203 4171 4239 4242 4389 4499 4502 4570 4635 4921 5072 5076 7184 7192 INHCST 397 1237 1239 1241 8039 8041 8388 8391 8392 8395 8517 8520 8521 8524 8595 8604 8605 8621 KIPAGE 406 416 418 1261 1263 1265 3952 3962 4014 4025 7194 7201 7207 7209 8305 8309 8314 8317 8685 8731 8840 8843 8847 8852 KLPAGE 409 413 415 1267 1269 1271 3953 3957 3963 3977 7195 7200 7203 7205 8304 8313 8319 8526 8589 8683 8839 8845 8862 8867 NOCST 400 421 423 1243 1245 1247 8383 8456 8463 8466 8480 8483 8484 8488 8514 8533 8590 8622 NONSTD 425 1249 1251 1253 SIM 391 2212 2217 2224 UBABLT 403 412 419 1255 1257 1259 5186 5260 7832 7834 7836 (U) T 937 # 2T 940 # 4414 4427 5294 5564 6138 6208 6272 6560 6697 6742 7337 7694 3T 941 # 2190 2415 2425 2580 3113 3287 3372 3406 3422 3512 3602 3686 3721 3729 3754 3758 3775 3780 3785 3822 3838 4063 4077 4180 4182 4201 4235 4372 4376 4426 4432 4433 4434 4451 4455 4476 4484 4565 4630 4647 4705 4720 4791 4809 4905 4949 4956 5036 5052 5056 5122 5124 5143 5167 5288 5322 5363 5394 5395 5398 5430 5433 5487 5489 5491 5493 5552 5553 5556 5558 5657 5658 5659 5703 5707 5709 5711 5719 5802 5808 5968 5986 5988 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 306 ; Cross Reference Listing 6036 6040 6103 6210 6224 6238 6270 6273 6358 6361 6393 6394 6422 6428 6431 6440 6465 6479 6506 6526 6527 6649 6656 6700 6759 6849 6856 6877 6891 6895 6898 6900 6936 6991 7121 7128 7141 7188 7197 7454 7479 7483 7491 7492 7493 7528 7532 7534 7701 8331 8339 8565 8582 8705 8716 8800 8830 4T 942 # 3018 3489 3503 4089 4094 4101 4104 4106 4996 5001 5982 6012 6189 6194 6219 6260 6433 6481 6621 6744 6945 7954 8251 8324 8327 8411 8414 8693 8703 5T 943 # 7255 7259 7263 7267 7271 7723 7740 (D) TEST 1352 # 2551 2551 2552 2552 2556 2556 2557 2557 2561 2561 2562 2562 2566 2566 2567 2567 2586 2604 2604 2605 2605 2609 2609 2610 2610 2614 2614 2615 2615 2619 2619 2620 2620 2624 2624 2625 2625 2629 2629 2630 2630 2634 2634 2635 2635 2639 2639 2640 2640 2646 2646 2647 2647 2651 2651 2652 2652 2656 2656 2657 2657 2661 2661 2662 2662 2666 2666 2667 2667 2671 2671 2672 2672 2676 2676 2677 2677 2681 2681 2682 2682 2778 2801 2801 2802 2802 2811 2811 2812 2812 2821 2821 2822 2822 2831 2831 2832 2832 2836 2836 2837 2837 2846 2846 2847 2847 2853 2853 2854 2854 2863 2863 2864 2864 2873 2873 2874 2874 2883 2883 2884 2884 2893 2893 2894 2894 2903 2903 2904 2904 2914 2914 2915 2915 2924 2924 2925 2925 2934 2934 2935 2935 2944 2944 2945 2945 3395 3396 3397 3398 3399 3400 3401 3402 3411 3412 3413 3414 3415 3416 3417 3418 4057 4057 4058 4058 4071 4071 4072 4072 4119 4119 4120 4120 4144 4144 4145 4145 4311 4311 4312 4312 4316 4316 4317 4317 4688 4690 5266 5266 5267 5267 5270 5270 5271 5271 5274 5274 5275 5275 5278 5278 5279 5279 5311 5311 5312 5312 5316 5316 5317 5317 5340 5340 5341 5341 5345 5345 5346 5346 7238 (U) TRAP1 1093 # 4137 4138 4162 4224 4344 4379 4410 4496 5003 5355 5367 5432 5720 (U) TRAP2 1092 # 3704 3760 3790 3794 (U) VECTOR CYCLE 1164 # 7523 (D) VMA 1354 # 2550 2555 2560 2565 2603 2608 2613 2618 2623 2628 2633 2638 2645 2650 2655 2660 2665 2670 2675 2680 2799 2800 2810 2820 2830 2835 2852 2862 2872 2882 2891 2892 2902 2913 2923 2933 2942 2943 2954 2955 2956 2958 2959 2960 3478 3492 3518 3768 4056 4070 4118 4143 4310 4315 (U) WAIT 1153 # 2230 2230 2231 2231 2233 2233 2234 2234 2253 2253 2270 2293 2293 2299 2299 2304 2310 2323 2333 2337 2341 2354 2363 2366 2367 2395 2406 2407 2407 2418 2421 2425 2432 2432 2496 2528 2534 2539 2542 2591 2591 2592 2787 2787 2789 2793 2793 3022 3022 3328 3328 3340 3340 3407 3407 3408 3455 3455 3456 3456 3459 3459 3460 3460 3527 3527 3528 3528 3529 3534 3538 3541 3550 3554 3554 3568 3571 3574 3589 3596 3596 3615 3618 3619 3632 3632 3635 3635 3638 3643 3643 3679 3684 3684 3696 3702 3711 3711 3721 3724 3734 3734 3739 3739 3741 3747 3755 3761 3817 3817 3818 3830 3830 3848 3849 3960 3970 3971 3973 3979 3984 3984 4005 4006 4018 4022 4031 4031 4041 4041 4045 4049 4223 4223 4698 4698 4707 4707 4735 4735 4741 4741 4742 4755 4759 4763 4767 4769 4775 4896 4896 4897 5100 5128 5128 5136 5136 5138 5152 5152 5157 5157 5161 5164 5175 5917 5933 5934 5936 5958 6105 6355 6356 6382 6455 6460 6516 6548 6548 6550 6594 6594 6596 6599 6627 6636 6752 6898 6899 6900 6901 6903 6917 6973 6976 6981 6984 6988 7119 7120 7223 7223 7255 7255 7256 7259 7259 7260 7263 7263 7264 7267 7267 7268 7271 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 307 ; Cross Reference Listing 7271 7272 7311 7312 7315 7340 7340 7343 7344 7344 7345 7351 7352 7387 7387 7405 7405 7406 7478 7489 7490 7505 7505 7526 7531 7532 7540 7620 7622 7655 7656 7658 7658 7681 7702 7703 7748 7751 7753 7761 7763 7765 7859 7861 7867 7867 7879 7881 7882 7882 7894 7894 7900 7965 7966 7967 7968 7968 7969 7970 7973 7974 7975 7975 7976 7977 7978 7978 7979 7980 7981 7981 7982 7983 7984 7984 7985 7986 7987 7987 7988 7989 7991 8329 8337 8342 8344 8389 8422 8426 8518 8583 8663 8666 8698 8712 8718 8834 8835 8849 8864 8866 8870 8873 8873 (U) WORK 1016 # AC0 1057 # AC1 1058 # AC2 1059 # AC3 1060 # ADJBPW 1035 # 5019 5040 ADJP 1030 # 4954 4981 ADJPTR 1032 # 4695 4972 5034 ADJQ1 1033 # 4977 4995 ADJR2 1034 # 4987 5054 ADJS 1031 # 4967 4982 5045 APR 1037 # 2170 7060 7082 7094 7186 7191 8234 BADW0 1017 # 8274 BADW1 1018 # 8275 BDH 1047 # 6302 6377 6386 6408 BDL 1048 # 6300 6343 6383 6387 CBR 1027 # 7245 7261 8597 CMS 1044 # 6125 6137 6138 6148 CSTM 1028 # 7249 7269 8601 DDIV SGN 1061 # DECHI 1066 # 2179 2181 6431 DECLO 1065 # 2178 2180 6422 DIV 1020 # DVSOR H 1062 # DVSOR L 1063 # E0 1039 # 5927 6353 6625 6635 E1 1040 # 5940 5943 6379 6558 6559 6734 6737 6742 6750 FILL 1043 # 6109 6132 6145 6620 6697 6703 6817 6919 FSIG 1045 # 6582 6584 HSBADR 1036 # 2162 7251 7273 7948 7953 MSK 1042 # 5990 6161 6743 MUL 1019 # PERIOD 1053 # 7301 7353 7358 PTA.E 1069 # 7439 8323 8410 8416 PTA.U 1070 # 7438 8326 8413 8418 PUR 1029 # 7247 7265 8386 8481 SBR 1026 # 7243 7257 8353 8355 8432 SLEN 1041 # 5973 5997 6001 6018 6030 6046 6050 6078 6085 6179 6183 6186 6190 6358 6359 6361 6364 6730 6824 6828 6830 6944 6958 6962 SV.ARX 1023 # 6062 6067 7874 7946 7957 7972 7995 8247 8578 8806 SV.AR 1022 # 6035 6065 7971 7992 8243 8586 SV.AR1 1072 # 8439 8493 SV.BRX 1025 # 5181 6063 6068 6935 6950 6959 8244 8580 SV.BR 1024 # 6061 6066 8254 8264 8266 8268 8270 8579 8764 SV.VMA 1021 # 7721 7727 7729 7961 7990 7993 8233 8246 8538 8781 8790 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 308 ; Cross Reference Listing TIME0 1051 # 2172 7290 7323 7333 TIME1 1052 # 2173 7281 7288 7320 7334 7337 8491 8775 TRAPPC 1071 # 6970 8794 TTG 1054 # 7295 7299 7354 YSAVE 1068 # 3665 7687 7690 7695 7707 7709 (D) WRITE 1355 # (U) WRITE CYCLE 1124 # 2571 2577 2591 2691 2693 2726 2732 2740 2742 2761 2763 2787 2793 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 3407 3632 3635 3643 3684 3734 3739 3817 3830 3960 3970 3984 4031 4041 4063 4077 4129 4135 4158 4160 4735 4741 4896 5128 5136 5152 5157 5449 5453 5499 5521 6548 6594 7223 7340 7344 7405 7505 7653 7664 7670 7867 7879 7882 7965 7968 7975 7978 7981 7984 7987 8389 8477 8498 8518 8557 8562 8752 8834 8857 8873 (U) WRITE TEST 1123 # 2571 2577 2591 2691 2693 2726 2732 2740 2742 2761 2763 2787 2793 2806 2816 2826 2858 2868 2888 2898 2909 2919 2949 3407 3632 3635 3643 3684 3734 3739 3817 3830 3960 3970 3984 4031 4041 4063 4077 4129 4135 4158 4160 4735 4741 4896 5128 5136 5152 5157 5449 5453 5499 5521 6548 6594 7223 7255 7259 7263 7267 7271 7340 7344 7405 7475 7489 7505 7522 7531 7614 7617 7653 7664 7670 7867 7879 7882 7896 7965 7968 7975 7978 7981 7984 7987 8284 8329 8337 8477 8557 8563 8834 8857 8870 8873 (U) WRU CYCLE 1160 # 7476 (U) # 971 # 2151 2153 2155 2157 2160 2190 2204 2240 2244 2247 2259 2262 2265 2422 2424 2437 2459 2460 2747 2749 2754 2756 2773 3044 3115 3117 3531 3540 3543 3545 3546 3547 3580 3585 3588 3594 3608 3609 3629 3642 3728 3757 3820 3837 3924 3926 3928 3930 3932 3934 3936 3938 3945 3948 3988 3993 3995 3998 4000 4028 4036 4043 4110 4111 4363 4400 4401 4411 4419 4464 4517 4543 4550 4641 4806 4950 4952 4957 4975 4979 4985 4989 5018 5023 5057 5061 5068 5121 5295 5296 5299 5300 5324 5325 5329 5357 5358 5394 5398 5418 5419 5556 5558 5638 5658 5659 5678 5681 5709 5711 5885 5887 5889 5891 5893 5895 5897 5899 5901 5918 5921 5945 5961 5965 6100 6102 6160 6165 6172 6177 6184 6188 6204 6246 6262 6263 6269 6275 6295 6308 6310 6317 6322 6329 6332 6388 6402 6404 6411 6436 6442 6458 6470 6473 6481 6493 6496 6513 6528 6586 6597 6606 6608 6624 6643 6664 6669 6678 6681 6757 6779 6783 6787 6791 6795 6799 6809 6815 6913 6924 6991 6996 7005 7006 7007 7011 7012 7013 7014 7019 7020 7021 7024 7025 7026 7027 7028 7029 7030 7031 7033 7036 7047 7062 7063 7066 7067 7069 7072 7074 7076 7088 7098 7101 7105 7126 7133 7137 7141 7148 7167 7187 7188 7189 7197 7198 7199 7215 7221 7227 7232 7252 7275 7284 7303 7318 7370 7371 7414 7416 7427 7429 7456 7457 7458 7459 7460 7461 7462 7463 7464 7465 7466 7467 7468 7469 7472 7483 7492 7493 7508 7528 7535 7625 7633 7639 7652 7684 7686 7700 7743 7829 7833 7838 7840 7842 7844 7846 7848 7884 7887 7898 7950 8228 8232 8235 8260 8262 8276 8286 8289 8295 8303 8307 8332 8340 8351 8358 8375 8382 8430 8442 8445 8453 8460 8471 8474 8500 8504 8507 8532 8545 8549 8553 8555 8568 8569 8571 8576 8600 8632 8638 8643 8649 8692 8702 8706 8716 8721 8737 8740 8743 8746 8755 8760 8768 8830 8841 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 309 ; Location / Line Number Index ; Dcode Loc'n 0 1 2 3 4 5 6 7 D 0000 3910 5854 5855 5856 5857 5858 5859 5860 D 0010 5862 5863 5864 5865 5867 5868 5869 5870 D 0020 5872 5873 5874 5875 5876 5877 5878 5879 D 0030 3857 3858 3859 3860 3861 3862 3863 3864 D 0040 3868 3869 3870 3871 3872 3873 3874 3875 D 0050 3876 3877 3878 3879 3880 3881 3882 3883 D 0060 3884 3885 3886 3887 3888 3889 3890 3891 D 0070 3892 3893 3894 3895 3896 3897 3898 3899 D 0100 3903 3904 3905 3906 3911 3768 3912 3913 D 0110 5539 5540 5628 5689 4084 4085 4168 4386 D 0120 2768 2769 5424 5913 2777 2778 5425 5389 D 0130 3914 3915 5390 4687 4688 4689 4690 4691 D 0140 5265 3916 5266 5267 5268 5269 5270 5271 D 0150 5273 3917 5274 5275 5276 5277 5278 5279 D 0160 5310 3918 5311 5312 5314 5315 5316 5317 D 0170 5339 3919 5340 5341 5343 5344 5345 5346 D 0200 2549 2550 2551 2552 2554 2555 2556 2557 D 0210 2559 2560 2561 2562 2564 2565 2566 2567 D 0220 4117 4118 4119 4120 4142 4143 4144 4145 D 0230 4309 4310 4311 4312 4314 4315 4316 4317 D 0240 2954 2955 2956 2957 2958 2959 2960 3920 D 0250 2586 5114 3506 3507 3518 3520 3649 8223 D 0260 3671 3672 3673 3674 3801 3802 3803 3804 D 0270 4055 4056 4057 4058 4069 4070 4071 4072 D 0300 3352 3353 3354 3355 3356 3357 3358 3359 D 0310 3361 3362 3363 3364 3365 3366 3367 3368 D 0320 3464 3465 3466 3467 3468 3469 3470 3471 D 0330 3378 3379 3380 3381 3382 3383 3384 3385 D 0340 3478 3479 3480 3481 3482 3483 3484 3485 D 0350 3395 3396 3397 3398 3399 3400 3401 3402 D 0360 3492 3493 3494 3495 3496 3497 3498 3499 D 0370 3411 3412 3413 3414 3415 3416 3417 3418 D 0400 2799 2800 2801 2802 2809 2810 2811 2812 D 0410 2819 2820 2821 2822 2829 2830 2831 2832 D 0420 2834 2835 2836 2837 2844 2845 2846 2847 D 0430 2851 2852 2853 2854 2861 2862 2863 2864 D 0440 2871 2872 2873 2874 2881 2882 2883 2884 D 0450 2891 2892 2893 2894 2901 2902 2903 2904 D 0460 2912 2913 2914 2915 2922 2923 2924 2925 D 0470 2932 2933 2934 2935 2942 2943 2944 2945 D 0500 2602 2603 2604 2605 2607 2608 2609 2610 D 0510 2612 2613 2614 2615 2617 2618 2619 2620 D 0520 2622 2623 2624 2625 2627 2628 2629 2630 D 0530 2632 2633 2634 2635 2637 2638 2639 2640 D 0540 2644 2645 2646 2647 2649 2650 2651 2652 D 0550 2654 2655 2656 2657 2659 2660 2661 2662 D 0560 2664 2665 2666 2667 2669 2670 2671 2672 D 0570 2674 2675 2676 2677 2679 2680 2681 2682 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 310 ; Location / Line Number Index ; Dcode Loc'n 0 1 2 3 4 5 6 7 D 0600 3177 3178 3179 3180 3181 3182 3183 3184 D 0610 3186 3187 3188 3189 3190 3191 3192 3193 D 0620 3195 3196 3197 3198 3199 3200 3201 3202 D 0630 3204 3205 3206 3207 3208 3209 3210 3211 D 0640 3213 3214 3215 3216 3217 3218 3219 3220 D 0650 3222 3223 3224 3225 3226 3227 3228 3229 D 0660 3230 3231 3232 3233 3234 3235 3236 3237 D 0670 3239 3240 3241 3242 3243 3244 3245 3246 D 0700 7001 7002 7238 7772 7853 7854 7773 7774 D 0710 7560 7561 7571 7572 7585 7586 7776 7777 D 0720 7562 7563 7573 7574 7587 7588 7779 7780 D 0730 7782 7783 7784 7785 7786 7787 7788 7789 D 0740 7791 7792 7793 7794 7795 7796 7797 7798 D 0750 7800 7801 7802 7803 7804 7805 7806 7807 D 0760 7809 7810 7811 7812 7813 7814 7815 7816 D 0770 7818 7819 7820 7821 7822 7823 7824 7825 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 311 ; Location / Line Number Index ; Ucode Loc'n 0 1 2 3 4 5 6 7 U 0000 2151: 7947: 2152 2160: 7888: 7890: 6539= 6540= U 0010 2184= 7948: 2185= 2153 3287= 3290= 3293= 3296= U 0020 3976= 4126= 3982= 3985= 7949= 4127= 7950= 3988= U 0030 3561= 4154= 3565= 4495= 3569= 4155= 3573= 4496= U 0040 2356: 2360: 2364: 2372: 2382: 2385: 2392: 2396: U 0050 2409: 2415: 2436: 2154 4417= 4419= 4453= 4454= U 0060 3633= 2155 5047= 5448= 3636= 3638= 5054= 7616= U 0070 4757= 2158 4761= 5449= 4765= 4421= 4768= 7617= U 0100 2162 2243= 2246= 2249= 7875= 2250= 2163 2254= U 0110 2165 2261= 2264= 2267= 7877= 2268= 7879= 2273= U 0120 4181= 4183= 4274= 4278= 4184= 2168 4282= 4286= U 0130 3833= 2170 5694= 5696= 3836= 3840= 7042: 7057: U 0140 2193= 2196= 4292= 4296= 5373= 5374= 4300= 4304= U 0150 3553= 2204= 3554= 5604= 5376= 5378= 5380= 5381= U 0160 4337= 4340= 2172 5328= 4343= 4344= 4346= 5330= U 0170 5930= 4190= 5932= 5605= 5933= 4191= 5934= 5382= U 0200 5787= 2294= 5789= 2300= 5791= 2306= 5793= 2311= U 0210 5795= 2319= 2173 2323= 2175 2333= 5796= 2337= U 0220 3711= 3713= 3715= 2176 2189= 2190= 2177 7652= U 0230 6898= 6850= 6899= 6851= 6900= 2178 6901= 7653= U 0240 4696= 4697= 2179 5675= 2180 4698= 6583= 6584= U 0250 3328= 3331= 3334= 3337= 3340= 3343= 3346= 3349= U 0260 2233= 2234= 5528= 5676= 4725= 4728= 5529= 4729= U 0270 3431= 3434= 3437= 3440= 3443= 3446= 3449= 3452= U 0300 3588= 3592= 5533= 3594= 7384= 7385= 5534= 3595= U 0310 4019= 2181 4021= 4024= 3972= 7387= 3974= 3596= U 0320 3608= 3609= 5837= 2182 2186 3610= 5839= 5513= U 0330 4362= 4364= 6698= 4367= 2187 3612= 6699= 5515= U 0340 4793= 4796= 4797= 2220 4798= 4799= 2222 4800= U 0350 4735= 4736= 4737= 4738= 4439= 4479= 4440= 4480= U 0360 4889= 4890= 4891= 2281 4892= 4893= 2343 4894= U 0370 4519= 2348 2401= 2403= 4520= 4521= 4522= 4523= U 0400 4041: 2366 2418= 2421= 2437= 2438= 2369 5531= U 0410 4200= 4202= 2459= 2460= 4203= 2374 2386 5532= U 0420 5486= 5487= 5488= 5489= 5490= 5491= 5492= 5493= U 0430 5494= 2388 2423 5587= 2541= 2544= 5495= 5588= U 0440 5506= 6326= 5507= 6328= 5508= 2424 5509= 6329= U 0450 5510= 2427 2428 5621= 2993= 2997= 5511= 5622= U 0460 6183= 6185= 5841= 5845= 6187= 6189= 5848= 2430 U 0470 7507= 2433 5611= 5613= 7509= 7511= 5614= 5615= U 0500 5998= 6000= 3023= 3024= 6002= 6004= 2594 6006= U 0510 6384= 2724 2730 5734= 3042= 3043= 6385= 5735= U 0520 5748= 5749= 5751= 5752= 5754= 5755= 5757= 5758= U 0530 5760= 2789 2794 6823= 3073= 3074= 5761= 6825= U 0540 6079= 6081= 6083= 4210= 3077= 3078= 6086= 4212= U 0550 4815= 4449= 4816= 4450= 3090= 3091= 5941= 5942= U 0560 6217= 6220= 6376= 4233= 2909 6221= 6377= 4235= U 0570 5018= 5020= 2975 5024= 5977= 5978= 5980= 5983= ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 312 ; Location / Line Number Index ; Ucode Loc'n 0 1 2 3 4 5 6 7 U 0600 6223= 6226= 8366= 8367= 4711= 6227= 4713= 8368= U 0610 5799= 2988 5801= 5803= 3097= 3099= 6175= 6178= U 0620 6234= 6235= 6239= 5644= 3103= 3105= 6240= 5648= U 0630 6027= 6029= 2991 6031= 3110= 3112= 6382= 6383= U 0640 6363= 6365= 3116= 3118= 3145= 3146= 3007 6366= U 0650 6045= 6047= 6049= 6050= 6467= 6468= 6469= 6470= U 0660 4976= 6482= 4977= 6485= 4986= 6487= 4987= 6489= U 0670 5290= 6491= 5291= 6494= 5432= 6497= 5433= 6499= U 0700 6560= 3009 6564= 6566= 6567= 6570= 3010 6572= U 0710 6507= 6509= 6511= 6514= 6515= 6517= 6736= 6737= U 0720 5434= 6774= 5435= 6776= 5722= 6780= 5723= 6784= U 0730 5649= 6788= 5661= 6792= 5650= 6796= 5662= 6800= U 0740 6605= 6607= 3149= 3151= 3391= 3392= 6609= 3012 U 0750 6089= 6090= 3015 6091= 6813= 6816= 6818= 6820= U 0760 6630= 6631= 3455= 3456= 3459= 3460= 6632= 3026 U 0770 7455= 7456= 7457= 7458= 7459= 7460= 7461= 7462= U 1000 8349= 8352= 8354= 8356= 3580= 3581= 3044 8358= U 1010 3585= 3586= 5668= 7597= 3629= 3630= 5673= 7599= U 1020 6122= 6124= 6125= 3045 3642= 3643= 3071 7625= U 1030 6131= 6133= 6134= 3079 3659= 3663= 3080 7626= U 1040 8412= 8415= 8417= 8419= 3699= 3703= 3094 8423= U 1050 6198= 6200= 6201= 3114 5726= 7694= 5727= 7696= U 1060 8252= 8254= 5919= 8258= 3119 8260= 5921= 8262= U 1070 8264= 8266= 8268= 8270= 6732= 6733= 6734= 3143 U 1100 8805= 8807= 8809= 8811= 8813= 8815= 8817= 8819= U 1110 8821= 8822= 8823= 8825= 7316= 7319= 3301 7321= U 1120 7338= 7340= 7341= 3302 7722= 7725= 7728= 7730= U 1130 8428= 8431= 8433= 8438= 8458= 8461= 3407 8471= U 1140 8777= 8778= 8779= 3408 3735= 3739= 3760= 3763= U 1150 3781= 3786= 3789= 3791= 3795= 3796= 3951= 3955= U 1160 3961= 3964= 3967= 3970= 3996= 3998= 4001= 4005= U 1170 4095= 4096= 4105= 4107= 4110= 4111= 4128= 4129= U 1200 4134= 4135= 4137= 4138= 4158= 4159= 4160= 4162= U 1210 4215= 4216= 4223= 4224= 4325= 4327= 4352= 4355= U 1220 4373= 4377= 4379= 4381= 4395= 4397= 4399= 4400= U 1230 4409= 4410= 4425= 4426= 4428= 4429= 4432= 4433= U 1240 4434= 4435= 4443= 4444= 4459= 4460= 4469= 4470= U 1250 4487= 4488= 4538= 4539= 4540= 4541= 4547= 4548= U 1260 4557= 4558= 4561= 4562= 4586= 4589= 4603= 4607= U 1270 4619= 4620= 4624= 4625= 4629= 4630= 4645= 4647= U 1300 4651= 4652= 4947= 4950= 4966= 4968= 4971= 4972= U 1310 5002= 5003= 5037= 5039= 5066= 5069= 5102= 5104= U 1320 5130= 5137= 5141= 5144= 5146= 5148= 5153= 5158= U 1330 5170= 5171= 5295= 5296= 5299= 5300= 5304= 5305= U 1340 5324= 5325= 5354= 5355= 5357= 5358= 5363= 5364= U 1350 5366= 5367= 5370= 5371= 5395= 5396= 5399= 5400= U 1360 5402= 5403= 5410= 5411= 5418= 5419= 5440= 5441= U 1370 5444= 5445= 5451= 5452= 5453= 5455= 5498= 5499= ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 313 ; Location / Line Number Index ; Ucode Loc'n 0 1 2 3 4 5 6 7 U 1400 2230: 2231: 2571: 2574: 2577: 2581: 2591: 2691: U 1410 2693: 2718: 2720: 2723: 2726: 2729: 2732: 2738: U 1420 2740: 2742: 2745: 2752: 2747: 2749: 2754: 2756: U 1430 2759: 3406: 2761: 2763: 2773: 8737 2774: 3422: U 1440 3475: 2806: 2816: 2826: 2841: 2858: 2868: 2878: U 1450 2888: 2898: 2908: 2919: 2929: 2939: 2949: 4090: U 1460 7578: 7582: 3019: 7579: 3069: 3070: 3088: 5917: U 1470 3141: 3142: 3271: 3273: 3276: 3279: 3372: 3390: U 1500 8761 8764 8771 8773 2487: 2492: 2498: 8782 U 1510 8785 8795 8834 8851 2519: 2524: 2530: 2536: U 1520 3527: 3528: 3530: 3531: 3532: 3535: 3536: 3537: U 1530 3539: 3540: 3542: 3543: 3544: 3545: 3546: 3547: U 1540 3603: 3653: 3503: 3680: 3693: 3722: 3755: 3513: U 1550 3808: 3773: 3815: 8229: 3830: 3845: 3946: 4036: U 1560 4063: 4077: 8855 8871 8873 2783: 4173: 2788: U 1570 5323: 4150: 5351: 5285: 5288: U 1600 4321: 4330: U 1610 4694: 3489: 2969: 2972: 7567: 4102: 5394: 7568: U 1620 4702: 5415: 2983: 2985: 4706: 4707: 5431: 4391: U 1630 4716: 5633: 3004: 3006: 4718: 5549: 5692: 5552: U 1640 5118: 4123: 5120: 5123: 7593: 7595: U 1650 7829: 7833: 7838: 7840: 7842: 7844: 7846: 7848: U 1660 3936: 3924: 3926: 3928: 3930: 3938: 3932: 3934: U 1670 U 1700 7047: 7005: 7006: 7007: 7060: 7094: 7008: 7009: U 1710 7011: 7012: 7013: 7014: 7367: 7364: 7015: 7016: U 1720 7019: 7221: 7412: 7119: 7181: 7212: 7020: 7021: U 1730 7024: 7025: 7026: 7027: 7028: 7029: 7030: 7031: U 1740 5885: 5887: 5889: 5891: 5893: 5895: 5897: U 1750 5899: 5901: 7860: 7868: U 1760 7243: 7245: 7247: 7249: 7327: 7359: 7251: 7252: U 1770 7255: 7259: 7263: 7267: 7311: 7351: 7271: 7275: U 2000 5502= 5504= 5517= 5518= 5519= 5520= 5557= 5559= U 2010 5562= 5564= 5568= 5569= 5576= 5577= 5618= 5619= U 2020 5636= 5637= 5658= 5659= 5679= 5680= 5682= 5684= U 2030 5699= 5700= 5709= 5710= 5718= 5719= 5720= 5721= U 2040 5737= 5738= 5770= 5771= 5775= 5776= 5780= 5782= U 2050 5807= 5808= 5815= 5816= 5825= 5826= 5944= 5946= U 2060 5962= 6100= 5966= 5969= 5963= 6101= 5971= 5972= U 2070 5988= 6064= 5989= 6065= 6014= 6016= 6020= 6021= U 2100 6035= 6037= 6040= 6042= 6053= 6055= 6104= 6105= U 2110 6102= 6459= 6108= 6110= 6103= 6460= 6118= 6119= U 2120 6145= 6146= 6152= 6155= 6167= 6301= 6168= 6303= U 2130 6170= 6173= 6191= 6195= 6205= 6206= 6209= 6211= U 2140 6245= 6246= 6258= 6259= 6262= 6263= 6266= 6267= U 2150 6272= 6274= 6275= 6277= 6285= 6286= 6296= 6297= U 2160 6306= 6308= 6314= 6315= 6310= 6427= 6312= 6429= U 2170 6320= 6323= 6333= 6334= 6338= 6339= 6344= 6345= ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 314 ; Location / Line Number Index ; Ucode Loc'n 0 1 2 3 4 5 6 7 U 2200 6347= 6351= 6389= 6390= 6394= 6395= 6401= 6402= U 2210 6403= 6404= 6405= 6406= 6423= 6424= 6430= 6431= U 2220 6437= 6438= 6443= 6445= 6464= 6465= 6472= 6473= U 2230 6478= 6479= 6505= 6506= 6530= 6533= 6547= 6548= U 2240 6557= 6880= 6558= 6881= 6577= 6578= 6598= 6600= U 2250 6622= 6624= 6626= 6627= 6644= 6646= 6667= 6671= U 2260 6673= 6675= 6702= 6703= 6756= 6757= 6761= 6763= U 2270 6807= 6809= 6829= 6831= 6846= 6847= 6856= 6860= U 2300 6875= 6878= 6932= 6933= 6892= 7292= 6893= 7294= U 2310 6940= 6941= 6948= 6949= 6951= 6952= 6978= 6986= U 2320 6995= 6996= 7068= 7069= 7070= 7071= 7073= 7074= U 2330 7075= 7076= 7078= 7079= 7129= 7134= 7149= 7155= U 2340 7164= 7168= 7183= 7186= 7189= 7190= 7198= 7199= U 2350 7214= 7215= 7222= 7224= 7231= 7232= 7289= 7290= U 2360 7300= 7301= 7332= 7333= 7368= 7369= 7370= 7371= U 2370 7374= 7375= 7376= 7377= 7378= 7379= 7380= 7381= U 2400 7382= 7383= 7415= 7417= 7423= 7424= 7428= 7430= U 2410 7436= 7438= 7477= 7480= 7481= 7482= 7493= 7494= U 2420 7504= 7505= 7521= 7523= 7525= 7527= 7529= 7531= U 2430 7535= 7536= 7550= 7551= 7554= 7555= 7612= 7613= U 2440 7621= 7624= 7631= 7633= 7637= 7639= 7650= 7651= U 2450 7657= 7658= 7663= 7665= 7669= 7671= 7682= 7683= U 2460 7686= 7688= 7691= 7692= 7701= 7702= 7708= 7709= U 2470 7736= 7737= 7742= 7743= 7883= 7884= 7895= 7896= U 2500 7899= 7903= 7956= 7958= 7966= 7969= 7967= 7970= U 2510 7971= 7973= 7972= 7974= 7976= 7979= 7977= 7980= U 2520 7982= 7985= 7983= 7986= 7988= 7990= 7989= 7991= U 2530 8236= 8237= 8287= 8290= 8301= 8303= 8312= 8316= U 2540 8325= 8327= 8330= 8333= 8338= 8340= 8360= 8362= U 2550 8374= 3556 8380= 8382= 8375= 8385= 3577 8386= U 2560 8390= 8451= 8400= 8409= 8396= 8453= 8440= 8443= U 2570 8447= 8448= 8475= 8477= 8478= 8482= 8502= 8504= U 2600 8492= 3582 8494= 8519= 8509= 8513= 3615 8532= U 2610 8537= 8539= 8543= 8546= 8553= 8555= 8571= 8573= U 2620 8576= 8577= 8598= 3618 8602= 8603= 8600= 3620 U 2630 8639= 8640= 8644= 8645= 8650= 8651= 8654= 8655= U 2640 8668= 8669= 8677= 8678= 8680= 8681= 8694= 8699= U 2650 8704= 8707= 8714= 8717= 8727= 8729= 8733= 8736= U 2660 8739= 8740= 8744= 8746= 8750= 8752= 8756= 8757= U 2670 8766= 8769= 8789= 8791= 8793= 8794= 8797= 8798= U 2700 8800= 3622 8831= 8832= 8837= 8841= 8844= 8848= U 2710 8857= 8858= 8865= 8866= 3624 3644 3666 3688 U 2720 3706 3725 3730 3744 3749 3759 3776 3811 U 2730 3817 3819 3823 3831 3846 3848 3851 3948 U 2740 3990 3991 3993 4007 4012 4029 4032 4044 U 2750 4046 4050 4098 4109 4124 4132 4151 4152 U 2760 4156 4174 4176 4193 4194 4205 4214 4217 U 2770 4218 4219 4220 4222 4228 4229 4230 4237 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 315 ; Location / Line Number Index ; Ucode Loc'n 0 1 2 3 4 5 6 7 U 3000 4253 4256 4268 4323 4331 4332 4334 4357 U 3010 4359 4393 4402 4403 4406 4411 4412 4414 U 3020 4438 4441 4442 4445 4451 4457 4458 4462 U 3030 4464 4465 4467 4472 4473 4475 4476 4482 U 3040 4485 4490 4498 4537 4543 4544 4550 4551 U 3050 4552 4553 4554 4559 4563 4564 4567 4597 U 3060 4615 4617 4622 4627 4632 4633 4634 4641 U 3070 4643 4650 4721 4722 4741 4742 4750 4752 U 3100 4773 4777 4810 4819 4822 4823 4824 4827 U 3110 4828 4829 4896 4897 4900 4903 4904 4905 U 3120 4906 4908 4911 4914 4915 4916 4918 4943 U 3130 4953 4954 4957 4959 4961 4980 4981 4982 U 3140 4983 4989 4997 5027 5041 5044 5045 5057 U 3150 5059 5062 5071 5098 5105 5106 5108 5110 U 3160 5111 5125 5140 5163 5165 5168 5176 5180 U 3170 5182 5184 5292 5293 5294 5302 5326 5331 U 3200 5334 5359 5360 5361 5384 5407 5416 5417 U 3210 5437 5521 5550 5555 5570 5574 5575 5578 U 3220 5583 5585 5590 5592 5593 5606 5608 5623 U 3230 5638 5639 5643 5651 5657 5663 5677 5678 U 3240 5681 5701 5705 5708 5711 5712 5715 5730 U 3250 5764 5767 5777 5805 5810 5812 5818 5923 U 3260 5925 5927 5928 5936 5974 5985 5986 5991 U 3270 6012 6018 6019 6022 6034 6051 6058 6061 U 3300 6062 6063 6066 6067 6069 6075 6076 6093 U 3310 6094 6120 6127 6128 6129 6137 6138 6139 U 3320 6140 6141 6142 6147 6148 6161 6163 6165 U 3330 6179 6204 6207 6230 6248 6251 6253 6261 U 3340 6264 6269 6271 6278 6287 6298 6299 6318 U 3350 6340 6342 6352 6353 6355 6356 6357 6358 U 3360 6359 6362 6368 6373 6380 6386 6387 6388 U 3370 6391 6392 6393 6408 6412 6432 6434 6439 U 3400 6440 6461 6462 6476 6525 6526 6528 6550 U 3410 6551 6587 6593 6594 6595 6596 6614 6635 U 3420 6637 6647 6650 6655 6656 6657 6658 6659 U 3430 6661 6664 6676 6679 6681 6683 6684 6701 U 3440 6742 6745 6750 6752 6827 6849 6852 6854 U 3450 6873 6891 6894 6896 6903 6904 6918 6920 U 3460 6925 6935 6936 6944 6946 6954 6956 6958 U 3470 6959 6960 6962 6965 6969 6971 6989 6992 U 3500 7033 7034 7036 7062 7063 7064 7066 7067 U 3510 7072 7081 7083 7086 7088 7091 7096 7099 U 3520 7102 7103 7105 7107 7122 7138 7142 7160 U 3530 7171 7173 7178 7187 7188 7191 7196 7197 U 3540 7218 7227 7228 7233 7256 7257 7260 7261 U 3550 7264 7265 7268 7269 7272 7273 6913: 6914: U 3560 7282 7284 7285 7286 7295 7297 7302 7303 U 3570 7306 7313 7324 7328 7329 7331 7335 7343 ; KS10.MCR[7,3] 15:03 7-JAN-1986 MICRO 31(254) KS10 MICROCODE V130, 7-JAN-86 Page 316 ; Location / Line Number Index ; Ucode Loc'n 0 1 2 3 4 5 6 7 U 3600 7344 7345 7352 7353 7355 7372 7373 7395 U 3610 7396 7397 7399 7405 7406 7413 7418 7431 U 3620 7440 7443 7463 7464 7465 7466 7467 7468 U 3630 7469 7472 7473 7474 7484 7486 7489 7491 U 3640 7492 7496 7519 7533 7537 7540 7553 7602 U 3650 7655 7684 7699 7700 7704 7711 7718 7733 U 3660 7749 7751 7753 7755 7757 7759 7761 7763 U 3670 7765 7767 7863 7870 7881 7954 7960 7962 U 3700 7965 7968 7975 7978 7981 7984 7987 7992 U 3710 7993 7994 7996 8230 8232 8233 8234 8235 U 3720 8244 8245 8246 8248 8274 8275 8276 8280 U 3730 8283 8284 8295 8297 8307 8343 8345 8472 U 3740 6099: 6456: 6160: 6293: 5959: 8498 8547 8550 U 3750 8551 6457: 8557 8559 5960: 8564 8566 8568 U 3760 8569 8570 8578 8579 8580 8583 8587 8632 U 3770 8634 8636 8665 8679 8690 8719 8721 8243: No errors detected End of microcode assembly 319 pages of listing Used 47.87 seconds, 118 pages of core Symbol table: 31P Text strings: 9P Loc'n assignment: 18P Cross reference: 53P Dist/rtl/ks10/cpu/useq/skip.v0000700000175100010010000001231712151540224014423 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // brief // Microcontroller Skip Logic // // details // This section of the microcontroller controls the SKIP // field selection. // // The microcontroller can execute simple branches based // on a selected boolean input value. Because the branch // logic is implemented as an OR gate, the skip logic can // only change the LSB of the control ROM address from a // zero to a one - this means that the 'skip not taken' // must be an even address and that the 'skip taken' // address must be the following odd address. // // The microcode assembler handles all the details regarding // how microcode addresses are selected. // // See the description of the dispatch logic and the // microcontroller for addtional details. // // file // skip.v // // author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "crom.vh" `include "drom.vh" module SKIP(crom, skip40, skip20, skip10, skipADDR); parameter cromWidth = `CROM_WIDTH; input [0:cromWidth-1] crom; // Control ROM Data input [1:7] skip40; // Skip 40 bits input [1:7] skip20; // Skip 20 bits input [1:7] skip10; // Skip 10 bits output [0:11] skipADDR; // Skip Address // // SKIP 40 // // Details // When this mux is selected, the mux can generate // a skip if the selected input is asserted. // // Trace // DPEA/E45 // reg skip0; always @(crom or skip40) begin if (`cromSKIP_EN_40) case (`cromSKIP_SEL) 3'b001: skip0 = skip40[1]; 3'b010: skip0 = skip40[2]; 3'b011: skip0 = skip40[3]; 3'b100: skip0 = skip40[4]; 3'b101: skip0 = skip40[5]; 3'b110: skip0 = skip40[6]; 3'b111: skip0 = skip40[7]; default: skip0 = 1'b0; endcase else skip0 = 1'b0; end // // SKIP 20 // // Details // When this mux is selected, the mux can generate // a skip if the selected input is asserted. // // Trace // DPEA/E38 // reg skip1; always @(crom or skip20) begin if (`cromSKIP_EN_20) case (`cromSKIP_SEL) 3'b001: skip1 = skip20[1]; 3'b010: skip1 = skip20[2]; 3'b011: skip1 = skip20[3]; 3'b100: skip1 = skip20[4]; 3'b101: skip1 = skip20[5]; 3'b110: skip1 = skip20[6]; 3'b111: skip1 = skip20[7]; default: skip1 = 1'b0; endcase else skip1 = 1'b0; end // // SKIP 10 // // Details // When this mux is selected, the mux can generate // a skip if the selected input is asserted. // // Trace // CRA2/E85 // reg skip2; always @(crom or skip10) begin if (`cromSKIP_EN_10) case (`cromSKIP_SEL) 3'b001: skip2 = skip10[1]; 3'b010: skip2 = skip10[2]; 3'b011: skip2 = skip10[3]; 3'b100: skip2 = skip10[4]; 3'b101: skip2 = skip10[5]; 3'b110: skip2 = skip10[6]; 3'b111: skip2 = skip10[7]; default: skip2 = 1'b0; endcase else skip2 = 1'b0; end // // Skip Address Generation // // Details: // This generates the 12-bit skip address that is "OR"ed into // the microsequencer address. // // Trace // CRA1/E111 // CRA1/E121 // assign skipADDR = (skip0 | skip1 | skip2) ? 12'o0001 : 12'o0000; endmodule Dist/rtl/ks10/cpu/useq/stack.v0000700000175100010010000001275712151540224014572 0ustar RobNone//////////////////////////////////////////////////////////////////// //! //! KS-10 Processor //! //! \brief //! Microcontroller Call Stack //! //! \details //! //! The call/return operation of the microcontroller is quite //! unique. The 'call' instruction pushes the address of the //! instruction (not the next instruction) on the call-stack. //! //! Doing nothing else would return the execution to the very //! same instruction as the original 'call' instruction. //! //! The return instruction also provides a dispatch offset //! which is combined with the return address from the stack //! to return to the next executable microcode statement. //! //! The 'called' function must know the offset to the next //! instruction. //! //! \file //! stack.v //! //! \author //! Rob Doyle - doyle (at) cox (dot) net //! //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // `default_nettype none `include "crom.vh" module STACK(clk, rst, clken, call, ret, addrIN, addrOUT); parameter cromWidth = `CROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input call; // Push addr onto stakc input ret; // Pop addr from stack input [0:11] addrIN; // Calling address for stack output [0:11] addrOUT; // Return address from stack // // Stack Pointer // // Details // The stack pointer is incremented on a 'call' and decremented // on a 'ret' instruction - otherwise the stack pointer does // not change. // // Trace // CRA3/E32 // reg [0:3] sp; always @(posedge clk or posedge rst) begin if (rst) sp <= 15; else if (clken) begin if (call) sp <= sp + 1'b1; else if (ret) sp <= sp - 1'b1; end end // // Current Address // // Details // This delay generates the current microcode address. The // 'addr' register that is supplied to this module always // has the address of the /NEXT/ instruction. // // This is a simple one-clock delay to get the proper address. // // Trace // CRA3/E114 // CRA3/E137 // CRA3/E161 // reg [0:11] currADDR; always @(posedge clk or posedge rst) begin if (rst) currADDR <= 12'b0; else if (clken) currADDR <= addrIN; end // // Write Pointer // // Details: // The write pointer is always offset from the stack pointer // by 1. // // Note: // This is different than the KS10. See below. // // Trace: // CRA3/E16 // CRA3/E17 // wire [0: 3] wp = sp + 1'b1; // // Dual Ported Stack // // Details // The stack is implemented quite a bit differently than the // KS10 just because the FPGA provides Dual Port RAMs. // // The 'read' port of the Dual Port RAM provides the return // address. This port always points to the top-of-stack and // can always be accessed independantly. // // The 'write' port of the Dual Port RAM is used to store // the next 'call' address. This port always points to the // address past the top-of-stack and can always be accessed // independantly. // // Once the 'call' address is stored, the stack pointer is // incremented and the return address automatically becomes // available at the new top-of-stack. // // This implementation saves all ths KS10 logic to dynamically // change RAM address depending if a 'call' or 'return' // instruction is being processed. It also allow the stack // to always update in a single clock cycle. // // Trace // CRA3/E70 // CRA3/E56 // CRA3/149 // CRA3/E79 // CRA3/E55 // CRA3/E160 // `ifndef SYNTHESIS integer i; `endif reg [0:11] stack[0:15]; always @(posedge clk or posedge rst) begin if (rst) `ifdef SYNTHESIS ; `else for (i = 0; i < 16; i = i + 1) stack[i] <= 0; `endif else if (clken & call) stack[wp] <= currADDR; end // // The stack read is asynchronous // assign addrOUT = stack[sp]; endmodule Dist/rtl/ks10/cpu/useq/useq.v0000700000175100010010000002661312151540224014436 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // brief // Microsequencer // // details // This file implements the KS10 microsequencer. // // file // useq.v // // author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `include "crom.vh" `include "drom.vh" `include "../alu.vh" `include "../pcflags.vh" `include "../regir.vh" module USEQ(clk, rst, clken, pageFAIL, dp, dispDIAG, cpuINTR, cpuEXEC, cpuCONT, iolatch, timerINTR, skipJFCL, opJRST0, trapCYCLE, scSIGN, aluFLAGS, dispPF, dispNI, dispBYTE, dispSCAD, regIR, pcFLAGS, drom, crom); parameter cromWidth = `CROM_WIDTH; parameter dromWidth = `DROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input pageFAIL; // Page Fail input [0:35] dp; // Datapath input [0:11] dispDIAG; // Diagnostic Addr input cpuINTR; // Extenal Interrupt input cpuEXEC; // Execute Switch Active input cpuCONT; // Continue Switch Active input iolatch; // IO Latch input timerINTR; // Timer Interrupt input trapCYCLE; // Trap Cycle input scSIGN; // SC Sign input [0: 8] aluFLAGS; // ALU Flags input skipJFCL; // JFCL Instruction input opJRST0; // JRST 0 Instruction input [0: 3] dispPF; // Page Fail Dispatch input [0: 3] dispNI; // Next Instruction Dispatch input [0: 3] dispBYTE; // Byte Size/Position Dispatch input [0: 3] dispSCAD; // SCAD Dispatch input [0:17] regIR; // Instruction Register input [0:17] pcFLAGS; // PC Flags input [0:dromWidth-1] drom; // Dispatch ROM Data output [0:cromWidth-1] crom; // Control ROM Data // // ALU Flags // wire aluQR37 = `aluQR37(aluFLAGS); wire aluLZERO = `aluLZERO(aluFLAGS); wire aluRZERO = `aluRZERO(aluFLAGS); wire aluLSIGN = `aluLSIGN(aluFLAGS); wire aluRSIGN = `aluRSIGN(aluFLAGS); wire aluCRY0 = `aluCRY0(aluFLAGS); wire aluCRY1 = `aluCRY1(aluFLAGS); wire aluCRY2 = `aluCRY2(aluFLAGS); wire aluZERO = `aluZERO(aluFLAGS); // // PC Flags // wire flagFPD = `flagFPD(pcFLAGS); wire flagUSER = `flagUSER(pcFLAGS); wire flagUSERIO = `flagUSERIO(pcFLAGS); // // Instruction Register // wire [ 9:12] regIR_AC = `IR_AC(regIR); wire regIR_I = `IR_I(regIR); wire regACZERO = `acZERO(regIR); wire regXRZERO = `xrZERO(regIR); // // Control ROM Address // wire [0:11] addr; wire [0:11] dispRET; wire [0:11] skipADDR; wire [0:11] dispADDR; // // ALU Zero // wire txxx = aluZERO != `dromTXXXEN; // Test Instruction Results // // Dispatch Addresses // wire [8:11] dispMUL = {1'b0, aluQR37, 1'b0, 1'b0}; wire [8:11] dispEA = {~opJRST0, regIR_I, regXRZERO, 1'b0}; wire [8:11] dispNORM = {aluZERO, dp[8:9], aluLSIGN}; // // Skip Logic // // Details // The skip logic allows the sequencer to conditionally // jump forward one micro-instruction. // // Note: // Like the dispatch, the skip logic can only set bits. // The skip must take place on an even address. // SKIP uSKIP (.crom(crom), .skip40({aluCRY0, aluLZERO, aluRZERO, ~flagUSER, flagFPD, regACZERO, cpuINTR }), .skip20({aluCRY2, aluLSIGN, aluRSIGN, flagUSERIO, skipJFCL, aluCRY1, txxx }), .skip10({trapCYCLE, aluZERO, scSIGN, cpuEXEC, ~iolatch, ~cpuCONT, ~timerINTR}), .skipADDR(skipADDR) ); // // Dispatch Logic // // Details // The dromJ is implemented slightly different than the KS-10. // In the KS10, the DROM J value is constained to be between 1400 // and 1777. This allows the dispatch function to hardwire // the upper 4 data bits instead of storing them in the DROM. // I've hooked all data lines up and will let the optimizer do // it's thing. The optimizer will determine that these lines // never change and replace the DROM columns with hardwired // constants. This design approach makes the design intent // much more obvious. // // Notes // Watch the index numbering on DROM_J! // // AREAD does dispatch to address 40-57 or address 1400-1777 // // Quoting the KS10 Technical Manual: // // dromAEQJ - "This bit causes an immediate dispatch on the J // field when the microword calls for the standard // AREAD dispatch on the A field. This is used for // instructions that require no memory access or // special setup (for example, MOVEI, JFCL)". // // dromACDISP - "This bit causes the AC field of the instruction // word to replace the right four bits of the J // field so that a jump to begin instruction // execution will actually dispatch to one of 16 // locations where the instruction code is expanded // to 13 bits." // // Trace: // DPEA/E111 // DPEA/E153 // CRA2/E158 // wire dromAEQJ = `dromAEQJ; wire dromACDISP = `dromACDISP; wire [0:11] dromJ = `dromJ; wire [0: 3] dromA = `dromA; wire [0: 3] dromB = `dromB; // // Jump Dispatch // // Trace // DPEA/E111 // reg [0:11] dispJ; always @(dromACDISP, regIR_AC, dromJ) begin if (dromACDISP) // Dispatch Address Range: dispJ = {dromJ[0:7], regIR_AC}; // 1400 to 1777 (4 upper address were hardwired) else dispJ = {dromJ[0:7], dromJ[8:11]}; // 1400 to 1777 (4 upper address were hardwired) end // // AREAD Dispatch // // Trace // CRA2/E158 // DPEA/E153 // reg [0:11] dispAREAD; always @(dromAEQJ, dispJ, dromA) begin if (dromAEQJ) // Dispatch Address Range: dispAREAD = dispJ; // 1400 to 1777 (4 upper address were hardwired) else dispAREAD = {8'b00000010, dromA}; // 0040 to 0057 end // // Dispatch MUX // DISPATCH uDISPATCH (.crom (crom), .dp (dp), .dispDIAG (dispDIAG), .dispRET (dispRET), .dispJ (dispJ), .dispAREAD (dispAREAD), .dispMUL (dispMUL), .dispPF (dispPF), .dispNI (dispNI), .dispBYTE (dispBYTE), .dispEA (dispEA), .dispSCAD (dispSCAD), .dispNORM (dispNORM), .dispDROM_A (dromA), .dispDROM_B (dromB), .dispADDR (dispADDR) ); // // Address 'MUX' // // Details // The CROM registers have been absorbed by the synchronous FPGA ROM. // Therefore the initial state of the microcode (address zero) must // be handled explicitly. // // The Microcode should begin execution at address o0000. // // The microsequencer continuously re-executes instruction at address // o0000 while the rst signal is asserted. It can only execute the // second instruction after the 'rst' signal is negated. // // This process assumes that the 'rst' negation is synchronized to // the clock and that the 'rst' signal is asserted for a few clock // cycles minimum to ensure that the instruction at address o0000 // is executed at least once. // // The synchronous 'rst' negation is handled earlier in the design // heirarchy. // // The Page Fail address is hard coded to address o3777 in the // microcode. // // Notes: // The microcode address space is 12-bits but only 11-bits (2048 // microcode words) are actually implemented. Therefore the amount // of microcode can be easily doubled without changing the micro- // architecture. // // If all 12-bits of the microcode ROM are implemented, the PAGE FAIL // code will have to be moved to address o7777 or otherwise dealt // with. // // Trace: // CRA1/E9 // CRA1/E18 // CRA1/E24 // CRA1/E25 // CRA1/E26 // CRA1/E35 // CRA1/E111 // CRA1/E121 // CRA1/E174 // CRA1/E183 // CRA1/E184 // CRA1/E186 // assign addr = (rst) ? 12'o0000 : (pageFAIL) ? 12'o7777 : (dispADDR | skipADDR | `cromJ); // // Control ROM // CROM uCROM (.clk (clk), .clken (clken), .rst (rst), .addr (addr), .crom (crom) ); // // Call/Return Instruction Decode: // // Details: // The address is pushed on the stack during a call or when a // PAGE FAIL occurs. // // Note: // The KS10 logic decodes a 'return dispatch' as "x0xx01" but // only o01 and o41 are used by the microcode. // // Trace // CRA2/E33 // CRA2/E34 // wire call = `cromCALL | pageFAIL; wire ret = ((`cromDISP == 6'o01) || // used (`cromDISP == 6'o05) || // not used (`cromDISP == 6'o11) || // not used (`cromDISP == 6'o15) || // not used (`cromDISP == 6'o41) || // used (`cromDISP == 6'o45) || // not used (`cromDISP == 6'o51) || // not used (`cromDISP == 6'o55)); // not used // // Call/Return Stack // STACK uSTACK (.clk (clk), .rst (rst), .clken (clken), .call (call), .ret (ret), .addrIN (addr), .addrOUT (dispRET) ); endmodule Dist/rtl/ks10/cpu/vma.v0000700000175100010010000001736212151540226013272 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Virtual Memory Address // // Details // // File // vma.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "pcflags.vh" `include "useq/crom.vh" `include "useq/drom.vh" module VMA(clk, rst, clken, crom, drom, dp, cpuEXEC, prevEN, pcFLAGS, vmaEXTENDED, vmaFLAGS, vmaADDR); parameter cromWidth = `CROM_WIDTH; parameter dromWidth = `DROM_WIDTH; input clk; // Clock input rst; // Reset input clken; // Clock Enable input [ 0:cromWidth-1] crom; // Control ROM Data input [ 0:dromWidth-1] drom; // Dispatch ROM Data input [ 0:35] dp; // Data path input cpuEXEC; // Execute input prevEN; // Previous Enable input [ 0:17] pcFLAGS; // PC Flags output vmaEXTENDED; // VMA Extended output [ 0:13] vmaFLAGS; // VMA Flags output [14:35] vmaADDR; // Virtual Memory Address // // PC Flags // wire flagUSER = `flagUSER(pcFLAGS); // User wire flagPCU = `flagPCU(pcFLAGS); // Previous Context User // // Microcode Decode // // Note // The cache clear and the previous selection are exclusive // operations. // // Trace // DPE5/E76 // DPE6/E53 // wire cacheSWEEP = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_CLRCACHE); wire selPREVIOUS = `cromSPEC_EN_20 & (`cromSPEC_SEL == `cromSPEC_SEL_PREVIOUS); // // VMA Register // // Details // The VMA is loaded when cromMEM_CYCLE is active and // the VMA is loaded. // // Trace // DPE3/E53 // DPM4/E55 // DPM4/E56 // DPM4/E74 // DPE3/E76 // DPM4/E82 // DPM4/E90 // DPM4/E97 // DPM4/E103 // DPM4/E115 // DPM4/E137 // DPM4/E152 // DPM4/E168 // DPM4/E175 // DPM4/E182 // DPM4/E183 // reg [14:35] vmaADDR; reg vmaEXTENDED; reg vmaUSER; reg vmaFETCH; reg vmaPHYSICAL; reg vmaPREVIOUS; reg vmaIOCYCLE; reg vmaWRUCYCLE; reg vmaVECTORCYCLE; reg vmaIOBYTECYCLE; wire vmaEN = ((`cromMEM_CYCLE & `cromMEM_LOADVMA ) | (`cromMEM_CYCLE & `cromMEM_AREAD & `dromVMA) | (cacheSWEEP)); always @(posedge clk or posedge rst) begin if (rst) begin vmaADDR <= 22'b0; vmaEXTENDED <= 1'b0; vmaUSER <= 1'b0; vmaFETCH <= 1'b0; vmaPHYSICAL <= 1'b0; vmaPREVIOUS <= 1'b0; vmaIOCYCLE <= 1'b0; vmaWRUCYCLE <= 1'b0; vmaVECTORCYCLE <= 1'b0; vmaIOBYTECYCLE <= 1'b0; end else if (clken & vmaEN) begin vmaADDR <= dp[14:35]; vmaEXTENDED <= `cromMEM_EXTADDR; if (`cromMEM_DPFUNC) begin vmaUSER <= dp[0]; vmaFETCH <= dp[2]; vmaPHYSICAL <= dp[8]; vmaPREVIOUS <= dp[9]; vmaIOCYCLE <= dp[10]; vmaWRUCYCLE <= dp[11]; vmaVECTORCYCLE <= dp[12]; vmaIOBYTECYCLE <= dp[13]; end else begin vmaUSER <= ((~`cromMEM_FORCEEXEC & flagUSER & ~cpuEXEC) | (`cromMEM_FETCHCYCLE & flagUSER ) | (prevEN & flagPCU ) | (selPREVIOUS & flagPCU ) | (`cromMEM_FORCEUSER)); vmaFETCH <= `cromMEM_FETCHCYCLE; vmaPHYSICAL <= `cromMEM_PHYSICAL; vmaPREVIOUS <= prevEN | selPREVIOUS; vmaIOCYCLE <= 1'b0; vmaWRUCYCLE <= 1'b0; vmaVECTORCYCLE <= 1'b0; vmaIOBYTECYCLE <= 1'b0; end end end // // Memory Cycle Control // // Details // The type of memory cycle can controlled by the microcode or // can be controlled by the Dispatch ROM. The Cycle Control is // loaded when cromMEM_CYCLE is active. // // Trace // DPM5/E48 // DPM5/E66 // DPM5/E33 // DPM5/E110 // reg vmaREADCYCLE; reg vmaWRTESTCYCLE; reg vmaWRITECYCLE; reg vmaCACHEINH; wire memEN = ((`cromMEM_CYCLE & `cromMEM_WAIT ) | (`cromMEM_CYCLE & `cromMEM_BWRITE & `dromCOND_FUNC)); always @(posedge clk or posedge rst) begin if (rst) begin vmaREADCYCLE <= 1'b0; vmaWRTESTCYCLE <= 1'b0; vmaWRITECYCLE <= 1'b0; vmaCACHEINH <= 1'b0; end else if (clken & memEN) begin if (`cromMEM_AREAD) begin vmaREADCYCLE <= `dromREADCYCLE; vmaWRTESTCYCLE <= `dromWRTESTCYCLE; vmaWRITECYCLE <= `dromWRITECYCLE; vmaCACHEINH <= 1'b0; end else if (`cromMEM_DPFUNC) begin vmaREADCYCLE <= dp[3]; vmaWRTESTCYCLE <= dp[4]; vmaWRITECYCLE <= dp[5]; vmaCACHEINH <= dp[7]; end else begin vmaREADCYCLE <= `cromMEM_READCYCLE; vmaWRTESTCYCLE <= `cromMEM_WRTESTCYCLE; vmaWRITECYCLE <= `cromMEM_WRITECYCLE; vmaCACHEINH <= `cromMEM_CACHEINH; end end end // // Fixup vmaFLAGS // assign vmaFLAGS[ 0] = vmaUSER; assign vmaFLAGS[ 1] = 1'b0; assign vmaFLAGS[ 2] = vmaFETCH; assign vmaFLAGS[ 3] = vmaREADCYCLE; assign vmaFLAGS[ 4] = vmaWRTESTCYCLE; assign vmaFLAGS[ 5] = vmaWRITECYCLE; assign vmaFLAGS[ 6] = 1'b0; assign vmaFLAGS[ 7] = vmaCACHEINH; assign vmaFLAGS[ 8] = vmaPHYSICAL; assign vmaFLAGS[ 9] = vmaPREVIOUS; assign vmaFLAGS[10] = vmaIOCYCLE; assign vmaFLAGS[11] = vmaWRUCYCLE; assign vmaFLAGS[12] = vmaVECTORCYCLE; assign vmaFLAGS[13] = vmaIOBYTECYCLE; endmodule Dist/rtl/ks10/cpu/vma.vh0000700000175100010010000000455212151540222013433 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Virtual Memory Address (VMA) Flag Definitions // // Details // Contains definitions that are useful to access VMA Flags // // File // vma.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __VMA_VH `define __VMA_VH // // VMA Flags // `define vmaUSER(reg) (reg[ 0]) // 1 = User Mode `define vmaEXEC(reg) (reg[ 1]) // 1 = Exec Mode `define vmaFETCH(reg) (reg[ 2]) // 1 = Instruction fetch `define vmaREADCYCLE(reg) (reg[ 3]) // 1 = Read Cycle (IO or Memory) `define vmaWRTESTCYCLE(reg) (reg[ 4]) // 1 = Perform write test for page fail `define vmaWRITECYCLE(reg) (reg[ 5]) // 1 = Write Cycle (IO or Memory) `define vmaUNUSED(reg) (reg[ 6]) // Spare/Unused bit `define vmaCACHEIHN(reg) (reg[ 7]) // 1 = Cache is inhibited `define vmaPHYSICAL(reg) (reg[ 8]) // 1 = Physical reference `define vmaPREVIOUS(reg) (reg[ 9]) // 1 = VMA Previous Context `define vmaIOCYCLE(reg) (reg[10]) // 1 = IO Cycle, 0 = Memory Cycle `define vmaWRUCYCLE(reg) (reg[11]) // 1 = Read interrupt controller number `define vmaVECTORCYCLE(reg) (reg[12]) // 1 = Read interrupt vector `define vmaIOBYTECYCLE(reg) (reg[13]) // 1 = Unibus Byte IO Operation `endif Dist/rtl/ks10/csl/0000700000175100010010000000000012151543336012303 5ustar RobNoneDist/rtl/ks10/csl/csl.v0000700000175100010010000003265012151540230013252 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS-10 Console // // Details // // Console Instruction Register (Device 0, IO Address 0200000) // // When the 'execute switch' is asserted at power-up the KS10 // microcode performs a IO read of the Console Instruction // Register (regIR) at IO address o200000 and then executes // that instruction. // // The Console Instruction Register is normally initialized // with a JRST instruction which causes the code to jump to // the entry point of the code/bootloader. // // This mechanism allowes the Console set the address that // the KS10 began execution. // // The JRST opcode is 0254. // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) |0 |1 |0 |1 |0 |1 |1 |0 |0 |0 |0 |0 |0 |0 |0 |0 |0 |0 | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | ADDRESS | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Console Address Register: // // The console can read from or write to KS10 memory and/or IO. // The address of the memory or IO location to be accessed is // placed in the Console Address Register prior to starting // the access. // // The format of the Console Address Register during Memory // Operations is: // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) |0 |0 |0 |RD|0 |WR|0 |0 |0 |0 |0 |0 |0 |0 |0 |0 |Addr | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | Memory Address | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // The format of the Console Address Register during IO // Operations is: // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) |0 |0 |0 |RD|0 |WR|0 |0 |0 |0 |1 |0 |0 |0 | DEV NO | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | IO Address | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Note: Bit 10 is asserted during IO operations and is // negated during Memory Operations. // // Note: 20-bit addressing of memory is supported. // // Console Data Register: // // Data to be written to Memory or IO is placed in the Console // Data Register. Similarly data that has been read from // from Memory or IO is placed in the Console Data Register. // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | DATA | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | DATA | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Console Memory Read Procedure // // The KS10 memory is read using the following procedure: // 1. The memory address is written to the Console Address // Register. The 'RD' bit should be asserted. The 'WR' // bit and the 'IO' bit should be negated. // 2. After the Console Address Register initialized, the // 'GO' bit of the Console Control/Status register should // be asserted. // 3. The state machine performs a read from memory and // places the results in the Console Data Register. The // 'GO' bit will remain asserted while the memory // transaction is active and will negate when the memory // transaction is completed. // // Console Memory Write Procedure // // The KS10 memory is written using the following procedure: // 1. The memory address is written to the Console Address // Register. The 'RD' bit should be asserted. The 'WR' // bit and the 'IO' bit should be negated. // 2. The data to be written to memory is written to the // Console Data Register. // 3. After the Console Address Register and Console Data // Register are both initialized, the 'GO' bit of the // Console Control/Status register should be asserted. // 4. The state machine performs a write to memory. The // 'GO' bit will remain asserted while the memory // transaction is active and will negate when the // memory transaction is completed. // // Console IO Read and Write Procedure // Console IO operations are similar to Console Memory // operations except that the IO bit in the Console // Address Register must be asserted and the IO address // must include the IO Device Number - which may be zero. // // Unibus IO Device Numbers are non-zero. Unibus IO // addresses are limited to 16-bits and therefore // Unibus IO addresses bits 18 and 19 must be zero. // // File // csl.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// module CSL(clk, rst, cslREGADDR, cslREGDATI, cslREGDATO, cslREGIR, cslBUSY, cslNXM, cslGO, busREQI, busREQO, busACKI, busACKO, busADDRI, busADDRO, busDATAI, busDATAO); input clk; // Clock input rst; // Reset input [0:35] cslREGADDR; // Console Address Register input [0:35] cslREGDATI; // Console Data Register In output [0:35] cslREGDATO; // Console Data Register Out input [0:35] cslREGIR; // Console Instructon Register input cslGO; // Console GO output cslBUSY; // Console BUSY output cslNXM; // Console NXM, NXD input busREQI; // Bus Request In output busREQO; // Bus Request Out input busACKI; // Bus Acknowledge In output busACKO; // Bus Acknowledge Out input [0:35] busADDRI; // Bus Address In output [0:35] busADDRO; // Bus Address Out input [0:35] busDATAI; // Bus Data In output [0:35] busDATAO; // Bus Data Out // // Console is Device 0 // parameter [0:3] cslDEV = 4'b0000; // // Console Instruction Register Address // parameter [18:35] addrCIR = 18'o200000; // // Memory Address and Flags // wire busREAD = busADDRI[ 3]; wire busWRITE = busADDRI[ 5]; wire busPHYSICAL = busADDRI[ 8]; wire busIO = busADDRI[10]; wire [14:17] busDEV = busADDRI[14:17]; wire [18:35] busADDR = busADDRI[18:35]; // // Console Instruction Register Read // wire cirREAD = busIO & busREAD & (busDEV == cslDEV) & (busADDR[18:35] == addrCIR); // // State Machine States // parameter [0:2] stateIDLE = 0, stateCHECK = 1, stateREAD = 2, stateWRITE = 3, stateFAIL = 4, stateDONE = 5; // // Read/Write State Machine // // Details // This creates 'backplane' bus cycles for the console to // read or write to KS10 IO or or KS10 memory. // // Like the KS10, the upper bits of the address bus are // used to control read/write and IO/memory. // reg [0:2] state; reg [0:9] timeout; always @(posedge clk or posedge rst) begin if (rst) begin timeout <= 0; state <= stateIDLE; end else case (state) stateIDLE : begin timeout <= 0; if ((cslGO & cslREGADDR[3]) | (cslGO & cslREGADDR[5])) state <= stateCHECK; end stateCHECK : if (timeout == 1023) state <= stateFAIL; else if (busACKI & cslREGADDR[3]) state <= stateREAD; else if (busACKI & cslREGADDR[5]) state <= stateWRITE; else timeout <= timeout + 1'b1; stateREAD : state <= stateDONE; stateWRITE : state <= stateDONE; stateFAIL : state <= stateDONE; stateDONE : state <= stateIDLE; endcase end // // Bus REQ // assign busREQO = ((state == stateCHECK) || (state == stateREAD ) || (state == stateWRITE)); // // Bus ACK // assign busACKO = cirREAD; // // NXM/NXD // assign cslNXM = (state == stateFAIL); // // BUSY // assign cslBUSY = (state != stateIDLE); // // Bus MUX // reg [0:35] busDATAO; always @(cirREAD or state or cslREGIR or cslREGDATI) begin if (cirREAD) busDATAO = cslREGIR; else if (state == stateWRITE) busDATAO = cslREGDATI; else busDATAO = 36'bx; end // // Print the Halt Status Block // `ifndef SYNTHESIS always @(posedge clk) begin if (busWRITE & ~busIO & busPHYSICAL) begin case (busADDR) 18'o000000 : begin $display(""); case (busDATAI[24:35]) 12'o0000 : $display("Microcode Startup."); 12'o0001 : $display("Halt Instruction."); 12'o0002 : $display("Console Halt."); 12'o0100 : $display("IO Page Failure."); 12'o0101 : $display("Illegal Interrupt Instruction."); 12'o0102 : $display("Pointer to Unibus Vector is zero."); 12'o1000 : $display("Illegal Microcode Dispatch."); 12'o1005 : $display("Microcode Startup Check Failed."); default : $display("Unknown Halt Cause."); endcase end 18'o000001 : $display("PC is %06o", busDATAI); 18'o376000 : $display("MAG is %06o", busDATAI); 18'o376001 : $display("PC is %06o", busDATAI); 18'o376002 : $display("HR is %06o", busDATAI); 18'o376003 : $display("AR is %06o", busDATAI); 18'o376004 : $display("ARX is %06o", busDATAI); 18'o376005 : $display("BR is %06o", busDATAI); 18'o376006 : $display("BRX is %06o", busDATAI); 18'o376007 : $display("ONE is %06o", busDATAI); 18'o376010 : $display("EBR is %06o", busDATAI); 18'o376011 : $display("UBR is %06o", busDATAI); 18'o376012 : $display("MSK is %06o", busDATAI); 18'o376013 : $display("FLG is %06o", busDATAI); 18'o376014 : $display("PI is %06o", busDATAI); 18'o376015 : $display("X1 is %06o", busDATAI); 18'o376016 : $display("TO is %06o", busDATAI); 18'o376017 : $display("T1 is %06o", busDATAI); 18'o376020 : $display("VMA is %06o", busDATAI); 18'o376021 : $display("FE is %06o", busDATAI); endcase end end `endif // // Bus Address Out is always set by Address Register // assign busADDRO = cslREGADDR; endmodule Dist/rtl/ks10/ks10.v0000700000175100010010000004116512151540230012467 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS10 System. The system consists of a CPU, a Bus Aribter, a // Memory Controller, and two Unibus Interfaces. // // Details // // File // ks10.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `include "ks10.vh" `include "uba/uba.vh" `include "uba/dz11/dz11.vh" `include "uba/rh11/rh11.vh" `default_nettype none module KS10(clk, rst, // DZ11 Interfaces dz11TXD, dz11RXD, dz11DTR, dz11CO, dz11RI, // RH11 Interfaces rh11CD, rh11WP, rh11MISO, rh11MOSI, rh11SCLK, rh11CS, rh11DEBUG, // Console Interfaces cslREGADDR, cslREGDATI, cslREGDATO, cslREGIR, cslBUSY, cslNXM, cslGO, cslRESET, cslSTEP, cslRUN, cslEXEC, cslCONT, cslHALT, cslTIMEREN, cslTRAPEN, cslCACHEEN, cslINTRI, cslINTRO, // CPU Interfaces cpuHALT, cpuRUN, cpuEXEC, cpuCONT, // SSRAM Interfaces ssramCLK, ssramCLKEN, ssramADV, ssramBWA_N, ssramBWB_N, ssramBWC_N, ssramBWD_N, ssramOE_N, ssramWE_N, ssramCE, ssramADDR, ssramDATA); parameter [14:17] ctlNUM1 = `ctlNUM1; parameter [14:17] ctlNUM3 = `ctlNUM3; input clk; // Clock input rst; // Reset // DZ11 Interfaces output [7: 0] dz11TXD; // DZ11 Transmitter Serial Data input [7: 0] dz11RXD; // DZ11 Receiver Serial Data input [7: 0] dz11CO; // DZ11 Carrier Detect Input input [7: 0] dz11RI; // DZ11 Ring Indicator Input output [7: 0] dz11DTR; // DZ11 Data Terminal Ready Output // RH11 Interfaces input rh11CD; // RH11 Card Detect input rh11WP; // RH11 Write Protect input rh11MISO; // RH11 Data In output rh11MOSI; // RH11 Data Out output rh11SCLK; // RH11 Clock output rh11CS; // RH11 Chip Select output [0:35] rh11DEBUG; // RH11 Debug // Console Interfaces input [0:35] cslREGADDR; // Console Address Register input [0:35] cslREGDATI; // Console Data Register In output [0:35] cslREGDATO; // Console Data Register Out input [0:35] cslREGIR; // Console Instruction Register output cslBUSY; // Console Busy output cslNXM; // Console NXM/NXD input cslGO; // Console Go input cslRESET; // Console Reset input cslSTEP; // Console Step input cslRUN; // Console Run input cslEXEC; // Console Exec input cslCONT; // Console Cont input cslHALT; // Console Halt input cslTIMEREN; // Console Timer Enable input cslTRAPEN; // Console Trap Enable input cslCACHEEN; // Console Cache Enable input cslINTRI; // Console Interrupt In output cslINTRO; // Console Interrupt Out // CPU Interfaces output cpuHALT; // CPU Halt output cpuRUN; // CPU Run output cpuEXEC; // CPU Exec output cpuCONT; // CPU Cont // SSRAM Interfaces output ssramCLK; // SSRAM Clock output ssramCLKEN; // SSRAM Clken output ssramADV; // SSRAM Advance output ssramBWA_N; // SSRAM BWA# output ssramBWB_N; // SSRAM BWB# output ssramBWC_N; // SSRAM BWC# output ssramBWD_N; // SSRAM BWD# output ssramOE_N; // SSRAM OE# output ssramWE_N; // SSRAM WE# output ssramCE; // SSRAM CE output [0:22] ssramADDR; // SSRAM Address Bus inout [0:35] ssramDATA; // SSRAM Data Bus // // Bus Arbiter Outputs // wire [0:35] arbADDRO; // Arbiter Address Out // // Console Interfaces // wire cslREQI; // Console Bus Request In wire cslREQO; // Console Bus Request Out wire cslACKI; // Console Bus Acknowledge In wire cslACKO; // Console Bus Acknowledge Out wire [0:35] cslADDRI; // Console Address In wire [0:35] cslADDRO; // Console Address Out wire [0:35] cslDATAI; // Console Data In wire [0:35] cslDATAO; // Console Data Out wire cslSTEP; // Console Single Step Switch wire cslCONT; // Console Continue Switch wire cslRUN; // Console Run Switch wire cslEXEC; // Console Exec Switch wire cslHALT; // Console Halt Switch wire cslTRAPEN; // Console Trap Enable wire cslTIMEREN; // Console Timer Enable wire cslCACHEEN; // Console Cache Enable // // CPU Interfaces // wire cpuREQO; // CPU Bus Request wire cpuACKI; // CPU Bus Acknowledge wire [0:35] cpuADDRO; // CPU Address Out wire [0:35] cpuDATAI; // CPU Data In wire [0:35] cpuDATAO; // CPU Data Out wire cpuHALT; // CPU Halt Status wire cpuRUN; // CPU Run Status wire cpuEXEC; // CPU Exec Status wire cpuCONT; // CPU Cont Status // // Memory Interfaces // wire [0:35] memDATAI; // Memory Data In wire [0:35] memDATAO; // Memory Data Out wire memREQ; // Memory REQ wire memACK; // Memory ACK // // Unibus Interfaces (x4) // wire [1: 7] ubaINTR; // Unibus Interrupt Request wire ubaREQI; // Unibus Bus Request In wire [0: 3] ubaREQO; // Unibus Bus Request Out wire [0: 3] ubaACKI; // Unibus Bus Acknowledge In wire [0: 3] ubaACKO; // Unibus Bus Acknowledge Out wire [0:35] ubaADDRO[0:3]; // Unibus Address Out wire [0:35] ubaDATAI; // Unibus Data In wire [0:35] ubaDATAO[0:3]; // Unibus Data Out wire [1: 7] ubaINTRO[0:3]; // Unibus Interrupt // // Bus Arbiter // ARB uARB (.clk (clk), // CPU .cpuREQI (cpuREQO), .cpuACKO (cpuACKI), .cpuADDRI (cpuADDRO), .cpuDATAI (cpuDATAO), .cpuDATAO (cpuDATAI), // Console .cslREQI (cslREQO), .cslREQO (cslREQI), .cslACKI (cslACKO), .cslACKO (cslACKI), .cslADDRI (cslADDRO), .cslDATAI (cslDATAO), .cslDATAO (cslDATAI), // Unibus .ubaREQI (ubaREQO), .ubaREQO (ubaREQI), .ubaACKI (ubaACKO), .ubaACKO (ubaACKI), .uba0ADDRI (ubaADDRO[0]), .uba1ADDRI (ubaADDRO[1]), .uba2ADDRI (ubaADDRO[2]), .uba3ADDRI (ubaADDRO[3]), .uba0DATAI (ubaDATAO[0]), .uba1DATAI (ubaDATAO[1]), .uba2DATAI (ubaDATAO[2]), .uba3DATAI (ubaDATAO[3]), .ubaDATAO (ubaDATAI), // Memory .memREQO (memREQ), .memACKI (memACK), .memDATAI (memDATAO), .memDATAO (memDATAI), // Arb .arbADDRO (arbADDRO) ); // // The KS10 CPU // CPU uCPU (.clk (clk), .rst (rst), // Console .cslRESET (cslRESET), .cslSTEP (cslSTEP), .cslRUN (cslRUN), .cslEXEC (cslEXEC), .cslCONT (cslCONT), .cslHALT (cslHALT), .cslTIMEREN (cslTIMEREN), .cslTRAPEN (cslTRAPEN), .cslCACHEEN (cslCACHEEN), .cslINTRI (cslINTRI), .cslINTRO (cslINTRO), // UBA .ubaINTR (ubaINTR), // CPU .cpuREQO (cpuREQO), .cpuACKI (cpuACKI), .cpuADDRO (cpuADDRO), .cpuDATAI (cpuDATAI), .cpuDATAO (cpuDATAO), .cpuHALT (cpuHALT), .cpuRUN (cpuRUN), .cpuEXEC (cpuEXEC), .cpuCONT (cpuCONT) ); // // Console // CSL uCSL (.clk (clk), .rst (rst), // Console Wrapper Interfaces .cslREGADDR (cslREGADDR), .cslREGDATI (cslREGDATI), .cslREGDATO (cslREGDATO), .cslREGIR (cslREGIR), .cslBUSY (cslBUSY), .cslNXM (cslNXM), .cslGO (cslGO), // KS10 Interfaces .busREQI (cslREQI), .busREQO (cslREQO), .busACKI (cslACKI), .busACKO (cslACKO), .busADDRI (arbADDRO), .busADDRO (cslADDRO), .busDATAI (cslDATAI), .busDATAO (cslDATAO) ); // // Memory // MEM uMEM (.clk (clk), .rst (rst), .clken (1'b1), .busREQI (memREQ), .busACKO (memACK), .busADDRI (arbADDRO), .busDATAI (memDATAI), .busDATAO (memDATAO), .ssramCLK (ssramCLK), .ssramCLKEN (ssramCLKEN), .ssramADV (ssramADV), .ssramBWA_N (ssramBWA_N), .ssramBWB_N (ssramBWB_N), .ssramBWC_N (ssramBWC_N), .ssramBWD_N (ssramBWD_N), .ssramOE_N (ssramOE_N), .ssramWE_N (ssramWE_N), .ssramCE (ssramCE), .ssramADDR (ssramADDR), .ssramDATA (ssramDATA) ); // // IO Bridge #1 // wire ctl1REQO; wire [ 0:35] ctl1ADDRO; wire [ 0:35] ctl1DATAO; wire [ 7: 4] ctl1INTA; wire ctl1RESET; wire ctl1rh1ACKO; wire rh1REQO; wire rh1ACKO; wire [ 0:35] rh1ADDRO; wire [ 0:35] rh1DATAO; wire [ 7: 4] rh1INTR; // // Stub Connected to IO Bridge 1 Device 2 // wire ctl1dev2REQI = 0; wire ctl1dev2ACKI = 0; wire [ 0:35] ctl1dev2ADDRI = 36'b0; wire [ 0:35] ctl1dev2DATAI = 36'b0; wire [ 7: 4] ctl1dev2INTR = 4'b0; wire ctl1dev2ACKO; UBA UBA1 (.clk (clk), .rst (rst), .clken (1'b1), .ctlNUM (ctlNUM1), .busREQI (ubaREQI), .busREQO (ubaREQO[1]), .busACKI (ubaACKI[1]), .busACKO (ubaACKO[1]), .busADDRI (arbADDRO), .busADDRO (ubaADDRO[1]), .busDATAI (ubaDATAI), .busDATAO (ubaDATAO[1]), .busINTR (ubaINTRO[1]), .devREQO (ctl1REQO), .devADDRO (ctl1ADDRO), .devDATAO (ctl1DATAO), .devINTA (ctl1INTA), .devRESET (ctl1RESET), .dev1REQI (rh1REQO), .dev1ACKI (rh1ACKO), .dev1ADDRI (rh1ADDRO), .dev1DATAI (rh1DATAO), .dev1INTR (rh1INTR), .dev1ACKO (ctl1rh1ACKO), .dev2REQI (ctl1dev2REQI), .dev2ACKI (ctl1dev2ACKI), .dev2ADDRI (ctl1dev2ADDRI), .dev2DATAI (ctl1dev2DATAI), .dev2INTR (ctl1dev2INTR), .dev2ACKO (ctl1dev2ACKO) ); // // RH11 #1 Connected to IO Bridge 1 Device 1 // RH11 uRH11 (.clk (clk), .rst (rst), .ctlNUM (ctlNUM1), // RH11 IO .rh11CD (rh11CD), .rh11WP (rh11WP), .rh11MISO (rh11MISO), .rh11MOSI (rh11MOSI), .rh11SCLK (rh11SCLK), .rh11CS (rh11CS), .rh11DEBUG (rh11DEBUG), // Reset .devRESET (ctl1RESET), // Interrupt .devINTR (rh1INTR), .devINTA (ctl1INTA), // Target .devREQI (ctl1REQO), .devACKO (rh1ACKO), .devADDRI (ctl1ADDRO), // Initiator .devREQO (rh1REQO), .devACKI (ctl1rh1ACKO), .devADDRO (rh1ADDRO), // Data .devDATAI (ctl1DATAO), .devDATAO (rh1DATAO) ); // // IO Bridge #3 // wire ctl3REQO; wire [ 0:35] ctl3ADDRO; wire [ 0:35] ctl3DATAO; wire [ 7: 4] ctl3INTA; wire ctl3RESET; wire ctl3dz1ACKO; wire dz1REQO; wire dz1ACKO; wire [ 0:35] dz1ADDRO; wire [ 0:35] dz1DATAO; wire [ 7: 4] dz1INTR; // // Stub Connected to IO Bridge 3 Device 2 // wire ctl3dev2REQI = 0; wire ctl3dev2ACKI = 0; wire [ 0:35] ctl3dev2ADDRI = 36'b0; wire [ 0:35] ctl3dev2DATAI = 36'b0; wire [ 7: 4] ctl3dev2INTR = 4'b0; wire ctl3dev2ACKO; UBA UBA3 (.clk (clk), .rst (rst), .clken (1'b1), .ctlNUM (ctlNUM3), .busREQI (ubaREQI), .busREQO (ubaREQO[3]), .busACKI (ubaACKI[3]), .busACKO (ubaACKO[3]), .busADDRI (arbADDRO), .busADDRO (ubaADDRO[3]), .busDATAI (ubaDATAI), .busDATAO (ubaDATAO[3]), .busINTR (ubaINTRO[3]), .devREQO (ctl3REQO), .devADDRO (ctl3ADDRO), .devDATAO (ctl3DATAO), .devINTA (ctl3INTA), .devRESET (ctl3RESET), .dev1REQI (dz1REQO), .dev1ACKI (dz1ACKO), .dev1ADDRI (dz1ADDRO), .dev1DATAI (dz1DATAO), .dev1INTR (dz1INTR), .dev1ACKO (ctl3dz1ACKO), .dev2REQI (ctl3dev2REQI), .dev2ACKI (ctl3dev2ACKI), .dev2ADDRI (ctl3dev2ADDRI), .dev2DATAI (ctl3dev2DATAI), .dev2INTR (ctl3dev2INTR), .dev2ACKO (ctl3dev2ACKO) ); // // DZ11 #1 Connected to IO Bridge 3 Device 1 // DZ11 uDZ11 (.clk (clk), .rst (rst), .ctlNUM (ctlNUM3), // DZ11 IO .dz11TXD (dz11TXD), .dz11RXD (dz11RXD), .dz11CO (dz11CO), .dz11RI (dz11RI), .dz11DTR (dz11DTR), // Reset .devRESET (ctl3RESET), // Interrupt .devINTR (dz1INTR), .devINTA (ctl3INTA), // Target .devREQI (ctl3REQO), .devACKO (dz1ACKO), .devADDRI (ctl3ADDRO), // Initiator .devREQO (dz1REQO), .devACKI (ctl3dz1ACKO), .devADDRO (dz1ADDRO), // Data .devDATAI (ctl3DATAO), .devDATAO (dz1DATAO) ); // // Interrupts // assign ubaINTR = ubaINTRO[0] | ubaINTRO[1] | ubaINTRO[2] | ubaINTRO[3]; // // Unused Unibus Devices // assign ubaREQO[0] = 0; assign ubaREQO[2] = 0; assign ubaACKO[0] = 0; assign ubaACKO[2] = 0; assign ubaADDRO[0] = 0; assign ubaADDRO[2] = 0; assign ubaDATAO[0] = 0; assign ubaDATAO[2] = 0; assign ubaINTRO[0] = 0; assign ubaINTRO[2] = 0; endmodule Dist/rtl/ks10/ks10.vh0000700000175100010010000000257112151540224012640 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // brief // KS10 definitions // // details // // todo // // file // ks10.vh // // author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __KS10_VH `define __KS10_VH `define CLKFRQ 50000000 // Clock Speed `endif Dist/rtl/ks10/mem/0000700000175100010010000000000012151543330012272 5ustar RobNoneDist/rtl/ks10/mem/mem.v0000700000175100010010000002035012151540230013236 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS-10 Memory Interface // // Details // This module is simply a wrapper for the external memory. // // Memory Status Register Write (IO addresses o100000) // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) |EH|UE|RE|PE| |PF| | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | | FCB |ED| // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Memory Status Register Read (IO addresses o100000) // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) |EH|UE|RE|PE|EE| ECP |PF| 0| ERA | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | ERA | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // // EH : Error Hold - Always read as 0. Writes // ignored. // UE : Uncorrectable Error - Always read as 0. Writes // ignored. // RE : Refresh Error - Always read as 0. Writes // ignored. // PE : Parity Error - Read/Writes PE bit. // EE : ECC Enable - Reads back inverse value set // by write to bit ED bit. // Writes ignored. See ED bit // below. // PF : Power Failure - Initialized to 1 at power-up, // Writing zero clears PF. // ED : ECC Disable - Always read as 0. // Writing zero sets EE bit, // Writing one clears EE bit. // FCB : Force Check Bits - Always read as 0. Writes // ignored. // ERA : Error Read Address - Always read as 0. Writes // ignored. // File // mem.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// // // Comments are formatted for doxygen // module MEM(clk, rst, clken, busREQI, busACKO, busADDRI, busDATAI, busDATAO, ssramCLK, ssramCLKEN, ssramADV, ssramBWA_N, ssramBWB_N, ssramBWC_N, ssramBWD_N, ssramOE_N, ssramWE_N, ssramCE, ssramADDR, ssramDATA); input clk; // Clock input rst; // Reset input clken; // Clock enable input busREQI; // Memory Request In output busACKO; // Memory Acknowledge Out input [0:35] busADDRI; // Address Address In input [0:35] busDATAI; // Data in output [0:35] busDATAO; // Data out output ssramCLK; // SSRAM Clock output ssramCLKEN; // SSRAM Clken output ssramADV; // SSRAM Advance (burst) output ssramBWA_N; // SSRAM BWA# output ssramBWB_N; // SSRAM BWB# output ssramBWC_N; // SSRAM BWC# output ssramBWD_N; // SSRAM BWD# output ssramOE_N; // SSRAM OE# output ssramWE_N; // SSRAM WE# output ssramCE; // SSRAM CE output [0:22] ssramADDR; // SSRAM Address Bus inout [0:35] ssramDATA; // SSRAM Data Bus // // Memory Status is Device 0 // wire [ 0: 3] memDEV = 4'b0000; // // Memory flags // // Details: // busADDRI[ 0:13] is flags // busADDRI[14:35] is address // wire busREAD = busADDRI[ 3]; wire busWRTEST = busADDRI[ 4]; wire busWRITE = busADDRI[ 5]; wire busIO = busADDRI[10]; wire [ 0: 3] busDEV = busADDRI[14:17]; wire [16:35] busADDR = busADDRI[16:35]; // // Memory Status Register (IO Address 100000) // // Details // Only the PE, EE, and PF change... and they are not really // implemented. // // FIXME: // SIMH igores writes to this register and reads zeros // always // reg statPE; // Parity Error reg statEE; // ECC Enabled reg statPF; // Power Failure always @(negedge clk or posedge rst) begin if (rst) begin statPE <= 1'b0; statEE <= 1'b1; statPF <= 1'b1; end else if (clken) begin if (busIO & busWRITE & (busDEV[0:3] == memDEV) & (busADDR == 18'o100000)) begin statPE <= busDATAI[ 3]; statPF <= busDATAI[12] & statPF; statEE <= ~busDATAI[35]; end end end wire [0:35] statREG = {3'b0, statPE, statEE, 7'b0, statPF, 23'b0}; // // Bus Multiplexer // // Details // This selects between SSRAM and the Memory Status Register. // // FIXME // Only 32K of memory is implemented. // reg busACKO; reg [0:35] busDATAO; always @(busIO or busADDR or busREAD or busWRITE or busWRTEST or ssramDATA or statREG) begin // // Memory Status Register // if (busIO & (busADDR == 18'o100000)) begin busACKO <= 1'b1; busDATAO <= statREG; `ifndef SYNTHESIS if (busREAD) $display("Memory Status Register Read.\n"); else if (busWRITE) $display("Memory Status Register Written.\n"); `endif end // // Memory // else if ((~busIO & busREAD & (busADDR < 32768)) | (~busIO & busWRITE ) | (~busIO & busWRTEST )) begin busACKO <= 1'b1; busDATAO <= ssramDATA; end // // Everything else. // else begin busACKO <= 1'b0; busDATAO <= ssramDATA; end end // // SSRAM Interface // assign ssramCLK = clk; assign ssramCLKEN = 1; assign ssramADV = 0; assign ssramBWA_N = 0; assign ssramBWB_N = 0; assign ssramBWC_N = 0; assign ssramBWD_N = 0; assign ssramOE_N = 0; assign ssramWE_N = ~(busWRITE & ~busIO); assign ssramCE = 1; assign ssramADDR = {3'b0, busADDR[16:35]}; assign ssramDATA = (~ssramWE_N) ? busDATAI : 36'bz; endmodule Dist/rtl/ks10/uba/0000700000175100010010000000000012151543077012273 5ustar RobNoneDist/rtl/ks10/uba/dz11/0000700000175100010010000000000012151543130013040 5ustar RobNoneDist/rtl/ks10/uba/dz11/dz11.v0000700000175100010010000004527512151540230014024 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS10 Processor // // Brief // DZ11 Asynchronous Terminal Multiplexer // // Details // The information used to design the DZ11 was obtained from the // following DEC docmument: // // DZ11 Asynchronous Multiplexer Technical Manual // DEC Publication EK-DZ110-TM-002 // // Notes // The KS10 is 36-bit big-endian and uses [0:35] notation. // // The 'Unibus' IO Bus is 16-bit little-endian and uses [15:0] // notation. Sorry about the mixed endian-ism. I didn't // create this stuff - I've just matched the exising notation. // // Whereas the 'Unibus' is 18-bit data and 16-bit address, I've // implemented the IO bus as 18-bit address and 36-bit data just // to keep things simple. // // File // dz11.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "dz11.vh" `include "../../ks10.vh" `include "uart/uart_brg.vh" module DZ11(clk, rst, ctlNUM, dz11TXD, dz11RXD, dz11CO, dz11RI, dz11DTR, devRESET, devINTR, devINTA, devREQI, devACKO, devADDRI, devREQO, devACKI, devADDRO, devDATAI, devDATAO); input clk; // Clock input rst; // Reset input [ 0: 3] ctlNUM; // Bridge Device Number // DZ11 Interfaces output [ 7: 0] dz11TXD; // DZ11 Transmitter Serial Data input [ 7: 0] dz11RXD; // DZ11 Receiver Serial Data input [ 7: 0] dz11CO; // DZ11 Carrier Detect Input input [ 7: 0] dz11RI; // DZ11 Ring Indicator Input output [ 7: 0] dz11DTR; // DZ11 Data Terminal Ready Output // Reset input devRESET; // IO Bus Bridge Reset // Interrupt output [ 7: 4] devINTR; // Interrupt Request input [ 7: 4] devINTA; // Interrupt Acknowledge // Target input devREQI; // Device Request In output devACKO; // Device Acknowledge Out input [ 0:35] devADDRI; // Device Address In // Initiator output devREQO; // Device Request Out input devACKI; // Device Acknowledge In output [ 0:35] devADDRO; // Device Address Out // Data input [ 0:35] devDATAI; // Data In output [ 0:35] devDATAO; // Data Out // // DZ Parameters // parameter [14:17] dzDEV = `dzDEV; // Device 3 parameter [18:35] dzADDR = `dz1ADDR; // DZ11 Base Address parameter [18:35] dzVECT = `dz1VECT; // DZ11 Interrupt Vector parameter [ 7: 4] dzINTR = `dzINTR; // DZ11 Interrupt // // DZ Register Addresses // parameter [18:35] csrADDR = dzADDR + `csrOFFSET; parameter [18:35] rbfADDR = dzADDR + `rbfOFFSET; parameter [18:35] lprADDR = dzADDR + `lprOFFSET; parameter [18:35] tcrADDR = dzADDR + `tcrOFFSET; parameter [18:35] msrADDR = dzADDR + `msrOFFSET; parameter [18:35] tdrADDR = dzADDR + `tdrOFFSET; // // DZ Interrupt Vectors // parameter [18:35] rxVECT = dzVECT; // DZ11 Receiver Interrupt Vector parameter [18:35] txVECT = dzVECT + 4; // DZ11 Transmitter Interrupt Vector // // Memory Address and Flags // // Details: // devADDRI[ 0:13] is flags // devADDRI[14:35] is address // wire devREAD = devADDRI[ 3]; // 1 = Read Cycle (IO or Memory) wire devWRITE = devADDRI[ 5]; // 1 = Write Cycle (IO or Memory) wire devIO = devADDRI[10]; // 1 = IO Cycle, 0 = Memory Cycle wire devVECT = devADDRI[12]; // 1 = Read interrupt vector wire devIOBYTE = devADDRI[13]; // 1 = Byte IO Operation wire [14:17] devDEV = devADDRI[14:17]; // Device Number wire [18:35] devADDR = devADDRI[18:35]; // Device Address wire devHIBYTE = devADDRI[35]; // Register High Byte wire devLOBYTE = ~devHIBYTE; // Register Low Byte // // Address Decoding // wire csrREAD = devIO & devREAD & (devDEV == dzDEV) & (devADDR[18:34] == csrADDR[18:34]); wire csrWRITE = devIO & devWRITE & (devDEV == dzDEV) & (devADDR[18:34] == csrADDR[18:34]); wire rbufREAD = devIO & devREAD & (devDEV == dzDEV) & (devADDR[18:34] == rbfADDR[18:34]) & ~devIOBYTE; wire lprWRITE = devIO & devWRITE & (devDEV == dzDEV) & (devADDR[18:34] == lprADDR[18:34]) & ~devIOBYTE; wire tcrREAD = devIO & devREAD & (devDEV == dzDEV) & (devADDR[18:34] == tcrADDR[18:34]); wire tcrWRITE = devIO & devWRITE & (devDEV == dzDEV) & (devADDR[18:34] == tcrADDR[18:34]); wire msrREAD = devIO & devREAD & (devDEV == dzDEV) & (devADDR[18:34] == msrADDR[18:34]); wire tdrWRITE = devIO & devWRITE & (devDEV == dzDEV) & (devADDR[18:34] == tdrADDR[18:34]); wire csrWRITEH = ((csrWRITE & devIOBYTE & devHIBYTE) | (csrWRITE & ~devIOBYTE)); wire csrWRITEL = ((csrWRITE & devIOBYTE & devLOBYTE) | (csrWRITE & ~devIOBYTE)); wire tcrWRITEH = ((tcrWRITE & devIOBYTE & devHIBYTE) | (tcrWRITE & ~devIOBYTE)); wire tcrWRITEL = ((tcrWRITE & devIOBYTE & devLOBYTE) | (tcrWRITE & ~devIOBYTE)); wire tdrWRITEH = ((tdrWRITE & devIOBYTE & devHIBYTE) | (tdrWRITE & ~devIOBYTE)); wire tdrWRITEL = ((tdrWRITE & devIOBYTE & devLOBYTE) | (tdrWRITE & ~devIOBYTE)); // // Interrupt Vector Read Operation // wire vectREAD = devIO & devVECT & (devDEV == ctlNUM); // // Big-endian to little-endian data bus fixup // wire [35:0] dzDATAI = devDATAI[0:35]; // // CSR[CLR] 15us one-shot // reg [9:0] clrCOUNT; always @(posedge clk or posedge rst or posedge devRESET) begin if (rst | devRESET) clrCOUNT <= 2; else begin if (csrWRITEL & dzDATAI[4]) clrCOUNT <= `CLKFRQ / 1000000 * 15; else if (csrCLR) clrCOUNT <= clrCOUNT - 1'b1; end end wire csrCLR = (clrCOUNT != 0); wire regRESET = csrCLR; // // CSR Register // // Details // The CSR is read/write and can be accessed as bytes or words. // reg csrTRDY; reg csrTIE; reg csrSAE; reg csrRIE; reg csrMSE; reg [2:0] csrTLINE; reg csrMAINT; always @(posedge clk or posedge regRESET) begin if (regRESET) begin csrTRDY <= 0; csrTIE <= 0; csrSAE <= 0; csrRIE <= 0; csrMSE <= 0; csrTLINE <= 0; csrMAINT <= 0; end else begin // // Write to high byte // if (csrWRITEH) begin csrTIE <= dzDATAI[14]; csrSAE <= dzDATAI[12]; end // // Write to low byte // if (csrWRITEL) begin csrRIE <= dzDATAI[ 6]; csrMSE <= dzDATAI[ 5]; csrMAINT <= dzDATAI[ 3]; end // // Transmitter Scan // if (csrTRDY & tdrWRITEL) csrTRDY <= 0; else if (tcrLIN[scan] & ttyTXEMPTY[scan]) begin csrTRDY <= 1; csrTLINE <= scan; end end end wire [15:0] regCSR = {csrTRDY, csrTIE, csrSA, csrSAE, 1'b0, csrTLINE, csrRDONE, csrRIE, csrMSE, csrCLR, csrMAINT, 3'b0}; // // Line Enable Decoder // reg [7:0] tlineMUX; always @(csrTLINE) begin case (csrTLINE) 0: tlineMUX <= 8'b0000_0001; 1: tlineMUX <= 8'b0000_0010; 2: tlineMUX <= 8'b0000_0100; 3: tlineMUX <= 8'b0000_1000; 4: tlineMUX <= 8'b0001_0000; 5: tlineMUX <= 8'b0010_0000; 6: tlineMUX <= 8'b0100_0000; 7: tlineMUX <= 8'b1000_0000; endcase end // // RBUF Register // // Details // RBUF is read only and can only be read as words // wire [15:0] regRBUF = rbufDATA; // // LPR Register // // Details // LPR is write-only and can only be written as words. // reg lprRXON; always @(posedge clk or posedge regRESET) begin if (regRESET) begin lprRXON <= 0; end else if (lprWRITE) begin lprRXON <= dzDATAI[12]; end end // // TCR Reguster // // Details // TCR is read/write and can be accessed as bytes or words // // The DTR registers are not reset by CSR[CLR]. // reg [7:0] tcrDTR; reg [7:0] tcrLIN; always @(posedge clk or posedge rst or posedge devRESET) begin if (rst | devRESET) begin tcrDTR <= 0; tcrLIN <= 0; end else if (csrCLR) begin tcrLIN <= 0; end else begin if (tcrWRITEH) tcrDTR <= dzDATAI[15:8]; if (tcrWRITEL) tcrLIN <= dzDATAI[ 7:0]; end end wire [15:0] regTCR = {tcrDTR, tcrLIN}; assign dz11DTR = tcrDTR; // // MSR Register // // Details // MSR can be accessed as bytes or words // wire [15:0] regMSR = {dz11CO, dz11RI}; // // TDR Register // // Details // TDR is write-only and can be accessed as bytes or words // // Note // The Break circuitry is not implemented // wire [7:0] ttyTXDATA = dzDATAI[7:0]; wire [7:0] ttyTXLOAD = (tdrWRITEL) ? (tlineMUX & tcrLIN) : 8'b0; // // Scanner // // Details // This just increments the scan signal. // reg [2:0] scan; always @(posedge clk or posedge rst or posedge csrCLR) begin if (rst | csrCLR) scan <= 0; else if (csrMSE) scan <= scan + 1'b1; end // // Scan Decoder // // Details // This decodes the scan variable. // reg [7:0] scanMUX; always @(scan) begin case (scan) 0: scanMUX <= 8'b0000_0001; 1: scanMUX <= 8'b0000_0010; 2: scanMUX <= 8'b0000_0100; 3: scanMUX <= 8'b0000_1000; 4: scanMUX <= 8'b0001_0000; 5: scanMUX <= 8'b0010_0000; 6: scanMUX <= 8'b0100_0000; 7: scanMUX <= 8'b1000_0000; endcase end // // Maintenance Loopback // // Details: // When CSR[MAINT] is asserted, the transmitter is looped // back to the receiver. // wire [7:0] ttyRXD = (csrMAINT) ? dz11TXD : dz11RXD; // // Clear receiver full flag // // Details: // If the receiver is full, empty the receiver into the // RXFIFO and clear the full flag. // wire [7:0] ttyRXCLR = scanMUX & ttyRXFULL; // // UART Baud Rate Generators // // Details // For now the UARTS are fixed programmed to 9600 baud // wire clkBR; UART_BRG ttyBRG (.clk (clk), .rst (rst | devRESET), .brgSEL (`BR115200), .brgCLKEN (clkBR) ); // // Generate Array of UARTS // // Details // The 'generate' loops below builds 8 UARTS. // // Note // For some reason, Xilinx ISE requires that the // genvar line is inside the generate statement. // Other tools don't seem to care. // wire [7:0] ttyRXFULL; // UART receiver has data wire [7:0] ttyRXDATA[0:7]; // UART received data wire [7:0] ttyTXEMPTY; // UART transmitter buffer is empty generate genvar i; for (i = 0; i < 8; i = i + 1) begin : uart_loop // // UART Transmitters // UART_BUFTX ttyTX (.clk (clk), .rst (rst | devRESET), .clkBR (lprRXON & clkBR), .load (ttyTXLOAD[i]), .data (ttyTXDATA), .empty (ttyTXEMPTY[i]), .txd (dz11TXD[i]) ); // // UART Receivers // UART_BUFRX ttyRX (.clk (clk), .rst (rst | devRESET), .clkBR (clkBR), .clr (ttyRXCLR[i]), .rxd (ttyRXD[i]), .full (ttyRXFULL[i]), .data (ttyRXDATA[i]) ); end endgenerate // // Read FIFO edge trigger // // Details: // The FIFO state is updated on the trailing edge of the read // pulse; i.e., after the read is completed. // wire fifoREAD; EDGETRIG uFIFOREAD(clk, rst, 1'b1, 1'b0, rbufREAD, fifoREAD); // // RBUF FIFO // wire [15:0] rbufDATA; wire fifoEMPTY; wire fifoWRITE = ttyRXFULL[scan]; DZFIFO uDZFIFO (.clk (clk), .rst (rst | csrCLR | devRESET), .din ({scan, ttyRXDATA[scan]}), .wr (fifoWRITE), .dout (rbufDATA), .rd (fifoREAD), .empty (fifoEMPTY) ); wire csrRDONE = ~fifoEMPTY; // // SILO Alarm Counter // reg [0:4] depth; always @(posedge clk or posedge regRESET) begin if (regRESET) depth <= 0; else if (fifoREAD) depth <= 0; else if (fifoWRITE) depth <= depth + 1'b1; end // // SILO Alarm // reg csrSA; always @(posedge clk or posedge regRESET) begin if (regRESET) csrSA <= 0; else if (fifoREAD) csrSA <= 0; else if (depth == 16) csrSA <= 1; end // // TX Interrupts // wire intTX; wire intTX0 = csrTRDY & csrTIE; EDGETRIG uINTTX(clk, rst, 1'b1, 1'b0, intTX0, intTX); // // RX Interrupts // wire intRX; wire intRX0 = ((~csrSAE & csrRDONE & csrRIE) | (csrSAE & csrSA & csrRIE)); EDGETRIG uINTRX(clk, rst, 1'b1, 1'b0, intRX0, intRX); // // Receiver Interrupts // // Details: // This process generates the receiver interrupt from the silo // alarm and from the receiver done register bits. // // Notes: // The receiver interrupt is cleared when: // 1. Reset // 2. IO Bus Reset // 3. CSR[CLR] // 4. Receiver interrupts are disabled // 5. The interrupt is acknowledged // reg dzRXINTR; always @(posedge clk or posedge regRESET) begin if (regRESET) dzRXINTR <= 0; else if (devINTA & dzINTR) dzRXINTR <= 0; else if (intRX) dzRXINTR <= 1; end // // Transmiter Interrupts // // Details: // This process generates the transmitter interrupt from the // transmitter ready register bit. // // Notes: // The transmitter interrupt is cleared when: // 1. Reset // 2. IO Bus Reset // 3. CSR[CLR] // 4. Transmitter interrupts are disabled // 5. The interrupt is acknowledged // reg dzTXINTR; always @(posedge clk or posedge regRESET) begin if (regRESET) dzTXINTR <= 0; else if (devINTA & dzINTR) dzTXINTR <= 0; else if (intTX) dzTXINTR <= 1; end // // Vector Type // reg dzRXVECT; always @(posedge clk or posedge regRESET) begin if (regRESET) dzRXVECT <= 0; else if (intRX) dzRXVECT <= 1; else if (intTX) dzRXVECT <= 0; end // // Bus Mux and little-endian to big-endian bus swap. // reg devACKO; reg [0:35] devDATAO; always @(csrREAD or csrWRITE or regCSR or rbufREAD or lprWRITE or regRBUF or tcrREAD or tcrWRITE or regTCR or msrREAD or tdrWRITE or regMSR or vectREAD or dzRXVECT or rxVECT or txVECT) begin devACKO = 0; devDATAO = 36'bx; if (csrREAD | csrWRITE) begin devACKO = 1; devDATAO = {20'b0, regCSR}; end if (rbufREAD | lprWRITE) begin devACKO = 1; devDATAO = {20'b0, regRBUF}; end if (tcrREAD | tcrWRITE) begin devACKO = 1; devDATAO = {20'b0, regTCR}; end if (msrREAD | tdrWRITE) begin devACKO = 1; devDATAO = {20'b0, regMSR}; end if (vectREAD) begin if (dzRXVECT) begin devACKO = 1; devDATAO = rxVECT; end else begin devACKO = 1; devDATAO = txVECT; end end end // // DZ11 Device Interface // assign devINTR = (dzRXINTR | dzTXINTR) ? dzINTR : 4'b0; assign devADDRO = 0; assign devREQO = 0; endmodule Dist/rtl/ks10/uba/dz11/dz11.vh0000700000175100010010000000464512151540222014171 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // DZ11 definitions // // Details // // Todo // // File // dz11.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __DZ11_VH `define __DZ11_VH // // DZ Device and Interrupt // `define dzDEV 4'd3 // Device 3 `define dzINTR 4'b0010 // Interrupt 5 // // DZ Register Address offsets // `define csrOFFSET 3'd0 // CSR Offset (RW) `define rbfOFFSET 3'd2 // RBUF Offset (RO) `define lprOFFSET 3'd2 // LPR Offset (WO) `define tcrOFFSET 3'd4 // TCR Offset (RW) `define msrOFFSET 3'd6 // MSR Offset (RO) `define tdrOFFSET 3'd6 // TDR Offset (WO) // // DZ #1 parameters // `define dz1VECT 36'o000000_000340 // Interrupt Vector `define dz1ADDR 18'o760010 // Base Address // // DZ #2 parameters // `define dz2VECT 36'o000000_000350 // Interrupt Vector `define dz2ADDR 18'o760020 // Base Address // // DZ #3 parameters // `define dz3VECT 36'o000000_000360 // Interrupt Vector `define dz3ADDR 18'o760030 // Base Address // // DZ #4 parameters // `define dz4VECT 36'o000000_000370 // Interrupt Vector `define dz4ADDR 18'o760040 // Base Address `endif Dist/rtl/ks10/uba/dz11/dzfifo.v0000700000175100010010000000766412151540230014526 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // DZ-11 SILO/FIFO // // Details // // File // dzfifo.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none module DZFIFO(clk, rst, din, wr, dout, rd, empty); input clk; // Clock input rst; // Reset input [10:0] din; // Data input input wr; // Push data into FIFO output [15:0] dout; // Data output input rd; // Pop data from FIFO output empty; // FIFO Empty // // FIFO State // reg [0:6] depth; reg [0:6] rd_ptr; reg [0:6] wr_ptr; always @(posedge clk or posedge rst) begin if (rst) begin rd_ptr <= 0; wr_ptr <= 0; depth <= 0; end else if (rd & ~wr & (depth != 0)) begin if (rd_ptr == 64) rd_ptr <= 0; else rd_ptr <= rd_ptr + 1'b1; depth <= depth - 1'b1; end else if (wr & ~rd & (depth != 64)) begin if (wr_ptr == 64) wr_ptr <= 0; else wr_ptr <= wr_ptr + 1'b1; depth <= depth + 1'b1; end end // // Full/Empty Flag // reg full; reg empty; always @(posedge clk or posedge rst) begin if (rst) begin full <= 0; empty <= 1; end else if (depth == 0) begin if (wr & ~rd) empty <= 0; else if (rd & ~wr) empty <= 1; end else if (depth == 64) begin if (wr & ~rd) full <= 1; else if (rd & ~wr) full <= 0; end end // // Overrun // reg overrun; always @(posedge clk or posedge rst) begin if (rst) overrun <= 0; else if (rd & empty) overrun <= 0; else if (wr & full) overrun <= 1; end // // Dual Port RAM // `ifndef SYNTHESIS integer i; `endif reg [10:0] DPRAM[0:64]; reg [10:0] fifoDATA; always @(posedge clk or posedge rst) begin if (rst) `ifdef SYNTHESIS ; `else for (i = 0; i < 65; i = i + 1) DPRAM[i] <= 0; `endif else begin if (wr) DPRAM[wr_ptr] <= din; fifoDATA <= DPRAM[rd_ptr]; end end // // FIFO Output // wire fifoOVR = (depth == 0) ? overrun : 0; assign dout = {~empty, fifoOVR, 3'b0, fifoDATA}; endmodule Dist/rtl/ks10/uba/dz11/uart/0000700000175100010010000000000012151543137014022 5ustar RobNoneDist/rtl/ks10/uba/dz11/uart/uart_brg.v0000700000175100010010000000601712151540230016014 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // DZ11 UART Baud Rate Generator // // Details // // File // uart_brg.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "uart_brg.vh" `include "../../../ks10.vh" module UART_BRG(clk, rst, brgSEL, brgCLKEN); parameter clkfrq = `CLKFRQ; // 50 MHz parameter clkdiv = `CLKDIV; // 16x Clock input clk; // Clock input rst; // Reset input [0:2] brgSEL; // Speed Select output brgCLKEN; // BRG Clock Enable // // Programmable Clock Divider. // // Details // This process generates a clkBR signal that is suitable for // use as a 16x Baud Rate clock. Both UART Transmitters and // UART Receivers require this 16x clock. // reg brgCLKEN; reg [0:31] count; always @(posedge clk or posedge rst) begin if (rst) begin brgCLKEN <= 0; count <= 0; end else if (count == 0) begin case (brgSEL) `BR1200 : count <= clkfrq/clkdiv/1200; // 1,200 (-0.016% `BR2400 : count <= clkfrq/clkdiv/2400; // 2,400 (-0.032%) `BR4800 : count <= clkfrq/clkdiv/4800; // 4,800 (-0.032%) `BR9600 : count <= clkfrq/clkdiv/9600; // 9,600 (+0.16%) `BR19200 : count <= clkfrq/clkdiv/19200; // 19,200 (+0.16%) `BR38400 : count <= clkfrq/clkdiv/38400; // 38,400 (+0.16%) `BR57600 : count <= clkfrq/clkdiv/57600; // 57,600 (+0.94%) `BR115200 : count <= clkfrq/clkdiv/115200; // 115,200 (+1.35%) endcase brgCLKEN <= 1; end else begin count <= count - 1'b1; brgCLKEN <= 0; end end endmodule Dist/rtl/ks10/uba/dz11/uart/uart_brg.vh0000700000175100010010000000305612151540222016165 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // brief // DZ11 UART Baud Rate Generator // // details // // todo // // file // uart_brg.vh // // author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __UART_BRG_VH `define __UART_BRG_VH `define CLKDIV 16 `define BR1200 3'd0 `define BR2400 3'd1 `define BR4800 3'd2 `define BR9600 3'd3 `define BR19200 3'd4 `define BR38400 3'd5 `define BR57600 3'd6 `define BR115200 3'd7 `endifDist/rtl/ks10/uba/dz11/uart/uart_bufrx.v0000700000175100010010000000470212151540230016367 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Double Buffered UART Receiver // // Details // // Note // // File // uart_bufrx.vhd // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2009-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// module UART_BUFRX(clk, rst, clkBR, clr, rxd, full, data); input clk; // Clock input rst; // Reset input clkBR; // Clock Enable from BRG input clr; // Clear Receiver input rxd; // Receiver Serial Data output full; // Buffer is full output [7:0] data; // Receiver Data // // Full Flag // // Details // This process maintains the receiver status // reg full; // Full flag wire intr; // Data available from receiver always @(posedge clk or posedge rst) begin if (rst) full <= 0; else begin if (clr) full <= 0; else if (intr) full <= 1; end end // // Unbuffered Receiver // UART_RX uUART_RX (.clk (clk), .rst (rst), .clkBR (clkBR), .rxd (rxd), .intr (intr), .data (data) ); endmodule Dist/rtl/ks10/uba/dz11/uart/uart_buftx.v0000700000175100010010000001047412151540230016374 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Double Buffered UART Transmitter // // Details // // Note // // File // uart_buftx.vhd // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2009-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// module UART_BUFTX(clk, rst, clkBR, load, data, empty, txd); input clk; // Clock input rst; // Reset input clkBR; // Clock Enable from BRG input [7:0] data; // Transmitter Data input load; // Load Transmitter output empty; // Buffer is empty output txd; // Transmitter Serial Data // // State machine states // parameter [0:1] stateEMPTY = 0, // Empty stateUART = 1, // Character in UART stateBUF = 2; // Character buffered and in UART // // State machine // wire txintr; reg [0:1] state; reg [0:7] txbuf; reg [0:7] txdata; always @(posedge clk or posedge rst) begin if (rst) begin txbuf <= 0; txdata <= 0; state <= stateEMPTY; end else case (state) stateEMPTY: begin if (load) begin txdata <= data; state <= stateUART; end end stateUART: begin if (load & ~txintr) begin txbuf <= data; state <= stateBUF; end if (txintr & ~load) begin txdata <= txbuf; state <= stateEMPTY; end if (txintr & load) begin txbuf <= data; txdata <= txbuf; state <= stateUART; end end stateBUF: begin if (txintr & ~load) begin state <= stateUART; end else if (txintr & load) begin txbuf <= data; txdata <= txbuf; state <= stateBUF; end end endcase end // // Generate load signal // // Details // The txload is delayed by a clock cycle so that the // data can be buffered into txdata or txbuf. // reg txload; always @(posedge clk or posedge rst) begin if (rst) txload <= 0; else txload <= load; end // // Unbuffered Transmitter // UART_TX uUART_TX (.clk (clk), .rst (rst), .clkBR (clkBR), .data (txdata), .load (txload), .intr (txintr), .txd (txd) ); // // Status // assign empty = (state == stateEMPTY); endmodule Dist/rtl/ks10/uba/dz11/uart/uart_rx.v0000700000175100010010000003007312151540230015672 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // brief // Generic UART Receiver // // Details // The UART Receiver is hard configured for: // - 8 data bits // - no parity // - 1 stop bit // // Note // This UART primitive receiver is kept simple intentionally and // is therefore unbuffered. If you require a double buffered UART, // then you will need to layer a set of buffers on top of this // device. // // File // uart_rx.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2009, 2010, 2011, 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// module UART_RX(clk, rst, clkBR, rxd, intr, data); input clk; // Clock input rst; // Reset input clkBR; // Clock Enable from BRG input rxd; // Receiver Serial Data output intr; // Data ready output [7:0] data; // Received Data // // State machine states // parameter [3:0] stateIDLE = 0, // Idle stateSYNC = 1, // Wait for Start Bit stateSTART = 2, // Working on Start Bit stateBIT0 = 3, // Working on Bit 7 stateBIT1 = 4, // Working on Bit 6 stateBIT2 = 5, // Working on Bit 5 stateBIT3 = 6, // Working on Bit 4 stateBIT4 = 7, // Working on Bit 3 stateBIT5 = 8, // Working on Bit 2 stateBIT6 = 9, // Working on Bit 1 stateBIT7 = 10, // Working on Bit 0 stateSTOP = 11, // Working on Stop Bit stateDONE = 12; // Generate Interrupt // // Synchronize the Received Data to this clock domain. // reg temp; reg rxdd; always @(posedge clk or posedge rst) begin if (rst) begin temp <= 1; rxdd <= 1; end else begin temp <= rxd; rxdd <= temp; end end // // UART Receiver // // Details // The clkBR is 16 clocks per bit. The UART receives LSB first. // // The state machine is initialized to the idle state where it // looks for a start bit. When it find the 'edge' of the start // bit starts the state machine which does the following: // // - Continuously sample the start bit for half a bit period. // If the start bit is narrower than half a bit then, go back // to the idle state and look for a real start bit. Othewise, // - Delay one bit time from the middle of the Start bit and // sample bit D7 (LSB), then // - Delay one bit time from the middle of D7 and sample bit D6, then // - Delay one bit time from the middle of D6 and sample bit D5, then // - Delay one bit time from the middle of D5 and sample bit D4, then // - Delay one bit time from the middle of D4 and sample bit D3, then // - Delay one bit time from the middle of D3 and sample bit D2, then // - Delay one bit time from the middle of D2 and sample bit D1, then // - Delay one bit time from the middle of D1 and sample bit D0, then // - Delay one bit time from the middle of D0 and sample Stop // Bit, then // - Generate INTR pulse for one clock cycle, then // - Go back to idle state and wait for a start bit. // reg [3:0] state; reg [7:0] rxREG; reg [3:0] brdiv; always @(posedge clk or posedge rst) begin if (rst) begin state <= stateIDLE; rxREG <= 0; brdiv <= 0; end else case (state) // // Receiver is waiting for IDLE condition // stateIDLE: begin if (rxdd) begin state <= stateSYNC; end end // // Wait for edge of Start bit // stateSYNC: begin if (clkBR) begin if (~rxdd) begin state <= stateSTART; brdiv <= 8; end end end // // Receive Start Bit // stateSTART: begin if (clkBR) begin if (~rxdd) begin if (brdiv == 0) begin brdiv <= 15; state <= stateBIT0; end else begin brdiv <= brdiv - 1'b1; end end else begin state <= stateIDLE; end end end // // Receive Bit 0 (LSB) // stateBIT0: begin if (clkBR) begin if (brdiv == 0) begin brdiv <= 15; rxREG <= {rxdd, rxREG[7:1]}; state <= stateBIT1; end else begin brdiv <= brdiv - 1'b1; end end end // // Receive Bit 1 // stateBIT1: begin if (clkBR) begin if (brdiv == 0) begin brdiv <= 15; rxREG <= {rxdd, rxREG[7:1]}; state <= stateBIT2; end else begin brdiv <= brdiv - 1'b1; end end end // // Receive Bit 2 // stateBIT2: begin if (clkBR) begin if (brdiv == 0) begin brdiv <= 15; rxREG <= {rxdd, rxREG[7:1]}; state <= stateBIT3; end else begin brdiv <= brdiv - 1'b1; end end end // // Receive Bit 3 // stateBIT3: begin if (clkBR) begin if (brdiv == 0) begin brdiv <= 15; rxREG <= {rxdd, rxREG[7:1]}; state <= stateBIT4; end else begin brdiv <= brdiv - 1'b1; end end end // // Receive Bit 4 // stateBIT4: begin if (clkBR) begin if (brdiv == 0) begin brdiv <= 15; rxREG <= {rxdd, rxREG[7:1]}; state <= stateBIT5; end else begin brdiv <= brdiv - 1'b1; end end end // // Receive Bit 5 // stateBIT5: begin if (clkBR) begin if (brdiv == 0) begin brdiv <= 15; rxREG <= {rxdd, rxREG[7:1]}; state <= stateBIT6; end else begin brdiv <= brdiv - 1'b1; end end end // // Receive Bit 6 // stateBIT6: begin if (clkBR) begin if (brdiv == 0) begin brdiv <= 15; rxREG <= {rxdd, rxREG[7:1]}; state <= stateBIT7; end else begin brdiv <= brdiv - 1'b1; end end end // // Receive Bit 7 (MSB) // stateBIT7: begin if (clkBR) begin if (brdiv == 0) begin brdiv <= 15; rxREG <= {rxdd, rxREG[7:1]}; state <= stateSTOP; end else begin brdiv <= brdiv - 1'b1; end end end // // Receive Stop Bit // stateSTOP: begin if (clkBR) begin if (brdiv == 0) begin if (rxdd) state <= stateDONE; else state <= stateIDLE; end else begin brdiv <= brdiv - 1'b1; end end end // // Generate Interrupt // stateDONE: begin state <= stateIDLE; end // // Everything else // default: begin state <= stateIDLE; end endcase end assign intr = (state == stateDONE); assign data = rxREG; endmodule Dist/rtl/ks10/uba/dz11/uart/uart_tx.v0000700000175100010010000002114012151540230015667 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Generic UART Transmitter // // Details // The UART Transmitter is hard configured for: // - 8 data bits // - no parity // - 1 stop bit // // To transmit a word of data, provide the data on the data // bus and assert the 'load' input for a clock cycle. When // the data is sent, the 'intr' output will be asserted for // a single clock cycle. // // Note // This UART primitive transmitter is kept simple ntentionally and // is therefore unbuffered. If you require a double buffered UART, // then you will need to layer a set of buffers on top of this // device. // // File // uart_tx.vhd // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2009, 2010, 2011, 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// module UART_TX(clk, rst, clkBR, load, intr, data, txd); input clk; // Clock input rst; // Reset input clkBR; // Clock Enable from BRG input [7:0] data; // Transmitter Data input load; // Load Transmitter output intr; // Data ready output txd; // Transmitter Serial Data // // State machine states // parameter [3:0] stateIDLE = 0, // Idle stateSTART = 1, // Working on Start Bit stateBIT0 = 2, // Working on Bit 7 stateBIT1 = 3, // Working on Bit 6 stateBIT2 = 4, // Working on Bit 5 stateBIT3 = 5, // Working on Bit 4 stateBIT4 = 6, // Working on Bit 3 stateBIT5 = 7, // Working on Bit 2 stateBIT6 = 8, // Working on Bit 1 stateBIT7 = 9, // Working on Bit 0 stateSTOP = 10, // Working on Stop Bit stateDONE = 11; // Generate Interrupt // // UART Transmitter: // // The clkBR is 16 clocks per bit. The UART transmits LSB first. // // When the load input is asserted, the data is loaded into the // Transmit Register and the state machine is started. // // Once the state machine is started, it proceeds as follows: // // - Send Start Bit, then // - Send bit 7 (LSB) // - Send bit 6 // - Send bit 5 // - Send bit 4 // - Send bit 3 // - Send bit 2 // - Send bit 1 // - Send bit 0 (MSB) // - Send Stop Bit 1 // - Trigger Interrupt output // reg [3:0] state; reg [7:0] txREG; reg [3:0] brdiv; always @(posedge clk or posedge rst) begin if (rst) begin state <= stateIDLE; txREG <= 0; brdiv <= 0; end else case (state) // // Transmitter is Idle // stateIDLE: if (load) begin brdiv <= 15; txREG <= data; state <= stateSTART; end // // Transmit Start Bit // stateSTART: if (clkBR) if (brdiv == 0) begin brdiv <= 15; state <= stateBIT0; end else brdiv <= brdiv - 1'b1; // // Transmit Bit 0 (LSB) // stateBIT0: if (clkBR) if (brdiv == 0) begin brdiv <= 15; state <= stateBIT1; end else brdiv <= brdiv - 1'b1; // // Transmit Bit 1 // stateBIT1: if (clkBR) if (brdiv == 0) begin brdiv <= 15; state <= stateBIT2; end else brdiv <= brdiv - 1'b1; // // Transmit Bit 2 // stateBIT2: if (clkBR) if (brdiv == 0) begin brdiv <= 15; state <= stateBIT3; end else brdiv <= brdiv - 1'b1; // // Transmit Bit 3 // stateBIT3: if (clkBR) if (brdiv == 0) begin brdiv <= 15; state <= stateBIT4; end else brdiv <= brdiv - 1'b1; // // Transmit Bit 4 // stateBIT4: if (clkBR) if (brdiv == 0) begin brdiv <= 15; state <= stateBIT5; end else brdiv <= brdiv - 1'b1; // // Transmit Bit 5 // stateBIT5: if (clkBR) if (brdiv == 0) begin brdiv <= 15; state <= stateBIT6; end else brdiv <= brdiv - 1'b1; // // Transmit Bit 6 // stateBIT6: if (clkBR) if (brdiv == 0) begin brdiv <= 15; state <= stateBIT7; end else brdiv <= brdiv - 1'b1; // // Transmit Bit 7 (MSB) // stateBIT7: if (clkBR) if (brdiv == 0) begin brdiv <= 15; state <= stateSTOP; end else brdiv <= brdiv - 1'b1; // // Transmit Stop Bit // stateSTOP: if (clkBR) if (brdiv == 0) state <= stateDONE; else brdiv <= brdiv - 1'b1; // // Generate Interrupt // stateDONE: state <= stateIDLE; // // Everything else // default: state <= stateIDLE; endcase end // // Data selector for TXD // reg txdata; always @(state or txREG) begin case (state) stateSTART : txdata = 0; stateBIT0 : txdata = txREG[0]; stateBIT1 : txdata = txREG[1]; stateBIT2 : txdata = txREG[2]; stateBIT3 : txdata = txREG[3]; stateBIT4 : txdata = txREG[4]; stateBIT5 : txdata = txREG[5]; stateBIT6 : txdata = txREG[6]; stateBIT7 : txdata = txREG[7]; default : txdata = 1; endcase end // // Interrupt // assign intr = (state == stateDONE); assign txd = txdata; endmodule Dist/rtl/ks10/uba/lp20/0000700000175100010010000000000012042650002013032 5ustar RobNoneDist/rtl/ks10/uba/rh11/0000700000175100010010000000000012151543103013034 5ustar RobNoneDist/rtl/ks10/uba/rh11/rh11.v0000700000175100010010000005471612151540230014014 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS-10 RH11 // // Details // // Notes // Unibus is little-endian and uses [15:0] notation // KS10 is big-endian and uses [0:35] notation. // // The addressing big-endian from the KS10. // The data bus little-endian from Unibus. Confusing? Sorry. // // File // rh11.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "rpxx.vh" `include "rh11.vh" `include "sd/sd.vh" module RH11(clk, rst, ctlNUM, rh11CD, rh11WP, rh11MISO, rh11MOSI, rh11SCLK, rh11CS, rh11DEBUG, devRESET, devINTR, devINTA, devREQI, devACKO, devADDRI, devREQO, devACKI, devADDRO, devDATAI, devDATAO); input clk; // Clock input rst; // Reset input [ 0: 3] ctlNUM; // Bridge Device Number // RH11 Interfaces input rh11CD; // RH11 Card Detect input rh11WP; // RH11 Write Protect input rh11MISO; // RH11 Data In output rh11MOSI; // RH11 Data Out output rh11SCLK; // RH11 Clock output rh11CS; // RH11 Chip Select output [ 0:35] rh11DEBUG; // RH11 Debug Output // Reset input devRESET; // IO Bus Bridge Reset // Interrupt output [ 7: 4] devINTR; // Interrupt Request input [ 7: 4] devINTA; // Interrupt Acknowledge // Target input devREQI; // Device Request In output devACKO; // Device Acknowledge Out input [ 0:35] devADDRI; // Device Address In // Initiator output devREQO; // Device Request Out input devACKI; // Device Acknowledge In output [ 0:35] devADDRO; // Device Address Out // Data input [ 0:35] devDATAI; // Data In output [ 0:35] devDATAO; // Data Out // // RH Parameters // parameter [ 7: 4] rhINTR = `rhINTR; // Interrupt 5 parameter [14:17] rhDEV = `rhDEV; // Device 3 parameter [18:35] rhADDR = `rh1ADDR; // RH11 #1 Base Address // // RH Register Addresses // parameter [18:35] cs1ADDR = rhADDR + `cs1OFFSET; // Massbus Addr 00 parameter [18:35] wcADDR = rhADDR + `wcOFFSET; // RH Register parameter [18:35] baADDR = rhADDR + `baOFFSET; // RH Register parameter [18:35] daADDR = rhADDR + `daOFFSET; // Massbus Addr 05 parameter [18:35] cs2ADDR = rhADDR + `cs2OFFSET; // RH Register parameter [18:35] dsADDR = rhADDR + `dsOFFSET; // Massbus Addr 01 parameter [18:35] er1ADDR = rhADDR + `er1OFFSET; // Massbus Addr 02 parameter [18:35] asADDR = rhADDR + `asOFFSET; // Massbus Addr 04 (Pseudo Reg) parameter [18:35] laADDR = rhADDR + `laOFFSET; // Massbus Addr 07 parameter [18:35] dbADDR = rhADDR + `dbOFFSET; // RH Register parameter [18:35] mrADDR = rhADDR + `mrOFFSET; // Massbus Addr 03 parameter [18:35] dtADDR = rhADDR + `dtOFFSET; // Massbus Addr 06 parameter [18:35] snADDR = rhADDR + `snOFFSET; // Massbus Addr 10 parameter [18:35] ofADDR = rhADDR + `ofOFFSET; // Massbus Addr 11 parameter [18:35] dcADDR = rhADDR + `dcOFFSET; // Massbus Addr 12 parameter [18:35] ccADDR = rhADDR + `ccOFFSET; // Massbus Addr 13 parameter [18:35] er2ADDR = rhADDR + `er2OFFSET; // Massbus Addr 14 parameter [18:35] er3ADDR = rhADDR + `er3OFFSET; // Massbus Addr 15 parameter [18:35] ec1ADDR = rhADDR + `ec1OFFSET; // Massbus Addr 16 parameter [18:35] ec2ADDR = rhADDR + `ec2OFFSET; // Massbus Addr 17 // // Memory Address and Flags // // Details: // devADDRI[ 0:13] is flags // devADDRI[14:35] is address // wire devREAD = devADDRI[ 3]; // 1 = Read Cycle (IO or Memory) wire devWRITE = devADDRI[ 5]; // 1 = Write Cycle (IO or Memory) wire devIO = devADDRI[10]; // 1 = IO Cycle, 0 = Memory Cycle wire devIOBYTE = devADDRI[13]; // 1 = Byte IO Operation wire [14:17] devDEV = devADDRI[14:17]; // Device Number wire [18:34] devADDR = devADDRI[18:34]; // Device Address wire devBYTE = devADDRI[35]; // 1 = High byte, 0 = low byte // // Big-endian to little-endian data bus swap // wire [35:0] rhDATAI = devDATAI[0:35]; // // Write Decoder // wire rhcs1WRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == cs1ADDR[18:34]); wire rhcs2WRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == cs2ADDR[18:34]); wire rhwcWRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == wcADDR[18:34]); wire rhbaWRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == baADDR[18:34]); wire rhdbWRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == dbADDR[18:34]); wire rhasWRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == asADDR[18:34]); // // Byte Selects // wire devHIBYTE = (devIOBYTE & devBYTE) | ~devIOBYTE; wire devLOBYTE = (devIOBYTE & ~devBYTE) | ~devIOBYTE; // // Clear Signal // CSR2[CLR] // wire rhCLR = rhcs2WRITE & rhDATAI[5]; // // Transfer Error Clear // wire treCLR = rhcs1WRITE & rhDATAI[14]; // // Clear Command // wire goCLR = rhcs1WRITE & (rhDATAI[5:1] == `funCLEAR) & rhDATAI[0] & rhRDY; // // RH11 Control/Status #1 (RHCS1) Register // reg rhTRE; reg rhPSEL; reg rhRDY; reg rhIE; reg rhIFF; reg lastWCE; reg lastPE; reg lastNEM; reg lastPGE; reg lastMXF; reg lastRDY; always @(posedge clk) begin if (rst | rhCLR | devRESET) begin rhTRE <= 0; rhPSEL <= 0; rhRDY <= 1; rhIE <= 0; rhIFF <= 0; lastWCE <= 0; lastPE <= 0; lastNEM <= 0; lastPGE <= 0; lastMXF <= 0; lastRDY <= 0; end else if (rhcs1WRITE) begin if (devHIBYTE) begin rhPSEL <= rhDATAI[10]; if (rhDATAI[14]) begin rhTRE <= 0; end end if (devLOBYTE) begin rhIE <= rhDATAI[6]; end end if (goCLR) begin rhTRE <= 0; end else if ((rhWCE & ~lastWCE) | (rhPE & ~lastPE) | (rhNEM & ~lastNEM) | (rhPGE & ~lastNEM) | (rhMXF & ~lastMXF)) begin rhTRE <= 1; end // // Done Interrupt Flip-flop // Set on transition or RDY from 0 -> 1 // Cleared by interrupt acknowledge // if (devINTA == rhINTR) begin rhIFF <= 0; end else if (rhRDY & ~lastRDY) begin rhIFF <= rhIE; end lastWCE <= rhWCE; lastPE <= rhPE; lastNEM <= rhNEM; lastPGE <= rhPGE; lastMXF <= rhMXF; lastRDY <= rhRDY; end wire rhSC = (rhTRE | rpDS[0][15] | rpDS[1][15] | rpDS[2][15] | rpDS[3][15] | rpDS[4][15] | rpDS[5][15] | rpDS[6][15] | rpDS[7][15]); wire rhMCPE = 0; wire rhDVA = 1; wire [ 5:1] rhFUN = rpFUN[rhUNITSEL]; wire rhGO = rpGO[rhUNITSEL]; wire [15:0] rhCS1 = {rhSC, rhTRE, rhMCPE, 1'b1, rhDVA, rhPSEL, rhBA[17:16], rhRDY, rhIE, rhFUN, rhGO}; // // RH11 Word Count (RHWC) Register // reg [15:0] rhWC; always @(posedge clk) begin if (rst | rhCLR | devRESET) begin rhWC <= 0; end else if (rhwcWRITE) begin if (devHIBYTE) begin rhWC[15:8] <= rhDATAI[15:8]; end if (devLOBYTE) begin rhWC[7:0] <= rhDATAI[7:0]; end end else if (sdINCWD) begin rhWC <= rhWC + 1'b1; end end // // RH11 Bus Address (RHBA) Register // reg [17:0] rhBA; always @(posedge clk) begin if (rst | rhCLR | devRESET) begin rhBA[17:0] <= 0; end else if (rhbaWRITE) begin if (devHIBYTE) begin rhBA[15:8] <= rhDATAI[15:8]; end if (devLOBYTE) begin rhBA[7:0] <= rhDATAI[7:0]; end end else if (rhcs1WRITE) begin if (devHIBYTE) begin rhBA[17:16] <= rhDATAI[9:8]; end end else if (sdINCWD & ~rhBAI) begin rhBA <= rhBA + 2'd2; end end // // RH11 Control/Status #2 (RHCS2) Register // reg rhWCE; reg rhPE; reg rhNEM; reg rhPGE; reg rhMXF; reg rhPAT; reg rhBAI; reg [2:0] rhUNIT; wire setWCE = 0; wire setNEM = 0; always @(posedge clk) begin if (rst | rhCLR | devRESET) begin rhWCE <= 0; rhPE <= 0; rhNEM <= 0; rhPGE <= 0; rhMXF <= 0; rhPAT <= 0; rhBAI <= 0; rhUNIT <= 0; end else if (treCLR) begin rhWCE <= 0; rhPE <= 0; rhNEM <= 0; rhPGE <= 0; rhMXF <= 0; end else if (goCLR) begin rhWCE <= 0; rhPE <= 0; rhNEM <= 0; rhMXF <= 0; end else if (rhcs2WRITE) begin if (devHIBYTE) begin rhPE <= rhDATAI[13]; rhMXF <= rhDATAI[ 9]; end if (devLOBYTE) begin rhPAT <= rhDATAI[4]; rhBAI <= rhDATAI[3]; rhUNIT <= rhDATAI[2:0]; end end if (setWCE) begin rhWCE <= 1; end if (setNEM) begin rhNEM <= 1; end end wire rhDLT = 0; // CS2[15] : Device Late wire rhNED = 0; // CS2[12] : Non-Existent Device (not implemented) wire rhMDPE = 0; // CS2[ 8] : Massbus Data Parity Error (not implemented) wire rhOR = 1; // CS2[ 7] : Output Ready wire rhIR = 1; // CS2[ 6] : Input Ready wire [15:0] rhCS2 = {rhDLT, rhWCE, rhPE, rhNED, rhNEM, rhPGE, rhMXF, rhMDPE, rhOR, rhIR, 1'b0, rhPAT, rhBAI, rhUNIT}; // // RH11 Data Buffer (RHDB) Register // reg [15:0] rhDB; always @(posedge clk) begin if (rst | rhCLR | devRESET) begin rhDB <= 0; end else if (rhdbWRITE) begin if (devHIBYTE) begin rhDB[15:8] <= rhDATAI[15:8]; end if (devLOBYTE) begin rhDB[7:0] <= rhDATAI[7:0]; end end end // // Attention Summary Pseudo Register // wire [ 7:0] ataCLR = (rhasWRITE) ? rhDATAI[7:0] : 8'b0; wire [15:0] rhAS = {8'b0, rpDS[7][15], rpDS[6][15], rpDS[5][15], rpDS[4][15], rpDS[3][15], rpDS[2][15], rpDS[1][15], rpDS[0][15]}; // // Completion Monitor // // Details: // The Completion Monitor scans the disk drives (round robbin) and // checks for drives that are requesting access to the SD Controller. // parameter [2:0] stateSCAN = 0, stateBUSY = 1, stateACK = 2; reg [2:0] state; reg [2:0] scan; always @(posedge clk) begin if (rst) begin scan <= 0; state <= stateSCAN; end else begin case (state) stateSCAN: begin if (rpSDREQ[sdUNITSEL]) begin if (rpSDOP[sdUNITSEL] == `sdopNOP) state <= stateACK; else state <= stateBUSY; end else begin scan <= scan + 1'b1; end end // // // stateBUSY: begin end // // ACK the RP so that it will complete it's operation and // become ready for the next operation. // stateACK: begin state <= stateSCAN; end endcase end end // // Unit Select Decoder for Registers // reg [7:0] rhUNITSEL; always @(rhUNIT) begin case (rhUNIT) 0: rhUNITSEL <= 8'b0000_0001; 1: rhUNITSEL <= 8'b0000_0010; 2: rhUNITSEL <= 8'b0000_0100; 3: rhUNITSEL <= 8'b0000_1000; 4: rhUNITSEL <= 8'b0001_0000; 5: rhUNITSEL <= 8'b0010_0000; 6: rhUNITSEL <= 8'b0100_0000; 7: rhUNITSEL <= 8'b1000_0000; endcase end // // Unit Select Decoder for Completion Monitor // reg [7:0] sdUNITSEL; always @(scan) begin case (scan) 0: sdUNITSEL <= 8'b0000_0001; 1: sdUNITSEL <= 8'b0000_0010; 2: sdUNITSEL <= 8'b0000_0100; 3: sdUNITSEL <= 8'b0000_1000; 4: sdUNITSEL <= 8'b0001_0000; 5: sdUNITSEL <= 8'b0010_0000; 6: sdUNITSEL <= 8'b0100_0000; 7: sdUNITSEL <= 8'b1000_0000; endcase end // // Generate ACK for the correct disk drive // assign rpSDACK[0] = ((scan == 0) & (state == stateACK)); assign rpSDACK[1] = ((scan == 1) & (state == stateACK)); assign rpSDACK[2] = ((scan == 2) & (state == stateACK)); assign rpSDACK[3] = ((scan == 3) & (state == stateACK)); assign rpSDACK[4] = ((scan == 4) & (state == stateACK)); assign rpSDACK[5] = ((scan == 5) & (state == stateACK)); assign rpSDACK[6] = ((scan == 6) & (state == stateACK)); assign rpSDACK[7] = ((scan == 7) & (state == stateACK)); // // Build Array 8 RP Register Sets // wire [15: 0] rpSN [7:0]; // SN Register wire [15: 0] rpDA [7:0]; // DA Register wire [15: 0] rpDS [7:0]; // DS Register wire [15: 0] rpER1 [7:0]; // ER1 Register wire [15: 0] rpLA [7:0]; // LA Register wire [15: 0] rpMR [7:0]; // MR Register wire [15: 0] rpOF [7:0]; // OF Register wire [15: 0] rpDC [7:0]; // DC Register wire [15: 0] rpCC [7:0]; // CC Register wire [ 5: 1] rpFUN [7:0]; // CS1[FUN] Register wire rpGO [7:0]; // CS1[GO] Register wire [ 1: 0] rpSDOP [7:0]; // SD Operation wire [31: 0] rpSDADDR[7:0]; // SD Sector Address wire [ 7: 0] rpSDREQ; // RP is ready for SD wire [ 7: 0] rpSDACK; // SD is done with RP wire simTIME = 0; // wire sdINCWD = 0; // SD has transferred a word wire sdINCSECT; // assign rpSN[0] = `rpSN0; assign rpSN[1] = `rpSN1; assign rpSN[2] = `rpSN2; assign rpSN[3] = `rpSN3; assign rpSN[4] = `rpSN4; assign rpSN[5] = `rpSN5; assign rpSN[6] = `rpSN6; assign rpSN[7] = `rpSN7; // // Build Array 8 RPxx (RP06 in this case) disk drives // genvar i; generate for (i = 0; i < 8; i = i + 1) begin : disk_loop RPXX uRPXX (.clk (clk), .rst (rst | rhCLR | devRESET), .simTIME (simTIME), .lastSECT (`rp06LASTSECT), .lastSURF (`rp06LASTSURF), .lastCYL (`rp06LASTCYL), .unitSEL (rhUNITSEL[i]), .incSECTOR(sdINCSECT), .rhCLR (rhCLR), .ataCLR (ataCLR[i]), .devRESET (devRESET), .devADDRI (devADDRI), .rhDATAI (rhDATAI), .rpCD (rh11CD), .rpWP (rh11WP), .rpDA (rpDA[i]), .rpDS (rpDS[i]), .rpER1 (rpER1[i]), .rpLA (rpLA[i]), .rpMR (rpMR[i]), .rpOF (rpOF[i]), .rpDC (rpDC[i]), .rpCC (rpCC[i]), .rpFUN (rpFUN[i]), .rpGO (rpGO[i]), .rpSDOP (rpSDOP[i]), .rpSDREQ (rpSDREQ[i]), .rpSDACK (rpSDACK[i]), .rpSDADDR (rpSDADDR[i]) ); end endgenerate // // SD Controller // `ifdef notyet wire sdSTAT; SD uSD (.clk (clk), .rst (rst), .sdMISO (rh11MISO), .sdMOSI (rh11MOSI), .sdSCLK (rh11SCLK), .sdCS (rh11CS), .sdREQ (rpSDREQ[sdUNITSEL]), .sdOP (rpSDOP[sdUNITSEL]), .sdSECTADDR(rpSDADDR[sdUNITSEL]), .sdWDCNT (rhWC), //here //.sdBUSADDR (sdBUSADDR), .dmaDATAI (devDATAI), .dmaDATAO (devDATAO), .dmaADDR (devADDR), .dmaREQ (devREQO), .dmaACK (devACKI), .sdINCWD (sdINCWD), .sdINCSECT (sdINCSECT), .sdSTAT (sdSTAT), .sdDEBUG (rh11DEBUG) ); `endif // // Demux Disk Array Registers // wire [15:0] muxRPDA = rpDA[rhUNITSEL]; wire [15:0] muxRPDS = rpDS[rhUNITSEL]; wire [15:0] muxRPER1 = rpER1[rhUNITSEL]; wire [15:0] muxRPLA = rpLA[rhUNITSEL]; wire [15:0] muxRPMR = rpMR[rhUNITSEL]; wire [15:0] muxRPSN = rpSN[rhUNITSEL]; wire [15:0] muxRPOF = rpOF[rhUNITSEL]; wire [15:0] muxRPDC = rpDC[rhUNITSEL]; wire [15:0] muxRPCC = rpCC[rhUNITSEL]; // // Bus Mux and little-endian to big-endian bus swap. // reg devACKO; reg [0:35] devDATAO; always @(devREAD or devIO or devDEV or rhDEV or devADDR or rhCS1 or rhWC or rhBA or muxRPDA or rhCS2 or muxRPDS or muxRPER1 or rhAS or muxRPLA or rhDB or muxRPMR or muxRPSN or muxRPOF or muxRPDC or muxRPCC) begin if (devREAD & devIO & (devDEV == rhDEV)) begin case (devADDR) cs1ADDR[18:34]: devDATAO = {20'b0, rhCS1}; wcADDR[18:34] : devDATAO = {20'b0, rhWC}; baADDR[18:34]: devDATAO = {18'b0, rhBA}; daADDR[18:34]: devDATAO = {20'b0, muxRPDA}; cs2ADDR[18:34]: devDATAO = {20'b0, rhCS2}; dsADDR[18:34]: devDATAO = {20'b0, muxRPDS}; er1ADDR[18:34]: devDATAO = {20'b0, muxRPER1}; asADDR[18:34]: devDATAO = {20'b0, rhAS}; laADDR[18:34]: devDATAO = {20'b0, muxRPLA}; dbADDR[18:34]: devDATAO = {20'b0, rhDB}; mrADDR[18:34]: devDATAO = {20'b0, muxRPMR}; dtADDR[18:34]: devDATAO = {20'b0, `rpRP06}; snADDR[18:34]: devDATAO = {20'b0, muxRPSN}; ofADDR[18:34]: devDATAO = {20'b0, muxRPOF}; dcADDR[18:34]: devDATAO = {20'b0, muxRPDC}; ccADDR[18:34]: devDATAO = {20'b0, muxRPCC}; er2ADDR[18:34], er3ADDR[18:34], ec1ADDR[18:34], ec2ADDR[18:34]: devDATAO = 36'b0; default: devDATAO = 36'b0; endcase devACKO = 1; end else begin devDATAO = 36'b0; devACKO = 0; end end // // Interrupt Request // assign devINTR = (rhIFF | (rhSC & rhRDY & rhIE)) ? rhINTR : 4'b0; endmodule Dist/rtl/ks10/uba/rh11/rh11.vh0000700000175100010010000000507012151540222014152 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // RH11 definitions // // Details // // Todo // // File // rh11.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __RH11_VH `define __RH11_VH // // RH Device and Interrupt // `define rhDEV 4'd1 // Device 1 `define rhINTR 4'b0100 // Interrupt 6 // // RH Register Address offsets // `define cs1OFFSET 6'o00 // CS1 Offset `define wcOFFSET 6'o02 // WC Offset `define baOFFSET 6'o04 // BA Offset `define daOFFSET 6'o06 // DA Offset `define cs2OFFSET 6'o10 // CS2 Offset `define dsOFFSET 6'o12 // DS Offset `define er1OFFSET 6'o14 // ER1 Offset `define asOFFSET 6'o16 // AS Offset `define laOFFSET 6'o20 // LA Offset `define dbOFFSET 6'o22 // DB Offset `define mrOFFSET 6'o24 // MR Offset `define dtOFFSET 6'o26 // DT Offset `define snOFFSET 6'o30 // SN Offset `define ofOFFSET 6'o32 // OF Offset `define dcOFFSET 6'o34 // DC rOffset `define ccOFFSET 6'o36 // HR Offset `define er2OFFSET 6'o40 // ER2 Offset `define er3OFFSET 6'o42 // ER2 Offset `define ec1OFFSET 6'o44 // EC1 Offset `define ec2OFFSET 6'o46 // EC2 Offset `define undOFFSET 6'o50 // Undefined // // RH #1 parameters // `define rh1VECT 18'o000254 // Interrupt Vector `define rh1ADDR 18'o776700 // Base Address `endif Dist/rtl/ks10/uba/rh11/rpxx.v0000700000175100010010000010136112151540230014227 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS-10 RP Style Disk Drive // // Details // // Notes // Unibus is little-endian and uses [15:0] notation // KS10 is big-endian and uses [0:35] notation. // // File // rpxx.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "rh11.vh" `include "rpxx.vh" `include "sd/sd.vh" module RPXX(clk, rst, lastSECT, lastSURF, lastCYL, simTIME, unitSEL, incSECTOR, rhCLR, ataCLR, devRESET, devADDRI, rhDATAI, rpCD, rpWP, rpDA, rpDS, rpER1, rpLA, rpMR, rpOF, rpDC, rpCC, rpFUN, rpGO, rpSDOP, rpSDREQ, rpSDACK, rpSDADDR); input clk; // Clock input rst; // Reset input simTIME; // Simulate Timing input [ 4: 0] lastSECT; // Last Sectors input [ 4: 0] lastSURF; // Last Surfaces input [ 9: 0] lastCYL; // Last Cylinder input unitSEL; // Unit Select input incSECTOR; // Increment Sector input rhCLR; // Clear input ataCLR; // Clear RPDS[ATA] input devRESET; // Device Reset input [ 0:35] devADDRI; // Device Address In input [35: 0] rhDATAI; // Data In input rpCD; // Card Detect from SD Card input rpWP; // Write Protect from SD Card output [15: 0] rpDA; // DA Register output [15: 0] rpDS; // DS Register output [15: 0] rpER1; // ER1 Register output [15: 0] rpLA; // LA Register output [15: 0] rpMR; // MR Register output [15: 0] rpOF; // OF Register output [15: 0] rpDC; // DC Register output [15: 0] rpCC; // CC Register output [ 5: 1] rpFUN; // CS1[FUN] Register output rpGO; // CS1[GO] Register output [ 1: 0] rpSDOP; // SD Operation output rpSDREQ; // SD Request input rpSDACK; // SD Complete Acknowledge output [31: 0] rpSDADDR; // SD Sector Address // // RH Parameters // parameter [14:17] rhDEV = `rhDEV; // Device 3 parameter [18:35] rhADDR = `rh1ADDR; // RH11 #1 Base Address // // RH Register Addresses // parameter [18:35] cs1ADDR = rhADDR + `cs1OFFSET; parameter [18:35] wcADDR = rhADDR + `wcOFFSET; parameter [18:35] baADDR = rhADDR + `baOFFSET; parameter [18:35] daADDR = rhADDR + `daOFFSET; parameter [18:35] cs2ADDR = rhADDR + `cs2OFFSET; parameter [18:35] dsADDR = rhADDR + `dsOFFSET; parameter [18:35] er1ADDR = rhADDR + `er1OFFSET; parameter [18:35] asADDR = rhADDR + `asOFFSET; parameter [18:35] laADDR = rhADDR + `laOFFSET; parameter [18:35] dbADDR = rhADDR + `dbOFFSET; parameter [18:35] mrADDR = rhADDR + `mrOFFSET; parameter [18:35] dtADDR = rhADDR + `dtOFFSET; parameter [18:35] snADDR = rhADDR + `snOFFSET; parameter [18:35] ofADDR = rhADDR + `ofOFFSET; parameter [18:35] dcADDR = rhADDR + `dcOFFSET; parameter [18:35] ccADDR = rhADDR + `ccOFFSET; parameter [18:35] er2ADDR = rhADDR + `er2OFFSET; parameter [18:35] er3ADDR = rhADDR + `er3OFFSET; parameter [18:35] ec1ADDR = rhADDR + `ec1OFFSET; parameter [18:35] ec2ADDR = rhADDR + `ec2OFFSET; parameter [18:35] undADDR = rhADDR + `undOFFSET; // // Timing Parameters parameter [24:0] fiveMS = 100000; // 5 milliseconds parameter [24:0] oneUS = 50; // 1 microsecond // // Register Decode // wire rpcsWRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == cs1ADDR[18:34]); wire rpdaWRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == daADDR[18:34]); wire rperWRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == er1ADDR[18:34]); wire rpofWRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == ofADDR[18:34]); wire rpdcWRITE = devWRITE & devIO & (devDEV == rhDEV) & (devADDR == dcADDR[18:34]); // // Function to calculate disk seek delay // The RP06 has 815 cyclinders // function [24:0] seekDELAY; input [9:0] newCYL; // New Cylinder input [9:0] oldCYL; // Old Cylinder reg [9:0] diffCYL; // Distance between Cylinders begin diffCYL = (newCYL > oldCYL) ? newCYL - oldCYL : oldCYL - newCYL; if (diffCYL < 1) seekDELAY = 0; // 0 ms, Same cylinder else if (diffCYL < 1) seekDELAY = fiveMS * 1; // 5 ms else if (diffCYL < 2) seekDELAY = fiveMS * 2; // 10 ms else if (diffCYL < 3) seekDELAY = fiveMS * 3; // 15 ms else if (diffCYL < 7) seekDELAY = fiveMS * 4; // 20 ms else if (diffCYL < 13) seekDELAY = fiveMS * 5; // 25 ms else if (diffCYL < 25) seekDELAY = fiveMS * 6; // 30 ms else if (diffCYL < 50) seekDELAY = fiveMS * 7; // 35 ms else if (diffCYL < 100) seekDELAY = fiveMS * 8; // 40 ms else if (diffCYL < 200) seekDELAY = fiveMS * 9; // 45 ms else if (diffCYL < 400) seekDELAY = fiveMS * 10; // 50 ms else seekDELAY = fiveMS * 11; // 55 ms end endfunction // // Memory Address and Flags // // Details: // devADDRI[ 0:13] is flags // devADDRI[14:35] is address // wire devREAD = devADDRI[ 3]; // 1 = Read Cycle (IO or Memory) wire devWRITE = devADDRI[ 5]; // 1 = Write Cycle (IO or Memory) wire devIO = devADDRI[10]; // 1 = IO Cycle, 0 = Memory Cycle wire devIOBYTE = devADDRI[13]; // 1 = Byte IO Operation wire [14:17] devDEV = devADDRI[14:17]; // Device Number wire [18:34] devADDR = devADDRI[18:34]; // Device Address wire devBYTE = devADDRI[35]; // 1 = High byte, 0 = low byte // // Byte Selects // wire devHIBYTE = (devIOBYTE & devBYTE) | ~devIOBYTE; wire devLOBYTE = (devIOBYTE & ~devBYTE) | ~devIOBYTE; // // rpGO // wire cmdGO = devLOBYTE & devWRITE & devIO & (devDEV == rhDEV) & (devADDR == cs1ADDR[18:34]) & rhDATAI[0]; // // State Definition // parameter [4:0] stateIDLE = 0, stateSEEK = 1, stateSEEKDLY = 2, stateROTDLY = 3, stateWAITSD = 4, stateCLEAR = 5, stateOFFSET = 6, stateRETURN = 7, statePRESET = 8, statePAKACK = 9, stateILLFUN = 10, stateINVADDR = 11, stateWRLOCK = 12, stateATA = 13, stateDONE = 31; reg [ 4: 0] state; // RPxx State // // RPxx Control/Status (RPCS1) Register // reg rpGO; reg [5:1] rpFUN; always @(posedge clk) begin if (rst | rhCLR | devRESET) begin rpGO <= 0; rpFUN <= 0; end else if (rpcsWRITE & unitSEL) begin if (devLOBYTE & rpDRY) begin rpFUN <= rhDATAI[5:1]; rpGO <= rhDATAI[ 0]; end end else if (state == stateDONE) begin rpGO <= 0; end end // // RPxx Disk Address (RPDA) Register // // Details // The disk address is incremented after the sector has been // transferred to the controller // reg [2:0] rpTAS; reg [4:0] rpTA; reg [2:0] rpSAS; reg [4:0] rpSA; wire incSECTOR = 0; always @(posedge clk) begin if (rst | rhCLR | devRESET | (state == statePRESET)) begin rpTAS <= 0; rpTA <= 0; rpSAS <= 0; rpSA <= 0; end else if (rpdaWRITE & unitSEL) begin if (devHIBYTE & rpDRY) begin rpTAS <= rhDATAI[15:13]; rpTA <= rhDATAI[12: 8]; end if (devLOBYTE & rpDRY) begin rpSAS <= rhDATAI[7:5]; rpSA <= rhDATAI[4:0]; end end else if (incSECTOR & unitSEL) begin if (rpSA == lastSECT) begin if (rpTA == lastSURF) begin rpTA <= 0; end else begin rpSA <= 0; rpTA <= rpTA + 1'b1; end end else begin rpSA <= rpSA + 1'b1; end end end assign rpDA = {rpTAS, rpTA, rpSAS, rpSA}; // // RPxx Disk Status (RPDS) Register // reg rpATA; reg rpLST; reg rpVV; reg rpOM; always @(posedge clk) begin if (rst | rhCLR | devRESET) begin rpATA <= 0; rpLST <= 0; rpVV <= 0; rpOM <= 0; end else if (ataCLR) begin rpATA <= 0; end else begin if (incSECTOR & (rpSA == lastSECT) & unitSEL) begin rpLST <= 1; end else if (rpdaWRITE & unitSEL) begin rpLST <= 0; end case (state) stateIDLE: begin rpVV <= rpVV & rpCD; end stateATA: begin rpATA <= 1; end stateCLEAR: begin rpATA <= 0; end statePRESET: begin rpVV <= rpCD; end stateOFFSET: begin rpOM <= 1; end stateRETURN: begin rpOM <= 0; end statePAKACK: begin rpVV <= rpCD; end endcase end end wire rpERR = (rpER1 != 0); wire rpPIP = (state == stateSEEKDLY); wire rpMOL = rpCD; wire rpWRL = rpWP; wire rpPGM = 0; wire rpDPR = 1; wire rpDRY = (state != stateIDLE); assign rpDS = {rpATA, rpERR, rpPIP, rpMOL, rpWRL, rpLST, rpPGM, rpDPR, rpDRY, rpVV, 5'b0, rpOM}; // // RPxx Error #1 (RPER1) Register // This register is not byte addressable. // reg rpDCK; reg rpUNS; reg rpOPI; reg rpDTE; reg rpWLE; reg rpIAE; reg rpAOE; reg rpHCRC; reg rpHCE; reg rpECH; reg rpWCF; reg rpFER; reg rpPAR; reg rpRMR; reg rpILR; reg rpILF; always @(posedge clk) begin if (rst | rhCLR | devRESET | (state == stateCLEAR)) begin rpDCK <= 0; rpUNS <= 0; rpOPI <= 0; rpDTE <= 0; rpWLE <= 0; rpIAE <= 0; rpAOE <= 0; rpHCRC <= 0; rpHCE <= 0; rpECH <= 0; rpWCF <= 0; rpFER <= 0; rpPAR <= 0; rpRMR <= 0; rpILR <= 0; rpILF <= 0; end else if (rperWRITE & unitSEL) begin if (rpDRY) begin rpDCK <= rhDATAI[15]; rpUNS <= rhDATAI[14]; rpOPI <= rhDATAI[13]; rpDTE <= rhDATAI[12]; rpWLE <= rhDATAI[11]; rpIAE <= rhDATAI[10]; rpAOE <= rhDATAI[ 9]; rpHCRC <= rhDATAI[ 8]; rpHCE <= rhDATAI[ 7]; rpECH <= rhDATAI[ 6]; rpWCF <= rhDATAI[ 5]; rpFER <= rhDATAI[ 4]; rpPAR <= rhDATAI[ 3]; rpRMR <= rhDATAI[ 2]; rpILR <= rhDATAI[ 1]; rpILF <= rhDATAI[ 0]; end else begin rpRMR <= 1; end end else begin if (incSECTOR & (rpDC == lastCYL) & (rpTA == lastSURF) & (rpSA == lastSECT) & unitSEL) begin rpAOE <= 1; end if (~rpDRY & unitSEL) begin if (rpcsWRITE | rpdaWRITE | rpofWRITE | rpdcWRITE) begin rpRMR <= 1; end end if (devWRITE & devIO & (devDEV == rhDEV) & (devADDR >= undADDR[18:34]) & unitSEL) begin rpILR <= 1; end case (state) stateWRLOCK: begin rpWLE <= 1; end stateINVADDR: begin rpIAE <= 1; end stateILLFUN: begin rpILF <= 1; end endcase end end assign rpER1 = {rpDCK, rpUNS, rpOPI, rpDTE, rpWLE, rpIAE, rpAOE, rpHCRC, rpHCE, rpECH, rpWCF, rpFER, rpPAR, rpRMR, rpILR, rpILF}; // // RPxx Look Ahead (RPLA) Register // assign rpLA = {5'b0, rpSA, 6'b0}; // // RPxx Maintenance Register // assign rpMR = 16'b0; // // RPxx Offset (RPOF) Register // reg rpF16; reg rpECI; reg rpHCI; reg rpOFD; reg rpNU; reg rpOF800; reg rpOF400; reg rpOF200; reg rpOF100; reg rpOF050; reg rpOF025; always @(posedge clk) begin if (rst | rhCLR | devRESET | (state == statePRESET)) begin rpF16 <= 0; rpECI <= 0; rpHCI <= 0; rpOFD <= 0; end else if (rpofWRITE & unitSEL) begin if (devHIBYTE & rpDRY) begin rpF16 <= rhDATAI[12]; rpECI <= rhDATAI[11]; rpECI <= rhDATAI[10]; end if (devLOBYTE & rpDRY) begin rpOFD <= rhDATAI[7]; rpNU <= rhDATAI[6]; rpOF800 <= rhDATAI[5]; rpOF400 <= rhDATAI[4]; rpOF200 <= rhDATAI[3]; rpOF100 <= rhDATAI[2]; rpOF050 <= rhDATAI[1]; rpOF025 <= rhDATAI[0]; end end end assign rpOF = {3'b0, rpF16, rpECI, rpHCI, 2'b0, rpOFD, rpNU, rpOF800, rpOF400, rpOF200, rpOF100, rpOF050, rpOF025}; // // RPxx Desired Cylinder (RPDC) Register // reg [9:0] rpDCA; always @(posedge clk) begin if (rst | rhCLR | devRESET | (state == statePRESET)) begin rpDCA <= 0; end else if (rpdcWRITE & unitSEL) begin if (devHIBYTE & rpDRY) begin rpDCA[9:8] <= rhDATAI[9:8]; end if (devLOBYTE & rpDRY) begin rpDCA[7:0] <= rhDATAI[7:0]; end end else if (incSECTOR & unitSEL) begin if ((rpTA == lastSURF) & (rpSA == lastSECT)) begin rpDCA <= rpDCA + 1'b1; end end end assign rpDC = {6'b0, rpDCA}; // // SD Sector Address Calculation // wire [31:0] rpSDADDR; SDADDR uSDADDR (.clk (clk), .rst (rst), .start (state == stateSEEK), .lastSURF (lastSECT), .lastSECT (lastSURF), .rpDCA (rpDCA), .rpTA (rpTA), .rpSA (rpSA), .sdADDR (rpSDADDR) ); // // Disk Motion Simlation State Machine // reg [ 1: 0] rpSDOP; // SD Operation reg [24: 0] delay; // RPxx Delay Simulation reg [ 9: 0] rpCCA; // Current Cylinder Address reg [ 9: 0] tempCYL; // Temporary Cylinder always @(posedge clk) begin if (rst | rhCLR | devRESET) begin state <= stateIDLE; rpSDOP <= `sdopNOP; delay <= 0; rpCCA <= 0; end else begin case (state) // // stateIDLE // Look for a function (command) to go process // stateIDLE: begin if (cmdGO) // // Decode Command (Function) // case (rhDATAI[6:0]) // // NOP Command // Does nothing // `funNOP: begin if (rpERR) state <= stateILLFUN; else state <= stateDONE; end // // Unload Head Command // On an RPxx disk, the seek command would // cause the heads to retract. This command // simulates head motion to cylinder 0. // `funUNLOAD: begin if (rpERR) state <= stateILLFUN; else begin tempCYL <= 0; delay <= seekDELAY(0, rpCCA); state <= stateSEEK; end end // // Seek Command // On an RPxx disk, the seek command causes // the heads to move to the cylinder // specified by the RPDC register. // // This command simulates head motion to // to the new cylinder specified by the RPDC // register // `funSEEK: begin if (rpERR) state <= stateILLFUN; else if ((rpDCA <= lastCYL) | (rpTA <= lastSURF) | (rpSA <= lastSECT)) begin tempCYL <= rpDCA; delay <= seekDELAY(rpDCA, rpCCA); state <= stateSEEK; end else state <= stateINVADDR; end // // Recalibrate Command // The seek command causes the heads to move // to cylinder 0. // `funRECAL: begin if (rpERR) state <= stateILLFUN; else begin tempCYL <= 0; delay <= seekDELAY(0, rpCCA); state <= stateSEEK; end end // // Device Clear Command // `funCLEAR: begin state <= stateCLEAR; end // // Port Release Command // This command does nothing // `funRELEASE: begin if (rpERR) state <= stateILLFUN; else state <= stateDONE; end // // Offset Comand // On an RPxx disk, the offset command moves // the heads off the track centerline 250 // microinches either toward the spindle or // away from the spindle. // // This command does nothing. // `funOFFSET: begin state <= stateATA; end // // Return to Centerline Command. // // On an RPxx disk, this command would return // the heads to the centerline of the track. // // This command does nothing. // `funRETURN: begin if (rpERR) state <= stateILLFUN; else state <= stateATA; end // // Read-in Preset Command // `funPRESET: begin if (rpERR) state <= stateILLFUN; else state <= statePRESET; end // // Pack Acknowldege Command // `funPAKACK: begin if (rpERR) state <= stateILLFUN; else state <= statePAKACK; end // // Search Command // On an RPxx disk, The search command // compares the actual sector address with // the requested sector address. When they // match, the adapter asserts the attention // line. // // This command behaves exactly the same as // a seek command. // `funSEARCH: begin if (rpERR) state <= stateILLFUN; else if ((rpDCA <= lastCYL) | (rpTA <= lastSURF) | (rpSA <= lastSECT)) begin tempCYL <= rpDCA; delay <= seekDELAY(rpDCA, rpCCA); state <= stateSEEK; end else state <= stateINVADDR; end //////////////////////////////////////////////////////////////////// // // Write Commands // `funWRCHK, `funWRCHKH: begin if (rpERR) state <= stateILLFUN; else begin if (simTIME) begin delay <= fiveMS; end else begin delay <= oneUS; end rpSDOP <= `sdopWRCHK; state <= stateROTDLY; end end `funWRITE, `funWRITEH: begin if (rpERR) state <= stateILLFUN; else if (rpWP) state <= stateWRLOCK; else begin if (simTIME) begin delay <= fiveMS; end else begin delay <= oneUS; end rpSDOP <= `sdopWR; state <= stateROTDLY; end end // // Read Commands // `funREAD, `funREADH: begin if (rpERR) state <= stateILLFUN; else begin if (simTIME) begin delay <= fiveMS; end else begin delay <= oneUS; end rpSDOP <= `sdopRD; state <= stateROTDLY; end end // // Functions that don't exist // default: begin state <= stateILLFUN; end endcase end // // stateSEEK // This state starts the SD Address Calculation // stateSEEK: begin state <= stateSEEKDLY; end // // stateSEEKDLY // Simulate Seek Timing on Seek Commands. // Update Current Cylinder Address after delay. // stateSEEKDLY: begin if (delay == 0) begin rpCCA <= tempCYL; state <= stateATA; end else delay <= delay - 1'b1; end // // stateROTDLY: // Simulate Rotation Latency on Reads/Writes // stateROTDLY: begin if (delay == 0) state <= stateWAITSD; else delay <= delay - 1'b1; end // // stateWAITSD: // // Wait for SD to handle Read/Write operaton // stateWAITSD: begin if (rpSDACK) begin state <= stateDONE; end end // // stateCLEAR // This state modifies the bits that occur // when Clear Command function is executed. // stateCLEAR: state <= stateDONE; // // statePRESET // This state modifies the bits that occur // when Preset Command function is executed. // statePRESET: state <= stateDONE; // // stateOFFSET // This state modifies the bits that occur // when Offset Command function is executed. // stateOFFSET: state <= stateDONE; // // stateRETURN // This state modifies the bits that occur // when Return Command function is executed. // stateRETURN: state <= stateDONE; // // statePAKACK // This state modifies the bits that occur // when Pack Acknowledge Command function // is executed. // statePAKACK: state <= stateDONE; // // stateILLFUN // This state modifies the bits that occur // when an illegal function is executed. // stateILLFUN: state <= stateDONE; // // stateINVADDR // This state modifies the bits that occur // when an invalid seek error is provided. // stateINVADDR: state <= stateDONE; // // stateWRLOCK // This state modifies the bits that occur // when a write-locked disk is written to // stateWRLOCK: state <= stateDONE; // // stateATA // This state sets the RPDS[ATA] bit. // stateATA: state <= stateDONE; // // stateDONE: // Update the disk state // stateDONE: begin rpSDOP <= `sdopNOP; state <= stateIDLE; end // // Everything else // default: state <= stateIDLE; endcase end end assign rpCC = {6'b0, rpCCA}; assign rpSDREQ = (state == stateWAITSD); endmodule Dist/rtl/ks10/uba/rh11/rpxx.vh0000700000175100010010000000552212151540222014402 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // RPxx definitions // // Details // // Todo // // File // rpxx.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __RPXX_VH `define __RPXX_VH // // RP Serial Numbers // `define rpSN0 16'o000021 `define rpSN1 16'o000022 `define rpSN2 16'o000023 `define rpSN3 16'o000024 `define rpSN4 16'o000025 `define rpSN5 16'o000026 `define rpSN6 16'o000027 `define rpSN7 16'o000030 // // RP/RM Drive Types // `define rpRP04 16'o020020 `define rpRP05 16'o020021 // Single Port RP05 `define rpRP06 16'o020022 // Single Port RP06 `define rpRM03 16'o020024 `define rpRM80 16'o020026 `define rpRM05 16'o020027 `define rpRM07 16'o020042 // // RP/RM Functions // // Note // The function code numbering in the book is a little strange - // It includes the GO bit, apparently. The LSB is always set. // `define funNOP 6'o00 // 01 `define funUNLOAD 6'o01 // 03 `define funSEEK 6'o02 // 05 `define funRECAL 6'o03 // 07 `define funCLEAR 6'o04 // 11 `define funRELEASE 6'o05 // 13 `define funOFFSET 6'o06 // 15 `define funRETURN 6'o07 // 17 `define funPRESET 6'o10 // 21 `define funPAKACK 6'o11 // 23 `define funSEARCH 6'o14 // 31 `define funWRCHK 6'o24 // 51 `define funWRCHKH 6'o25 // 53 `define funWRITE 6'o30 // 61 `define funWRITEH 6'o31 // 63 `define funREAD 6'o34 // 71 `define funREADH 6'o35 // 73 // // rp06 Disk Parametes // `define rp06LASTSECT 5'd19 // 20 sectors per track numbered 0 to 19 `define rp06LASTSURF 5'd18 // 19 tracks per cylinder numbered 0 to 18 `define rp06LASTCYL 10'd814 // 815 Cylinders `endifDist/rtl/ks10/uba/rh11/sd/0000700000175100010010000000000012151543111013441 5ustar RobNoneDist/rtl/ks10/uba/rh11/sd/sd.v0000700000175100010010000020254512151540230014250 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS10 Processor // // Brief // RPXX Secure Digital Interface // // Details // // File // sd.vhd // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `include "sd.vh" `include "sdspi.vh" module SD(clk, rst, // SPI Interface sdMISO, sdMOSI, sdSCLK, sdCS, // Control sdOP, sdSECTADDR, sdWDCNT, sdBUSADDR, // DMA Interface dmaDATAI, dmaDATAO, dmaADDR, dmaREQ, dmaACK, // sdINCWD, sdINCSECT, sdSTAT, // Debug sdDEBUG); input clk; // Clock input rst; // Reset // SPI Interface input sdMISO; // SD Data In output sdMOSI; // SD Data Out output sdSCLK; // SD Clock output sdCS; // SD Chip Select // Control input [ 1:0] sdOP; // SD Operation input [31:0] sdSECTADDR; // SD Sector Number input [15:0] sdWDCNT; // SD Word Count input [15:0] sdBUSADDR; // SD Bus Address // DMA Interface input [0:35] dmaDATAI; // DMA Data Input output [0:35] dmaDATAO; // DMA Data Output output [0:35] dmaADDR; // DMA Address output dmaREQ; // DMA Request input dmaACK; // DMA Acknowledge // Outputs output sdINCWD; // Increment Word Count output sdINCSECT; // Increment Sector output sdSTAT; // Status // Diagnostics output [35:0] sdDEBUG; // Debug Output // // SD Commands: // Sending leading 0xff just sends clocks with data parked. // parameter [7:0] sdCMD0 [0:5] = {8'h40, 8'h00, 8'h00, 8'h00, 8'h00, 8'h95}; parameter [7:0] sdCMD8 [0:5] = {8'h48, 8'h00, 8'h00, 8'h01, 8'haa, 8'h87}; parameter [7:0] sdCMD13 [0:5] = {8'h4d, 8'h00, 8'h00, 8'h00, 8'h00, 8'hff}; parameter [7:0] sdACMD41 [0:5] = {8'h69, 8'h40, 8'h00, 8'h00, 8'h00, 8'hff}; parameter [7:0] sdCMD55 [0:5] = {8'h77, 8'h00, 8'h00, 8'h00, 8'h00, 8'hff}; parameter [7:0] sdCMD58 [0:5] = {8'h7a, 8'h00, 8'h00, 8'h00, 8'h00, 8'hff}; // // Timing parameters // parameter [15:0] nCR = 8; // NCR from SD Spec parameter [15:0] nAC = 1023; // NAC from SD Spec parameter [15:0] nWR = 20; // NWR from SD Spec // // States // parameter [ 6:0] stateRESET = 0, // Init States stateINIT00 = 1, stateINIT01 = 2, stateINIT02 = 3, stateINIT03 = 4, stateINIT04 = 5, stateINIT05 = 6, stateINIT06 = 7, stateINIT07 = 8, stateINIT08 = 9, stateINIT09 = 10, stateINIT10 = 11, stateINIT11 = 12, stateINIT12 = 13, stateINIT13 = 14, stateINIT14 = 15, stateINIT15 = 16, stateINIT16 = 17, stateINIT17 = 18, // Read States stateREAD00 = 19, stateREAD01 = 20, stateREAD02 = 21, stateREAD03 = 22, stateREAD04 = 23, stateREAD05 = 24, stateREAD06 = 25, stateREAD07 = 26, stateREAD08 = 27, stateREAD09 = 28, stateREAD10 = 29, stateREAD11 = 30, stateREAD12 = 31, stateREAD13 = 32, stateREAD14 = 33, // Write States stateWRITE00 = 34, stateWRITE01 = 35, stateWRITE02 = 36, stateWRITE03 = 37, stateWRITE04 = 38, stateWRITE05 = 39, stateWRITE06 = 40, stateWRITE07 = 41, stateWRITE08 = 42, stateWRITE09 = 43, stateWRITE10 = 44, stateWRITE11 = 45, stateWRITE12 = 46, stateWRITE13 = 47, stateWRITE14 = 48, stateWRITE15 = 49, stateWRITE16 = 50, // Write Check States stateWRCHK00 = 51, // Other States stateFINI = 52, stateIDLE = 53, stateDONE = 54, stateINFAIL = 55, stateRWFAIL = 56; reg [ 2:0] spiOP; // SPI Op reg [ 7:0] spiRXD; // SPI Received Data reg [ 7:0] spiTXD; // SPI Transmit Data reg [15:0] loopCNT; // Byte Counter reg [ 7:0] sdCMD17[0:5]; // CMD17 reg [ 7:0] sdCMD24[0:5]; // CMD24 reg [20:0] busFLAGS; // Bus Flags reg abort; // Abort this command reg [19:0] timeout; // Timeout reg [ 7:0] sdRDCNT; // Read Counter reg [ 7:0] sdWRCNT; // Write Counter reg [ 7:0] sdVAL; // Error Value reg [ 4:0] sdERR; // Error State reg sdINCSECT; // Increment Sector reg sdINCWD; // Increment Word reg rwDONE; // Read/Write Completed reg readOP; // Read/Write Operation reg dmaREQ; // DMA Request reg [0:35] dmaDATAO; // DMA Data Out reg [ 6:0] state; // Current State wire spiDONE; // Asserted by SPI when done // // SD_STATE: // This process assumes a 50 MHz clock // always @(posedge clk or posedge rst) begin if (rst) begin sdERR <= 0; sdVAL <= 0; sdRDCNT <= 0; sdWRCNT <= 0; sdINCSECT <= 0; sdINCWD <= 0; loopCNT <= 0; dmaDATAO <= 0; readOP <= 0; spiTXD <= 0; abort <= 0; rwDONE <= 0; sdCMD17[0] <= 0; sdCMD17[1] <= 0; sdCMD17[2] <= 0; sdCMD17[3] <= 0; sdCMD17[4] <= 0; sdCMD17[5] <= 0; sdCMD24[0] <= 0; sdCMD24[1] <= 0; sdCMD24[2] <= 0; sdCMD24[3] <= 0; sdCMD24[4] <= 0; sdCMD24[5] <= 0; spiOP <= `spiNOP; timeout <= 499999; state <= stateRESET; end else begin dmaREQ <= 0; sdINCSECT <= 0; spiOP <= `spiNOP; //if ((sdOP == `sdopABORT) & (state != stateIDLE)) // begin // abort <= 1; // end case (state) // // stateRESET: // stateRESET: begin timeout <= timeout - 1'b1; loopCNT <= 0; state <= stateINIT00; end // // stateINIT00 // Send 8x8 clocks cycles // stateINIT00: begin timeout <= timeout - 1'b1; if (spiDONE | (loopCNT == 0)) begin if (loopCNT == nCR) begin loopCNT <= 0; spiOP <= `spiCSL; state <= stateINIT01; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end end // // stateINIT01: // Send GO_IDLE_STATE command (CMD0) // stateINIT01: begin timeout <= timeout - 1'b1; if (spiDONE | (loopCNT == 0)) begin if (loopCNT == 6) begin loopCNT <= 0; state <= stateINIT02; end else begin spiOP <= `spiTR; spiTXD <= sdCMD0[loopCNT]; loopCNT <= loopCNT + 1'b1; end end end // // stateINIT02: // Read R1 Response from CMD0 // Response should be 8'h01 // stateINIT02: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin if (spiDONE) begin if (spiRXD == 8'hff) begin if (loopCNT == nCR) begin spiOP <= `spiCSH; loopCNT <= 0; state <= stateRESET; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin spiOP <= `spiCSH; loopCNT <= 0; if (spiRXD == 8'h01) state <= stateINIT03; else state <= stateRESET; end end end end // // stateINIT03: // Send 8 clock cycles // stateINIT03: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else if (spiDONE) begin spiOP <= `spiCSL; loopCNT <= 0; state <= stateINIT04; end end // // stateINIT04: // Send SEND_IF_COND (CMD8) // stateINIT04: begin timeout <= timeout - 1'b1; if (spiDONE | (loopCNT == 0)) begin if (loopCNT == 6) begin loopCNT <= 0; state <= stateINIT05; end else begin spiOP <= `spiTR; spiTXD <= sdCMD8[loopCNT]; loopCNT <= loopCNT + 1'b1; end end end // // stateINIT05 // Read first byte R1 of R7 Response // Response should be 8'h01 for V2.00 initialization or // 8'h05 for V1.00 initialization. // stateINIT05: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin if (spiDONE) begin if (spiRXD == 8'hff) begin if (loopCNT == nCR) begin spiOP <= `spiCSH; loopCNT <= 0; sdERR <= 1; state <= stateINFAIL; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin loopCNT <= 0; if (spiRXD == 8'h01) begin state <= stateINIT06; end else if (spiRXD == 8'h05) begin spiOP <= `spiCSH; sdERR <= 2; state <= stateINFAIL; end else begin spiOP <= `spiCSH; sdERR <= 3; state <= stateINFAIL; end end end end end // // stateINIT06 // Read 32-bit Response to CMD8 // Response should be 8'h00_00_01_aa // 8'h01 - Voltage // 8'h55 - Pattern // stateINIT06: begin timeout <= timeout - 1'b1; case (loopCNT) 0: begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end 1: begin if (spiDONE) begin if (spiRXD == 8'h00) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 2; end else begin sdERR <= 4; state <= stateINFAIL; end end end 2: begin if (spiDONE) begin if (spiRXD == 8'h00) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 3; end else begin sdERR <= 5; state <= stateINFAIL; end end end 3: begin if (spiDONE) begin if (spiRXD == 8'h01) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 4; end else begin sdERR <= 6; state <= stateINFAIL; end end end 4: begin if (spiDONE) begin if (spiRXD == 8'haa) begin spiOP <= `spiCSH; loopCNT <= 0; state <= stateINIT07; end else begin sdERR <= 7; state <= stateINFAIL; end end end default: begin ; end endcase end // // stateINIT07: // Send 8 clock cycles // stateINIT07: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else if (spiDONE) begin spiOP <= `spiCSL; loopCNT <= 0; state <= stateINIT08; end end // // stateINIT08: // Send APP_CMD (CMD55) // stateINIT08: begin timeout <= timeout - 1'b1; if (spiDONE | (loopCNT == 0)) begin if (loopCNT == 6) begin loopCNT <= 0; state <= stateINIT09; end else begin spiOP <= `spiTR; spiTXD <= sdCMD55[loopCNT]; loopCNT <= loopCNT + 1'b1; end end end // // stateINIT09: // Read R1 response from CMD55. // Response should be 8'h01 // stateINIT09: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin if (spiDONE) begin if (spiRXD == 8'hff) begin if (loopCNT == nCR) begin spiOP <= `spiCSH; loopCNT <= 0; sdERR <= 8; state <= stateINFAIL; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin spiOP <= `spiCSH; loopCNT <= 0; if (spiRXD == 8'h01) begin state <= stateINIT10; end else begin state <= stateINIT07; end end end end end // // stateINIT10: // Send 8 clock cycles // stateINIT10: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else if (spiDONE) begin spiOP <= `spiCSL; loopCNT <= 0; state <= stateINIT11; end end // // stateINIT11: // Send SD_SEND_OP_COND (ACMD41) // stateINIT11: begin timeout <= timeout - 1'b1; if (spiDONE | (loopCNT == 0) ) begin if (loopCNT == 6) begin loopCNT <= 0; state <= stateINIT12; end else begin spiOP <= `spiTR; spiTXD <= sdACMD41[loopCNT]; loopCNT <= loopCNT + 1'b1; end end end // // stateINIT12: // Read R1 response from ACMD41. // Response should be 8'h00 // stateINIT12: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin if (spiDONE) begin if (spiRXD == 8'hff) begin if (loopCNT == nCR) begin spiOP <= `spiCSH; loopCNT <= 0; sdERR <= 9; state <= stateINFAIL; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin spiOP <= `spiCSH; loopCNT <= 0; if (spiRXD == 8'h00) begin state <= stateINIT13; end else begin state <= stateINIT07; end end end end end // // stateINIT13 // Send 8 clock cycles // stateINIT13: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else if (spiDONE) begin spiOP <= `spiCSL; loopCNT <= 0; state <= stateINIT14; end end // // stateINIT14: // Send READ_OCR (CMD58) // stateINIT14: begin timeout <= timeout - 1'b1; if (spiDONE | (loopCNT == 0)) begin if (loopCNT == 6) begin loopCNT <= 0; state <= stateINIT15; end else begin spiOP <= `spiTR; spiTXD <= sdCMD58[loopCNT]; loopCNT <= loopCNT + 1'b1; end end end // // stateINIT15 // Read first byte of R3 response to CMD58 // Response should be 8'h00 // stateINIT15: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin if (spiDONE) begin if (spiRXD == 8'hff) begin if (loopCNT == nCR) begin spiOP <= `spiCSH; loopCNT <= 0; sdERR <= 10; state <= stateINFAIL; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin loopCNT <= 0; if (spiRXD == 8'h00) state <= stateINIT16; else spiOP <= `spiCSH; sdERR <= 11; state <= stateINFAIL; end end end end // // stateINIT16 // Response should be e0_ff_80_00 // Read 32-bit OCR response to CMD58 // stateINIT16: begin timeout <= timeout - 1'b1; case (loopCNT) 0: begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end 1: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 2; end end 2: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 3; end end 3: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 4; end end 4: begin if (spiDONE) begin spiOP <= `spiCSH; loopCNT <= 0; state <= stateINIT17; end end default begin ; end endcase end // // stateINIT17: // Send 8 clock cycles // stateINIT17: begin timeout <= timeout - 1'b1; if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else if (spiDONE) begin loopCNT <= 0; `ifdef GOFAST spiOP <= spiFAST; `endif state <= stateIDLE; end end // // stateIDLE: // Wait for a command to process. // Once the SD card is initialized, it waits in this state // for either a read (sdopRD) or a write (sdopWR) command. // stateIDLE: begin abort <= 0; case (sdOP) `sdopNOP: begin state <= stateIDLE; end `sdopRD: begin sdRDCNT <= sdRDCNT + 1'b1; readOP <= 1; state <= stateREAD00; end `sdopWR: begin sdWRCNT <= sdWRCNT + 1'b1; readOP <= 0; state <= stateWRITE00; end `sdopWRCHK: begin sdRDCNT <= sdRDCNT + 1'b1; readOP <= 1; state <= stateWRCHK00; end default: begin state <= stateIDLE; end endcase end // // stateREAD00: // Setup Read Single Block (CMD17) // This is a loop destination // stateREAD00: begin sdCMD17[0] <= 8'h51; sdCMD17[1] <= sdSECTADDR[31:24]; sdCMD17[2] <= sdSECTADDR[23:16]; sdCMD17[3] <= sdSECTADDR[15: 8]; sdCMD17[4] <= sdSECTADDR[ 7: 0]; sdCMD17[5] <= 8'hff; loopCNT <= 0; spiOP <= `spiCSL; state <= stateREAD01; end // // stateREAD01: // Send Read Single Block (CMD17) // stateREAD01: begin if (spiDONE | (loopCNT == 0)) begin if (loopCNT == 6) begin loopCNT <= 0; state <= stateREAD02; end else begin spiOP <= `spiTR; spiTXD <= sdCMD17[loopCNT]; loopCNT <= loopCNT + 1'b1; end end end // // stateREAD02: // Read R1 response from CMD17 // Response should be 8'h00 // stateREAD02: begin if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin if (spiDONE) begin if (spiRXD == 8'hff) begin if (loopCNT == nCR) begin spiOP <= `spiCSH; loopCNT <= 0; sdERR <= 12; state <= stateRWFAIL; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin loopCNT <= 0; if (spiRXD == 8'h00) begin state <= stateREAD03; end else begin spiOP <= `spiCSH; sdERR <= 13; state <= stateRWFAIL; end end end end end // // stateREAD03: // Find 'Read Start token' which should be 8'hfe // stateREAD03: begin if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin if (spiDONE) begin if (spiRXD == 8'hff) begin if (loopCNT == nAC) begin spiOP <= `spiCSH; loopCNT <= 0; sdERR <= 14; state <= stateRWFAIL; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin loopCNT <= 0; if (spiRXD == 8'hfe) begin rwDONE <= 0; spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 0; state <= stateREAD04; end else begin spiOP <= `spiCSH; sdERR <= 15; sdVAL <= spiRXD; state <= stateRWFAIL; end end end end end // // stateREAD04: // Read byte[0] of data from disk. (LS Byte) // This is a loop destination // stateREAD04: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; dmaDATAO[28:35] <= spiRXD; state <= stateREAD05; end end // // stateREAD05: // Read byte[1] of data from disk. // stateREAD05: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; dmaDATAO[20:27] <= spiRXD; state <= stateREAD06; end end // // stateREAD06: // Read byte[2] of data from disk. // stateREAD06: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; dmaDATAO[12:19] <= spiRXD; state <= stateREAD07; end end // // stateREAD07: // Read byte[3] of data from disk. // stateREAD07: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; dmaDATAO[ 4:11] <= spiRXD; state <= stateREAD08; end end // // stateREAD08: // Read byte[4] of data from disk. (MS Nibble) // stateREAD08: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; dmaDATAO[0:3] <= spiRXD[4:7]; state <= stateREAD09; end end // // stateREAD09: // Read byte[5] of data from disk. // This byte is ignored by the disk controller // stateREAD09: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; state <= stateREAD10; end end // // stateREAD10: // Read byte[6] of data from disk. // This byte is ignored by the disk controller // stateREAD10: begin if (spiDONE) begin spiOP <= `spiTR; spiTXD <= 8'hff; state <= stateREAD11; end end // // stateREAD11: // Read byte[7] of data from disk. // This byte is ignored by the disk controller // stateREAD11: begin if (spiDONE) begin if (rwDONE) begin state <= stateREAD13; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; dmaREQ <= 1; state <= stateREAD12; end end end // // stateREAD12: // Write disk data to memory. // stateREAD12: begin if (dmaACK) begin state <= stateREAD13; end end //////////////////////////////////////////////////////////////////// // // stateREAD13: // The SIMH uses 1024 byte sectors. This is // because a PDP10 sector is 128 words and SIMH uses // 8 bytes (64-bits) per word. Therefore each PDP10 // sector corresponds to two SD sectors. // // This state checks the various loop conditions: // // - When Word Count increments to zero, we are done // storing data in memory but we continue reading // until the end-of-sector. In this case we set // 'rwDONE' // // stateREAD13: begin if (abort) begin spiOP <= `spiCSH; loopCNT <= 0; state <= stateFINI; end else begin if (sdWDCNT == 0) begin rwDONE <= 0; end if (loopCNT == 63) begin sdINCSECT <= 1; state <= stateREAD00; end else if (loopCNT == 127) begin sdINCSECT <= 1; state <= stateREAD00; end end end // // stateREAD14: // Read 2 bytes of CRC which is required for the SD Card. // stateREAD14: begin if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin if (spiDONE) begin if (loopCNT) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 2; end else if (loopCNT == 2) begin spiOP <= `spiCSH; loopCNT <= 0; state <= stateFINI; end end end end // // stateWRITE00: // Setup Write Single Block (CMD24) // stateWRITE00: begin sdCMD24[0] <= 8'h58; sdCMD24[1] <= sdSECTADDR[31: 24]; sdCMD24[2] <= sdSECTADDR[23: 16]; sdCMD24[3] <= sdSECTADDR[15: 8]; sdCMD24[4] <= sdSECTADDR[ 7: 0]; sdCMD24[5] <= 8'hff; loopCNT <= 0; spiOP <= `spiCSL; state <= stateWRITE01; end // // stateWRITE01: // Send Write Single Block (CMD24) // stateWRITE01: begin if (spiDONE | (loopCNT == 0)) begin if (loopCNT == 6) begin loopCNT <= 0; state <= stateWRITE02; end else begin spiOP <= `spiTR; spiTXD <= sdCMD24[loopCNT]; loopCNT <= loopCNT + 1'b1; end end end // // stateWRITE02: // Read R1 response from CMD24 // Response should be 8'h00 // stateWRITE02: begin if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin if (spiDONE) begin if (spiRXD == 8'hff) begin if (loopCNT == nCR) begin spiOP <= `spiCSH; loopCNT <= 0; sdERR <= 16; state <= stateRWFAIL; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin loopCNT <= 0; if (spiRXD == 8'h00) begin state <= stateWRITE03; end else begin spiOP <= `spiCSH; sdVAL <= spiRXD; sdERR <= 17; end end end end end // // stateWRITE03: // Send 8 clock cycles // stateWRITE03: begin if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else if (spiDONE) begin loopCNT <= 0; state <= stateWRITE04; end end // // stateWRITE04: // Send Write Start Token. The write start token is 8'hfe // stateWRITE04: begin if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hfe; loopCNT <= 1; end else if (spiDONE) begin loopCNT <= 0; state <= stateWRITE05; end end // // stateWRITE05: // Start a DMA Read Address Cycle // stateWRITE05: begin dmaREQ <= 1; if (dmaACK) begin state <= stateWRITE06; end end // // stateWRITE06: // This is a loop destination // stateWRITE06: begin if (dmaREQ) begin //dmaRD <= 1; end state <= stateWRITE07; end // // stateWRITE07: // Write LSBYTE of data to disk (even addresses) // This state has two modes: // If dmaREQ is asserted we are operating normally. // If dmaREQ is negated we are writing the last 128 // words of a 128 word operation. Therefore we // write zeros. See file header. // stateWRITE07: begin spiOP <= `spiTR; if (dmaREQ) begin spiTXD <= dmaDATAI[4:11]; end else begin spiTXD <= 8'b0; end state <= stateWRITE08; end // // stateWRITE08: // Write MSBYTE of data to disk (odd addresses) // Note: The top 4 bits of the MSBYTE are zero. // stateWRITE08: begin if (spiDONE) begin spiOP <= `spiTR; loopCNT <= loopCNT + 1'b1; state <= stateWRITE09; end end // // stateWRITE09: // This is the addr phase of the read cycle. // stateWRITE09: begin if (spiDONE) begin if (abort) begin dmaREQ <= 0; spiOP <= `spiCSH; loopCNT <= 0; state <= stateFINI; end else if (loopCNT == 511) begin dmaREQ <= 0; spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 0; //memADDR <= memADDR + 1'b1; state <= stateWRITE10; end else begin loopCNT <= loopCNT + 1'b1; //memADDR <= memADDR + 1'b1; state <= stateWRITE06; end end end // // stateWRITE10: // Write CRC bytes // stateWRITE10: begin if (spiDONE) begin if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 0; state <= stateWRITE11; end end end // // stateWRITE11: // Read Data Response. The response is is one byte long // and has the following format: // // xxx0sss1 // // Where x is don't-care and sss is a 3-bit status field. // 010 is accepted, // 101 is rejected due to CRC error and // 110 is rejected due to write error. // stateWRITE11: begin if (spiDONE) begin if (spiRXD[3:7] == 5'b0_010_1) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 0; state <= stateWRITE12; end else begin spiOP <= `spiCSH; sdVAL <= spiRXD; sdERR <= 18; loopCNT <= 0; state <= stateRWFAIL; end end end // // stateWRITE12: // Wait for busy token to clear. The disk reports // all zeros while the write is occurring. // stateWRITE12: begin if (spiDONE) begin if (spiRXD == 0) begin if (loopCNT == 65535) begin spiOP <= `spiCSH; loopCNT <= 0; sdERR <= 19; state <= stateRWFAIL; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin loopCNT <= 0; state <= stateWRITE13; end end end // // stateWRITE13: // Send Send Status Command (CMD13) // stateWRITE13: begin if (spiDONE | (loopCNT == 0)) begin if (loopCNT == 6) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 0; state <= stateWRITE14; end else begin spiOP <= `spiTR; spiTXD <= sdCMD13[loopCNT]; loopCNT <= loopCNT + 1'b1; end end end // // stateWRITE14: // Check first byte of CMD13 response // Status: // Bit 0: Zero // Bit 1: Parameter Error // Bit 2: Address Error // Bit 3: Erase Sequence Error // Bit 4: COM CRC Error // Bit 5: Illegal Command // Bit 6: Erase Reset // Bit 7: Idle State // stateWRITE14: begin if (spiDONE) begin if (spiRXD == 8'hff) begin if (loopCNT == nCR) begin spiOP <= `spiCSH; loopCNT <= 0; sdERR <= 20; state <= stateRWFAIL; end else begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= loopCNT + 1'b1; end end else begin if (spiRXD == 8'h00 | spiRXD == 8'h01) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 0; state <= stateWRITE15; end else begin spiOP <= `spiCSH; loopCNT <= 0; sdVAL <= spiRXD; sdERR <= 21; end end end end // // stateWRITE15: // Check second byte of CMD13 response // Status: // Bit 0: Out of range // Bit 1: Erase Param // Bit 2: WP Violation // Bit 3: ECC Error // Bit 4: CC Error // Bit 5: Error // Bit 6: WP Erase Skip // Bit 7: Card is locked // stateWRITE15: begin if (spiDONE) begin if (spiRXD == 8'h00) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; state <= stateWRITE16; end else begin spiOP <= `spiCSH; loopCNT <= 0; sdVAL <= spiRXD; sdERR <= 22; state <= stateRWFAIL; end end end // // stateWRITE16: // Send 8 clock cycles. Pull CS High. // stateWRITE16: begin if (spiDONE) begin spiOP <= `spiCSH; loopCNT <= 0; state <= stateFINI; end end // // stateWRCHK00: // Setup Read Single Block (CMD17) - (same as stateRD00) // stateWRCHK00: begin sdCMD17[0] <= 8'h51; sdCMD17[1] <= sdSECTADDR[31:24]; sdCMD17[2] <= sdSECTADDR[23:16]; sdCMD17[3] <= sdSECTADDR[15: 8]; sdCMD17[4] <= sdSECTADDR[ 7: 0]; sdCMD17[5] <= 8'hff; loopCNT <= 0; spiOP <= `spiCSL; state <= stateWRCHK00; end // // stateFINI: // Send 8 clock cycles // stateFINI: begin if (loopCNT == 0) begin spiOP <= `spiTR; spiTXD <= 8'hff; loopCNT <= 1; end else if (spiDONE) begin loopCNT <= 0; state <= stateDONE; end end // // stateDONE: // stateDONE: begin state <= stateIDLE; end // // stateINFAIL: // Initialization failed somehow. // stateINFAIL: begin state <= stateINFAIL; end // // stateRWFAIL: // Read or Write failed somehow. // stateRWFAIL: begin state <= stateRWFAIL; end endcase; if (timeout == 0) begin state <= stateINFAIL; end end end // // SPI Interface // SDSPI uSDSPI (.clk (clk), .rst (rst), .spiOP (spiOP), .spiTXD (spiTXD), .spiRXD (spiRXD), .spiMISO (sdMISO), .spiMOSI (sdMOSI), .spiSCLK (sdSCLK), .spiCS (sdCS), .spiDONE (spiDONE) ); // // Debug Output // assign sdDEBUG = {sdERR[4:0], state[6:0], sdVAL[7:0], sdWRCNT[7:0], sdRDCNT[7:0]}; // // Create address // parameter [0:19] rdFLAGS = 20'b0001_0000_0000_0000_0000; parameter [0:19] wrFLAGS = 20'b0000_0100_0000_0000_0000; assign dmaADDR = (readOP) ? {rdFLAGS, sdBUSADDR} : {wrFLAGS, sdBUSADDR}; endmodule Dist/rtl/ks10/uba/rh11/sd/sd.vh0000700000175100010010000000274012151540222014414 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Secure Digital Card (SD) Definitions // // Details // // Todo // // File // sd.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __SD_VH `define __SD_VH // // SD Operations // `define sdopNOP 2'd0 `define sdopRD 2'd1 `define sdopWR 2'd2 `define sdopWRCHK 2'd3 // // SD Status // `endifDist/rtl/ks10/uba/rh11/sd/sdspi.v0000700000175100010010000001642212151540230014761 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS10 Processor // // Brief // Secure Digital SPI Interface // // Details // This interface communicates with the Secure Digital Chip // at the physical layer. // // File // sdspi.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `include "sdspi.vh" module SDSPI(clk, rst, spiOP, spiTXD, spiRXD, spiMISO, spiMOSI, spiSCLK, spiCS, spiDONE); input clk; // Clock input rst; // Reset input [1:0] spiOP; // Operation input [7:0] spiTXD; // Transmit Data output [7:0] spiRXD; // Receive Data input spiMISO; // SD Data In output spiMOSI; // SD Data Out output spiSCLK; // SD Clock output spiCS; // SD Chip Select output spiDONE; // Done // // State Machine States // parameter [2:0] stateRESET = 0, stateIDLE = 1, stateTXH = 2, stateTXL = 3, stateTXM = 4, stateTXN = 5; // // Clock Speed Divisors // parameter [5:0] slowDiv = 63; parameter [5:0] fastDiv = 1; // // State Variables // reg [2:0] state; reg [2:0] bitcnt; reg [7:0] txd; reg [7:0] rxd; reg [5:0] clkcnt; reg [5:0] clkdiv; reg spiDONE; reg spiCS; always @(posedge clk) begin if (rst) begin spiDONE <= 0; txd <= 8'b1111_1111; rxd <= 8'b1111_1111; spiCS <= 1; bitcnt <= 0; clkcnt <= 0; clkdiv <= slowDiv; state <= stateRESET; end else begin case (state) // // StateRESET // Initialize variables // stateRESET: begin clkdiv <= slowDiv; state <= stateIDLE; end // // StateIDLE // Wait for a command to start the state machine. // stateIDLE: begin spiDONE <= 0; case (spiOP) `spiNOP: begin ; end `spiCSL: begin spiCS <= 0; end `spiCSH: begin spiCS <= 1; end `spiFAST: begin clkdiv <= fastDiv; end `spiSLOW: begin clkdiv <= slowDiv; end `spiTR: begin clkcnt <= clkdiv; bitcnt <= 7; txd <= spiTXD; state <= stateTXL; end default: begin state <= stateIDLE; end endcase; end // // Clock Low // stateTXL: begin if (clkcnt == 0) begin clkcnt <= clkdiv; rxd <= {rxd[6:0] & spiMISO}; state <= stateTXH; end else begin clkcnt <= clkcnt - 1'b1; end end // // Clock High // stateTXH: begin if (clkcnt == 0) begin if (bitcnt == 0) begin clkcnt <= clkdiv; state <= stateTXM; end else begin clkcnt <= clkdiv; txd <= {txd[6:0], 1'b1}; bitcnt <= bitcnt - 1'b1; state <= stateTXL; end end else begin clkcnt <= clkcnt - 1; end end // // Last bit clock high // stateTXM: begin if (clkcnt == 0) begin clkcnt <= clkdiv; state <= stateTXN; end else begin clkcnt <= clkcnt - 1'b1; end end // // Lst bit clock low // stateTXN: begin if (clkcnt == 0) begin clkcnt <= clkdiv; spiDONE <= 1; state <= stateIDLE; end else begin clkcnt <= clkcnt - 1; end end // // Everything else // default: begin state <= stateIDLE; end endcase end end assign spiSCLK = (state != stateTXL); assign spiMOSI = txd[0]; assign spiRXD = rxd; endmodule Dist/rtl/ks10/uba/rh11/sd/sdspi.vh0000700000175100010010000000302212151540222015122 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // Secure Digital Card (SD) SPI Inteface Definitions // // Details // // Todo // // File // sdspi.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __SDSPI_VH `define __SDSPI_VH // // SD SPI Operations // `define spiNOP 3'd0 `define spiCSL 3'd1 `define spiCSH 3'd2 `define spiFAST 3'd3 `define spiSLOW 3'd4 `define spiTR 3'd5 `endif Dist/rtl/ks10/uba/rh11/sdaddr.v0000700000175100010010000000773312151540230014477 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // SD Card Sector Address Calculator // // Details // This calculates: // // // File // sdaddr.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// module SDADDR(clk, rst, start, lastSURF, lastSECT, rpDCA, rpTA, rpSA, sdADDR); input clk; // Clock input rst; // Reset input start; // input [ 4: 0] lastSURF; // Number of Surfaces input [ 4: 0] lastSECT; // Number of Sectors input [ 9: 0] rpDCA; // Cylinder input [ 4: 0] rpTA; // Track input [ 4: 0] rpSA; // Sector output [31: 0] sdADDR; // SD Sector Address // // States // parameter [2:0] stateIDLE = 0, stateTRACK = 1, stateSECT = 2, stateWORD = 3; // // SD Sector Address Calculator State Machine // reg [31:0] sum; reg [31:0] temp; reg [ 2:0] state; reg [ 4:0] loop; always @(posedge clk or posedge rst) begin if (rst) begin sum <= 0; temp <= 0; loop <= 0; state <= stateIDLE; end else begin case (state) stateIDLE: begin if (start) begin sum <= 0; temp <= rpDCA; loop <= lastSURF; state <= stateTRACK; end end stateTRACK: begin if (loop == 0) begin sum <= 0; temp <= sum + rpTA; loop <= lastSECT; state <= stateSECT; end else begin sum <= sum + temp; loop <= loop - 1'b1; end end stateSECT: begin if (loop == 0) begin sum <= sum + rpSA; state <= stateWORD; end else begin sum <= sum + temp; loop <= loop - 1'b1; end end stateWORD: begin sum <= sum + sum; state <= stateIDLE; end endcase end end assign sdADDR = sum; endmodule Dist/rtl/ks10/uba/uba.v0000700000175100010010000005311712151540230013227 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS10 IO Bus Bridge // // Details // This device 'bridges' the KS10 FPGA backplane bus to the IO // IO Bus. On a real KS10, the IO bus was UNIBUS. The IO // Bus in the KS10 FPGA is not UNIBUS. // // Notes // Important addresses: // // 763000-763077 : IO Bridge Paging RAM // 763100 : IO Bridge Status Register // 763101 : IO Bridge Maintenace Register // // File // uba.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "uba.vh" `include "../ks10.vh" module UBA(clk, rst, clken, ctlNUM, // KS10 Bus Interface busREQI, busREQO, busACKI, busACKO, busADDRI, busADDRO, busDATAI, busDATAO, busINTR, // Device Interface devREQO, devADDRO, devDATAO, devINTA, devRESET, // Device #1 Interface dev1REQI, dev1ACKI, dev1ADDRI, dev1DATAI, dev1INTR, dev1ACKO, // Device #2 Interface dev2REQI, dev2ACKI, dev2ADDRI, dev2DATAI, dev2INTR, dev2ACKO); input clk; // Clock input rst; // Reset input clken; // Clock enable input [ 0: 3] ctlNUM; // Bridge Device Number // KS10 Backplane Bus Interface input busREQI; // Backplane Bus Request In output busREQO; // Backplane Bus Request Out input busACKI; // Backplane Bus Acknowledge In output busACKO; // Backplane Bus Acknowledge Out input [ 0:35] busADDRI; // Backplane Bus Address In output [ 0:35] busADDRO; // Backplane Bus Address Out input [ 0:35] busDATAI; // Backplane Bus Data In output [ 0:35] busDATAO; // Backplane Bus Data Out output [ 1: 7] busINTR; // Backplane Bus Interrupt Request // Device Interface output devREQO; // IO Device Request Out output [ 0:35] devADDRO; // IO Device Address Out output [ 0:35] devDATAO; // IO Device Data Out output [ 7: 4] devINTA; // IO Device Interrupt Acknowledge output devRESET; // IO Device Reset // Device #1 Interface input dev1REQI; // IO Device #1 Request In input dev1ACKI; // IO Device #1 Acknowledge In input [ 0:35] dev1ADDRI; // IO Device #1 Address In input [ 0:35] dev1DATAI; // IO Device #1 Data In input [ 7: 4] dev1INTR; // IO Device #1 Interrupt Request output dev1ACKO; // IO Device #1 Acknowledge Out // Device #2 Interface input dev2REQI; // IO Device #2 Request In input dev2ACKI; // IO Device #2 Acknowledge In input [ 0:35] dev2ADDRI; // IO Device #2 Address In input [ 0:35] dev2DATAI; // IO Device #2 Data In input [ 7: 4] dev2INTR; // IO Device #2 Interrupt Request output dev2ACKO; // IO Device #2 Acknowledge Out // // IO Bridge Configuration // parameter [14:17] ctlNUM0 = `ctlNUM0; // IO Bridge Device 0 parameter [14:17] ctlNUM1 = `ctlNUM1; // IO Bridge Device 1 parameter [14:17] ctlNUM2 = `ctlNUM2; // IO Bridge Device 2 parameter [14:17] ctlNUM3 = `ctlNUM3; // IO Bridge Device 3 parameter [18:35] wruNUM0 = `wruNUM0; // IO Bridge Device 0 WRU Response (bit 18) parameter [18:35] wruNUM1 = `wruNUM1; // IO Bridge Device 1 WRU Response (bit 19) parameter [18:35] wruNUM2 = `wruNUM2; // IO Bridge Device 2 WRU Response (bit 20) parameter [18:35] wruNUM3 = `wruNUM3; // IO Bridge Device 3 WRU Response (bit 21) // // IO Addresses // parameter [18:35] pageADDR = 18'o763000; // Paging RAM Address parameter [18:35] statADDR = 18'o763100; // Status Register Address parameter [18:35] maintADDR = 18'o763101; // Maintenance Register Address parameter [18:26] ctrlADDR = 9'o763; // Bridge Registers // // Address Bus // // Details: // busADDRI[ 0:13] is flags // busADDRI[14:35] is address // wire busREAD = busADDRI[ 3]; // 1 = Read Cycle (IO or Memory) wire busWRITE = busADDRI[ 5]; // 1 = Write Cycle (IO or Memory) wire busPHYS = busADDRI[ 8]; // 1 = Physical reference wire busIO = busADDRI[10]; // 1 = IO Cycle, 0 = Memory Cycle wire busWRU = busADDRI[11]; // 1 = Read interrupting controller number wire busVECT = busADDRI[12]; // 1 = Read interrupt vector wire busIOBYTE = busADDRI[13]; // 1 = IO Bridge Byte IO Operation wire [15:17] busPI = busADDRI[15:17]; // IO Bridge PI Request wire [14:17] busCTL = busADDRI[14:17]; // IO Bridge Device Number wire [18:35] busADDR = busADDRI[18:35]; // IO Address // // Address Decoding // wire wruREAD = busIO & busWRU & busPHYS; wire vectREAD = busIO & busVECT & (busCTL == ctlNUM); wire pageREAD = busIO & busREAD & (busCTL == ctlNUM) & (busADDR[18:29] == pageADDR[18:29]); wire pageWRITE = busIO & busWRITE & (busCTL == ctlNUM) & (busADDR[18:29] == pageADDR[18:29]); wire statWRITE = busIO & busWRITE & (busCTL == ctlNUM) & (busADDR[18:35] == statADDR[18:35]); wire statREAD = busIO & busREAD & (busCTL == ctlNUM) & (busADDR[18:35] == statADDR[18:35]); wire devREAD = busIO & busREAD & (busCTL == ctlNUM) & (busADDR[18:20] == ctrlADDR[18:20]) & (busADDR[21:26] != ctrlADDR[21:26]); wire devWRITE = busIO & busWRITE & (busCTL == ctlNUM) & (busADDR[18:20] == ctrlADDR[18:20]) & (busADDR[21:26] != ctrlADDR[21:26]); // // IO Bridge Interrupt Request // wire [7:4] intREQ = dev1INTR | dev2INTR; wire statINTHI = intREQ[7] | intREQ[6]; wire statINTLO = intREQ[5] | intREQ[4]; // // High Priority Interrupt // // Trace // UBA3/E180 // reg [1:7] devINTRH; always @(statINTHI or statPIH) begin if (statINTHI) case (statPIH) 0: devINTRH <= 7'b0000000; 1: devINTRH <= 7'b1000000; 2: devINTRH <= 7'b0100000; 3: devINTRH <= 7'b0010000; 4: devINTRH <= 7'b0001000; 5: devINTRH <= 7'b0000100; 6: devINTRH <= 7'b0000010; 7: devINTRH <= 7'b0000001; endcase else devINTRH <= 7'b0000000; end // // High Priority Interrupt // // Trace // UBA3/E182 // reg [1:7] devINTRL; always @(statINTLO or statPIL) begin if (statINTLO) case (statPIL) 0: devINTRL <= 7'b0000000; 1: devINTRL <= 7'b1000000; 2: devINTRL <= 7'b0100000; 3: devINTRL <= 7'b0010000; 4: devINTRL <= 7'b0001000; 5: devINTRL <= 7'b0000100; 6: devINTRL <= 7'b0000010; 7: devINTRL <= 7'b0000001; endcase else devINTRL <= 7'b0000000; end // // IO Bridge Interrupt Request // // Trace // UBA3/E179 // UBA3/E181 // assign busINTR = devINTRL | devINTRH; // // IO Bridge Interrupt Acknowledge // // Trace // UBA7/E27 // UBA7/E39 // UBA7/E53 // UBA7/E113 // UBA7/E184 // UBA7/E185 // reg [7:4] devINTA; always @(posedge clk or posedge rst) begin if (rst) devINTA = 4'b0; else begin if (wruREAD & (busPI == statPIH)) begin if (intREQ[7]) devINTA = 4'b1000; else if (intREQ[6]) devINTA = 4'b0100; else devINTA = 4'b0000; end else if (wruREAD & (busPI == statPIL)) begin if (intREQ[5]) devINTA = 4'b0010; else if (intREQ[4]) devINTA = 4'b0001; else devINTA = 4'b0000; end else devINTA = 4'b0000; end end // // NXM and NXD Decoding // // Details // NXD is asserted on an 'un-acked' IO request to the devices. // NXM is asserted on an 'un-acked' memory request to the devices. // wire devACKI = dev1ACKI | dev2ACKI; wire setNXD = ((devREQO & busREAD & busIO & ~devACKI) | (devREQO & busWRITE & busIO & ~devACKI)); wire setNXM = ((devREQO & busREAD & ~busIO & ~devACKI) | (devREQO & busWRITE & ~busIO & ~devACKI)); // // IO Bridge Status Register (IO Address 763100) // // Details: // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) |NM|BM|PE|ND| |HI|LO|PF| |DX|IN| PIH | PIL | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Register Definitions // // NM : Non-existent Memory - Set by NXM. Cleared by // writing a 1. // BM : Bad Memory Data - Always read as 0. Writes // are ignored. // PE : Bus Parity Error - Always read as 0. Writes // are ignored. // ND : Non-existant Device - Set by NXD. Cleared by // writing a 1. // HI : Hi level intr pend - IRQ on BR7 or BR6. Writes // are ignored. // LO : Lo level intr pend - IRQ on BR5 or BR4. Writes // are ignored. // PF : Power Fail - Always read as 0. Writes // are ignored. // DX : Diable Transfer - Read/Write. Does nothing. // IN : Initialize - Always read as 0. Writing // 1 resets all IO Bridge Devices. // PIH : Hi level PIA - R/W // PIL : Lo level PIA - R/W // reg statNM; reg statND; reg statDX; reg [0:2] statPIH; reg [0:2] statPIL; always @(posedge clk or posedge rst) begin if (rst) begin statNM <= 0; statND <= 0; statDX <= 0; statPIH <= 0; statPIL <= 0; end else if (clken) begin if (statWRITE) begin if (busDATAI[29]) begin statNM <= 0; statND <= 0; statDX <= 0; statPIH <= 0; statPIL <= 0; end else begin statNM <= statNM & ~busDATAI[18]; statND <= statND & ~busDATAI[21]; statDX <= busDATAI[28]; statPIH <= busDATAI[30:32]; statPIL <= busDATAI[33:35]; end end else begin // FIXME //statNM <= statNM | setNXM; //statND <= statNM | setNXD; end end end wire [18:35] regSTAT = {statNM, 2'b0, statND, 2'b0, statINTHI, statINTLO, 2'b0, statDX, 1'b0, statPIH, statPIL}; // // IO Bridge Reset Output // assign devRESET = statWRITE & busDATAI[29]; // // IO Bridge Maintenance Register (IO Address 763101) // // Details // SIMH reads this register as zero always and ignores writes. // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | |CR| // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // // CR : Change Register - Always read as 0. Writes // are ignored. // // // // IO Bridge Pager. IO Bridge Paging RAM is 763000 - 763077 // // Details // The page table translates IO Bridge addresses to phyical // addresses. There are 64 virtual pages which map to 2048 // physical pages. // // The IO Bridge Paging RAM is 64x15 bits. // // Note // The implementation is different than the KS10 implementation. // I have chosen to use a Dual Port RAM which allows the KS10 bus // interface to be implemented on one port (Read/Write) and the // IO Bridge Paging to be implemented on the second port (Read-only). // // This saves a whole ton of multiplexers and uses some free DPRAM. // // The IO Bridge addressing was little endian. This has all been // converted to big-endian to keep things consistent. // // 18 19 24 25 33 34 35 // +--+--------------------+--------------------+--+--+ // | 0| Virtual Page Number| Word Number |W | B| // +--+--------------------+--------------------+--+--+ // |6 |9 // | | // \ / | // +-------+-------+ | // | Page | | // | Translation | | // +-------+-------+ | // | | // | | // \ /11 \ /9 // +------------------------+------------------------+ // | Physical Page Number | Word Number | // +------------------------+------------------------+ // 16 26 27 35 // // Paging RAM Write // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) |FR|ES|FM|VA| 0| 0| 0| PPN | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Paging RAM Read // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | | 0|FR|ES|FM|VA| | PPN | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | PPN (cont) | | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Paging RAM Internal Format: // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // |FR|ES|FM|PV| PPN | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Paging RAM Definitions // // FR : Force Read-Pause-Write (AKA Read Reverse in the // documents). // ES : Enable 16-bit IO Bridge Transfers. Disable 18-bit // IO Bridge transfers. // FM : Fast Transfer Mode. In this mode, both odd and // even words of IO Bridge data are transferred during // a single KS10 memory operation (i.e., all 36 bits). // PV : Page valid. This bit is set to one when the page // data is loaded. // PPN : Physical Page Number. // wire [0: 5] addr = busADDRI[30:35]; reg [0:14] pageRAM[0:63]; always @(negedge clk) begin if (pageWRITE) pageRAM[addr] <= {busDATAI[18:21], busDATAI[25:35]}; end // // KS10 readback of Paging RAM // wire [0:35] pageDATAO = {5'b0, pageRAM[addr][0:3], 7'b0, pageRAM[addr][4:14], 9'b0}; // // IO Bridge Paging // wire [ 0:35] devADDRI = ((dev1REQI) ? dev1ADDRI : (dev2REQI) ? dev2ADDRI : 36'b0); wire [ 0: 5] virtPAGE = devADDRI[19:24]; // Virtual Page Number wire forceRPW = pageRAM[virtPAGE][0]; wire enable16 = pageRAM[virtPAGE][1]; wire fastMode = pageRAM[virtPAGE][2]; wire pageVALID = pageRAM[virtPAGE][3]; wire [16:26] physPAGE = pageRAM[virtPAGE][4:14]; // // Bus Initiator Paging // assign busADDRO = {devADDRI[0:13], 2'b0, physPAGE[16:26], devADDRI[27:35]}; assign busREQO = dev1REQI | dev2REQI; // // Bus Target Paging // assign devADDRO = busADDRI; assign dev1ACKO = 0; // FIXME assign dev2ACKO = 0; // FIXME // // Bus Data Out // reg busACKO; reg [0:35] busDATAO; always @(pageREAD or pageDATAO or statREAD or regSTAT or wruREAD or wruNUM1 or wruNUM3 or ctlNUM or statINTHI or statINTLO or busPI or statPIH or statPIL or devREAD or devWRITE or vectREAD or dev1ACKI or dev2ACKI or dev1DATAI or dev2DATAI or statWRITE) begin busACKO = 1'b0; busDATAO = 36'bx; if (pageREAD) begin busACKO = 1'b1; busDATAO = pageDATAO; end if (statREAD) begin busACKO = 1'b1; busDATAO = {18'b0, regSTAT}; end if ((wruREAD & (busPI == statPIH)) | (wruREAD & (busPI == statPIL))) begin busACKO = 1'b1; case (ctlNUM) ctlNUM0: busDATAO = wruNUM0; // Bit 18 ctlNUM1: busDATAO = wruNUM1; // Bit 19 ctlNUM2: busDATAO = wruNUM2; // Bit 20 ctlNUM3: busDATAO = wruNUM3; // Bit 21 default: busDATAO = 36'b0; endcase end if (devREAD | devWRITE | vectREAD) begin busACKO = dev1ACKI | dev2ACKI; if (dev1ACKI) busDATAO = dev1DATAI; else if (dev2ACKI) busDATAO = dev2DATAI; else busDATAO = 36'b0; end if (statWRITE) begin busACKO = 1; busDATAO = 36'b0; end end // // Device Data Out // assign devDATAO = busDATAI; endmodule Dist/rtl/ks10/uba/uba.vh0000700000175100010010000000412412151540222013372 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // IO Bus (Unibus) Definitions // // Details // Contains definitions that are useful to the IO Bus (Unibus) // adapters. // // File // uba.vh // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `ifndef __UBA_VH `define __UBA_VH // // UBA Device Number Definitions // `define ctlNUM0 (4'd0) // IO Bridge Controller #0 (not implemented) `define ctlNUM1 (4'd1) // IO Bridge Controller #1 `define ctlNUM2 (4'd2) // IO Bridge Controller #2 (not implemented) `define ctlNUM3 (4'd3) // IO Bridge Controller #3 // // Who Are You (WRU) Responses // `define wruNUM0 36'o000000_400000 // IO Bridge Controller #0 WRU Response `define wruNUM1 36'o000000_200000 // IO Bridge Controller #1 WRU Response `define wruNUM2 36'o000000_100000 // IO Bridge Controller #2 WRU Response `define wruNUM3 36'o000000_040000 // IO Bridge Controller #3 WRU Response `endif Dist/rtl/ks10/uba/ubanew.v0000700000175100010010000005156012120030224013732 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS-10 Processor // // Brief // KS10 IO Bus Bridge // // Details // This device 'bridges' the KS10 FPGA backplane bus to the IO // IO Bus. On a real KS10, the IO bus was UNIBUS. The IO // Bus in the KS10 FPGA is not UNIBUS. // // Notes // Important addresses: // // 763000-763077 : IO Bridge Paging RAM // 763100 : IO Bridge Status Register // 763101 : IO Bridge Maintenace Register // // File // uba.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none `include "uba.vh" `include "../ks10.vh" module UBA(clk, rst, clken, ctlNUM, // KS10 Bus Interface busREQI, busREQO, busACKI, busACKO, busADDRI, busADDRO, busDATAI, busDATAO, busINTR, // Device Interface devREQI, devREQO, devACKI, devACKO, devADDRI, devADDRO, devDATAI, devDATAO, devINTA, devRESET); input clk; // Clock input rst; // Reset input clken; // Clock enable input [ 0: 3] ctlNUM; // Bridge Device Number // KS10 Backplane Bus Interface input busREQI; // Backplane Bus Request In output busREQO; // Backplane Bus Request Out input busACKI; // Backplane Bus Acknowledge In output busACKO; // Backplane Bus Acknowledge Out input [ 0:35] busADDRI; // Backplane Bus Address In output [ 0:35] busADDRO; // Backplane Bus Address Out input [ 0:35] busDATAI; // Backplane Bus Data In output [ 0:35] busDATAO; // Backplane Bus Data Out output [ 1: 7] busINTR; // Backplane Bus Interrupt Request // Device Interface input [ 0: 3] devREQI; // IO Device Request In output devREQO; // IO Device Request Out input [ 0: 3] devACKI; // IO Device Acknowledge In output [ 0: 3] devACKO; // IO Device Acknowledge Out input [ 0:35] devADDRI[0:3]; // IO Device Address In output [ 0:35] devADDRO; // IO Device Address Out input [ 0:35] devDATAI[0:3]; // IO Device Data In output [ 0:35] devDATAO; // IO Device Data Out output devRESET; // IO Device Reset // // IO Bridge Configuration // parameter [14:17] ctlNUM0 = `ctlNUM0; // IO Bridge Device 0 parameter [14:17] ctlNUM1 = `ctlNUM1; // IO Bridge Device 1 parameter [14:17] ctlNUM2 = `ctlNUM2; // IO Bridge Device 2 parameter [14:17] ctlNUM3 = `ctlNUM3; // IO Bridge Device 3 parameter [18:35] wruNUM0 = `wruNUM0; // IO Bridge Device 0 WRU Response (bit 18) parameter [18:35] wruNUM1 = `wruNUM1; // IO Bridge Device 1 WRU Response (bit 19) parameter [18:35] wruNUM2 = `wruNUM2; // IO Bridge Device 2 WRU Response (bit 20) parameter [18:35] wruNUM3 = `wruNUM3; // IO Bridge Device 3 WRU Response (bit 21) // // IO Addresses // parameter [18:35] pageADDR = 18'o763000; // Paging RAM Address parameter [18:35] statADDR = 18'o763100; // Status Register Address parameter [18:35] maintADDR = 18'o763101; // Maintenance Register Address parameter [18:26] ctrlADDR = 9'o763; // Bridge Registers // // Address Bus // // Details: // busADDRI[ 0:13] is flags // busADDRI[14:35] is address // wire busREAD = busADDRI[ 3]; // 1 = Read Cycle (IO or Memory) wire busWRITE = busADDRI[ 5]; // 1 = Write Cycle (IO or Memory) wire busPHYS = busADDRI[ 8]; // 1 = Physical reference wire busIO = busADDRI[10]; // 1 = IO Cycle, 0 = Memory Cycle wire busWRU = busADDRI[11]; // 1 = Read interrupting controller number wire busVECT = busADDRI[12]; // 1 = Read interrupt vector wire busIOBYTE = busADDRI[13]; // 1 = IO Bridge Byte IO Operation wire [15:17] busPI = busADDRI[15:17]; // IO Bridge PI Request wire [14:17] busCTL = busADDRI[14:17]; // IO Bridge Device Number wire [18:35] busADDR = busADDRI[18:35]; // IO Address // // Address Decoding // wire wruREAD = busIO & busWRU & busPHYS; wire vectREAD = busIO & busVECT & (busCTL == ctlNUM); wire pageREAD = busIO & busREAD & (busCTL == ctlNUM) & (busADDR[18:29] == pageADDR[18:29]); wire pageWRITE = busIO & busWRITE & (busCTL == ctlNUM) & (busADDR[18:29] == pageADDR[18:29]); wire statWRITE = busIO & busWRITE & (busCTL == ctlNUM) & (busADDR[18:35] == statADDR[18:35]); wire statREAD = busIO & busREAD & (busCTL == ctlNUM) & (busADDR[18:35] == statADDR[18:35]); wire devREAD = busIO & busREAD & (busCTL == ctlNUM) & (busADDR[18:20] == ctrlADDR[18:20]) & (busADDR[21:26] != ctrlADDR[21:26]); wire devWRITE = busIO & busWRITE & (busCTL == ctlNUM) & (busADDR[18:20] == ctrlADDR[18:20]) & (busADDR[21:26] != ctrlADDR[21:26]); // // IO Bridge Interrupt Request // wire [7:4] intREQ = dev1INTR | dev2INTR; wire statINTHI = intREQ[7] | intREQ[6]; wire statINTLO = intREQ[5] | intREQ[4]; // // High Priority Interrupt // // Trace // UBA3/E180 // reg [1:7] devINTRH; always @(statINTHI or statPIH) begin if (statINTHI) case (statPIH) 0: devINTRH <= 7'b0000000; 1: devINTRH <= 7'b1000000; 2: devINTRH <= 7'b0100000; 3: devINTRH <= 7'b0010000; 4: devINTRH <= 7'b0001000; 5: devINTRH <= 7'b0000100; 6: devINTRH <= 7'b0000010; 7: devINTRH <= 7'b0000001; endcase else devINTRH <= 7'b0000000; end // // High Priority Interrupt // // Trace // UBA3/E182 // reg [1:7] devINTRL; always @(statINTLO or statPIL) begin if (statINTLO) case (statPIL) 0: devINTRL <= 7'b0000000; 1: devINTRL <= 7'b1000000; 2: devINTRL <= 7'b0100000; 3: devINTRL <= 7'b0010000; 4: devINTRL <= 7'b0001000; 5: devINTRL <= 7'b0000100; 6: devINTRL <= 7'b0000010; 7: devINTRL <= 7'b0000001; endcase else devINTRL <= 7'b0000000; end // // IO Bridge Interrupt Request // // Trace // UBA3/E179 // UBA3/E181 // assign busINTR = devINTRL | devINTRH; // // IO Bridge Interrupt Acknowledge // // Trace // UBA7/E27 // UBA7/E39 // UBA7/E53 // UBA7/E113 // UBA7/E184 // UBA7/E185 // reg [7:4] devINTA; always @(posedge clk or posedge rst) begin if (rst) devINTA = 4'b0; else begin if (wruREAD & (busPI == statPIH)) begin if (intREQ[7]) devINTA = 4'b1000; else if (intREQ[6]) devINTA = 4'b0100; else devINTA = 4'b0000; end else if (wruREAD & (busPI == statPIL)) begin if (intREQ[5]) devINTA = 4'b0010; else if (intREQ[4]) devINTA = 4'b0001; else devINTA = 4'b0000; end else devINTA = 4'b0000; end end // // NXM and NXD Decoding // // Details // NXD is asserted on an 'un-acked' IO request to the devices. // NXM is asserted on an 'un-acked' memory request to the devices. // wire devACK = devACKI[0] | devACKI[1] | devACKI[2] | devACKI[3]; wire setNXD = ((devREQO & busREAD & busIO & ~devACK) | (devREQO & busWRITE & busIO & ~devACK)); wire setNXM = ((devREQO & busREAD & ~busIO & ~devACK) | (devREQO & busWRITE & ~busIO & ~devACK)); // // IO Bridge Status Register (IO Address 763100) // // Details: // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) |NM|BM|PE|ND| |HI|LO|PF| |DX|IN| PIH | PIL | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Register Definitions // // NM : Non-existent Memory - Set by NXM. Cleared by // writing a 1. // BM : Bad Memory Data - Always read as 0. Writes // are ignored. // PE : Bus Parity Error - Always read as 0. Writes // are ignored. // ND : Non-existant Device - Set by NXD. Cleared by // writing a 1. // HI : Hi level intr pend - IRQ on BR7 or BR6. Writes // are ignored. // LO : Lo level intr pend - IRQ on BR5 or BR4. Writes // are ignored. // PF : Power Fail - Always read as 0. Writes // are ignored. // DX : Diable Transfer - Read/Write. Does nothing. // IN : Initialize - Always read as 0. Writing // 1 resets all IO Bridge Devices. // PIH : Hi level PIA - R/W // PIL : Lo level PIA - R/W // reg statNM; reg statND; reg statDX; reg [0:2] statPIH; reg [0:2] statPIL; always @(posedge clk or posedge rst) begin if (rst) begin statNM <= 0; statND <= 0; statDX <= 0; statPIH <= 0; statPIL <= 0; end else if (clken) begin if (statWRITE) begin if (busDATAI[29]) begin statNM <= 0; statND <= 0; statDX <= 0; statPIH <= 0; statPIL <= 0; end else begin statNM <= statNM & ~busDATAI[18]; statND <= statND & ~busDATAI[21]; statDX <= busDATAI[28]; statPIH <= busDATAI[30:32]; statPIL <= busDATAI[33:35]; end end else begin // FIXME //statNM <= statNM | setNXM; //statND <= statNM | setNXD; end end end wire [18:35] regSTAT = {statNM, 2'b0, statND, 2'b0, statINTHI, statINTLO, 2'b0, statDX, 1'b0, statPIH, statPIL}; // // IO Bridge Reset Output // assign devRESET = statWRITE & busDATAI[29]; // // IO Bridge Maintenance Register (IO Address 763101) // // Details // SIMH reads this register as zero always and ignores writes. // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | |CR| // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // // CR : Change Register - Always read as 0. Writes // are ignored. // // // // IO Bridge Pager. IO Bridge Paging RAM is 763000 - 763077 // // Details // The page table translates IO Bridge addresses to phyical // addresses. There are 64 virtual pages which map to 2048 // physical pages. // // The IO Bridge Paging RAM is 64x15 bits. // // Note // The implementation is different than the KS10 implementation. // I have chosen to use a Dual Port RAM which allows the KS10 bus // interface to be implemented on one port (Read/Write) and the // IO Bridge Paging to be implemented on the second port (Read-only). // // This saves a whole ton of multiplexers and uses some free DPRAM. // // The IO Bridge addressing was little endian. This has all been // converted to big-endian to keep things consistent. // // 18 19 24 25 33 34 35 // +--+--------------------+--------------------+--+--+ // | 0| Virtual Page Number| Word Number |W | B| // +--+--------------------+--------------------+--+--+ // |6 |9 // | | // \ / | // +-------+-------+ | // | Page | | // | Translation | | // +-------+-------+ | // | | // | | // \ /11 \ /9 // +------------------------+------------------------+ // | Physical Page Number | Word Number | // +------------------------+------------------------+ // 16 26 27 35 // // Paging RAM Write // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) |FR|ES|FM|VA| 0| 0| 0| PPN | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Paging RAM Read // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (LH) | | 0|FR|ES|FM|VA| | PPN | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // (RH) | PPN (cont) | | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Paging RAM Internal Format: // // 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // |FR|ES|FM|PV| PPN | // +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ // // Paging RAM Definitions // // FR : Force Read-Pause-Write (AKA Read Reverse in the // documents). // ES : Enable 16-bit IO Bridge Transfers. Disable 18-bit // IO Bridge transfers. // FM : Fast Transfer Mode. In this mode, both odd and // even words of IO Bridge data are transferred during // a single KS10 memory operation (i.e., all 36 bits). // PV : Page valid. This bit is set to one when the page // data is loaded. // PPN : Physical Page Number. // wire [0: 5] addr = busADDRI[30:35]; reg [0:14] pageRAM[0:63]; always @(negedge clk) begin if (pageWRITE) pageRAM[addr] <= {busDATAI[18:21], busDATAI[25:35]}; end // // KS10 readback of Paging RAM // wire [0:35] pageDATAO = {5'b0, pageRAM[addr][0:3], 7'b0, pageRAM[addr][4:14], 9'b0}; // // IO Bridge Paging // wire [ 0:35] devADDR = ((devREQI[0]) ? devADDRI[0] : (devREQI[1]) ? devADDRI[1] : (devREQI[2]) ? devADDRI[2] : (devREQI[3]) ? devADDRI[3] : 36'b0); wire [ 0: 5] virtPAGE = devADDR[19:24]; // Virtual Page Number wire forceRPW = pageRAM[virtPAGE][0]; wire enable16 = pageRAM[virtPAGE][1]; wire fastMode = pageRAM[virtPAGE][2]; wire pageVALID = pageRAM[virtPAGE][3]; wire [16:26] physPAGE = pageRAM[virtPAGE][4:14]; // // Bus Initiator Paging // assign busADDRO = {devADDR[0:13], 2'b0, physPAGE[16:26], devADDR[27:35]}; assign busREQO = devREQI[0] | devREQI[1] | devREQI[2] | devREQI[3]; // // Bus Target Paging // assign devADDRO = busADDRI; assign devACKO = 0; // FIXME // // Bus Data Out // reg busACKO; reg [0:35] busDATAO; always @(pageREAD or pageDATAO or statREAD or regSTAT or wruREAD or wruNUM1 or wruNUM3 or ctlNUM or statINTHI or statINTLO or busPI or statPIH or statPIL or devREAD or devWRITE or vectREAD or devACKI or devDATAI or statWRITE) begin busACKO = 1'b0; busDATAO = 36'b0; if (pageREAD) begin busACKO = 1; busDATAO = pageDATAO; end if (statREAD) begin busACKO = 1; busDATAO = {18'b0, regSTAT}; end if ((wruREAD & (busPI == statPIH)) | (wruREAD & (busPI == statPIL))) begin busACKO = 1; case (ctlNUM) ctlNUM0: busDATAO = wruNUM0; // Bit 18 ctlNUM1: busDATAO = wruNUM1; // Bit 19 ctlNUM2: busDATAO = wruNUM2; // Bit 20 ctlNUM3: busDATAO = wruNUM3; // Bit 21 endcase end if (devREAD | devWRITE | vectREAD) begin busACKO = devACKI[0] | devACKI[1] | devACKI[2] | devACKI[3]; if (devACKI[0]) busDATAO = devDATAI[0]; else if (devACKI[1]) busDATAO = devDATAI[1]; else if (devACKI[2]) busDATAO = devDATAI[2]; else if (devACKI[3]) busDATAO = devDATAI[3]; end if (statWRITE) begin busACKO = 1; busDATAO = 36'b0; end end // // Device Data Out // assign devDATAO = busDATAI; endmodule Dist/rtl/ks10/utils/0000700000175100010010000000000012151543066012662 5ustar RobNoneDist/rtl/ks10/utils/utils.v0000700000175100010010000000352112151540224014206 0ustar RobNone//////////////////////////////////////////////////////////////////// // // KS10 Processor // // Brief // Utilities // // Details // // Notes // // File // utils.v // // Author // Rob Doyle - doyle (at) cox (dot) net // //////////////////////////////////////////////////////////////////// // // Copyright (C) 2012-2013 Rob Doyle // // This source file may be used and distributed without // restriction provided that this copyright statement is not // removed from the file and that any derivative work contains // the original copyright notice and the associated disclaimer. // // This source file is free software; you can redistribute it // and/or modify it under the terms of the GNU Lesser General // Public License as published by the Free Software Foundation; // version 2.1 of the License. // // This source is distributed in the hope that it will be // useful, but WITHOUT ANY WARRANTY; without even the implied // warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR // PURPOSE. See the GNU Lesser General Public License for more // details. // // You should have received a copy of the GNU Lesser General // Public License along with this source; if not, download it // from http://www.gnu.org/licenses/lgpl.txt // //////////////////////////////////////////////////////////////////// `default_nettype none module EDGETRIG(clk, rst, clken, pol, i, o); input clk; // Clock input rst; // Reset input clken; // Clock Enable input pol; // Polarity input i; // Input output o; // Output reg last; always @(posedge clk or posedge rst) begin if (rst) last <= 0; else if (clken) last <= i; end assign o = (pol) ? (i & ~last) : (~i & last); endmodule Dist/rtl/status.txt0000700000175100010010000000373112151540236013033 0ustar RobNoneTest Status DSKAAA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 1) Test Pass DSKABA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 2) Test Pass DSKACA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 3) Test Pass DSKADA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 4) Test Pass DSKAEA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 5) Test Pass DSKAFA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 6) Test Pass DSKAGA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 7) Test Pass DSKAHA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 8) Test Pass DSKAIA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC ( 9) Test Pass DSKAJA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (10) Test Pass DSKAKA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (11) Test Pass DSKALA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (12) Test Pass DSKAMA0 DECSYSTEM 2020 BASIC INSTRUCTION DIAGNOSTIC (13) Test Pass DSKBAA0 DECSYSTEM 2020 BASIC INSTRUCTION RELIABILITY DIAGNOSTIC (1) Test Pass DSKCAA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (1) Test Pass DSKCBA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (2) Test Pass DSKCCA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (3) Test Pass DSKCDA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (4) Test Pass DSKCEA0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (5) Test Pass DSKCFC0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (6) Test Pass DSKCGB0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (7) Test Fail at PC=030644 (read x from addr 000041) DSKDAB0 DECSYSTEM 2020 CPU & MEMORY RELIABILITY DIAGNOSTIC DSKEAA0 DECSYSTEM 2020 PAGING HARDWARE DIAGNOSTIC Test Fail at PC=30702 (note 4) DSKEBA0 KS10 - CACHE DIAGNOSTIC DSKECB0 KS10 - KL-PAGING DIAGNOSTIC DSKFAA0 DECSYSTEM 2020 INSTRUCTION TIMING DIAGNOSTIC DSQDCC0 DECSYSTEM 2020 DIAGNOSTIC MONITOR DSDZA.SAV TODO: 1. NI_DISP : fix memory cycle. 2. CPU : fix memory timing. 3. mem.awk : fix to work on sixbit 4. Search for FIXME is the code. Dist/rtl/testbench/0000700000175100010010000000000012151542777012733 5ustar RobNoneDist/rtl/testbench/MAINDEC-10-DSKCF-RD00.SEQ0000700000175100010010000306760612151540234016065 0ustar RobNone;DSKCF SEQ 0001 IDENTIFICATION -------------- PRODUCT CODE: AH-F247C-DD DIAGNOSTIC CODE: DSKCF PRODUCT NAME: DSKCFC0 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (6) VERSION: 0.3 DATE RELEASED: SEPTEMBER 1979 MAINTAINED BY: DIAGNOSTIC ENGINEERING AUTHOR: JOHN R. KIRCHOFF RICHARD E. STOCKDALE COPYRIGHT (C) 1978, 1979 DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS. THIS SOFTWARE IS FURNISHED UNDER A LICENSE FOR USE ONLY ON A SINGLE COMPUTER SYSTEM AND MAY BE COPIED ONLY WITH THE INCLUSION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE, OR ANY OTHER COPIES THEREOF, MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY OTHER PERSON EXCEPT FOR USE ON SUCH SYSTEM AND TO ONE WHO AGREES TO THESE LICENSE TERMS. TITLE TO AND OWNERSHIP OF THE SOFTWARE SHALL AT ALL TIMES REMAIN IN DIGITAL EQUIPMENT CORPORATION. THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL EQUIPMENT CORPORATION. DIGITAL EQUIPMENT CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF ITS SOFTWARE IN EQUIPMENT WHICH IS NOT SUPPLIED BY DIGITAL EQUIPMENT CORPORATION. MAINDEC-10-DSKCF.TXT PAGE 2 SEQ 0002 TABLE OF CONTENTS ----------------- 1.0 ABSTRACT 2.0 REQUIREMENTS 2.1 EQUIPMENT 2.2 STORAGE 2.3 PRELIMINARY PROGRAMS 3.0 PROGRAM PROCEDURES 3.1 LOADING PROCEDURE 3.2 STARTING PROCEDURE 3.3 OPERATING PROCEDURE 4.0 DATA SWITCH FUNCTIONS 5.0 ERRORS 6.0 ITERATION COUNTER 7.0 CYCLE TIME 8.0 OPERATIONAL VARIATIONS 9.0 MISCELLANEOUS 10.0 LISTING MAINDEC-10-DSKCF.TXT PAGE 3 SEQ 0003 1.0 ABSTRACT THIS DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC IS THE SIXTH IN A SERIES OF DECSYSTEM 2020 ADVANCED PROCESSOR DIAGNOSTICS. THE DIAGNOSTIC PERFORMS LOGIC TESTING OF THE PROCESSOR AND MICRO-CODE DOUBLE PRECISION FIXED POINT INSTRUCTIONS: DADD, DSUB, DMUL, DDIV. 2.0 REQUIREMENTS 2.1 EQUIPMENT A DECSYSTEM 2020 EQUIPPED WITH A MINIMUM OF 32K OF MEMORY CONSOLE PROCESSOR CONSOLE TELETYPE LOAD DEVICE 2.2 STORAGE THE PROGRAM RUNS WITHIN 32K OF MEMORY. 2.3 PRELIMINARY PROGRAMS PREVIOUS PROCESSOR DIAGNOSTICS 3.0 PROGRAM PROCEDURES 3.1 LOADING PROCEDURE ****** NOTE ****** THIS DIAGNOSTIC REQUIRES THAT THE DECSYSTEM 2020 SUBROUTINE PROGRAM BE RESIDENT IN THE DECSYSTEM 2020. FOLLOW THE APPROPRIATE DIAGNOSTIC LOADING PROCEDURES. MAINDEC-10-DSKCF.TXT PAGE 4 SEQ 0004 3.2 STARTING PROCEDURE A. SELECT OPERATIONAL CONSOLE DATA SWITCH SETTINGS (REFER TO 4.0 DATA SWITCH FUNCTIONS). RUN UNDER "SMMON". THE FOLLOWING QUESTIONS WILL BE ASKED TO SELECT THE OPERATIONAL SWITCHES: TELETYPE SWITCH CONTROL ? 0,S OR Y (CR) - IF THE OPERATOR TYPES "Y", THE FOLLOWING QUESTIONS ARE ASKED AND THE OPERATOR RESPONDS BY TYPING THE ANSWER AS SIX OCTAL DIGITS REPRESENTING THE DESIRED SWITCH SETTINGS. SPECIFY LH SWITCHES IN OCTAL- SPECIFY RH SWITCHES IN OCTAL- IF THE OPERATOR TYPES "0", ZERO'S ARE USED FOR THE SWITCH SETTINGS. IF THE OPERATOR TYPES "S", PREVIOUSLY SET SWITCHES ARE USED. THIS IS ONLY VALID UPON RESTARTING OF AN INTERRUPTED PROGRAM. MAINDEC-10-DSKCE.TXT PAGE 5 SEQ 0005 3.3 OPERATING PROCEDURE A. TO THROUGHLY TEST ALL HARDWARE, ALL TEST CONTROL DATA SWITCHES SHOULD BE SET TO 0. B. WHEN DEBUGGING HARDWARE, SET SWITCHES TO 0. ALLOW THE TELETYPE TO PRINT THE ERROR MESSAGES. THIS ALLOWS THE PROGRAM TO RUN A COMPLETE PASS AND THEN THE ERROR MESSAGES MAY BE CORRELATED TO QUICKLY DIAGNOSE THE FAILURE. IF A HARDWARE PROBLEM IS SUCH THAT THE ERROR MESSAGES, AFTER THE FIRST ONE, HAVE NO MEANING (FIRST ERROR CAUSES ALL FOLLOWING TESTS TO FAIL) SET THE LOOP ON ERROR SWITCH AND RESTART THE TEST FROM THE BEGINNING. THE FIRST FAILURE WILL THEN CAUSE THE PROGRAM TO ENTER A LOOP SUITABLE FOR SCOPING. THE ERROR MESSAGE USED IN CONJUNCTION WITH THE LISTING AND SCOPING IF NECESSARY SHOULD ALLOW THE FAILING CONPONENT TO BE ISOLATED AND REPLACED AND/OR REPAIRED. C. WHEN TAKING MARGINS, SET DATA SWITCHES 'NOPNT' AND 'DING'. THIS WILL INHIBIT PRINTOUT BUT WILL ALLOW THE TELETYPE BELL TO BE RUNG WHEN A ERROR OCCURS. IF THE MARGIN OBTAINED IS UNACCEPTABLE, THE OPERATOR MAY REVERT TO STANDARD SWITCH SETTINGS FOR DEBUGGING PURPOSES. D. ERROR INFORMATION MAY BE OBTAINED QUICKLY BY PRINTING ERRORS ON THE LINE PRINTER. E. IN THE EVENT OF A PRINT ROUTINE FAILURE THE 'NOPNT' SWITCH AND THE 'ERSTOP' SWITCH MAY BE SET TO INHIBIT PRINTOUT BUT HALT THE PROGRAM POINTING TO THE ERROR. MAINDEC-10-DSKCF.TXT PAGE 6 SEQ 0006 4.0 DATA SWITCH FUNCTIONS SWITCH STATE FUNCTION ------ ----- -------- 0 ABORT 0 NORMAL OPERATION 1 ABORT AT END OF PASS 1 RSTART NOT USED 2 TOTALS NOT USED 3 NOPNT 0 NORMAL TYPEOUT 1 INHIBIT ALL PRINT/TYPEOUT (EXCEPT FORCED) 4 PNTLPT 0 NORMAL OUTPUT TO TTY 1 PRINT ALL DATA ON LPT (LOGICAL DEVICE, USER MODE) 5 DING 0 NO FUNCTION 1 RING TTY BELL ON ERROR 6 LOOPER 0 PROCEED TO NEXT TEST 1 ENTER SCOPE LOOP ON TEST ERROR 7 ERSTOP 0 NO FUNCTION 1 HALT ON TEST ERROR 8 PALERS 0 PRINT ONLY FIRST ERROR WHEN LOOPING 1 PRINT ALL ERRORS, EVEN IF SAME ERROR 9 RELIAB NOT USED 10 TXTINH 0 PRINT FULL ERROR MESSAGES. 1 INHIBIT COMMENT PORTION OF ERROR MESSAGES. 11 INHPAG 0 ALLOW PAGING AND TRAP ENABLE 1 INHIBIT PAGING AND TRAPPING 12 MODDVC NOT USED 13 INHCSH 0 ALLOW CACHE USE 1 INHIBIT CACHE MAINDEC-10-DSKCF.TXT PAGE 7 SEQ 0007 5.0 ERRORS ERRORS ARE PRINTED ON THE TTY OR LINE PRINTER. THE ERROR PRINTOUT CONTAINS THE TEST TITLE, THE PC OF THE FAILURE, ERROR NUMBER AND THE CONTENTS OF AN APPLICABLE AC. THE PC VALUE IS USEFUL IN RELATING THE FAILURE TO THE LISTING. THE ERROR NUMBER IS PROVIDED SUCH THAT AN ERROR DICTIONARY MAY BE MADE AT SOME FUTURE DATE. IF AN AUDIO INDICATION OF A CONTINUING ERROR IS DESIRED THE 'DING' SWITCH MAY BE SET. 6.0 ITERATION COUNTER THE ITERATION COUNT OF THE PROGRAM IS PRINTED BY THE CONSOLE PROCESSOR. 7.0 CYCLE TIME THE CYCLE TIME OF THE PROGRAM IS IN THE MILLISECOND RANGE AND IS THEREFORE SUITABLE FOR TAKING MARGINS, VIBRATION TESTS, ETC. MAINDEC-10-DSKCF.TXT PAGE 8 SEQ 0008 8.0 OPERATIONAL VARIATIONS A. DIAGNOSTIC MONITOR THE PROGRAM IS USABLE WITH THE DIAGNOSTIC MONITOR TO PROVIDE RELIABILITY TESTS, ACCEPTANCE TESTS, AND/OR TO PROVIDE A QUICK METHOD OF ISOLATION OF A FAULT TO A PARTICULAR AREA OF THE PROCESSOR. CERTAIN PROCEDURES ARE USED WHEN THE PROGRAM IS USED IN THIS MANNER. THEY ARE: 1. THE DIAGNOSTIC MONITOR TRANSFERS CONTROL TO THE PROGRAM AND STARTS IT AT LOCATION 30002. 2. MONCTL - LOCATION 30043 IS USED AS THE DIAGNOSTIC MONITOR CONTROL WORD. LH = 0, STAND-ALONE OPERATION -1, RUNNING UNDER DIAGNOSTIC MONITOR RH = RIGHT HALF OF CONSOLE SWITCHES IF UNDER DIAGNOSTIC MONITOR CONTROL. B. USER MODE TO OUTPUT THE PRINTED ERROR MESSAGES TO A USER SPECIFIED DEVICE IN USER MODE, ASSIGN THE DESIRED OUTPUT DEVICE TO DEVICE NAME 'DEV' AND SET SWITCH 'PNTLPT'. THE PHYSICAL DEVICE USED CAN BE ANY DEVICE THAT CAN ACCEPT ASCII OUTPUT FORMAT SUCH AS LPT, DSK, DTA, ETC. THE CORRESPONDING OUTPUT FILE IS 'DSKCF.LPT' EXAMPLE DEVICE ASSIGNMENT: .ASSIGN DSK DEV IN USER MODE THE PROGRAM WILL MAKE 10(8) PASSES AND THEN RETURN TO SMMON COMMAND MODE. MAINDEC-10-DSKCF.TXT PAGE 9 SEQ 0009 8.0 OPERATIONAL VARIATIONS (CON'T) THE OUTPUT FILE (IF USED) MAY THEN BE LISTED BY USING THE NORMAL MONITOR COMMANDS (PRINT, LIST, TYPE, PIP, ETC.). IF THE PROGRAM IS ABORTED BEFORE COMPLETION (BY ^C, ETC.) THE OUTPUT FILE MAY BE CLOSED BY USING THE MONITOR 'REENTER' COMMAND. C. SYSTEM EXERCISER START ADDRESS IS 30003. DATA SWITCHES ARE PRESTORED IN 'SWTEXR' LOC 30023. 9.0 MISCELLANEOUS THE NON-EX-MEMORY AND PARITY STOP SWITCHES SHOULD BE RESET (0). THESE ERRORS, ILLEGAL UUO'S AND OTHER ERRORS OF THIS TYPE ARE HANDLED BY PRINTOUT ON THE TELETYPE. 10.0 LISTING HISTORY FILE FOR DSKCF SEQ 0010 --------------------------------------------------------------- CODE: MAINDEC-10-DSKCF TITLE: DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC (6) VERSION: 0.3 DATE: SEPTEMBER 1979 AUTHOR: JOHN R. KIRCHOFF REASON: CLEANUP OF DOCUMENTATION PRIOR TO CONVERSION TO A KL10 PROGRAM. --------------------------------------------------------------- VERSION: 0.2 DATE: APRIL 1979 AUTHOR: RICHARD E. STOCKDALE REASON: ADDED ADDL CODE TO ALLOW IT TO RUN ON A KL10 AS WELL AS A KS10 (RE: DDIV AND HOW OVERFLOW CONDITION IS HANDLED). --------------------------------------------------------------- VERSION: 0.1 DATE: NOVEMBER 1978 AUTHOR: RICHARD E. STOCKDALE REASON: ORIGINAL RELEASE OF THIS PROGRAM FOR KS-10. --------------------------------------------------------------- DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 1 SEQ 0011 DOCUMENT ************** DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 ************** COPYRIGHT 1979 DIGITAL EQUIPMENT CORPORATION MAYNARD, MASS. 01754 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 2 SEQ 0012 TABLE OF CONTENTS ******************* 29 ASSEMBLY TIME PARAMETERS 72 MACROS 280 CONSOLE DATA SWITCH ASSIGNMENTS, SEPTEMBER 1979 315 PROGRAM/SUBROUTINE PARAMETERS 517 ERROR HANDLING UUO DEFINITIONS 555 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 883 INITIALIZATION SECTION 922 DADD - TEST A 1112 DADD - TEST B 1618 DADD - TEST C 1671 DADD - TEST D 1730 DADD - TEST E 2062 DADD - TEST F 3680 DADD - TEST G 4143 DSUB - TEST A 4307 DSUB - TEST B 4455 DSUB - TEST C 5533 DSUB - TEST D 6006 DMUL - TEST A 6269 DMUL - TEST B 6509 DMUL - TEST C 7076 DMUL - TEST D DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 3 SEQ 0013 TABLE OF CONTENTS ******************* 7647 DMUL - TEST E (OVERFLOW) 7698 DMUL - TEST F - TEST NEGATIVE OPERANDS 7819 DMUL - TEST G 8479 DDIV - TEST A 8531 DDIV - TEST B 8581 DDIV - TEST C 9075 DDIV - TEST D 9419 DDIV - TEST E 9882 DDIV - TEST F 10130 DDIV - TEST G 11106 TESTING SUBROUTINES 11281 ADDL ERROR PRINT ROUTINES 11453 *STOR* RESERVED STORAGE, SEPTEMBER 1979 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 4 SEQ 0014 1 MAINDEC-10-DSKCF 18 COPYRIGHT 1979 DIGITAL EQUIPMENT CORPORATION MARLBORO, MASS. 22 JOHN R. KIRCHOFF RICHARD E. STOCKDALE ***************************************************************** 29 ASSEMBLY TIME PARAMETERS ***************************************************************** 32 ACCUMULATOR DEFINITIONS 46 BEGIN PARAMETERS ***************************************************************** 72 MACROS ***************************************************************** 75 PCSAVE - GET AND SAVE PC 85 TFLAG - TEST PC FLAGS SET BY THE PRIOR DADD/DSUB 98 MULT - PERFORM DMUL AND TEST RESULTS 115 MULTF - PERFORM DMUL AND TEST RESULTS & PC FLAGS 136 PDIV - PERFORM DDIV AND TEST RESULTS 154 PDIVF - PERFORM DDIV AND TEST RESULTS & PC FLAGS 176 ODIV - PERFORM DDIV AND TEST RESULTS & PC FLAGS (HANDLES OVERFLOW/NO DIVIDE CONDITIONS) 200 CHECKA - CHECK RESULTS OF A DADD & DO ERROR HANDLING (RESULT 'R1' IS PASSED AS THE OCTAL DATA ITSELF) 220 CHECKS - CHECK RESULTS OF A DSUB & DO ERROR HANDLING (RESULT 'R1' IS PASSED AS THE OCTAL DATA ITSELF) 241 CHECKB - CHECK RESULTS OF A DADD & DO ERROR HANDLING (RESULT 'R1' IS PASSED AS THE ADDRESS OF THE DATA) 261 CHECKT - CHECK RESULTS OF A DSUB & DO ERROR HANDLING (RESULT 'R1' IS PASSED AS THE ADDRESS OF THE DATA) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 5 SEQ 0015 ***************************************************************** 280 CONSOLE DATA SWITCH ASSIGNMENTS, SEPTEMBER 1979 ***************************************************************** 285 DATA SWITCHES LEFT HALF SWITCHES ARE PRE-ASSIGNED FOR SUBROUTINE PACKAGE USE AND CONTROL LOOPING, PRINTING (TTY OR OTHER DEVICE) AND MISC. FUNCTIONS ***************************************************************** 315 PROGRAM/SUBROUTINE PARAMETERS ***************************************************************** 318 SPECIAL SUBPROGRAM LINKAGES 329 SPECIAL SUBROUTINE FATAL HALTS USED TO REPORT ERRORS THAT CAUSE THE SUBROUTINES TO BE UNUSABLE ***************************************************************** 517 ERROR HANDLING UUO DEFINITIONS ***************************************************************** ***************************************************************** 555 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 ***************************************************************** ***************************************************************** 883 INITIALIZATION SECTION ***************************************************************** ***************************************************************** 922 DADD - TEST A ***************************************************************** 927 DADD - TEST A 0,# + 0,0 = 0,# SIMPLE TESTS TO SEE IF DADD #,0 + 0,0 = #,0 WORKS AT ALL. #,# + 0,0 = #,# 0,0 + 0,# = 0,# 0,0 + #,0 = #,0 0,0 + #,# = #,# 0,0 + 0,0 = 0,0 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 6 SEQ 0016 ***************************************************************** 1112 DADD - TEST B ***************************************************************** 1116 FLOATING 1 + 0 = FLOATING 1 THESE TESTS ARE DONE FOR A 1 OR 0 + FLOATING 1 = FLOATING 1 A 0 IN BITS 0,34,36,70 OF THE FLOATING 0 + 0 = FLOATING 0 DOUBLEWORD ADDEND OR AUGEND. 0 + FLOATING 0 = FLOATING 0 THIS WILL TEST THE WORD BOUND- ARY INTEGRITY OF THE DADD INSTRUCTION. 1126 REPEAT THE FOLLOWING BLOCK OF CODE 8 TIMES TO STEP DOWN A LIST OF TEST CASES. THE TEST CASES CONSIST OF 8 DOUBLEWORDS - THE FIRST 4 FLOAT A 1 ACROSS IN BITS 0,34,36,70; THE SECOND 4 FLOAT A 0 ACROSS IN BITS 0,34,36,70. THE RESULT SHOULD BE ACS WITH CONTENTS EQUAL TO THE FLOATING 1/0. ***************************************************************** 1618 DADD - TEST C ***************************************************************** 1622 FLOATING 1 + FLOATING 1 = FLOATING 1 SHIFTED LEFT ONE BIT AT A TIME ACROSS THE DOUBLEWORD EXCLUDING SIGN BITS AND THE MOST SIGNIFICANT BIT (WE'RE NOT TESTING OVERFLOW CONDITIONS). THIS TEST VERIFIES THE ABILITY OF THE DADD TO HANDLE A SINGLE CARRY PROPAGATED 1 BIT WHETHER IT CROSSES A WORD BOUNDARY OR NOT. ***************************************************************** 1671 DADD - TEST D ***************************************************************** 1674 DADD - TEST D 0,-1 + 0,1 = 1,0 ADDITIONAL TEST TO SEE THAT A 0,1 + 0,-1 = 1,0 CARRY IS PROPAGATED ACROSS WORD BOUNDARIES. DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 7 SEQ 0017 ***************************************************************** 1730 DADD - TEST E ***************************************************************** 1733 DADD - TEST E FLOATING 0 + 1 = 11111000.. 1 + FLOATING 0 = 11111000.. 1740 THE NEXT 6 TESTS VERIFY THAT A CARRY IS PROPERLY PROPAGATED DOWN A WORD. A 1 IS ADDED TO A FLOATING 0 CAUSING THE CARRY TO RIPPLE DOWN THE WORD. THE RESULT IS VERIFIED AS 1111..110000.... THE FLOATING 0 IS LOCATED IN BITS 34,36, 71 FOR NEGATIVE NUMBERS AND BITS 33,36,70 FOR POSITIVE NUMBERS. CARRY FLAGS ARE VERIFIED IN ADDITION. ***************************************************************** 2062 DADD - TEST F ***************************************************************** 2065 DADD - TEST F THE FOLLOWING TESTS VERIFY THAT THE DADD INSTRUCTION HANDLES THE SIGN OF THE RESULT PROPERLY (COPYING THE SIGN INTO THE HIGH ORDER BIT OF EACH WORD OF THE DOUBLEWORD RESULT. THE TESTS ADD VARIOUS COMBINATIONS OF INCONSISTENT SIGNS IN THE ADDEND AND AUGEND AND VERIFY THAT THE SIGNS OF THE RESULT ARE CORRECT. THERE ARE 5 SETS OF TEST: (1) 0 + P/N = P/N (2) N + N = N (3) P + P = P (4) N + P = N (5) N + P = P WHERE N-NEGATIVE NUMBER P-POSITIVE NUMBER ***************************************************************** 3680 DADD - TEST G ***************************************************************** 3683 DADD - TEST G 2**N + (2**70 - 2**N) = 1000... (AROV & CARRY 1 SET) (2**70 - 2**N) + 2**N = 1000... (AROV & CARRY 1 SET) -2**N + (-2**70 + 2**N - 1) = 0111... (AROV & CARRY 0 SET) (-2**70 + 2**N - 1) + -2**N = 0111... (AROV & CARRY 0 SET) THEST TESTS CHECK THE SETTING OF AROV & CARRY 1 AND AROV & CARRY 0 FLAGS. CHECKED FOR BITS 0,34,36,70. DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 8 SEQ 0018 3695 THE FOLLOWING SECTION OF CODE IS REPEATED 8 TIMES. THE FIRST 4 TESTS FLOAT A 1 ACROSS A DOUBLEWORD IN BITS 0,35,36,71. THIS NUMBER IS THEN ADDED TO THE SMALLEST POSITIVE INTEGER WHICH WILL PRODUCE AN OVERFLOW - THE RESULT IS A DOUBLEWORD OF 0S WITH 1 IN THE SIGN BIT - WITH OVERFLOW & CARRY 1 SET. THE NEXT 4 TESTS FLOAT A 0 ACROSS A DOUBLEWORD IN BITS 1, 35,36,71 (A NEGATIVE NUMBER). THIS NUMBER IS ADDED TO THE SMALLEST NEGATIVE INTEGER WHICH WILL PRODUCE AN OVERFLOW - THE RESULT IS A DOUBLEWORD OF 1S WITH A 0 IN THE SIGN BIT - WITH OVERFLOW AND CARRY 0 SET. THE DOUBLEWORDS USED IN THIS TEST ARE LOCATED IN THE LIST 'CONST2'. ***************************************************************** 4143 DSUB - TEST A ***************************************************************** 4148 DSUB - TEST A 0,# - 0,0 = 0,# GENERAL TESTING TO SEE THAT #,0 - 0,0 = #,0 DSUB CAN HANDLE DOUBLEWORDS #,# - 0,0 = #,# 0,0 - 0,# = -(0,#) 0,0 - #,0 = -(#,0) 0,0 - #,# = -(#,#) ***************************************************************** 4307 DSUB - TEST B ***************************************************************** 4310 DSUB - TEST B TEST ALL PERMUTATIONS OF 0,1,-1 IN THE MINUEND AND SUBTRAHEND -- TEST: 0,0 - 0,0 0,1 - 0,0 0,-1 - 0,0 .... 0,0 - 0,1 0,1 - 0,1 0,-1 - 0,1 .... 0,0 - 0,-1 0,1 - 0,-1 0,-1 - 0,-1 .... 0,0 - 1,0 .... .... .... 0,0 - 1,1 .... .... .... 0,0 - 1,-1 .... .... .... 0,0 - -1,0 .... .... .... 0,0 - -1,1 .... .... .... 0,0 - -1,-1 .... .... .... 4326 THESE COMBINATIONS TEST THE ABILITY OF THE DSUB TO HANDLE BORROWS FROM THE NEXT WORD AND SIGNS CHANGING. THE RESULT IS VERIFIED AND THE PC FLAGS ARE CHECKED TO SEE THAT THEY ARE SET PROPERLY. DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 9 SEQ 0019 4333 PROCEDURE - (1) SET UP A POINTER 'MINU' TO SEQUENCE THE MINUEND (2) LOOP ON MINUEND (3) SET UP A POINTER 'SUBTR' TO SEQUENCE THE SUBTRAHEND (4) LOOP ON SUBTRAHEND (5) CALCULATE THE EXPECTED RESULT OF THE DSUB (6) DO DSUB (7) COMPARE RESULTS - ACTUAL VS. EXPECTED (8) TEST FLAGS (9) CONTINUE AT (4) ***************************************************************** 4455 DSUB - TEST C ***************************************************************** 4458 DSUB - TEST C THE FOLLOWING TESTS VERIFY THAT THE DSUB INSTRUCTION HANDLES THE SIGN OF THE RESULT PROPERLY (COPYING THE SIGN INTO THE HIGH ORDER BIT OF EACH WORD OF THE DOUBLEWORD RESULT. THE TESTS SUBTRACT VARIOUS COMBINATIONS OF INCONSISTENT SIGNS IN THE SUBTRAHEND AND MINUEND AND VERIFY THAT THE SIGNS OF THE RESULT ARE CORRECT. THERE ARE 5 SETS OF TEST: (1) 0 - P/N = N/P (2) N - N = P/N (3) P - P = N/P (4) N - P = N/P (5) N - P = N/P WHERE N-NEGATIVE NUMBER P-POSITIVE NUMBER ***************************************************************** 5533 DSUB - TEST D ***************************************************************** 5536 DSUB - TEST D 2**N - (-2**70 + 2**N) = 1000... (AROV & CARRY 1 SET) (-2**70 + 2**N) - 2**N = 1000... (AROV & CARRY 1 SET) -2**N - (2**70 - 2**N + 1) = 0111... (AROV & CARRY 0 SET) (2**70 - 2**N + 1) - -2**N = 0111... (AROV & CARRY 0 SET) 5545 THE FOLLOWING SECTION OF CODE IS REPEATED 8 TIMES. THE FIRST 4 TESTS FLOAT A 1 ACROSS A DOUBLEWORD IN BITS 1,35,37,71. FROM THIS NUMBER IS SUBTRACTED THE SMALLEST (MAGNITUDE) NEGATIVE INTEGER WHICH WILL PRODUCE AN OVERFLOW - THE RESULT IS A DOUBLEWORD OF 0'S WITH 1 IN THE SIGN BIT - WITH OVERFLOW & CARRY 1 SET. THE NEXT 4 TESTS FLOAT A 0 ACROSS A DOUBLE- WORD IN BITS 1,35,37,71 (A NEG NUMBER). FROM THIS NUMBER IS SUBTRACTED THE SMALLEST POSITIVE INTEGER WHICH WILL PRODUCE AN OVERFLOW - THE RESULT IS A DOUBLEWORD OF 1S WITH A 0 IN THE SIGN BIT - WITH OVERFLOW AND CARRY 0 SET. THE DOUBLEWORDS USED IN THIS TEST ARE LOCATED IN THE LIST 'SCOND'. DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 10 SEQ 0020 ***************************************************************** 6006 DMUL - TEST A ***************************************************************** 6011 DMUL - TEST A 0,# * 0 = 0 0 * 0,# = 0 THESE ARE GENERAL TESTS TO #,0 * 0 = 0 0 * #,0 = 0 ASCERTAIN THAT THE DMUL CAN #,# * 0 = 0 0 * #,# = 0 HANDLE DOUBLEWORDS. THE ACS -1,-# * 0 = 0 0 * -1,-# = 0 WILL CONTAIN THE RESULT ARE -#,0 * 0 = 0 0 * -#,0 = 0 FILLED WITH GARBAGE AND THE -#,-# * 0 = 0 0 * -#,-# = 0 RESULT IS CHECKED TO SEE THAT 0,0 * 0 = 0 DMUL PRODUCES A 4-WORD LONG RESULT IN THE ACS. ***************************************************************** 6269 DMUL - TEST B ***************************************************************** 6272 DMUL - TEST B 0,# * 1 = 0,# THESE TEST THE DMUL ON A SLIGHTLY #,0 * 1 = #,0 STEEPER GRADIENT. THIS WILL VERIFY #,# * 1 = #,# THAT THE DMUL HANDLES DOUBLEWORDS AND -1,-# * 1 = -1,-# A NON-ZERO MULTIPLIER. THESE TESTS ARE -#,-1 * 1 = -#,-1 REPEATED WITH THE MULTIPLICAND AND THE -#,-# * 1 = -#,-# MULTIPLIER REVERSED. ***************************************************************** 6509 DMUL - TEST C ***************************************************************** 6512 DMUL - TEST C 0,1777.. * 2 THESE TESTS VERIFY THAT BITS ARE 0,3777.. * 2 SHIFTED ACROSS WORD BOUNDARIES. A WORD 1777..,3777.. * 2 OF ONES IS MULTIPLIED BY A FLOATING 1 3777..,3777.. * 2 WHICH WILL CAUSE A SHIFT ACROSS WORD 0,3777.. * 1,0 BOUNDARIES OR NOT. THE TEST VERIFIES 1,3777.. * 1,0 THAT THE SHIFT IS DONE PROPERLY FOR 3777..,3777.. * 1,0 BOUNDARY CONDITIONS. 0,1777.. * 2,0 IN EACH TEST THE PC FLAGS ARE TESTED 0,3777.. * 2,0 SINCE THERE ARE NO OVERFLOW CONDITIONS 3777..,3777.. * 2,0 THE LEFTMOST BIT OF THE PC SHOULD BE 0 (NO AROV). THESE TESTS ARE REPEATED WITH MULT- PLICAND AND MULTIPLIER REVERSED. DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 11 SEQ 0021 ***************************************************************** 7076 DMUL - TEST D ***************************************************************** 7079 DMUL - TEST D 7777..,6000.. * 2 THESE TESTS VERIFY THAT BITS ARE 7777..,4000.. * 2 SHIFTED ACROSS WORD BOUNDARIES. A WORD 6000..,4000.. * 2 OF ONES IS MULTIPLIED BY A FLOATING 1 4000..,4000.. * 2 WHICH WILL CAUSE A SHIFT ACROSS WORD 777..,400.. * 1,0 BOUNDARIES OR NOT. THE TEST VERIFIES ..776,400.. * 1,0 THAT THE SHIFT IS DONE PROPERLY FOR 400..,400.. * 1,0 BOUNDARY CONDITIONS. 777..,600.. * 2,0 IN EACH TEST THE PC FLAGS ARE TESTED 777..,400.. * 2,0 SINCE THERE ARE NO OVERFLOW CONDITIONS 400..,400.. * 2,0 THE LEFTMOST BIT OF THE PC SHOULD BE 0 (NO AROV). THESE TESTS ARE REPEATED WITH MULT- PLICAND AND MULTIPLIER REVERSED. ***************************************************************** 7647 DMUL - TEST E (OVERFLOW) ***************************************************************** 7650 DMUL - TEST E -2^70 * -2^70 THIS IS THE ONLY CASE THAT CAN SET THE AROV FLAG. THIS TEST VERIFIES THE RESULT AND CHECKS THE SETTING OF THE AROV FLAG. ------- MULTIPLICAND = (4000...,4000...) ------- MULTIPLIER === (4000...,4000...) ------- RESULT ======= (4000...,4000...,4000...,4000...) ***************************************************************** 7698 DMUL - TEST F - TEST NEGATIVE OPERANDS ***************************************************************** 7701 DMUL - TEST F -2 * -3 THESE TESTS VERIFY THAT THE DMUL HANDLES -2,0 * -3 THE SIGNS PROPERLY WHEN MULTIPLYING -2 * -3,0 OPERANDS WHICH ARE BOTH NEGATIVE. TESTS -2,0 * -3,0 B,C,D TESTED THE COMBINATIONS POS*POS, POS*NEG AND NEG*POS BUT NOT NEG*NEG. THE AROV FLAG IS ALSO TESTED TO ASCERTAIN THAT IT WAS NOT SET. DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 12 SEQ 0022 ***************************************************************** 7819 DMUL - TEST G ***************************************************************** 7822 DMUL - TEST G 2 * 3 2,0 * 3,0 THESE TESTS MULTIPLY NUMBERS WHICH HAVE 2 * -3 2,0 * -3,0 INCONSISTENT SIGNS AMONGST THE WORDS OF -2 * 3 -2,-1 * 3,0 EACH OPERAND. THE FLAGS IS ALSO TESTED -2 * -3 -2,-1 * -3,0 TO VERIFY THAT IT IS NOT SET. ***************************************************************** 8479 DDIV - TEST A ***************************************************************** 8484 DDIV - TEST A (0,0,0,#) / 1 THESE BASIC TESTS VERIFY THAT THE DDIV (0,0,#,0) / 1 HANDLES A QUADRUPLE WORD DIVIDEND. FOR EACH TEST ALL PERMUTATIONS OF POSITIVE AND NEGATIVE OPERANDS ARE TESTED. ***************************************************************** 8531 DDIV - TEST B ***************************************************************** 8534 DDIV - TEST B (0,0,0,#) / # THESE TESTS PERFORM SOME CASES MORE (0,0,#,0) / (#,0) DIFFICULT THAN (A). PERMUTATIONS OF POSITIVE AND NEGATIVE OPERANDS ARE TESTED. ***************************************************************** 8581 DDIV - TEST C ***************************************************************** 8584 DDIV - TEST C (0,0,0,1) (0,0,1,0) (0,0,1,0) (0,1,0,0) (0,1,0,0) (1,0,0,0) ------- ------- ------- ------- ------- ------- 2 2 2,0 2 2,0 2,0 THESE TESTS PERFORM DIVISIONS WHICH RESULT IN A SHIFT OF THE THE DIVIDEND ACROSS WORD BOUNDARIES. THESE TESTS ARE REPEATED FOR THE VARIOUS PERMUTATIONS OF POSITIVE AND NEGATIVE OPERANDS. DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 13 SEQ 0023 ***************************************************************** 9075 DDIV - TEST D ***************************************************************** 9078 DDIV - TEST D MISCELLANEOUS TESTING. THESE TESTS DIVIDE 2 NUMBERS AND JUST CHECK TO SEE THAT THE DDIV GETS THE CORRECT ANSWERS. ***************************************************************** 9419 DDIV - TEST E ***************************************************************** 9422 DDIV - TEST E -4/-2 -4/2 4/-2 4/2 (-3,0,0,0)/(-6,0) (-3,0,0,0)/(6,0) 3/-6 3/6 THESE TESTS VERIFY THAT THE DDIV HANDLES THE SIGN OF ITS OPERANDS PROPERLY. THE SIGN BITS OF THE LOW ORDER WORDS ARE INITIALLY DIFFERENT FROM THE HIGH ORDER WORD. THE SIGN SHOULD BE FORMED CORRECTLY IN SPITE OF THAT. ***************************************************************** 9882 DDIV - TEST F ***************************************************************** 9885 DDIV - TEST F 1,0,0,0 -1,0,0,0 0,-1,-1,-1 -1,0,0,1 ------- -------- ---------- -------- 1,1 1,1 1,0 1,0 1,0,0,0 -1,0,0,0 0,-1,-1,-1 -1,0,0,1 ------- -------- ---------- -------- -2,-1 -2,-1 -1,0 -1,0 THESE TESTS VERIFY THAT THE DDIV WILL NOT GENERATE AN OVERFLOW AND NO DIVIDE CONDITION WHEN THE DIVISOR IS JUST LARGE ENOUGH TO NOT CAUSE ONE. DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 14 SEQ 0024 ***************************************************************** 10130 DDIV - TEST G ***************************************************************** 10133 DDIV - TEST G 1 1,0 1,0,0 1,0,0,0 -1 - --- ----- ------- - 0 0 0 0 0 1,0,0 1,0,0 1,0,0,0 1,0,0,0 ----- ----- ------- ------- 1 -1 1 -1 -1,0,0 -1,0,0 -1,0,0,0 -1,0,0,0 ------ ------ -------- -------- 1 -1 1 -1 1,0,0,0 1,0,0,0 -1,0,0,0 -1,0,0,0 ------- ------- -------- -------- 1,0 -1,0 1,0 -1,0 0,-1,-1,-1 0,-1,-1,-1 -1,0,0,1 -1,0,0,1 ---------- ---------- -------- -------- 0,-1 -1,1 0,-1 -1,1 1,0,-1,-1 1,0,-1,-1 -2,-1,0,1 -2,-1,0,1 --------- --------- --------- --------- 0,-1 -1,1 0,-1 -1,1 -2^140 2^140-1 2^140-1 -2^70+1,-2^70 ------ ------- ------- ------------- -2^70 2^70-1 -2^70+1 2^70-1 THESE TESTS ATTEMPT TO PERFORM VARIOUS DIVISIONS THAT SHOULD RESULT IN OVERFLOW. THE SETTING OF AROV AND NO DIVIDE FLAGS IS VERIFIED AND THE DIVIDEND IS CHECKED TO SEE THAT IT DID NOT CHANGE. ALSO TRY A FEW WITH INCONSISTENT SIGNS IN THE LEAST SIGNIFICANT WORDS OF THE DIVIDEND AND DIVISOR JUST TO MAKE SURE THAT THE DIVIDEND DOES NOT CHANGE ON ANY CONDITION. DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 15 SEQ 0025 ***************************************************************** 11106 TESTING SUBROUTINES ***************************************************************** 11109 MSUBR - SUBROUTINE TO DO MULTIPLICATION CALCULATIONS ARGUMENTS: MCAND - CONTAINS MULTIPLICAND MPLIER - CONTAINS MULTIPLIER MRES - CONTAINS THE EXPECTED RESULT 11157 PSUBR - SUBROUTINE TO DO DIVISION CALCULATIONS ARGUMENTS: PDEND - CONTAINS DIVIDEND PISOR - CONTAINS DIVISOR PRES - CONTAINS THE EXPECTED RESULT 11205 OSUBR - SUBROUTINE TO DO DIVISION CALCULATIONS ARGUMENTS: ODEND - CONTAINS DIVIDEND OISOR - CONTAINS DIVISOR NOTE: WHEN ENCOUNTERING A OVERFLOW/NO DIVIDE SITUATION THE PROCESSOR ENSURES THAT THE OPERANDS DO NOT CHANGE. THE KL10 ENSURES THAT NEITHER THE MAGNITUDE PORTION NOR THE SIGN BITS CHANGE. THE KS10 ENSURES THAT THE MAGNITUDE PORTION OF EITHER WORD DOES NOT CHANGE - HOWEVER, IT ONLY PROTECTS THE SIGN BIT OF THE MOST SIGNIFICANT WORD. THE SIGN BIT OF THE OTHER WORD IS INDETERMINATE. THIS TEST CHECKS TO FIND OUT WHAT TYPE OF PROCESSOR WE HAVE AND WILL MODIFY THE TEST FOR A KS10. THE ABOVE WAS NOTICED WHEN RUNNING THE DIAGNOSTIC ON THE KS10 AFTER DEBUGGING ON A KL10. ACCORDING TO DON LEWINE, THIS WAS DONE TO SAVE SPACE IN THE KS10 MICROCODE. ***************************************************************** 11281 ADDL ERROR PRINT ROUTINES ***************************************************************** 11284 APRINT - ADDITION ERROR PRINTER 11321 SPRINT - SUBTRACTION ERROR PRINTER 11358 MPRINT - MULTIPLICATION ERROR PRINTER 11401 DPRINT - DIVIDE ERROR PRINTER DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 DECDOC VER 00.24 26-SEP-79 15:52:49 PAGE 16 SEQ 0026 ***************************************************************** 11453 *STOR* RESERVED STORAGE, SEPTEMBER 1979 ***************************************************************** DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1 DSKCFT MAC 26-Sep-79 15:41 CONSOLE DATA SWITCH ASSIGNMENTS, SEPTEMBER 1979 SEQ 0027 1 ;*MAINDEC-10-DSKCF 2 3 000000 MCNVER=0 4 000003 DECVER=3 5 6 XLIST 7 LIST 8 LALL 9 10 NAME \MCNVER,\DECVER^ 11 12 TITLE DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 13 ^ 14 15 000137 LOC 137 16 000137 000000 000003 MCNVER,,DECVER 17 18 ;*COPYRIGHT 1979 19 ;*DIGITAL EQUIPMENT CORPORATION 20 ;*MARLBORO, MASS. 21 22 ;*JOHN R. KIRCHOFF 23 ;*RICHARD E. STOCKDALE 24 25 SEARCH MONSYM 26 NOSYM 27 28 IF2, DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 2 DSKCFT MAC 26-Sep-79 15:41 ASSEMBLY TIME PARAMETERS SEQ 0028 29 SUBTTL ASSEMBLY TIME PARAMETERS 30 31 ; ********************************************************************** 32 ;*ACCUMULATOR DEFINITIONS 33 ; ********************************************************************** 34 35 000001 AC1=1 ;AC,AC+1,AC+2,AC+3 - CONTAIN OPERANDS USED 36 ; BY DADD,DSUB,DMUL,DDIV 37 38 000011 CNT=11 ;COUNT AC 39 40 000012 SCR0=12 ;SCRATCH ACS USED IN THE ADDL ERROR PRINT 41 000013 SCR1=SCR0+1 ; ROUTINE 42 000014 SCR2=SCR0+2 43 000015 SCR3=SCR0+3 44 45 ; ********************************************************************** 46 ;*BEGIN PARAMETERS 47 ; ********************************************************************** 48 49 030624 SADR1=STARTA 50 030624 SADR2=STARTA 51 030623 SADR3=START 52 030007 SADR4=SRTDDT 53 030624 SADR5=STARTA 54 040450 SADR6=PHALT 55 254200 030000 SADR7=HALT BEGIN 56 254200 030000 SADR8=HALT BEGIN 57 254200 030000 SADR9=HALT BEGIN 58 254200 030000 SADR10=HALT BEGIN 59 254200 030000 SADR11=HALT BEGIN 60 000010 ITERAT=10 61 000000 PAREA1=0 62 000000 PAREA2=0 63 446353 434600 PAREA3=SIXBIT/DSKCF/ 64 546364 000000 PAREA4=SIXBIT/LST/ 65 000000 PAREA5=0 66 000000 PAREA6=0 67 68 000001 PGMEND==1 69 000001 EXCASB==1 70 000001 USRASB==1 71 000030 DEBUG==30 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3 DSKCFT MAC 26-Sep-79 15:41 MACROS SEQ 0029 72 SUBTTL MACROS 73 74 ; ********************************************************************** 75 ;*PCSAVE - GET AND SAVE PC 76 ; ********************************************************************** 77 78 DEFINE PCSAVE< 79 JSR .+1 ;STORE PC 80 FLAGL=. ;LOCATION OF PC 81 0 ;PC 82 > 83 84 ; ********************************************************************** 85 ;*TFLAG - TEST PC FLAGS SET BY THE PRIOR DADD/DSUB 86 ; ********************************************************************** 87 88 DEFINE TFLAG (FLGGS,TT,ADDR,LOC)< 89 90 MOVE SCR1,FLAGL ;GET FLAGS 91 MOVE SCR2,FLGGS ;SCR2 - CORRECT FLAGS 92 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 93 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 94 ERROR (LOC,13,SCR2,FLAGL,,^_ 95 TEST 'TT' - PC FLAGS INCORRECT (LEFT 4 BITS),ADDR) 96 > 97 ; ********************************************************************** 98 ;*MULT - PERFORM DMUL AND TEST RESULTS 99 ; ********************************************************************** 100 101 DEFINE MULT (T,A1<0>,A2<0>,E1<0>,E2<0>,R1<0>,R2<0>,R3<0>,R4<0>,%BEGIN)< 102 103 ; --- MULTIPLICAND = (A1,A2) 104 ; --- MULTIPLIER === (E1,E2) 105 ; --- RESULT ======= (R1,R2,R3,R4) 106 107 %BEGIN: MOVE AC1,[[EXP A1,A2,E1,E2,R1,R2,R3,R4],,MCAND] 108 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 109 GO MSUBR ;GO DO TEST 110 ERROR (%BEGIN,14,SCR1,SCR2,,^_ 111 TEST 'T' - RESULT CALCULATED INCORRECTLY,MPRINT) 112 > DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 4 DSKCFT MAC 26-Sep-79 15:41 MACROS SEQ 0030 113 114 ; ********************************************************************** 115 ;*MULTF - PERFORM DMUL AND TEST RESULTS & PC FLAGS 116 ; ********************************************************************** 117 118 DEFINE MULTF (T,A1<0>,A2<0>,E1<0>,E2<0>,R1<0>,R2<0>,R3<0>,R4<0>,%BEGIN,%TSTPC)< 119 120 ; --- MULTIPLICAND = (A1,A2) 121 ; --- MULTIPLIER === (E1,E2) 122 ; --- RESULT ======= (R1,R2,R3,R4) 123 124 %BEGIN: MOVE AC1,[[EXP A1,A2,E1,E2,R1,R2,R3,R4],,MCAND] 125 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 126 GO MSUBR ;GO DO TEST 127 ERROR (%BEGIN,14,SCR1,SCR2,,^_ 128 TEST 'T' - RESULT CALCULATED INCORRECTLY,MPRINT) 129 130 %TSTPC: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 131 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 132 ERROR (%BEGIN,13,SCR2,MFLOC,,^_ 133 TEST 'T' - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT) 134 > 135 ; ********************************************************************** 136 ;*PDIV - PERFORM DDIV AND TEST RESULTS 137 ; ********************************************************************** 138 139 DEFINE PDIV (T,A1,A2,A3,A4,E1,E2,R1<0>,R2<0>,R3<0>,R4<0>,%BEGIN)< 140 141 ; --- DIVIDEND == (A1,A2,A3,A4) 142 ; --- DIVISOR === (E1,E2) 143 ; --- QUOTIENT == (R1,R2) 144 ; --- REMAINDER = (R3,R4) 145 146 %BEGIN: MOVE AC1,[[EXP A1,A2,A3,A4,E1,E2,R1,R2,R3,R4],,PDEND] 147 BLT AC1,PRES+3 ;SET UP OPERANDS 148 GO PSUBR ;GO DO TEST 149 ERROR (%BEGIN,14,SCR1,SCR2,,^_ 150 TEST 'T' - QUOTIENT/REMAINDER INCORRECT,DPRINT) 151 > DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 5 DSKCFT MAC 26-Sep-79 15:41 MACROS SEQ 0031 152 153 ; ********************************************************************** 154 ;*PDIVF - PERFORM DDIV AND TEST RESULTS & PC FLAGS 155 ; ********************************************************************** 156 157 DEFINE PDIVF (T,A1,A2,A3,A4,E1,E2,R1<0>,R2<0>,R3<0>,R4<0>,%BEGIN,%TSTPC)< 158 159 ; --- DIVIDEND == (A1,A2,A3,A4) 160 ; --- DIVISOR === (E1,E2) 161 ; --- QUOTIENT == (R1,R2) 162 ; --- REMAINDER = (R3,R4) 163 164 %BEGIN: MOVE AC1,[[EXP A1,A2,A3,A4,E1,E2,R1,R2,R3,R4],,PDEND] 165 BLT AC1,PRES+3 ;SET UP OPERANDS 166 GO PSUBR ;GO DO TEST 167 ERROR (%BEGIN,14,SCR1,SCR2,,^_ 168 TEST 'T' - QUOTIENT/REMAINDER INCORRECT,DPRINT) 169 170 %TSTPC: MOVE SCR2,PFLOC ;GET PC 171 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 172 ERROR (%BEGIN,13,SCR2,PFLOC,,^_ 173 TEST 'T' - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT) 174 > 175 ; ********************************************************************** 176 ;*ODIV - PERFORM DDIV AND TEST RESULTS & PC FLAGS 177 ;* (HANDLES OVERFLOW/NO DIVIDE CONDITIONS) 178 ; ********************************************************************** 179 180 DEFINE ODIV (A1,A2,A3,A4,E1,E2,%BEGIN,%TSTPC)< 181 182 ; --- DIVIDEND == (A1,A2,A3,A4) 183 ; --- DIVISOR === (E1,E2) 184 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 185 186 %BEGIN: MOVE AC1,[[EXP A1,A2,A3,A4,E1,E2],,ODEND] 187 BLT AC1,ORES-1 ;SET UP OPERANDS 188 GO OSUBR ;GO DO TEST 189 ERROR (%BEGIN,14,SCR1,SCR2,,^_ 190 TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT) 191 192 %TSTPC: MOVE SCR2,OFLOC ;GET PC 193 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 194 CAME SCR2,OFLOC ;PC CORRECT? 195 ERROR (%BEGIN,13,SCR2,OFLOC,,^_ 196 TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT) 197 > DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 6 DSKCFT MAC 26-Sep-79 15:41 MACROS SEQ 0032 198 199 ; ********************************************************************** 200 ;*CHECKA - CHECK RESULTS OF A DADD & DO ERROR HANDLING 201 ;* (RESULT 'R1' IS PASSED AS THE OCTAL DATA ITSELF) 202 ; ********************************************************************** 203 204 DEFINE CHECKA (LOC,T,R1< 0>,R2< 0>,%ERROR,%END)< 205 206 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 207 CAME AC1,[R1] ;IS LEFT HALF OF RESULT CORRECT? 208 JRST %ERROR ;NO - GO TO ERROR HANDLING 209 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 210 CAMN AC1+1,[R2] ;IS RIGHT HALF CORRECT? 211 JRST %END+1 ;YES - DONT DO ERROR HANDLING 212 ; EXCEPT FOR ERLOOP 213 214 %ERROR: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 215 MOVE SCR1,[EXP R1,R2](SCR1) ;GET CORRECT RESULT 216 %END: ERROR (LOC,14,SCR1,SCR2,,^_ 217 TEST 'T' - RESULT IS INCORRECT,APRINT) 218 > 219 ; ********************************************************************** 220 ;*CHECKS - CHECK RESULTS OF A DSUB & DO ERROR HANDLING 221 ;* (RESULT 'R1' IS PASSED AS THE OCTAL DATA ITSELF) 222 ; ********************************************************************** 223 224 DEFINE CHECKS (LOC,T,R1< 0>,R2< 0>,%ERROR,%END)< 225 226 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 227 CAME AC1,[R1] ;IS LEFT HALF OF RESULT CORRECT? 228 JRST %ERROR ;NO - GO TO ERROR HANDLING 229 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 230 CAMN AC1+1,[R2] ;IS RIGHT HALF CORRECT? 231 JRST %END+1 ;YES - DONT DO ERROR HANDLING 232 ; EXCEPT FOR ERLOOP 233 234 %ERROR: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 235 MOVE SCR1,[EXP R1,R2](SCR1) ;GET CORRECT RESULT 236 %END: ERROR (LOC,14,SCR1,SCR2,,^_ 237 TEST 'T' - RESULT IS INCORRECT,SPRINT) 238 > DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 7 DSKCFT MAC 26-Sep-79 15:41 MACROS SEQ 0033 239 240 ; ********************************************************************** 241 ;*CHECKB - CHECK RESULTS OF A DADD & DO ERROR HANDLING 242 ;* (RESULT 'R1' IS PASSED AS THE ADDRESS OF THE DATA) 243 ; ********************************************************************** 244 245 DEFINE CHECKB (LOC,T,R1,%ERROR,%END)< 246 247 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 248 CAME AC1,R1 ;IS LEFT HALF OF RESULT CORRECT? 249 JRST %ERROR ;NO - GO TO ERROR HANDLING 250 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 251 CAMN AC1+1,R1+1 ;IS RIGHT HALF CORRECT? 252 JRST %END+1 ;YES - DONT DO ERROR HANDLING 253 ; EXCEPT FOR ERLOOP 254 255 %ERROR: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 256 MOVE SCR1,R1(SCR1) ;GET CORRECT WORD OF RESULT 257 %END: ERROR (LOC,14,SCR1,SCR2,,^_ 258 TEST 'T' - RESULT IS INCORRECT,APRINT) 259 > 260 ; ********************************************************************** 261 ;*CHECKT - CHECK RESULTS OF A DSUB & DO ERROR HANDLING 262 ;* (RESULT 'R1' IS PASSED AS THE ADDRESS OF THE DATA) 263 ; ********************************************************************** 264 265 DEFINE CHECKT (LOC,T,R1,%ERROR,%END)< 266 267 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 268 CAME AC1,R1 ;IS LEFT HALF OF RESULT CORRECT? 269 JRST %ERROR ;NO - GO TO ERROR HANDLING 270 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 271 CAMN AC1+1,R1+1 ;IS RIGHT HALF CORRECT? 272 JRST %END+1 ;YES - DONT DO ERROR HANDLING 273 ; EXCEPT FOR ERLOOP 274 275 %ERROR: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 276 MOVE SCR1,R1(SCR1) ;GET CORRECT WORD OF RESULT 277 %END: ERROR (LOC,14,SCR1,SCR2,,^_ 278 TEST 'T' - RESULT IS INCORRECT,SPRINT) 279 > DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1 PARAM KSM 18-Sep-79 17:18 CONSOLE DATA SWITCH ASSIGNMENTS, SEPTEMBER 1979 SEQ 0034 280 SUBTTL CONSOLE DATA SWITCH ASSIGNMENTS, SEPTEMBER 1979 281 282 DEFINE S,<; *********************************************************************> 283 284 ; ********************************************************************** 285 ;*DATA SWITCHES 286 ;*LEFT HALF SWITCHES ARE PRE-ASSIGNED FOR SUBROUTINE PACKAGE USE 287 ;*AND CONTROL LOOPING, PRINTING (TTY OR OTHER DEVICE) AND MISC. FUNCTIONS 288 ; ********************************************************************** 289 290 400000 ABORT== 400000 ;ABORT PROGRAM ON PASS COMPLETION 291 200000 RSTART==200000 ;RESTART TEST, PRINT TOTALS 292 100000 TOTALS==100000 ;PRINT TOTALS, CONTINUE 293 294 040000 NOPNT== 040000 ;INHIBIT ALL PRINT/TYPE OUT (EXCEPT FORCED) 295 020000 PNTLPT==020000 ;PRINT ALL DATA ON LPT (LOGICAL DEVICE, USER MODE) 296 010000 DING== 010000 ;RING BELL ON ERROR 297 298 004000 LOOPER==004000 ;ENTER EXERCISE/CHECK LOOP ON ERROR 299 002000 ERSTOP==002000 ;HALT ON TEST ERROR 300 001000 PALERS==001000 ;PRINT ALL ERRORS 301 302 000400 RELIAB==000400 ;RELIABILITY MODE 303 000200 TXTINH==000200 ;INHIBIT ERROR TEXT 304 000100 INHPAG==000100 ;INHIBIT PAGING 305 306 000040 MODDVC==000040 ;MODIFY DEVICE CODE 307 000020 INHCSH==000020 ;INHIBIT CACHE 308 000010 OPRSEL==000010 ;OPERATOR SELECTION 309 310 000004 CHAIN== 000004 ;CHAIN CONTROL SWITCH 311 312 ;SWITCH 16 RESERVED 313 314 ;SWITCH 17 RESERVED !!! DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 2 PARAM KSM 18-Sep-79 17:18 PROGRAM/SUBROUTINE PARAMETERS SEQ 0035 315 SUBTTL PROGRAM/SUBROUTINE PARAMETERS 316 317 ; ********************************************************************** 318 ;*SPECIAL SUBPROGRAM LINKAGES 319 ; ********************************************************************** 320 321 027772 FSELNK= 27772 ;FILE SELECT LINK 322 027773 FRDLNK= 27773 ;FILE READ LINK 323 027774 LDLNK= 27774 ;LOAD LINKAGE ADDRESS 324 027775 DDTLNK= 27775 ;DDT LINKAGE ADDRESS 325 027776 MODLNK= 27776 ;OPERATIONAL MODE CHECK LINKAGE ADDRESS 326 027777 SUBLNK= 27777 ;SUBROUTINE LINKAGE ADDRESS 327 328 ; ********************************************************************** 329 ;*SPECIAL SUBROUTINE FATAL HALTS 330 ;*USED TO REPORT ERRORS THAT CAUSE THE SUBROUTINES TO BE UNUSABLE 331 ; ********************************************************************** 332 333 ;ADDRESS TAG REASON 334 ;--------------------- 335 336 ; 1010 NOEXEC ;PROGRAM NOT CODED FOR EXEC MODE OPERATION 337 ; 1011 PLERR ;FATAL PUSH LIST POINTER ERROR 338 ; 1012 PLERR1 ;INITIAL PUSH LIST POINTER ERROR 339 ; 1013 MUOERR ;MUUO WITH LUUO HANDLER WIPED OUT 340 ; 1014 SMBER ;KS-10 INTERRUPT WITHOUT DOORBELL 341 ; 1015 SMCER ;KS-10 CLOCK INTERRUPT WITHOUT FLAG SET 342 ; 1016 CPIERR ;CPU INITIALIZATION ERROR 343 ; 1017 EOPERR ;END OF PROGRAM ERROR 344 ; 1020 LUOERR ;INTERRUPT WITH LUUO HANDLER WIPED OUT 345 346 ; ********************************************************************** DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3 PARAM KSM 18-Sep-79 17:18 PROGRAM/SUBROUTINE PARAMETERS SEQ 0036 347 ; ********************************************************************** 348 ;OPERATOR DEFINITIONS (NON-UUO'S) 349 ; ********************************************************************** 350 351 260740 000000 OPDEF GO [PUSHJ P,] ;SUBROUTINE CALL 352 263740 000000 OPDEF RTN [POPJ P,] ;SUBROUTINE RETURN 353 261740 000000 OPDEF PUT [PUSH P,] ;PUT DATA ON PUSH LIST 354 262740 000000 OPDEF GET [POP P,] ;GET DATA FROM PUSH LIST 355 254000 000000 OPDEF PJRST [JRST ] ;JRST TO ROUTINE THAT RTN'S 356 254200 000000 OPDEF HALT [JRST 4,] ;DEFINITION FOR DDT 357 254100 000000 OPDEF JRSTF [JRST 2,] ;DEFINITION FOR DDT 358 254500 000000 OPDEF JEN [JRST 12,] ;DEFINITION FOR DDT 359 360 ; ********************************************************************** 361 ;SUBROUTINE INITIALIZATION CALL 362 ; ********************************************************************** 363 364 265000 030011 OPDEF PGMINT [JSP 0,SBINIT] ;SUBROUTINE INITIALIZATION 365 366 ; ********************************************************************** 367 ;HALTING UUO'S (A MORE GRACEFUL HALT THAN SIMPLY USING THE HALT INSTRUCTION). 368 ; ********************************************************************** 369 370 037640 000004 OPDEF FATAL [37B8!15B12!4] ;FATAL PROGRAMMING HALT 371 037600 000004 OPDEF ERRHLT [37B8!14B12!4] ;PROGRAM ERROR HALT 372 373 ; ********************************************************************** 374 ;TERMINAL INPUT UUO'S 375 ;ALWAYS COME FROM THE CONSOLE TERMINAL IN EXEC MODE OR THE 376 ;CONTROLLING TERMINAL (REAL TERMINAL OR PTY) IN USER MODE. 377 ; ********************************************************************** 378 379 037000 000003 OPDEF TTICHR [37B8!0B12!3] ;TTY, INPUT ANY CHARACTER 380 037040 000003 OPDEF TTIYES [37B8!1B12!3] ;TTY, NORMAL RETURN Y 381 037100 000003 OPDEF TTINO [37B8!2B12!3] ;TTY, NORMAL RETURN N 382 037140 000003 OPDEF TTIOCT [37B8!3B12!3] ;TTY, INPUT OCTAL WORD 383 037200 000003 OPDEF TTIDEC [37B8!4B12!3] ;TTY, INPUT DECIMAL WORD 384 037240 000003 OPDEF TTICNV [37B8!5B12!3] ;TTY, INPUT CONVERTABLE WORD 385 037300 000003 OPDEF TTLOOK [37B8!6B12!3] ;TTY, KEYBOARD CHECK 386 037340 000003 OPDEF TTALTM [37B8!7B12!3] ;TTY, ALT-MODE CHECK 387 037400 000003 OPDEF TTSIXB [37B8!10B12!3] ;TTY, INPUT SIXBIT WORD 388 037440 000003 OPDEF TTYINP [37B8!11B12!3] ;TTY, IMAGE MODE INPUT 389 037500 000003 OPDEF TTICLR [37B8!12B12!3] ;TTY, CLEAR INPUT DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 4 PARAM KSM 18-Sep-79 17:18 PROGRAM/SUBROUTINE PARAMETERS SEQ 0037 390 ;TERMINAL OUTPUT UUO'S. 391 392 037000 000000 OPDEF PNTA [37B8!0B12!0] ;PRINT ASCII WORD 393 037000 000001 OPDEF PNTAF [37B8!0B12!1] ;PRINT ASCII WORD FORCED 394 037740 000000 OPDEF PNTAL [37B8!17B12!0] ;PRINT ASCIZ LINE 395 037740 000001 OPDEF PNTALF [37B8!17B12!1] ;PRINT ASCIZ LINE FORCED 396 037600 000003 OPDEF PSIXL [37B8!14B12!3] ;PRINT SIXBIT'Z LINE 397 037640 000003 OPDEF PSIXLF [37B8!15B12!3] ;PRINT SIXBIT'Z LINE FORCED 398 037000 000000 OPDEF PNTMSG [37B8!0B12!0] ;PRINT MESSAGE IMMEDIATE 399 037040 000000 OPDEF PNTMSF [37B8!1B12!0] ;PRINT MESSAGE IMMEDIATE FORCED 400 037100 000000 OPDEF PSIXM [37B8!2B12!0] ;PRINT SIXBIT'Z MSG IMMEDIATE 401 037200 000000 OPDEF PSIXMF [37B8!4B12!0] ;PRINT SIXBIT'Z MSG IMM FORCED 402 037000 000000 OPDEF PNTCI [37B8!0B12!0] ;PRINT CHARACTER IMMEDIATE 403 037040 000000 OPDEF PNTCIF [37B8!1B12!0] ;PRINT CHARACTER IMMEDIATE FORCED 404 037500 000000 OPDEF PNTCHR [37B8!12B12!0] ;PRINT CHARACTER 405 037500 000001 OPDEF PNTCHF [37B8!12B12!1] ;PRINT CHARACTER FORCED 406 037040 000000 OPDEF PNT1 [37B8!1B12!0] ;PRINT ONE OCTAL DIGIT 407 037040 000001 OPDEF PNT1F [37B8!1B12!1] ;PRINT 1 OCTAL DIGIT FORCED 408 037100 000000 OPDEF PNT2 [37B8!2B12!0] ;PRINT TWO OCTAL DIGITS 409 037100 000001 OPDEF PNT2F [37B8!2B12!1] ;PRINT 2 OCTAL DIGITS FORCED 410 037140 000000 OPDEF PNT3 [37B8!3B12!0] ;PRINT THREE OCTAL DIGITS 411 037140 000001 OPDEF PNT3F [37B8!3B12!1] ;PRINT THREE OCTAL DIGITS FORCED 412 037200 000000 OPDEF PNT4 [37B8!4B12!0] ;PRINT FOUR OCTAL DIGITS 413 037200 000001 OPDEF PNT4F [37B8!4B12!1] ;PRINT FOUR OCTAL DIGITS FORCED 414 037240 000000 OPDEF PNT5 [37B8!5B12!0] ;PRINT FIVE OCTAL DIGITS 415 037240 000001 OPDEF PNT5F [37B8!5B12!1] ;PRINT FIVE OCTAL DIGITS FORCED 416 037300 000000 OPDEF PNT6 [37B8!6B12!0] ;PRINT SIX OCTAL DIGITS 417 037300 000001 OPDEF PNT6F [37B8!6B12!1] ;PRINT SIX OCTAL DIGITS FORCED 418 037340 000000 OPDEF PNT7 [37B8!7B12!0] ;PRINT 7 OCTAL DIGITS 419 037340 000001 OPDEF PNT7F [37B8!7B12!1] ;PRINT 7 OCTAL DIGITS FORCED 420 037440 000000 OPDEF PNT11 [37B8!11B12!0] ;PRINT 11 OCTAL DIGITS 421 037440 000001 OPDEF PNT11F [37B8!11B12!1] ;PRINT 11 OCTAL DIGITS FORCED. 422 037400 000000 OPDEF PNTADR [37B8!10B12!0] ;PRINT PHYSICAL ADDRESS 423 037400 000001 OPDEF PNTADF [37B8!10B12!1] ;PRINT PHYSICAL ADDRESS FORCED 424 037600 000000 OPDEF PNTOCT [37B8!14B12!0] ;PRINT FULL WORD OCTAL 425 037600 000001 OPDEF PNTOTF [37B8!14B12!1] ;PRINT FULL WORD OCTAL FORCED 426 037540 000000 OPDEF PNTHW [37B8!13B12!0] ;PRINT OCTAL HALF WORDS, 6 SP 6 427 037540 000001 OPDEF PNTHWF [37B8!13B12!1] ;PRINT OCTAL HALF WORDS, 6 SP 6 FORCED 428 037700 000003 OPDEF PNTOCS [37B8!16B12!3] ;PRINT OCTAL, SUPPRESS LEADING 0'S 429 037740 000003 OPDEF PNTOCF [37B8!17B12!3] ;PRINT OCTAL, SUPPRESS LEADING 0'S FORCED 430 037640 000000 OPDEF PNTDEC [37B8!15B12!0] ;PRINT DECIMAL, SUPRESS LEADING 0'S 431 037640 000001 OPDEF PNTDCF [37B8!15B12!1] ;PRINT DECIMAL, SUPRESS LEADING 0'S FORCED 432 037700 000000 OPDEF PNTDS [37B8!16B12!0] ;PRINT DECIMAL, SPACES FOR LD 0'S 433 037700 000001 OPDEF PNTDSF [37B8!16B12!1] ;PRINT DECIMAL, SPACES FOR LD 0'S FORCED DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 5 PARAM KSM 18-Sep-79 17:18 PROGRAM/SUBROUTINE PARAMETERS SEQ 0038 434 037200 000002 OPDEF PNTNM [37B8!4B12!2] ;PRINT PROGRAM NAME 435 037000 000002 OPDEF PNTSIX [37B8!0B12!2] ;PRINT SIXBIT WORD 436 037040 000002 OPDEF PNTSXF [37B8!1B12!2] ;PRINT SIXBIT WORD FORCED 437 037240 000002 OPDEF DROPDV [37B8!5B12!2] ;CLOSE LOGICAL FILE, USER MODE 438 037100 000002 OPDEF PNTCW [37B8!2B12!2] ;PRINT DF10 CONTROL WORD 439 037140 000002 OPDEF PNTCWF [37B8!3B12!2] ;PRINT DF10 CONTROL WORD FORCED 440 037000 030242 OPDEF PCRL [37B8!0B12!CRLF] ;PRINT CARRIAGE RETURN/LINE FEED 441 037040 030242 OPDEF PCRLF [37B8!1B12!CRLF] ;PRINT CARRIAGE RETURN/LINE FEED FORCED 442 037000 000040 OPDEF PSP [37B8!0B12!40] ;PRINT SPACE 443 037040 000040 OPDEF PSPF [37B8!1B12!40] ;PRINT SPACE FORCED 444 037000 030243 OPDEF PCRL2 [37B8!0B12!CRLF2] ;PRINT CARRIAGE RETURN/LINE FEED (TWICE) 445 037040 030243 OPDEF PCRL2F [37B8!1B12!CRLF2] ;PRINT CARRIAGE RETURN/LINE FEED (TWICE) FORCED 446 037040 000007 OPDEF PBELL [37B8!1B12!7] ;PRINT TTY BELL 447 448 037040 000026 OPDEF PFORCE [37B8!1B12!26] ;PRINT FORCE, CONTROL O OVERRIDE 449 450 DEFINE PMSG (ARG),< 451 PSIXM [SIXBIT\ARG'_\]> 452 453 DEFINE PMSGF (ARG),< 454 PSIXMF [SIXBIT\ARG'_\]> 455 456 ;SIXBTZ -- MACRO TO GENERATE SIXBIT DATA FOR PRINTING 457 ; CONSERVES CORE OVER ASCIZ 458 459 DEFINE SIXBTZ (ARG),< [SIXBIT\ARG'_\]> 460 461 ;CONSOLE SWITCH INPUT UUO. 462 ;READS CONSOLE SWITCHES IF IN EXEC MODE OR ASKS FOR THEM IF 463 ; USER MODE. 464 465 037400 000002 OPDEF SWITCH [37B8!10B12!2] ;INPUT CONSOLE SWITCHES 466 467 ;CLOCK INITIALIZATION UUO - TO SET DESIRED CLOCK OPERATION 468 ;EITHER IGNORE CLOCK, ONLY LET IT TICK OR CAUSE INTERRUPT TO OCCUR. 469 470 037540 000004 OPDEF CLOKOP [37B8!13B12!4] ;CLOCK OPERATION UUO - CLOCK 471 037200 000004 OPDEF MTROP [37B8!4B12!4] ;CLOCK OPERATION UUO - METER 472 473 ;KS-10 CACHE OPERATION UUO'S 474 475 037040 000004 OPDEF CINVAL [37B8!1B12!4] ;CACHE INVALIDATE 476 037100 000004 OPDEF CFLUSH [37B8!2B12!4] ;CACHE FLUSH 477 037140 000004 OPDEF CWRTBI [37B8!3B12!4] ;CACHE WRITE-BACK & INVALIDATE DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 6 PARAM KSM 18-Sep-79 17:18 PROGRAM/SUBROUTINE PARAMETERS SEQ 0039 478 ;END OF PASS/PROGRAM UUOS 479 480 ;PERFORMS THE END OF PASS FUNCTIONS. INCREMENT PASS COUNT, 481 ;DECREMENT ITERATION COUNT, CHECK IF FINISHED WITH THIS PROGRAM ETC. 482 483 037500 000004 OPDEF ENDUUO [37B8!12B12!4] ;UUO TO DISPLAY LIGHTS 484 037700 000004 OPDEF EOPUUO [37B8!16B12!4] ;END OF PROGRAM UUO 485 486 ;MEMORY MANAGEMENT UUO'S 487 ;UUO'S TO PERFORM VARIOUS MEMORY FUNCTIONS. MAPPING, ZEROING, PAGING, 488 ;ADDRESS CONVERSION, ETC... 489 490 037000 000004 OPDEF MAPMEM [37B8!0B12!4] ;MAP MEMORY 491 037500 000002 OPDEF MEMZRO [37B8!12B12!2] ;ZERO MEMORY 492 037440 000002 OPDEF MEMSEG [37B8!11B12!2] ;SETUP MEMORY SEGMENT 493 037540 000002 OPDEF MAPADR [37B8!13B12!2] ;VIRTUAL TO PHYSICAL ADR CONVERT 494 037640 000002 OPDEF MAPCNK [37B8!15B12!2] ;MAP MEMORY CHUNK 495 037600 000002 OPDEF MAPSET [37B8!14B12!2] ;SET KI10 EXEC PAGE MAP 496 037740 000002 OPDEF MAPPNT [37B8!17B12!2] ;PRINT MEMORY MAP 497 498 ;DEVICE CODE MODIFICATION UUO 499 ;ALLOWS THE MODIFICATION OF IOT'S TO ONE DEVICE TO BE CHANGED TO 500 ;IOT'S TO A DIFFERENT DEVICE CODE. 501 502 037340 000002 OPDEF MODPCU [37B8!7B12!2] ;MODIFY PERHIPERAL CODE, USER 503 037300 000002 OPDEF MODPCP [37B8!6B12!2] ;MODIFY PERHIPERAL CODE, PROGRAM 504 505 030000 IFNDEF MODDVL, 506 030000 IFNDEF MODDVU, 507 508 ;"DIAMON" FILE SELECTION AND READ UUOS 509 510 037240 000004 OPDEF FSELECT [37B8!5B12!4] ;FILE SELECTION 511 037300 000004 OPDEF FREAD [37B8!6B12!4] ;FILE READ - ASCII DATA 512 037340 000004 OPDEF FRD36 [37B8!7B12!4] ;FILE READ - 36 BIT DATA 513 037400 000004 OPDEF FRD8 [37B8!10B12!4] ;FILE READ - 8 BIT DATA 514 515 XLIST 516 IFNDEF EROLD, 541 542 ;A MACRO TO REPORT AN ERROR AND NOT LOOP 543 544 DEFINE ERROR1 (FORMAT,CORECT,ACTUAL,F,D,ERR)< 545 SALL 546 ERUUO FORMAT,[T,,[SIXBIT\F'_\] 547 CORECT,,ACTUAL 548 [SIXBIT\D'_\],,ERR] 549 XALL> 550 551 >;END OF EROLD CONDITIONAL 552 553 XLIST 554 LIST DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1 FIXED KSM 18-Sep-79 17:08 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 SEQ 0041 555 SUBTTL *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 556 557 030000 LOC 30000 558 559 ; ********************************************************************** 560 ;PROGRAM STARTING ADDRESSES 561 ;THESE ADDRESSES CALL VARIOUS SPECIAL START ROUTINES AND OR OPTIONS 562 ;NORMAL START ADDRESS IS 30000 ALL OTHERS ARE SPECIAL. INVOKED BECAUSE 563 ;OF END OF PASS, POWER FAILURE, DDT START, RE-ENTERING(TYPICALLY USER 564 ;MODE), OR ANY NUMBER OF SPECIAL FEATURE TESTS. 565 ; ********************************************************************** 566 567 030000 254 00 1 00 027776 BEGIN: JRST @MODLNK ;STAND-ALONE START 568 030001 254 00 0 00 030623 $START: JRST START ;MODE CHECK STARTING ADDRESS 569 570 030002 254 00 1 00 027774 DIAGMN: JRST @LDLNK ;DIAGNOSTIC MONITOR START 571 572 030003 254 00 1 00 027774 SYSEXR: JRST @LDLNK ;SYSTEM EXERCISER START 573 574 030004 254 00 0 00 030624 SFSTRT: JRST SADR1 ;SPECIAL FEATURE START 575 576 030005 254 00 0 00 030624 PFSTRT: JRST SADR2 ;POWER FAIL RESTART 577 578 030006 254 00 0 00 030623 REENTR: JRST SADR3 ;REENTER START(USUALLY USER MODE ONLY) 579 580 030007 SRTDDT: ;COMMONLY MISTAKEN NAME FOR "DDTSRT" 581 030007 254 00 1 00 027775 DDTSRT: JRST @DDTLNK ;DDT START 582 583 030010 254 00 0 00 030624 BEGIN1: JRST STARTA ;LOOP START(END OF PASS COMES HERE) 584 030011 254 00 1 00 027777 SBINIT: JRST @SUBLNK ;PMGINT LINKAGE 585 030012 000000 000000 RETURN: 0 ;RETURN ADDRESS STORAGE 586 587 030013 254200 030000 START1: SADR7 ;OPTIONAL STARTING ADR/INSTRUCTIONS 588 030014 254200 030000 START2: SADR8 ; " 589 030015 254200 030000 START3: SADR9 ; " 590 030016 254200 030000 START4: SADR10 ; " 591 030017 254200 030000 START5: SADR11 ; " DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 2 FIXED KSM 18-Sep-79 17:08 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 SEQ 0042 592 ; ********************************************************************** 593 ;PROGRAM FIXED PARAMETER AREA 594 ; ********************************************************************** 595 596 030020 446353 434600 PNTNAM: PAREA3 ;SIXBIT PROGRAM NAME 597 030021 546364 000000 PNTEXT: PAREA4 ;SIXBIT PROGRAM EXTENSION 598 030022 000000 000000 RANDBS: PAREA1 ;RANDOM BASE NUMBER 599 030023 000000 000000 SWTEXR: PAREA2 ;SYSTEM EXERCISER SWITCHES 600 030024 000000 000010 ITRCNT: ITERAT ;PROGRAM ITERATIONS 601 030025 000000 030600 $PNAME: PGMNAM ;POINTER TO PROGRAMS NAME 602 030026 000000 000003 $PVER: MCNVER,,DECVER ;MCN & DEC VERSION LEVEL 603 030027 000000 030000 $MODVL: MODDVL ;DEVICE CODE CHANGE LOWER LIMIT 604 030030 000000 030000 $MODVU: MODDVU ;DEVICE CODE CHANGE UPPER LIMIT 605 030031 777777 777777 $EMODE: IFNDEF EXCASB,<0> IFDEF EXCASB,<-1> ;EXEC ALLOWED 606 030032 777777 777777 $UMODE: IFNDEF USRASB,<0> IFDEF USRASB,<-1> ;USER ALLOWED 607 030033 000000 000000 $DSKUP: IFNDEF DSKUPD,<0> IFDEF DSKUPD,<-1> ;DISK UPDATE MODE 608 030034 000000 000000 $MMAP: IFNDEF MEMMAP,<0> IFDEF MEMMAP,<-1> ;ALLOW MEMORY RTNS 609 030035 000000 000000 PAREA7: PAREA5 ;OPTIONAL PARAMETER 610 030036 000000 000000 PAREA8: PAREA6 ;OPTIONAL PARAMETER 611 612 ; ********************************************************************** 613 ;PROGRAM VARIABLE PARAMETER AREA 614 ; ********************************************************************** 615 616 030037 000000 000000 USER: 0 ; 0 = EXEC, -1 = USER MODE FLAG 617 030040 000000 000000 KAIFLG: 0 ;PROCESSOR TYPE, 0 = KA10, -1 = KI10 618 030041 777777 777777 KLFLG: -1 ;PROCESSOR TYPE, 0 = KA/KI, -1 = KL10 619 030042 777777 777777 MONFLG: -1 ;DIAG MONITOR SPECIAL USER FLAG 620 030043 000000 000000 MONCTL: 0 ;DIAG MON/SYS EXR FLAG 621 030044 000000 000000 MONTEN: 0 ;-1= LOADED BY 10 622 030045 000000 000000 CLOCKF: 0 ;CLOCK TICKED FLAG 623 030046 000000 000000 CONSW: 0 ;CONSOLE SWITCH SETTINGS 624 030047 000000 000000 PASCNT: 0 ;PROGRAM PASS COUNT 625 030050 000000 000000 RUNFLG: 0 ;PROGRAM RUN FLAG 626 030051 000000 000000 TESTPC: 0 ;SUBTEST PC 627 030052 000000 000000 ERRPC: 0 ;ERROR PC 628 030053 000000 000000 ERRTLS: 0 ;ERROR TOTALS 629 030054 000000 000000 TICKS: 0 ;PROGRAM RUNNING TIME 630 030055 000000 000000 MARGIN: 0 ;KI10 MARGIN WORD VALUE 631 030056 000000 000000 $ONETM: 0 ;SUBROUTINE INITIALIZATION FLAG DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3 FIXED KSM 18-Sep-79 17:08 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 SEQ 0043 632 ; ********************************************************************** 633 ;SPECIAL PROGRAM DISPATCH ADDRESSES 634 ; ********************************************************************** 635 636 030057 037 12 0 00 000004 BEGEND: ENDUUO ;END OF PASS 637 030060 254 00 0 00 030010 $BEND1: JRST BEGIN1 ;KEEP RUNNING PROGRAM 638 030061 037 16 0 00 000004 $BEND2: EOPUUO ;END OF PROGRAM - NO RETURN 639 030062 000000 030624 CNTLC: SADR5 ;CONTROL C XFER ADDRESS 640 030063 000000 040450 ALTMGO: SADR6 ;ALTMODE XFER ADDRESS 641 030064 CPOPJ1: ;SKIP RETURN 642 030064 350 00 0 17 000000 UUOSKP: AOS (P) ;SKIP RETURN FROM UUO 643 030065 CPOPJ: ;NON-SKIP REGULAR RETURN 644 030065 263 17 0 00 000000 UUOEXT: RTN ;UUO RETURN 645 030066 255 00 0 00 000000 UUORTN: JFCL ;ADDITIONAL USERS UUO ROUTINE 646 030067 255 00 0 00 000000 $UORTX: JFCL ;ADDITIONAL UUO LINKAGE 647 030070 255 00 0 00 000000 $UUOER: JFCL ;INITED AS (JRST $UOERX) 648 030071 255 00 0 00 000000 $ITRHL: JFCL ;ADDITIONAL INTERRUPT LINKAGE 649 030072 255 00 0 00 000000 $ITRX1: JFCL ; " 650 030073 255 00 0 00 000000 $USRHL: JFCL ; " 651 030074 255 00 0 00 000000 $RSRTX: JFCL ;ADDITIONAL POWER FAIL LINKAGE 652 030075 255 00 0 00 000000 $RSRTY: JFCL ; " 653 030076 255 00 0 00 000000 RESRT1: JFCL ; INITED AS (JRST RESRTX) 654 030077 255 00 0 00 000000 RESRT2: JFCL ; " 655 030100 255 00 0 00 000000 $PARER: JFCL ;ADDITIONAL PARITY ERROR LINKAGE 656 030101 255 00 0 00 000000 ERMORE: JFCL ;ADDITIONAL ERROR HANDLER LINKAGE 657 030102 254 04 0 00 030102 HALT . ;IMPROPER TRANSFER HALT 658 659 030103 000000 000000 $PSHER: 0 ;INITED AS (JRST PSHERR) 660 030104 000000 000000 ITRCH1: 0 ;PC & FLAGS OF CURRENT INTERRUPT 661 030105 000000 000000 0 ;INITED AS (JRST $ITRC1) 662 663 ; ********************************************************************** 664 ;PROCESSOR CONTROL STORAGE 665 ; ********************************************************************** 666 667 030106 000000 000000 $ACC0: 0 ;INTERRUPT SAVED AC0 668 030107 000000 000000 $SVPI: 0 ;INTERRUPT SAVED PI 669 030110 000000 000000 $SVAPR: 0 ;INTERRUPT SAVED APR 670 030111 000000 000000 $SVPAG: 0 ;INTERRUPT SAVED PAG (DATAI) 671 030112 000000 000000 $SPAG1: 0 ;INTERRUPT SAVED PAG (CONI) 672 673 030113 000000 000000 $SVUUO: 0 ;CURRENT USERS UUO 674 030114 000000 000000 $SVUPC: 0 ;PC OF CURRENT USERS UUO 675 676 030115 000000 000000 REPTU: 0 ;REPEAT UUO ITERATIONS 677 030116 000000 000000 SCOPE: 0 ;ERROR HANDLER SCOPE LOOP FLAG 678 030117 000000 000000 %CORFLG:0 ; " CORRECT FLAG 679 030120 000000 000000 %COREC: 0 ; " CORRECT DATA 680 030121 000000 000000 %ACTFL: 0 ; " ACTUAL FLAG 681 030122 000000 000000 %ACTUL: 0 ; " ACTUAL DATA 682 030123 000000 000000 %DISCR: 0 ; " DISCREPENCY DATA DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 4 FIXED KSM 18-Sep-79 17:08 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 SEQ 0044 683 ; ********************************************************************** 684 ;UUO DISPATCH TABLE 685 ; ********************************************************************** 686 XLIST 687 LIST 688 030124 030070 030070 UUODIS: LUUO1,,$UUOER 689 030125 030070 030070 LUUO3,,LUUO2 690 030126 030070 030070 LUUO5,,LUUO4 691 030127 030070 030070 LUUO7,,LUUO6 692 030130 030070 030070 LUUO11,,LUUO10 693 030131 030070 030070 LUUO13,,LUUO12 694 030132 030070 030070 LUUO15,,LUUO14 695 030133 030070 030070 LUUO17,,LUUO16 696 030134 030070 030070 LUUO21,,LUUO20 697 030135 030070 030070 LUUO23,,LUUO22 698 030136 030070 030070 LUUO25,,LUUO24 699 030137 030070 030070 LUUO27,,LUUO26 700 030140 030070 030070 LUUO31,,LUUO30 701 030141 030070 030070 LUUO33,,LUUO32 702 703 ; ********************************************************************** 704 ;MEMORY MANAGMENT STORAGE 705 ; ********************************************************************** 706 707 030142 000000 000000 DF22F: 0 ;DF10 CONTROL FLAG, 0 = 18, -1 = 22 BIT 708 030143 000000 000000 MAPNEW: 0 ;MEMORY MAPPING CONTROL FLAG, -1 = 4096K MAPPING 709 030144 000000 000000 MEMTOT: 0 ;TOTAL MEMORY SIZE IN K (1024.) 710 030145 000000 000000 MEMLOW: 0 ;LOWEST USABLE MEMORY 711 030146 MEMSIZ: BLOCK ^D41 ;MEMORY SEGMENT POINTER TABLE 712 713 ; ********************************************************************** 714 ;PRINT CONTROL STORAGE 715 ; ********************************************************************** 716 717 030217 000000 000000 PNTFLG: 0 ;PRINT FLAG, -1 WHILE IN PRINT ROUTINE 718 030220 000000 000000 PNTENB: 0 ;PRINT ENABLE 719 030221 000000 000000 PDISF: 0 ;PRINT DISABLED FLAG 720 030222 000000 000000 PNTINH: 0 ;INHIBIT PRINT INPUT CHECKS 721 030223 000000 000000 PNTSPC: 0 ;PRINT SPACE CONTROL 722 030224 000000 000000 OPTIME: 0 ;TYPE-IN WAIT TIME 723 030225 000000 000000 $TWCNT: 0 ;TIME WAITED 724 030226 000000 000000 $DVOFF: 0 ;LOGICAL DEVICE INITED FLAG 725 030227 000000 000000 TTYFIL: 0 ;TTY EXEC FILLERS FLAG 726 030230 000000 000000 TTYSPD: 0 ;TTY EXEC BAUD RATE 727 030231 000000 000000 $TTCHR: 0 ;ACTUAL TYPED IN CHAR 728 030232 000000 000000 $CHRIN: 0 ;UPPER CASED & PARITY STRIPPED CHAR 729 030233 000000 000000 $TYPNB: 0 ;TYPED IN NUMBER 730 030234 000000 000000 $CRLF: 0 ;FREE CR/LF FLAG 731 030235 000000 000000 $TABF: 0 ;TAB CONVERSION FLAG 732 030236 000000 000000 $FFF: 0 ;FORM FEED CONVERSION FLAG 733 030237 000000 000000 $VTF: 0 ;VERTICAL TAB CONVERSION FLAG 734 030240 000000 000000 USRLFF: 0 ;USER LF FILLERS 735 030241 000000 000000 USRCRF: 0 ;USER CR FILLERS DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 5 FIXED KSM 18-Sep-79 17:08 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 SEQ 0045 736 ; ********************************************************************** 737 ;THE FOLLOWING MISCELLANEOUS PRINT CHARACTERS ARE INCLUDED 738 ;TO FACILITATE PRINTING AND ARE CALLED AS FOLLOWS: 739 ; MOVEI NAME 740 ; PNTA ;OR PNTAF 741 ; ********************************************************************** 742 743 030242 CRLF: ASCII/ 744 030242 015 012 000 000 000 / 745 030243 CRLF2: ASCII/ 746 747 030243 015 012 015 012 000 / 748 030244 054 000 000 000 000 COMMA: ASCII/,/ 749 030245 056 000 000 000 000 PERIOD: ASCII/./ 750 030246 040 000 000 000 000 SPACE: ASCII/ / 751 030247 011 000 000 000 000 TAB: ASCII/ / 752 030250 MINUS: 753 030250 055 000 000 000 000 HYPEN: ASCII/-/ 754 030251 053 000 000 000 000 PLUS: ASCII/+/ 755 030252 052 000 000 000 000 AST: ASCII/*/ 756 030253 100 000 000 000 000 ATSIN: ASCII/@/ 757 030254 050 000 000 000 000 LFP: ASCII/(/ 758 030255 051 000 000 000 000 RTP: ASCII/)/ 759 030256 007 0000000000 BELL: BYTE (7) 007 760 030257 077 000 000 000 000 QUEST: ASCII/?/ 761 030260 057 000 000 000 000 SLASH: ASCII!/! 762 030261 044 000 000 000 000 DOLLAR: ASCII/$/ 763 030262 000000 000012 RADIX: ^D10 ;DECIMAL PRINT RADIX 764 030263 000000 000040 RADLSP: 40 ;DECIMAL PRINT LEADING CHAR 765 030264 000000 000012 RADLSC: ^D10 ;DECIMAL PRINT LEADING CHAR COUNT 766 767 ; ********************************************************************** 768 ;USER MODE OUTPUT FILE INFORMATION 769 ; ********************************************************************** 770 771 030265 $OBUF: BLOCK 3 ;LOGICAL FILE OUTPUT BUFFER HEADER 772 030270 60 62 51 56 64 00 $OUTNM: SIXBIT /PRINT/ ;FILE NAME 773 030271 60 56 64 00 00 00 $OUTEX: SIXBIT /PNT/ ;FILE NAME EXTENSION 774 030272 BLOCK 2 775 776 ; ********************************************************************** 777 ;DISK UPDATE MODE FILE INFORMATION 778 ; ********************************************************************** 779 780 030274 $IBUF: BLOCK 3 781 030277 60 62 51 56 64 00 $INNM: SIXBIT /PRINT/ 782 030300 60 56 64 00 00 00 $INEXT: SIXBIT /PNT/ 783 030301 BLOCK 2 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 6 FIXED KSM 18-Sep-79 17:08 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 SEQ 0046 784 ; ********************************************************************** 785 ;PUSHDOWN LIST CONTROL INFORMATION 786 ; ********************************************************************** 787 788 030303 777577 030303 PLIST: PLIST-PLISTE,,PLIST 789 030304 PLISTS: BLOCK 200 790 030504 000000 000000 PLISTE: 0 ;END OF PUSHDOWN LIST 791 792 ; ********************************************************************** 793 ;POWER LINE CLOCK FREQUENCY FLAG 794 ; ********************************************************************** 795 796 030505 000000 000000 CYCL60: 0 ;0 = 60, -1 = 50 CYCLE 797 798 ; ********************************************************************** 799 ;KL10 CACHE CONTROL FLAGS 800 ; ********************************************************************** 801 802 030506 000000 000000 CSHFLG: 0 ;ALLOW CACHE IF 0 803 030507 000000 000000 CSHMEM: 0 ;CACHE MEMORY SEGMENTS IF 0 804 805 ; ********************************************************************** 806 ;NUMBER INPUT DIGIT FLAG 807 ; ********************************************************************** 808 809 030510 000000 000000 TTNBRF: 0 ;-1 IF ANY DIGIT TYPED 810 811 ; ********************************************************************** 812 ;KL10 & KI10 "INHPAG" SWITCH PAGING PREVENTION 813 ; ********************************************************************** 814 815 030511 000000 000000 PVPAGI: 0 ;IF NON-ZERO, OVERRIDE "INHPAG" SWITCH ACTION 816 817 ; ********************************************************************** 818 ;ERROR REPORTING ROUTINE ADDITIONAL USERS CONTROL INSTRUCTIONS 819 ; ********************************************************************** 820 821 030512 000000 000000 %ERHI1: 0 ;IF NON-ZERO, XCT'D AT START OF %ERUUO 822 030513 000000 000000 %ERHI2: 0 ;IF NON-ZERO, XCT'D AT END OF %ERUUO 823 030514 000000 000000 %ERHI3: 0 ;IF NON-ZERO, XCT'D AFTER "PC" OF %ERUUO 824 825 ; ********************************************************************** 826 ;SPECIAL USERS UUO INTERCEPT INSTRUCTION 827 ; ********************************************************************** 828 829 030515 000000 000000 $$UUO: 0 ;IF NON-ZERO, XCT'D AT START OF $UORTN DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 7 FIXED KSM 18-Sep-79 17:08 *FIXED* FIXED CONTROL AND DISPATCH STORAGE, SEPTEMBER 1979 SEQ 0047 830 ; ********************************************************************** 831 ;USER MODE MONITOR TYPE FLAG 832 ; ********************************************************************** 833 834 030516 000000 000000 MONTYP: 0 ;0 = TOPS10, -1 = TOPS20 835 836 ; ********************************************************************** 837 ;SPECIAL USERS MUUO INTERCEPT INSTRUCTION 838 ; ********************************************************************** 839 840 030517 000000 000000 $$MUUO: 0 ;IF NON-ZERO, XCT'D AT START OF MUUOER 841 842 ; ********************************************************************** 843 ;SPECIAL USERS USER MODE OUTPUT ERROR INTERCEPT INSTUCTION 844 ; ********************************************************************** 845 846 030520 000000 000000 $$OUTER:0 ;IF NON-ZERO, XCT'D AT END OF USER MODE ERROR 847 848 ; ********************************************************************** 849 ;"SWITCH" CALL USAGE CONTROL 850 ; ********************************************************************** 851 852 030521 000000 000000 $$TOGGLE:0 ;IF NON-ZERO, USE C(CONSW) FOR SWITCHES 853 854 ; ********************************************************************** 855 ;SPECIAL USERS ALTMODE SWITCH CALL INTERCEPT INSTRUCTIONS 856 ; ********************************************************************** 857 858 030522 000000 000000 $$TAX1: 0 ;IF NON-ZERO, XCT'D AT START OF ALTMODE SWITCH CALL 859 030523 000000 000000 $$TAX2: 0 ;IF NON-ZERO, XCT'D AT END OF ALTMODE SWITCH CALL 860 861 ; ********************************************************************** 862 ;SM10 (KS-10) PROCESSOR TYPE FLAG 863 ; ********************************************************************** 864 865 030524 777777 777777 SM10: 0 ;IF -1 THIS IS AN KS-10 866 867 ; ********************************************************************** 868 ;RIGHT HALF SWITCHES PROMPT TABLE ADDRESS 869 ; ********************************************************************** 870 871 030525 000000 000000 SWPTAB: 0 ;0 = NO PROMPT, ADR = ADR OF SIXBIT PROMPT TABLE 872 873 ; ********************************************************************** 874 ;SPECIAL FUTURE EXPANSION ROOM 875 ; ********************************************************************** 876 877 ; ********************************************************************** 878 ;END OF FIXED STORAGE 879 ; ********************************************************************** 880 881 030577 LOC 30577 882 030577 000000 000000 ENDFIX: 0 ;END OF FIXED STORAGE DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1 DSKCFM MAC 26-Sep-79 15:49 INITIALIZATION SECTION SEQ 0048 883 SUBTTL INITIALIZATION SECTION 884 885 LALL ;EXPAND MACROS 886 887 030600 PGMNAM: ASCIZ/ 888 030600 015 012 104 105 103 DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6 [DSKCF] 889 030601 123 131 123 124 105 890 030602 115 040 062 060 062 891 030603 060 040 101 104 126 892 030604 101 116 103 105 104 893 030605 040 111 116 123 124 894 030606 122 125 103 124 111 895 030607 117 116 040 104 111 896 030610 101 107 116 117 123 897 030611 124 111 103 040 043 898 030612 066 040 133 104 123 899 030613 113 103 106 135 015 900 030614 012 104 117 125 102 DOUBLE PRECISION INSTRUCTIONS 901 030615 114 105 040 120 122 902 030616 105 103 111 123 111 903 030617 117 116 040 111 116 904 030620 123 124 122 125 103 905 030621 124 111 117 116 123 906 030622 015 012 000 000 000 / 907 123456 765432 NUM=123456765432 908 909 ; A MACRO TO REPORT AN ERROR AND LOOP 910 ; THIS IS REDEFINED HERE TO CHANGE THE LISTING CONTROL STATEMENTS 911 912 DEFINE ERROR (ADR,FORMAT,CORECT,ACTUAL,F,D,ERR) 919 920 030623 265 00 0 00 030011 START: PGMINT ;INITIALIZE PROGRAM 921 030624 STARTA: DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 2 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST A SEQ 0049 922 SUBTTL DADD - TEST A 923 SALL 924 041016 T=SIXBTZ 925 LALL 926 ; ********************************************************************** 927 ;*DADD - TEST A 928 ;* 929 ;* 0,# + 0,0 = 0,# SIMPLE TESTS TO SEE IF DADD 930 ;* #,0 + 0,0 = #,0 WORKS AT ALL. 931 ;* #,# + 0,0 = #,# 932 ;* 0,0 + 0,# = 0,# 933 ;* 0,0 + #,0 = #,0 934 ;* 0,0 + #,# = #,# 935 ;* 0,0 + 0,0 = 0,0 936 ; ********************************************************************** 937 938 ; ********************************************************************** 939 ; ---------- DADD (0,#) + (0,0) = (0,#) ---------- 940 ; ********************************************************************** 941 942 030624 200 15 0 00 041024 ATEST1: MOVE SCR3,[[EXP 0,NUM],,[EXP 0,0]] ;ADDR FOR APRINT 943 030625 120 01 0 00 041020 DMOVE AC1,[EXP 0,NUM] ;INIT AUGEND TO (0,#) 944 030626 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD (0,#)+(0,0) 945 CHECKA (ATEST1,A1,0,NUM)^ 946 947 030627 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 948 030630 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 949 030631 254 00 0 00 030635 JRST ..0001 ;NO - GO TO ERROR HANDLING 950 030632 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 951 030633 316 02 0 00 041021 CAMN AC1+1,[NUM] ;IS RIGHT HALF CORRECT? 952 030634 254 00 0 00 030640 JRST ..0002+1 ;YES - DONT DO ERROR HANDLING 953 ; EXCEPT FOR ERLOOP 954 955 030635 200 14 0 13 000001 ..0001: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 956 030636 200 13 0 13 041020 MOVE SCR1,[EXP 0,NUM](SCR1) ;GET CORRECT RESULT 957 030637 ..0002: ERROR (ATEST1,14,SCR1,SCR2,,TEST A1 - RESULT IS INCORRECT,APRINT)^SALL 958 030637 036 14 0 00 041033 959 030640 255 00 0 00 000000 960 ^ 961 ^ 962 963 ; ********************************************************************** 964 ; ---------- DADD (#,0) + (0,0) = (#,0) ---------- 965 ; ********************************************************************** 966 967 030641 200 15 0 00 041036 ATEST2: MOVE SCR3,[[EXP NUM,0],,[EXP 0,0]] ;ADDR FOR APRINT 968 030642 120 01 0 00 041021 DMOVE AC1,[EXP NUM,0] ;INIT AUGEND TO (#,0) 969 030643 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD (#,0)+(0,0) 970 CHECKA (ATEST2,A2,NUM,0)^ 971 972 030644 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 973 030645 312 01 0 00 041021 CAME AC1,[NUM] ;IS LEFT HALF OF RESULT CORRECT? 974 030646 254 00 0 00 030652 JRST ..0003 ;NO - GO TO ERROR HANDLING 975 030647 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 976 030650 316 02 0 00 041020 CAMN AC1+1,[0] ;IS RIGHT HALF CORRECT? DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 2-1 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST A SEQ 0050 977 030651 254 00 0 00 030655 JRST ..0004+1 ;YES - DONT DO ERROR HANDLING 978 ; EXCEPT FOR ERLOOP 979 980 030652 200 14 0 13 000001 ..0003: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 981 030653 200 13 0 13 041021 MOVE SCR1,[EXP NUM,0](SCR1) ;GET CORRECT RESULT 982 030654 ..0004: ERROR (ATEST2,14,SCR1,SCR2,,TEST A2 - RESULT IS INCORRECT,APRINT)^SALL 983 030654 036 14 0 00 041044 984 030655 255 00 0 00 000000 985 ^ 986 ^ 987 988 ; ********************************************************************** 989 ; ---------- DADD (#,#) + (0,0) = (#,#) ---------- 990 ; ********************************************************************** 991 992 030656 200 15 0 00 041051 ATEST3: MOVE SCR3,[[EXP NUM,NUM],,[EXP 0,0]] ;ADDR FOR APRINT 993 030657 120 01 0 00 041047 DMOVE AC1,[EXP NUM,NUM] ;INIT AUGEND TO (#,#) 994 030660 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD (#,#)+(0,0) 995 CHECKA (ATEST3,A3,NUM,NUM)^ 996 997 030661 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 998 030662 312 01 0 00 041021 CAME AC1,[NUM] ;IS LEFT HALF OF RESULT CORRECT? 999 030663 254 00 0 00 030667 JRST ..0005 ;NO - GO TO ERROR HANDLING 1000 030664 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1001 030665 316 02 0 00 041021 CAMN AC1+1,[NUM] ;IS RIGHT HALF CORRECT? 1002 030666 254 00 0 00 030672 JRST ..0006+1 ;YES - DONT DO ERROR HANDLING 1003 ; EXCEPT FOR ERLOOP 1004 1005 030667 200 14 0 13 000001 ..0005: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1006 030670 200 13 0 13 041047 MOVE SCR1,[EXP NUM,NUM](SCR1) ;GET CORRECT RESULT 1007 030671 ..0006: ERROR (ATEST3,14,SCR1,SCR2,,TEST A3 - RESULT IS INCORRECT,APRINT)^SALL 1008 030671 036 14 0 00 041057 1009 030672 255 00 0 00 000000 1010 ^ 1011 ^ 1012 1013 ; ********************************************************************** 1014 ; ---------- DADD (0,0) + (0,#) = (0,#) ---------- 1015 ; ********************************************************************** 1016 1017 030673 200 15 0 00 041062 ATEST4: MOVE SCR3,[[EXP 0,0],,[EXP 0,NUM]] ;ADDR FOR APRINT 1018 030674 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1019 030675 114 01 0 00 041020 DADD AC1,[EXP 0,NUM] ;ADD (0,0) + (0,#) 1020 CHECKA (ATEST4,A4,0,NUM)^ 1021 1022 030676 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1023 030677 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 1024 030700 254 00 0 00 030704 JRST ..0007 ;NO - GO TO ERROR HANDLING 1025 030701 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1026 030702 316 02 0 00 041021 CAMN AC1+1,[NUM] ;IS RIGHT HALF CORRECT? 1027 030703 254 00 0 00 030707 JRST ..0010+1 ;YES - DONT DO ERROR HANDLING 1028 ; EXCEPT FOR ERLOOP 1029 1030 030704 200 14 0 13 000001 ..0007: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1031 030705 200 13 0 13 041020 MOVE SCR1,[EXP 0,NUM](SCR1) ;GET CORRECT RESULT DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 2-2 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST A SEQ 0051 1032 030706 ..0010: ERROR (ATEST4,14,SCR1,SCR2,,TEST A4 - RESULT IS INCORRECT,APRINT)^SALL 1033 030706 036 14 0 00 041070 1034 030707 255 00 0 00 000000 1035 ^ 1036 ^ 1037 1038 ; ********************************************************************** 1039 ; ---------- DADD (0,0) + (#,0) = (#,0) ---------- 1040 ; ********************************************************************** 1041 1042 030710 200 15 0 00 041073 ATEST5: MOVE SCR3,[[EXP 0,0],,[EXP NUM,0]] ;ADDR FOR APRINT 1043 030711 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1044 030712 114 01 0 00 041021 DADD AC1,[EXP NUM,0] ;ADD (0,0) + (#,0) 1045 CHECKA (ATEST5,A5,NUM,0)^ 1046 1047 030713 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1048 030714 312 01 0 00 041021 CAME AC1,[NUM] ;IS LEFT HALF OF RESULT CORRECT? 1049 030715 254 00 0 00 030721 JRST ..0011 ;NO - GO TO ERROR HANDLING 1050 030716 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1051 030717 316 02 0 00 041020 CAMN AC1+1,[0] ;IS RIGHT HALF CORRECT? 1052 030720 254 00 0 00 030724 JRST ..0012+1 ;YES - DONT DO ERROR HANDLING 1053 ; EXCEPT FOR ERLOOP 1054 1055 030721 200 14 0 13 000001 ..0011: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1056 030722 200 13 0 13 041021 MOVE SCR1,[EXP NUM,0](SCR1) ;GET CORRECT RESULT 1057 030723 ..0012: ERROR (ATEST5,14,SCR1,SCR2,,TEST A5 - RESULT IS INCORRECT,APRINT)^SALL 1058 030723 036 14 0 00 041101 1059 030724 255 00 0 00 000000 1060 ^ 1061 ^ 1062 1063 ; ********************************************************************** 1064 ; ---------- DADD (0,0) + (#,#) = (#,#) ---------- 1065 ; ********************************************************************** 1066 1067 030725 200 15 0 00 041104 ATEST6: MOVE SCR3,[[EXP 0,0],,[EXP NUM,NUM]] ;ADDR FOR APRINT 1068 030726 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1069 030727 114 01 0 00 041047 DADD AC1,[EXP NUM,NUM] ;ADD (0,0)+(#,#) 1070 CHECKA (ATEST6,A6,NUM,NUM)^ 1071 1072 030730 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1073 030731 312 01 0 00 041021 CAME AC1,[NUM] ;IS LEFT HALF OF RESULT CORRECT? 1074 030732 254 00 0 00 030736 JRST ..0013 ;NO - GO TO ERROR HANDLING 1075 030733 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1076 030734 316 02 0 00 041021 CAMN AC1+1,[NUM] ;IS RIGHT HALF CORRECT? 1077 030735 254 00 0 00 030741 JRST ..0014+1 ;YES - DONT DO ERROR HANDLING 1078 ; EXCEPT FOR ERLOOP 1079 1080 030736 200 14 0 13 000001 ..0013: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1081 030737 200 13 0 13 041047 MOVE SCR1,[EXP NUM,NUM](SCR1) ;GET CORRECT RESULT 1082 030740 ..0014: ERROR (ATEST6,14,SCR1,SCR2,,TEST A6 - RESULT IS INCORRECT,APRINT)^SALL 1083 030740 036 14 0 00 041112 1084 030741 255 00 0 00 000000 1085 ^ 1086 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 2-3 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST A SEQ 0052 1087 1088 ; ********************************************************************** 1089 ; ---------- DADD (0,0) + (0,0) = (0,0) ---------- 1090 ; ********************************************************************** 1091 1092 030742 200 15 0 00 041115 ATEST7: MOVE SCR3,[[EXP 0,0],,[EXP 0,0]] ;ADDR FOR APRINT 1093 030743 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1094 030744 114 01 0 00 000001 DADD AC1,AC1 ;ADD (0,0) + (0,0) 1095 CHECKA (ATEST7,A7,0,0)^ 1096 1097 030745 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1098 030746 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 1099 030747 254 00 0 00 030753 JRST ..0015 ;NO - GO TO ERROR HANDLING 1100 030750 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1101 030751 316 02 0 00 041020 CAMN AC1+1,[0] ;IS RIGHT HALF CORRECT? 1102 030752 254 00 0 00 030756 JRST ..0016+1 ;YES - DONT DO ERROR HANDLING 1103 ; EXCEPT FOR ERLOOP 1104 1105 030753 200 14 0 13 000001 ..0015: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1106 030754 200 13 0 13 041022 MOVE SCR1,[EXP 0,0](SCR1) ;GET CORRECT RESULT 1107 030755 ..0016: ERROR (ATEST7,14,SCR1,SCR2,,TEST A7 - RESULT IS INCORRECT,APRINT)^SALL 1108 030755 036 14 0 00 041123 1109 030756 255 00 0 00 000000 1110 ^ 1111 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0053 1112 SUBTTL DADD - TEST B 1113 1114 ; ********************************************************************** 1115 ;DADD - TEST B 1116 ;* 1117 ;* FLOATING 1 + 0 = FLOATING 1 THESE TESTS ARE DONE FOR A 1 OR 1118 ;* 0 + FLOATING 1 = FLOATING 1 A 0 IN BITS 0,34,36,70 OF THE 1119 ;* FLOATING 0 + 0 = FLOATING 0 DOUBLEWORD ADDEND OR AUGEND. 1120 ;* 0 + FLOATING 0 = FLOATING 0 THIS WILL TEST THE WORD BOUND- 1121 ;* ARY INTEGRITY OF THE DADD 1122 ;* INSTRUCTION. 1123 ; ********************************************************************** 1124 1125 ; ********************************************************************** 1126 ;* REPEAT THE FOLLOWING BLOCK OF CODE 8 TIMES TO STEP DOWN A LIST 1127 ;* OF TEST CASES. THE TEST CASES CONSIST OF 8 DOUBLEWORDS - THE 1128 ;* FIRST 4 FLOAT A 1 ACROSS IN BITS 0,34,36,70; THE SECOND 4 FLOAT 1129 ;* A 0 ACROSS IN BITS 0,34,36,70. THE RESULT SHOULD BE ACS WITH 1130 ;* CONTENTS EQUAL TO THE FLOATING 1/0. 1131 ; ********************************************************************** 1132 1133 000000 REP=0 1134 000000 REPP=0 1135 1136 REPEAT ^D8,< 1137 ; ************************************************ 1138 1139 REP=REP+1 1140 LOC=. ;ERROR LOOP RETURN ADDRESS 1141 ALEFT=0+IFE REP-3,<1>+IFE REP-4,<1B1> 1142 ARIGHT=0+IFE REP-1,<1>+IFE REP-2,<1B1> 1143 IFE REPP-1, 1145 1146 MOVE SCR3,[[EXP ALEFT,ARIGHT],,[EXP 0,0]] ;ADDR FOR APRINT 1147 DMOVE AC1,[EXP ALEFT,ARIGHT] ;INIT AUGEND TO FLOATING 1/0 1148 DADD AC1,[EXP 0,0] ;ADD FLOATING 1/0 + (0,0) 1149 CHECKA (LOC,B1,ALEFT,ARIGHT) 1150 1151 LOC=. ;ERROR LOOP RETURN ADDRESS 1152 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1153 MOVE SCR3,[[EXP 0,0],,[EXP ALEFT,ARIGHT]] ;ADDR FOR APRINT 1154 DADD AC1,[EXP ALEFT,ARIGHT] ;ADD (0,0) + FLOATING 1/0 1155 CHECKA (LOC,B2,ALEFT,ARIGHT) 1156 1157 IFE REP-4, 1159 ; ************************************************ 1160 > 1161 1162 ; ************************************************ 1163 1164 000001 REP=REP+1 1165 030757 LOC=. ;ERROR LOOP RETURN ADDRESS 1166 000000 ALEFT=0+IFE REP-3,<1>+IFE REP-4,<1B1> DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3-1 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0054 1167 000001 ARIGHT=0+IFE REP-1,<1>+IFE REP-2,<1B1> 1168 IFE REPP-1, 1170 1171 030757 200 15 0 00 041130 MOVE SCR3,[[EXP ALEFT,ARIGHT],,[EXP 0,0]] ;ADDR FOR APRINT 1172 030760 120 01 0 00 041126 DMOVE AC1,[EXP ALEFT,ARIGHT] ;INIT AUGEND TO FLOATING 1/0 1173 030761 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD FLOATING 1/0 + (0,0) 1174 CHECKA (LOC,B1,ALEFT,ARIGHT)^ 1175 1176 030762 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1177 030763 312 01 0 00 041020 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1178 030764 254 00 0 00 030770 JRST ..0017 ;NO - GO TO ERROR HANDLING 1179 030765 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1180 030766 316 02 0 00 041127 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1181 030767 254 00 0 00 030773 JRST ..0020+1 ;YES - DONT DO ERROR HANDLING 1182 ; EXCEPT FOR ERLOOP 1183 1184 030770 200 14 0 13 000001 ..0017: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1185 030771 200 13 0 13 041126 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1186 030772 ..0020: ERROR (LOC,14,SCR1,SCR2,,TEST B1 - RESULT IS INCORRECT,APRINT)^SALL 1187 030772 036 14 0 00 041136 1188 030773 255 00 0 00 000000 1189 ^ 1190 ^ 1191 1192 030774 LOC=. ;ERROR LOOP RETURN ADDRESS 1193 030774 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1194 030775 200 15 0 00 041141 MOVE SCR3,[[EXP 0,0],,[EXP ALEFT,ARIGHT]] ;ADDR FOR APRINT 1195 030776 114 01 0 00 041126 DADD AC1,[EXP ALEFT,ARIGHT] ;ADD (0,0) + FLOATING 1/0 1196 CHECKA (LOC,B2,ALEFT,ARIGHT)^ 1197 1198 030777 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1199 031000 312 01 0 00 041020 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1200 031001 254 00 0 00 031005 JRST ..0021 ;NO - GO TO ERROR HANDLING 1201 031002 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1202 031003 316 02 0 00 041127 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1203 031004 254 00 0 00 031010 JRST ..0022+1 ;YES - DONT DO ERROR HANDLING 1204 ; EXCEPT FOR ERLOOP 1205 1206 031005 200 14 0 13 000001 ..0021: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1207 031006 200 13 0 13 041126 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1208 031007 ..0022: ERROR (LOC,14,SCR1,SCR2,,TEST B2 - RESULT IS INCORRECT,APRINT)^SALL 1209 031007 036 14 0 00 041147 1210 031010 255 00 0 00 000000 1211 ^ 1212 ^ 1213 1214 IFE REP-4, 1216 ; ************************************************ 1217 1218 1219 ; ************************************************ 1220 1221 000002 REP=REP+1 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3-2 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0055 1222 031011 LOC=. ;ERROR LOOP RETURN ADDRESS 1223 000000 ALEFT=0+IFE REP-3,<1>+IFE REP-4,<1B1> 1224 200000 000000 ARIGHT=0+IFE REP-1,<1>+IFE REP-2,<1B1> 1225 IFE REPP-1, 1227 1228 031011 200 15 0 00 041154 MOVE SCR3,[[EXP ALEFT,ARIGHT],,[EXP 0,0]] ;ADDR FOR APRINT 1229 031012 120 01 0 00 041152 DMOVE AC1,[EXP ALEFT,ARIGHT] ;INIT AUGEND TO FLOATING 1/0 1230 031013 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD FLOATING 1/0 + (0,0) 1231 CHECKA (LOC,B1,ALEFT,ARIGHT)^ 1232 1233 031014 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1234 031015 312 01 0 00 041020 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1235 031016 254 00 0 00 031022 JRST ..0023 ;NO - GO TO ERROR HANDLING 1236 031017 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1237 031020 316 02 0 00 041153 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1238 031021 254 00 0 00 031025 JRST ..0024+1 ;YES - DONT DO ERROR HANDLING 1239 ; EXCEPT FOR ERLOOP 1240 1241 031022 200 14 0 13 000001 ..0023: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1242 031023 200 13 0 13 041152 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1243 031024 ..0024: ERROR (LOC,14,SCR1,SCR2,,TEST B1 - RESULT IS INCORRECT,APRINT)^SALL 1244 031024 036 14 0 00 041136 1245 031025 255 00 0 00 000000 1246 ^ 1247 ^ 1248 1249 031026 LOC=. ;ERROR LOOP RETURN ADDRESS 1250 031026 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1251 031027 200 15 0 00 041155 MOVE SCR3,[[EXP 0,0],,[EXP ALEFT,ARIGHT]] ;ADDR FOR APRINT 1252 031030 114 01 0 00 041152 DADD AC1,[EXP ALEFT,ARIGHT] ;ADD (0,0) + FLOATING 1/0 1253 CHECKA (LOC,B2,ALEFT,ARIGHT)^ 1254 1255 031031 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1256 031032 312 01 0 00 041020 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1257 031033 254 00 0 00 031037 JRST ..0025 ;NO - GO TO ERROR HANDLING 1258 031034 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1259 031035 316 02 0 00 041153 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1260 031036 254 00 0 00 031042 JRST ..0026+1 ;YES - DONT DO ERROR HANDLING 1261 ; EXCEPT FOR ERLOOP 1262 1263 031037 200 14 0 13 000001 ..0025: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1264 031040 200 13 0 13 041152 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1265 031041 ..0026: ERROR (LOC,14,SCR1,SCR2,,TEST B2 - RESULT IS INCORRECT,APRINT)^SALL 1266 031041 036 14 0 00 041147 1267 031042 255 00 0 00 000000 1268 ^ 1269 ^ 1270 1271 IFE REP-4, 1273 ; ************************************************ 1274 1275 1276 ; ************************************************ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3-3 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0056 1277 1278 000003 REP=REP+1 1279 031043 LOC=. ;ERROR LOOP RETURN ADDRESS 1280 000001 ALEFT=0+IFE REP-3,<1>+IFE REP-4,<1B1> 1281 000000 ARIGHT=0+IFE REP-1,<1>+IFE REP-2,<1B1> 1282 IFE REPP-1, 1284 1285 031043 200 15 0 00 041160 MOVE SCR3,[[EXP ALEFT,ARIGHT],,[EXP 0,0]] ;ADDR FOR APRINT 1286 031044 120 01 0 00 041156 DMOVE AC1,[EXP ALEFT,ARIGHT] ;INIT AUGEND TO FLOATING 1/0 1287 031045 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD FLOATING 1/0 + (0,0) 1288 CHECKA (LOC,B1,ALEFT,ARIGHT)^ 1289 1290 031046 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1291 031047 312 01 0 00 041127 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1292 031050 254 00 0 00 031054 JRST ..0027 ;NO - GO TO ERROR HANDLING 1293 031051 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1294 031052 316 02 0 00 041020 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1295 031053 254 00 0 00 031057 JRST ..0030+1 ;YES - DONT DO ERROR HANDLING 1296 ; EXCEPT FOR ERLOOP 1297 1298 031054 200 14 0 13 000001 ..0027: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1299 031055 200 13 0 13 041156 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1300 031056 ..0030: ERROR (LOC,14,SCR1,SCR2,,TEST B1 - RESULT IS INCORRECT,APRINT)^SALL 1301 031056 036 14 0 00 041136 1302 031057 255 00 0 00 000000 1303 ^ 1304 ^ 1305 1306 031060 LOC=. ;ERROR LOOP RETURN ADDRESS 1307 031060 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1308 031061 200 15 0 00 041161 MOVE SCR3,[[EXP 0,0],,[EXP ALEFT,ARIGHT]] ;ADDR FOR APRINT 1309 031062 114 01 0 00 041156 DADD AC1,[EXP ALEFT,ARIGHT] ;ADD (0,0) + FLOATING 1/0 1310 CHECKA (LOC,B2,ALEFT,ARIGHT)^ 1311 1312 031063 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1313 031064 312 01 0 00 041127 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1314 031065 254 00 0 00 031071 JRST ..0031 ;NO - GO TO ERROR HANDLING 1315 031066 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1316 031067 316 02 0 00 041020 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1317 031070 254 00 0 00 031074 JRST ..0032+1 ;YES - DONT DO ERROR HANDLING 1318 ; EXCEPT FOR ERLOOP 1319 1320 031071 200 14 0 13 000001 ..0031: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1321 031072 200 13 0 13 041156 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1322 031073 ..0032: ERROR (LOC,14,SCR1,SCR2,,TEST B2 - RESULT IS INCORRECT,APRINT)^SALL 1323 031073 036 14 0 00 041147 1324 031074 255 00 0 00 000000 1325 ^ 1326 ^ 1327 1328 IFE REP-4, 1330 ; ************************************************ 1331 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3-4 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0057 1332 1333 ; ************************************************ 1334 1335 000004 REP=REP+1 1336 031075 LOC=. ;ERROR LOOP RETURN ADDRESS 1337 200000 000000 ALEFT=0+IFE REP-3,<1>+IFE REP-4,<1B1> 1338 000000 ARIGHT=0+IFE REP-1,<1>+IFE REP-2,<1B1> 1339 IFE REPP-1, 1341 1342 031075 200 15 0 00 041164 MOVE SCR3,[[EXP ALEFT,ARIGHT],,[EXP 0,0]] ;ADDR FOR APRINT 1343 031076 120 01 0 00 041162 DMOVE AC1,[EXP ALEFT,ARIGHT] ;INIT AUGEND TO FLOATING 1/0 1344 031077 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD FLOATING 1/0 + (0,0) 1345 CHECKA (LOC,B1,ALEFT,ARIGHT)^ 1346 1347 031100 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1348 031101 312 01 0 00 041153 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1349 031102 254 00 0 00 031106 JRST ..0033 ;NO - GO TO ERROR HANDLING 1350 031103 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1351 031104 316 02 0 00 041020 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1352 031105 254 00 0 00 031111 JRST ..0034+1 ;YES - DONT DO ERROR HANDLING 1353 ; EXCEPT FOR ERLOOP 1354 1355 031106 200 14 0 13 000001 ..0033: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1356 031107 200 13 0 13 041162 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1357 031110 ..0034: ERROR (LOC,14,SCR1,SCR2,,TEST B1 - RESULT IS INCORRECT,APRINT)^SALL 1358 031110 036 14 0 00 041136 1359 031111 255 00 0 00 000000 1360 ^ 1361 ^ 1362 1363 031112 LOC=. ;ERROR LOOP RETURN ADDRESS 1364 031112 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1365 031113 200 15 0 00 041165 MOVE SCR3,[[EXP 0,0],,[EXP ALEFT,ARIGHT]] ;ADDR FOR APRINT 1366 031114 114 01 0 00 041162 DADD AC1,[EXP ALEFT,ARIGHT] ;ADD (0,0) + FLOATING 1/0 1367 CHECKA (LOC,B2,ALEFT,ARIGHT)^ 1368 1369 031115 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1370 031116 312 01 0 00 041153 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1371 031117 254 00 0 00 031123 JRST ..0035 ;NO - GO TO ERROR HANDLING 1372 031120 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1373 031121 316 02 0 00 041020 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1374 031122 254 00 0 00 031126 JRST ..0036+1 ;YES - DONT DO ERROR HANDLING 1375 ; EXCEPT FOR ERLOOP 1376 1377 031123 200 14 0 13 000001 ..0035: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1378 031124 200 13 0 13 041162 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1379 031125 ..0036: ERROR (LOC,14,SCR1,SCR2,,TEST B2 - RESULT IS INCORRECT,APRINT)^SALL 1380 031125 036 14 0 00 041147 1381 031126 255 00 0 00 000000 1382 ^ 1383 ^ 1384 1385 000001 IFE REP-4, DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3-5 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0058 1387 ; ************************************************ 1388 1389 1390 ; ************************************************ 1391 1392 000001 REP=REP+1 1393 031127 LOC=. ;ERROR LOOP RETURN ADDRESS 1394 000000 ALEFT=0+IFE REP-3,<1>+IFE REP-4,<1B1> 1395 000001 ARIGHT=0+IFE REP-1,<1>+IFE REP-2,<1B1> 1396 777777 777777 IFE REPP-1, 1398 1399 031127 200 15 0 00 041170 MOVE SCR3,[[EXP ALEFT,ARIGHT],,[EXP 0,0]] ;ADDR FOR APRINT 1400 031130 120 01 0 00 041166 DMOVE AC1,[EXP ALEFT,ARIGHT] ;INIT AUGEND TO FLOATING 1/0 1401 031131 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD FLOATING 1/0 + (0,0) 1402 CHECKA (LOC,B1,ALEFT,ARIGHT)^ 1403 1404 031132 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1405 031133 312 01 0 00 041166 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1406 031134 254 00 0 00 031140 JRST ..0037 ;NO - GO TO ERROR HANDLING 1407 031135 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1408 031136 316 02 0 00 041167 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1409 031137 254 00 0 00 031143 JRST ..0040+1 ;YES - DONT DO ERROR HANDLING 1410 ; EXCEPT FOR ERLOOP 1411 1412 031140 200 14 0 13 000001 ..0037: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1413 031141 200 13 0 13 041166 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1414 031142 ..0040: ERROR (LOC,14,SCR1,SCR2,,TEST B1 - RESULT IS INCORRECT,APRINT)^SALL 1415 031142 036 14 0 00 041136 1416 031143 255 00 0 00 000000 1417 ^ 1418 ^ 1419 1420 031144 LOC=. ;ERROR LOOP RETURN ADDRESS 1421 031144 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1422 031145 200 15 0 00 041171 MOVE SCR3,[[EXP 0,0],,[EXP ALEFT,ARIGHT]] ;ADDR FOR APRINT 1423 031146 114 01 0 00 041166 DADD AC1,[EXP ALEFT,ARIGHT] ;ADD (0,0) + FLOATING 1/0 1424 CHECKA (LOC,B2,ALEFT,ARIGHT)^ 1425 1426 031147 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1427 031150 312 01 0 00 041166 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1428 031151 254 00 0 00 031155 JRST ..0041 ;NO - GO TO ERROR HANDLING 1429 031152 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1430 031153 316 02 0 00 041167 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1431 031154 254 00 0 00 031160 JRST ..0042+1 ;YES - DONT DO ERROR HANDLING 1432 ; EXCEPT FOR ERLOOP 1433 1434 031155 200 14 0 13 000001 ..0041: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1435 031156 200 13 0 13 041166 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1436 031157 ..0042: ERROR (LOC,14,SCR1,SCR2,,TEST B2 - RESULT IS INCORRECT,APRINT)^SALL 1437 031157 036 14 0 00 041147 1438 031160 255 00 0 00 000000 1439 ^ 1440 ^ 1441 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3-6 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0059 1442 IFE REP-4, 1444 ; ************************************************ 1445 1446 1447 ; ************************************************ 1448 1449 000002 REP=REP+1 1450 031161 LOC=. ;ERROR LOOP RETURN ADDRESS 1451 000000 ALEFT=0+IFE REP-3,<1>+IFE REP-4,<1B1> 1452 200000 000000 ARIGHT=0+IFE REP-1,<1>+IFE REP-2,<1B1> 1453 777777 777777 IFE REPP-1, 1455 1456 031161 200 15 0 00 041174 MOVE SCR3,[[EXP ALEFT,ARIGHT],,[EXP 0,0]] ;ADDR FOR APRINT 1457 031162 120 01 0 00 041172 DMOVE AC1,[EXP ALEFT,ARIGHT] ;INIT AUGEND TO FLOATING 1/0 1458 031163 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD FLOATING 1/0 + (0,0) 1459 CHECKA (LOC,B1,ALEFT,ARIGHT)^ 1460 1461 031164 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1462 031165 312 01 0 00 041166 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1463 031166 254 00 0 00 031172 JRST ..0043 ;NO - GO TO ERROR HANDLING 1464 031167 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1465 031170 316 02 0 00 041173 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1466 031171 254 00 0 00 031175 JRST ..0044+1 ;YES - DONT DO ERROR HANDLING 1467 ; EXCEPT FOR ERLOOP 1468 1469 031172 200 14 0 13 000001 ..0043: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1470 031173 200 13 0 13 041172 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1471 031174 ..0044: ERROR (LOC,14,SCR1,SCR2,,TEST B1 - RESULT IS INCORRECT,APRINT)^SALL 1472 031174 036 14 0 00 041136 1473 031175 255 00 0 00 000000 1474 ^ 1475 ^ 1476 1477 031176 LOC=. ;ERROR LOOP RETURN ADDRESS 1478 031176 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1479 031177 200 15 0 00 041175 MOVE SCR3,[[EXP 0,0],,[EXP ALEFT,ARIGHT]] ;ADDR FOR APRINT 1480 031200 114 01 0 00 041172 DADD AC1,[EXP ALEFT,ARIGHT] ;ADD (0,0) + FLOATING 1/0 1481 CHECKA (LOC,B2,ALEFT,ARIGHT)^ 1482 1483 031201 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1484 031202 312 01 0 00 041166 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1485 031203 254 00 0 00 031207 JRST ..0045 ;NO - GO TO ERROR HANDLING 1486 031204 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1487 031205 316 02 0 00 041173 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1488 031206 254 00 0 00 031212 JRST ..0046+1 ;YES - DONT DO ERROR HANDLING 1489 ; EXCEPT FOR ERLOOP 1490 1491 031207 200 14 0 13 000001 ..0045: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1492 031210 200 13 0 13 041172 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1493 031211 ..0046: ERROR (LOC,14,SCR1,SCR2,,TEST B2 - RESULT IS INCORRECT,APRINT)^SALL 1494 031211 036 14 0 00 041147 1495 031212 255 00 0 00 000000 1496 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3-7 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0060 1497 ^ 1498 1499 IFE REP-4, 1501 ; ************************************************ 1502 1503 1504 ; ************************************************ 1505 1506 000003 REP=REP+1 1507 031213 LOC=. ;ERROR LOOP RETURN ADDRESS 1508 000001 ALEFT=0+IFE REP-3,<1>+IFE REP-4,<1B1> 1509 000000 ARIGHT=0+IFE REP-1,<1>+IFE REP-2,<1B1> 1510 777777 777776 IFE REPP-1, 1512 1513 031213 200 15 0 00 041200 MOVE SCR3,[[EXP ALEFT,ARIGHT],,[EXP 0,0]] ;ADDR FOR APRINT 1514 031214 120 01 0 00 041176 DMOVE AC1,[EXP ALEFT,ARIGHT] ;INIT AUGEND TO FLOATING 1/0 1515 031215 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD FLOATING 1/0 + (0,0) 1516 CHECKA (LOC,B1,ALEFT,ARIGHT)^ 1517 1518 031216 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1519 031217 312 01 0 00 041167 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1520 031220 254 00 0 00 031224 JRST ..0047 ;NO - GO TO ERROR HANDLING 1521 031221 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1522 031222 316 02 0 00 041166 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1523 031223 254 00 0 00 031227 JRST ..0050+1 ;YES - DONT DO ERROR HANDLING 1524 ; EXCEPT FOR ERLOOP 1525 1526 031224 200 14 0 13 000001 ..0047: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1527 031225 200 13 0 13 041176 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1528 031226 ..0050: ERROR (LOC,14,SCR1,SCR2,,TEST B1 - RESULT IS INCORRECT,APRINT)^SALL 1529 031226 036 14 0 00 041136 1530 031227 255 00 0 00 000000 1531 ^ 1532 ^ 1533 1534 031230 LOC=. ;ERROR LOOP RETURN ADDRESS 1535 031230 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1536 031231 200 15 0 00 041201 MOVE SCR3,[[EXP 0,0],,[EXP ALEFT,ARIGHT]] ;ADDR FOR APRINT 1537 031232 114 01 0 00 041176 DADD AC1,[EXP ALEFT,ARIGHT] ;ADD (0,0) + FLOATING 1/0 1538 CHECKA (LOC,B2,ALEFT,ARIGHT)^ 1539 1540 031233 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1541 031234 312 01 0 00 041167 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1542 031235 254 00 0 00 031241 JRST ..0051 ;NO - GO TO ERROR HANDLING 1543 031236 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1544 031237 316 02 0 00 041166 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1545 031240 254 00 0 00 031244 JRST ..0052+1 ;YES - DONT DO ERROR HANDLING 1546 ; EXCEPT FOR ERLOOP 1547 1548 031241 200 14 0 13 000001 ..0051: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1549 031242 200 13 0 13 041176 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1550 031243 ..0052: ERROR (LOC,14,SCR1,SCR2,,TEST B2 - RESULT IS INCORRECT,APRINT)^SALL 1551 031243 036 14 0 00 041147 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3-8 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0061 1552 031244 255 00 0 00 000000 1553 ^ 1554 ^ 1555 1556 IFE REP-4, 1558 ; ************************************************ 1559 1560 1561 ; ************************************************ 1562 1563 000004 REP=REP+1 1564 031245 LOC=. ;ERROR LOOP RETURN ADDRESS 1565 200000 000000 ALEFT=0+IFE REP-3,<1>+IFE REP-4,<1B1> 1566 000000 ARIGHT=0+IFE REP-1,<1>+IFE REP-2,<1B1> 1567 577777 777777 IFE REPP-1, 1569 1570 031245 200 15 0 00 041204 MOVE SCR3,[[EXP ALEFT,ARIGHT],,[EXP 0,0]] ;ADDR FOR APRINT 1571 031246 120 01 0 00 041202 DMOVE AC1,[EXP ALEFT,ARIGHT] ;INIT AUGEND TO FLOATING 1/0 1572 031247 114 01 0 00 041022 DADD AC1,[EXP 0,0] ;ADD FLOATING 1/0 + (0,0) 1573 CHECKA (LOC,B1,ALEFT,ARIGHT)^ 1574 1575 031250 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1576 031251 312 01 0 00 041173 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1577 031252 254 00 0 00 031256 JRST ..0053 ;NO - GO TO ERROR HANDLING 1578 031253 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1579 031254 316 02 0 00 041166 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1580 031255 254 00 0 00 031261 JRST ..0054+1 ;YES - DONT DO ERROR HANDLING 1581 ; EXCEPT FOR ERLOOP 1582 1583 031256 200 14 0 13 000001 ..0053: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1584 031257 200 13 0 13 041202 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT 1585 031260 ..0054: ERROR (LOC,14,SCR1,SCR2,,TEST B1 - RESULT IS INCORRECT,APRINT)^SALL 1586 031260 036 14 0 00 041136 1587 031261 255 00 0 00 000000 1588 ^ 1589 ^ 1590 1591 031262 LOC=. ;ERROR LOOP RETURN ADDRESS 1592 031262 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT AUGEND TO (0,0) 1593 031263 200 15 0 00 041205 MOVE SCR3,[[EXP 0,0],,[EXP ALEFT,ARIGHT]] ;ADDR FOR APRINT 1594 031264 114 01 0 00 041202 DADD AC1,[EXP ALEFT,ARIGHT] ;ADD (0,0) + FLOATING 1/0 1595 CHECKA (LOC,B2,ALEFT,ARIGHT)^ 1596 1597 031265 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1598 031266 312 01 0 00 041173 CAME AC1,[ALEFT] ;IS LEFT HALF OF RESULT CORRECT? 1599 031267 254 00 0 00 031273 JRST ..0055 ;NO - GO TO ERROR HANDLING 1600 031270 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1601 031271 316 02 0 00 041166 CAMN AC1+1,[ARIGHT] ;IS RIGHT HALF CORRECT? 1602 031272 254 00 0 00 031276 JRST ..0056+1 ;YES - DONT DO ERROR HANDLING 1603 ; EXCEPT FOR ERLOOP 1604 1605 031273 200 14 0 13 000001 ..0055: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1606 031274 200 13 0 13 041202 MOVE SCR1,[EXP ALEFT,ARIGHT](SCR1) ;GET CORRECT RESULT DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 3-9 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST B SEQ 0062 1607 031275 ..0056: ERROR (LOC,14,SCR1,SCR2,,TEST B2 - RESULT IS INCORRECT,APRINT)^SALL 1608 031275 036 14 0 00 041147 1609 031276 255 00 0 00 000000 1610 ^ 1611 ^ 1612 1613 000001 IFE REP-4, 1615 ; ************************************************ 1616 1617 031277 AENDB: DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 4 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST C SEQ 0063 1618 SUBTTL DADD - TEST C 1619 1620 ; ********************************************************************** 1621 ;DADD - TEST C 1622 ;* 1623 ;* FLOATING 1 + FLOATING 1 = FLOATING 1 SHIFTED LEFT ONE BIT AT 1624 ;* A TIME ACROSS THE DOUBLEWORD EXCLUDING SIGN BITS AND THE MOST 1625 ;* SIGNIFICANT BIT (WE'RE NOT TESTING OVERFLOW CONDITIONS). THIS 1626 ;* TEST VERIFIES THE ABILITY OF THE DADD TO HANDLE A SINGLE CARRY 1627 ;* PROPAGATED 1 BIT WHETHER IT CROSSES A WORD BOUNDARY OR NOT. 1628 ; ********************************************************************** 1629 1630 ; ********************************************************************** 1631 ;DADD FLOATING 1 + FLOATING 1 = FLOATING 1 * 2 1632 ; ********************************************************************** 1633 1634 031277 400 11 0 00 000000 SETZ CNT, ;COUNT FROM 0 TO 68 1635 031300 120 01 0 00 041126 DMOVE AC1,[EXP 0,1] ;SET UP OPERANDS - AUGEND,ADDEND - EACH 1636 ; WILL BE THE DOUBLEWORD - AC1,AC1+1 1637 031301 137 11 0 00 031333 ALOOP: DPB CNT,ASHIFT ;SET UP ASHC TO CALCULATE OPERANDS 1638 031302 256 00 0 00 031333 XCT ASHIFT ;DO THE SHIFT - RESULT IS A DOUBLEWORD 1639 ; FLOATING 1 IN AC1,AC1+1 1640 031303 124 01 0 00 031327 DMOVEM AC1,ADATA ;SAVE THE ARGUMENTS FOR ADDL PRINT 1641 031304 200 15 0 00 041206 MOVE SCR3,[ADATA,,ADATA] ; ROUTINE & PUT INTO SCR3 1642 031305 244 01 0 00 000001 ASHC AC1,1 ;CALCULATED EXPECTED RESULT 1643 031306 124 01 0 00 031331 DMOVEM AC1,TEMP ;SAVE RESULTS 1644 031307 120 01 0 00 031327 DMOVE AC1,ADATA ;GET BACK ORIGINAL AUGEND 1645 1646 031310 114 01 0 00 000001 DADD AC1,AC1 ;ADD FLOATING 1 + FLOATING 1 1647 1648 031311 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1649 031312 312 01 0 00 031331 CAME AC1,TEMP ;RESULT - AC1 SHOULD = TEMP 1650 031313 254 00 0 00 031317 JRST AERR ;NOT CORRECT - DO ERROR HANDLING 1651 031314 201 13 0 00 000001 MOVEI SCR1,1 ;POINTER ADJUSTED TO NEXT WORD 1652 031315 316 02 0 00 031332 CAMN AC1+1,TEMP+1 ;RESULT - AC1+1 SHOULD = TEMP+1 1653 031316 254 00 0 00 031322 JRST AERRC+1 ;NO ERRORS - DO ERLOOP ANYWAY 1654 1655 031317 200 14 0 13 031331 AERR: MOVE SCR2,TEMP(SCR1) ;GET CORRECT DATA 1656 031320 200 13 0 13 000001 MOVE SCR1,AC1(SCR1) ;GET ACTUAL DATA 1657 031321 AERRC: ERROR (LOC,14,SCR2,SCR1,,TEST C - RESULT INCORRECT,APRINT)^SALL 1658 031321 036 14 0 00 041214 1659 031322 255 00 0 00 000000 1660 ^ 1661 1662 031323 350 00 0 00 000011 AOS CNT ;INCREMENT SHIFT COUNT 1663 031324 302 11 0 00 000105 CAIE CNT,^D69 ;ARE WE DONE WITH 69 ITERATIONS? 1664 031325 254 00 0 00 031301 JRST ALOOP ; NO - REPEAT THIS TEST 1665 031326 254 00 0 00 031335 JRST ADADDI+1 ; YES - GO ON TO NEXT TEST 1666 1667 031327 ADATA: BLOCK 2 ;DADD OPERANDS 1668 031331 TEMP: BLOCK 2 ;TEMPORARY STORAGE FOR RESULT 1669 031333 43 10 0 00 031334 ASHIFT: POINT 8,ADADDI,0 ;FOR CALCULATING OPERANDS 1670 031334 244 01 0 00 000000 ADADDI: ASHC AC1,0 ;CALCULATE DOUBLEWORD FLOATING 1 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 5 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST D SEQ 0064 1671 SUBTTL DADD - TEST D 1672 1673 ; ********************************************************************** 1674 ;*DADD - TEST D 1675 ;* 1676 ;* 0,-1 + 0,1 = 1,0 ADDITIONAL TEST TO SEE THAT A 1677 ;* 0,1 + 0,-1 = 1,0 CARRY IS PROPAGATED ACROSS WORD 1678 ;* BOUNDARIES. 1679 ; ********************************************************************** 1680 1681 ; ********************************************************************** 1682 ; ---------- DADD (0,-1) + (0,1) = (1,0) ---------- 1683 ; ********************************************************************** 1684 1685 031335 200 15 0 00 041221 ATSTD1: MOVE SCR3,[[EXP 0,-1],,[EXP 0,1]] ;ADDR FOR APRINT 1686 031336 120 01 0 00 041217 DMOVE AC1,[EXP 0,-1] ;INIT AUGEND TO (0,-1) 1687 031337 114 01 0 00 041126 DADD AC1,[EXP 0,1] ;ADD (0,-1) + (0,1) 1688 CHECKA (ATSTD1,D1,1,0)^ 1689 1690 031340 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1691 031341 312 01 0 00 041127 CAME AC1,[1] ;IS LEFT HALF OF RESULT CORRECT? 1692 031342 254 00 0 00 031346 JRST ..0057 ;NO - GO TO ERROR HANDLING 1693 031343 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1694 031344 316 02 0 00 041020 CAMN AC1+1,[0] ;IS RIGHT HALF CORRECT? 1695 031345 254 00 0 00 031351 JRST ..0060+1 ;YES - DONT DO ERROR HANDLING 1696 ; EXCEPT FOR ERLOOP 1697 1698 031346 200 14 0 13 000001 ..0057: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1699 031347 200 13 0 13 041156 MOVE SCR1,[EXP 1,0](SCR1) ;GET CORRECT RESULT 1700 031350 ..0060: ERROR (ATSTD1,14,SCR1,SCR2,,TEST D1 - RESULT IS INCORRECT,APRINT)^SALL 1701 031350 036 14 0 00 041227 1702 031351 255 00 0 00 000000 1703 ^ 1704 ^ 1705 1706 ; ********************************************************************** 1707 ; ---------- DADD (0,1) + (0,-1) = (1,0) ---------- 1708 ; ********************************************************************** 1709 1710 031352 200 15 0 00 041232 ATSTD2: MOVE SCR3,[[EXP 0,1],,[EXP 0,-1]] ;ADDR FOR APRINT 1711 031353 120 01 0 00 041126 DMOVE AC1,[EXP 0,1] ;INIT AUGEND TO (0,1) 1712 031354 114 01 0 00 041217 DADD AC1,[EXP 0,-1] ;ADD (0,1) + (0,-1) 1713 CHECKA (ATSTD2,D2,1,0)^ 1714 1715 031355 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1716 031356 312 01 0 00 041127 CAME AC1,[1] ;IS LEFT HALF OF RESULT CORRECT? 1717 031357 254 00 0 00 031363 JRST ..0061 ;NO - GO TO ERROR HANDLING 1718 031360 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1719 031361 316 02 0 00 041020 CAMN AC1+1,[0] ;IS RIGHT HALF CORRECT? 1720 031362 254 00 0 00 031366 JRST ..0062+1 ;YES - DONT DO ERROR HANDLING 1721 ; EXCEPT FOR ERLOOP 1722 1723 031363 200 14 0 13 000001 ..0061: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1724 031364 200 13 0 13 041156 MOVE SCR1,[EXP 1,0](SCR1) ;GET CORRECT RESULT 1725 031365 ..0062: ERROR (ATSTD2,14,SCR1,SCR2,,TEST D2 - RESULT IS INCORRECT,APRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 5-1 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST D SEQ 0065 1726 031365 036 14 0 00 041240 1727 031366 255 00 0 00 000000 1728 ^ 1729 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 6 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST E SEQ 0066 1730 SUBTTL DADD - TEST E 1731 1732 ; ********************************************************************** 1733 ;*DADD - TEST E 1734 ;* 1735 ;* FLOATING 0 + 1 = 11111000.. 1736 ;* 1 + FLOATING 0 = 11111000.. 1737 ; ********************************************************************** 1738 1739 ; ********************************************************************** 1740 ;* THE NEXT 6 TESTS VERIFY THAT A CARRY IS PROPERLY PROPAGATED 1741 ;* DOWN A WORD. A 1 IS ADDED TO A FLOATING 0 CAUSING THE 1742 ;* CARRY TO RIPPLE DOWN THE WORD. THE RESULT IS VERIFIED AS 1743 ;* 1111..110000.... THE FLOATING 0 IS LOCATED IN BITS 34,36, 1744 ;* 71 FOR NEGATIVE NUMBERS AND BITS 33,36,70 FOR POSITIVE 1745 ;* NUMBERS. CARRY FLAGS ARE VERIFIED IN ADDITION. 1746 ; ********************************************************************** 1747 1748 031576 CNUM=ACONE-4 1749 1750 REPEAT 6,< 1751 ; ************************************************ 1752 1753 LOC=. 1754 CNUM=CNUM+4 1755 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0 1756 JFCL 17,.+1 ;CLEAR PC FLAGS 1757 HRLI SCR3,CNUM ;SCR3 - ADDRESS OF OPERANDS FOR 1758 HRRI SCR3,[EXP 0,1] ; ADDL ERROR PRINT ROUTINE 1759 DADD AC1,[EXP 0,1] ;ADD - FLOATING 0 + 1 1760 PCSAVE 1761 CHECKB (LOC,E,CNUM+2) 1762 TFLAG ([0],E) 1763 ; ************************************************ 1764 > 1765 1766 ; ************************************************ 1767 1768 031367 LOC=. 1769 031602 CNUM=CNUM+4 1770 031367 120 01 0 00 031602 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0 1771 031370 255 17 0 00 031371 JFCL 17,.+1 ;CLEAR PC FLAGS 1772 031371 505 15 0 00 031602 HRLI SCR3,CNUM ;SCR3 - ADDRESS OF OPERANDS FOR 1773 031372 541 15 0 00 041126 HRRI SCR3,[EXP 0,1] ; ADDL ERROR PRINT ROUTINE 1774 031373 114 01 0 00 041126 DADD AC1,[EXP 0,1] ;ADD - FLOATING 0 + 1 1775 PCSAVE^ 1776 031374 264 00 0 00 031375 JSR .+1 ;STORE PC 1777 031375 FLAGL=. ;LOCATION OF PC 1778 031375 000000 000000 0 ;PC 1779 ^ 1780 CHECKB (LOC,E,CNUM+2)^ 1781 1782 031376 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1783 031377 312 01 0 00 031604 CAME AC1,CNUM+2 ;IS LEFT HALF OF RESULT CORRECT? 1784 031400 254 00 0 00 031404 JRST ..0063 ;NO - GO TO ERROR HANDLING DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 6-1 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST E SEQ 0067 1785 031401 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1786 031402 316 02 0 00 031605 CAMN AC1+1,CNUM+2+1 ;IS RIGHT HALF CORRECT? 1787 031403 254 00 0 00 031407 JRST ..0064+1 ;YES - DONT DO ERROR HANDLING 1788 ; EXCEPT FOR ERLOOP 1789 1790 031404 200 14 0 13 000001 ..0063: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1791 031405 200 13 0 13 031604 MOVE SCR1,CNUM+2(SCR1) ;GET CORRECT WORD OF RESULT 1792 031406 ..0064: ERROR (LOC,14,SCR1,SCR2,,TEST E - RESULT IS INCORRECT,APRINT)^SALL 1793 031406 036 14 0 00 041250 1794 031407 255 00 0 00 000000 1795 ^ 1796 ^ 1797 TFLAG ([0],E)^ 1798 1799 031410 200 13 0 00 031375 MOVE SCR1,FLAGL ;GET FLAGS 1800 031411 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 1801 031412 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 1802 031413 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 1803 ERROR (LOC,13,SCR2,FLAGL,,TEST E - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 1804 031414 036 13 0 00 041262 1805 031415 255 00 0 00 000000 1806 ^ 1807 ^ 1808 ; ************************************************ 1809 1810 1811 ; ************************************************ 1812 1813 031416 LOC=. 1814 031606 CNUM=CNUM+4 1815 031416 120 01 0 00 031606 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0 1816 031417 255 17 0 00 031420 JFCL 17,.+1 ;CLEAR PC FLAGS 1817 031420 505 15 0 00 031606 HRLI SCR3,CNUM ;SCR3 - ADDRESS OF OPERANDS FOR 1818 031421 541 15 0 00 041126 HRRI SCR3,[EXP 0,1] ; ADDL ERROR PRINT ROUTINE 1819 031422 114 01 0 00 041126 DADD AC1,[EXP 0,1] ;ADD - FLOATING 0 + 1 1820 PCSAVE^ 1821 031423 264 00 0 00 031424 JSR .+1 ;STORE PC 1822 031424 FLAGL=. ;LOCATION OF PC 1823 031424 000000 000000 0 ;PC 1824 ^ 1825 CHECKB (LOC,E,CNUM+2)^ 1826 1827 031425 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1828 031426 312 01 0 00 031610 CAME AC1,CNUM+2 ;IS LEFT HALF OF RESULT CORRECT? 1829 031427 254 00 0 00 031433 JRST ..0065 ;NO - GO TO ERROR HANDLING 1830 031430 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1831 031431 316 02 0 00 031611 CAMN AC1+1,CNUM+2+1 ;IS RIGHT HALF CORRECT? 1832 031432 254 00 0 00 031436 JRST ..0066+1 ;YES - DONT DO ERROR HANDLING 1833 ; EXCEPT FOR ERLOOP 1834 1835 031433 200 14 0 13 000001 ..0065: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1836 031434 200 13 0 13 031610 MOVE SCR1,CNUM+2(SCR1) ;GET CORRECT WORD OF RESULT 1837 031435 ..0066: ERROR (LOC,14,SCR1,SCR2,,TEST E - RESULT IS INCORRECT,APRINT)^SALL 1838 031435 036 14 0 00 041250 1839 031436 255 00 0 00 000000 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 6-2 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST E SEQ 0068 1840 ^ 1841 ^ 1842 TFLAG ([0],E)^ 1843 1844 031437 200 13 0 00 031424 MOVE SCR1,FLAGL ;GET FLAGS 1845 031440 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 1846 031441 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 1847 031442 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 1848 ERROR (LOC,13,SCR2,FLAGL,,TEST E - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 1849 031443 036 13 0 00 041265 1850 031444 255 00 0 00 000000 1851 ^ 1852 ^ 1853 ; ************************************************ 1854 1855 1856 ; ************************************************ 1857 1858 031445 LOC=. 1859 031612 CNUM=CNUM+4 1860 031445 120 01 0 00 031612 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0 1861 031446 255 17 0 00 031447 JFCL 17,.+1 ;CLEAR PC FLAGS 1862 031447 505 15 0 00 031612 HRLI SCR3,CNUM ;SCR3 - ADDRESS OF OPERANDS FOR 1863 031450 541 15 0 00 041126 HRRI SCR3,[EXP 0,1] ; ADDL ERROR PRINT ROUTINE 1864 031451 114 01 0 00 041126 DADD AC1,[EXP 0,1] ;ADD - FLOATING 0 + 1 1865 PCSAVE^ 1866 031452 264 00 0 00 031453 JSR .+1 ;STORE PC 1867 031453 FLAGL=. ;LOCATION OF PC 1868 031453 000000 000000 0 ;PC 1869 ^ 1870 CHECKB (LOC,E,CNUM+2)^ 1871 1872 031454 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1873 031455 312 01 0 00 031614 CAME AC1,CNUM+2 ;IS LEFT HALF OF RESULT CORRECT? 1874 031456 254 00 0 00 031462 JRST ..0067 ;NO - GO TO ERROR HANDLING 1875 031457 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1876 031460 316 02 0 00 031615 CAMN AC1+1,CNUM+2+1 ;IS RIGHT HALF CORRECT? 1877 031461 254 00 0 00 031465 JRST ..0070+1 ;YES - DONT DO ERROR HANDLING 1878 ; EXCEPT FOR ERLOOP 1879 1880 031462 200 14 0 13 000001 ..0067: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1881 031463 200 13 0 13 031614 MOVE SCR1,CNUM+2(SCR1) ;GET CORRECT WORD OF RESULT 1882 031464 ..0070: ERROR (LOC,14,SCR1,SCR2,,TEST E - RESULT IS INCORRECT,APRINT)^SALL 1883 031464 036 14 0 00 041250 1884 031465 255 00 0 00 000000 1885 ^ 1886 ^ 1887 TFLAG ([0],E)^ 1888 1889 031466 200 13 0 00 031453 MOVE SCR1,FLAGL ;GET FLAGS 1890 031467 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 1891 031470 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 1892 031471 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 1893 ERROR (LOC,13,SCR2,FLAGL,,TEST E - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 1894 031472 036 13 0 00 041270 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 6-3 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST E SEQ 0069 1895 031473 255 00 0 00 000000 1896 ^ 1897 ^ 1898 ; ************************************************ 1899 1900 1901 ; ************************************************ 1902 1903 031474 LOC=. 1904 031616 CNUM=CNUM+4 1905 031474 120 01 0 00 031616 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0 1906 031475 255 17 0 00 031476 JFCL 17,.+1 ;CLEAR PC FLAGS 1907 031476 505 15 0 00 031616 HRLI SCR3,CNUM ;SCR3 - ADDRESS OF OPERANDS FOR 1908 031477 541 15 0 00 041126 HRRI SCR3,[EXP 0,1] ; ADDL ERROR PRINT ROUTINE 1909 031500 114 01 0 00 041126 DADD AC1,[EXP 0,1] ;ADD - FLOATING 0 + 1 1910 PCSAVE^ 1911 031501 264 00 0 00 031502 JSR .+1 ;STORE PC 1912 031502 FLAGL=. ;LOCATION OF PC 1913 031502 000000 000000 0 ;PC 1914 ^ 1915 CHECKB (LOC,E,CNUM+2)^ 1916 1917 031503 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1918 031504 312 01 0 00 031620 CAME AC1,CNUM+2 ;IS LEFT HALF OF RESULT CORRECT? 1919 031505 254 00 0 00 031511 JRST ..0071 ;NO - GO TO ERROR HANDLING 1920 031506 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1921 031507 316 02 0 00 031621 CAMN AC1+1,CNUM+2+1 ;IS RIGHT HALF CORRECT? 1922 031510 254 00 0 00 031514 JRST ..0072+1 ;YES - DONT DO ERROR HANDLING 1923 ; EXCEPT FOR ERLOOP 1924 1925 031511 200 14 0 13 000001 ..0071: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1926 031512 200 13 0 13 031620 MOVE SCR1,CNUM+2(SCR1) ;GET CORRECT WORD OF RESULT 1927 031513 ..0072: ERROR (LOC,14,SCR1,SCR2,,TEST E - RESULT IS INCORRECT,APRINT)^SALL 1928 031513 036 14 0 00 041250 1929 031514 255 00 0 00 000000 1930 ^ 1931 ^ 1932 TFLAG ([0],E)^ 1933 1934 031515 200 13 0 00 031502 MOVE SCR1,FLAGL ;GET FLAGS 1935 031516 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 1936 031517 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 1937 031520 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 1938 ERROR (LOC,13,SCR2,FLAGL,,TEST E - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 1939 031521 036 13 0 00 041273 1940 031522 255 00 0 00 000000 1941 ^ 1942 ^ 1943 ; ************************************************ 1944 1945 1946 ; ************************************************ 1947 1948 031523 LOC=. 1949 031622 CNUM=CNUM+4 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 6-4 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST E SEQ 0070 1950 031523 120 01 0 00 031622 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0 1951 031524 255 17 0 00 031525 JFCL 17,.+1 ;CLEAR PC FLAGS 1952 031525 505 15 0 00 031622 HRLI SCR3,CNUM ;SCR3 - ADDRESS OF OPERANDS FOR 1953 031526 541 15 0 00 041126 HRRI SCR3,[EXP 0,1] ; ADDL ERROR PRINT ROUTINE 1954 031527 114 01 0 00 041126 DADD AC1,[EXP 0,1] ;ADD - FLOATING 0 + 1 1955 PCSAVE^ 1956 031530 264 00 0 00 031531 JSR .+1 ;STORE PC 1957 031531 FLAGL=. ;LOCATION OF PC 1958 031531 000000 000000 0 ;PC 1959 ^ 1960 CHECKB (LOC,E,CNUM+2)^ 1961 1962 031532 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 1963 031533 312 01 0 00 031624 CAME AC1,CNUM+2 ;IS LEFT HALF OF RESULT CORRECT? 1964 031534 254 00 0 00 031540 JRST ..0073 ;NO - GO TO ERROR HANDLING 1965 031535 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 1966 031536 316 02 0 00 031625 CAMN AC1+1,CNUM+2+1 ;IS RIGHT HALF CORRECT? 1967 031537 254 00 0 00 031543 JRST ..0074+1 ;YES - DONT DO ERROR HANDLING 1968 ; EXCEPT FOR ERLOOP 1969 1970 031540 200 14 0 13 000001 ..0073: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 1971 031541 200 13 0 13 031624 MOVE SCR1,CNUM+2(SCR1) ;GET CORRECT WORD OF RESULT 1972 031542 ..0074: ERROR (LOC,14,SCR1,SCR2,,TEST E - RESULT IS INCORRECT,APRINT)^SALL 1973 031542 036 14 0 00 041250 1974 031543 255 00 0 00 000000 1975 ^ 1976 ^ 1977 TFLAG ([0],E)^ 1978 1979 031544 200 13 0 00 031531 MOVE SCR1,FLAGL ;GET FLAGS 1980 031545 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 1981 031546 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 1982 031547 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 1983 ERROR (LOC,13,SCR2,FLAGL,,TEST E - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 1984 031550 036 13 0 00 041276 1985 031551 255 00 0 00 000000 1986 ^ 1987 ^ 1988 ; ************************************************ 1989 1990 1991 ; ************************************************ 1992 1993 031552 LOC=. 1994 031626 CNUM=CNUM+4 1995 031552 120 01 0 00 031626 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0 1996 031553 255 17 0 00 031554 JFCL 17,.+1 ;CLEAR PC FLAGS 1997 031554 505 15 0 00 031626 HRLI SCR3,CNUM ;SCR3 - ADDRESS OF OPERANDS FOR 1998 031555 541 15 0 00 041126 HRRI SCR3,[EXP 0,1] ; ADDL ERROR PRINT ROUTINE 1999 031556 114 01 0 00 041126 DADD AC1,[EXP 0,1] ;ADD - FLOATING 0 + 1 2000 PCSAVE^ 2001 031557 264 00 0 00 031560 JSR .+1 ;STORE PC 2002 031560 FLAGL=. ;LOCATION OF PC 2003 031560 000000 000000 0 ;PC 2004 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 6-5 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST E SEQ 0071 2005 CHECKB (LOC,E,CNUM+2)^ 2006 2007 031561 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2008 031562 312 01 0 00 031630 CAME AC1,CNUM+2 ;IS LEFT HALF OF RESULT CORRECT? 2009 031563 254 00 0 00 031567 JRST ..0075 ;NO - GO TO ERROR HANDLING 2010 031564 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2011 031565 316 02 0 00 031631 CAMN AC1+1,CNUM+2+1 ;IS RIGHT HALF CORRECT? 2012 031566 254 00 0 00 031572 JRST ..0076+1 ;YES - DONT DO ERROR HANDLING 2013 ; EXCEPT FOR ERLOOP 2014 2015 031567 200 14 0 13 000001 ..0075: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2016 031570 200 13 0 13 031630 MOVE SCR1,CNUM+2(SCR1) ;GET CORRECT WORD OF RESULT 2017 031571 ..0076: ERROR (LOC,14,SCR1,SCR2,,TEST E - RESULT IS INCORRECT,APRINT)^SALL 2018 031571 036 14 0 00 041250 2019 031572 255 00 0 00 000000 2020 ^ 2021 ^ 2022 TFLAG ([0],E)^ 2023 2024 031573 200 13 0 00 031560 MOVE SCR1,FLAGL ;GET FLAGS 2025 031574 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2026 031575 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2027 031576 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2028 ERROR (LOC,13,SCR2,FLAGL,,TEST E - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2029 031577 036 13 0 00 041301 2030 031600 255 00 0 00 000000 2031 ^ 2032 ^ 2033 ; ************************************************ 2034 2035 031601 254 00 0 00 031632 JRST AENDD ;SKIP OVER DATA DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 7 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST E SEQ 0072 2036 2037 031602 777777 777777 ACONE: EXP -1,577777777777,-1,^B11B1 2038 031603 577777 777777 2039 031604 777777 777777 2040 031605 600000 000000 2041 031606 777777 777776 EXP -2,-1,-1,1B0 2042 031607 777777 777777 2043 031610 777777 777777 2044 031611 400000 000000 2045 031612 577777 777777 EXP 577777777777,-1,^B11B1,1B0 2046 031613 777777 777777 2047 031614 600000 000000 2048 031615 400000 000000 2049 031616 377777 777777 EXP 377777777777,177777777777,377777777777,1B1 2050 031617 177777 777777 2051 031620 377777 777777 2052 031621 200000 000000 2053 031622 377777 777776 EXP 377777777776,377777777777,377777777777,0 2054 031623 377777 777777 2055 031624 377777 777777 2056 031625 000000 000000 2057 031626 177777 777777 EXP 177777777777,377777777777,1B1,0 2058 031627 377777 777777 2059 031630 200000 000000 2060 031631 000000 000000 2061 031632 AENDD: DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0073 2062 SUBTTL DADD - TEST F 2063 2064 ; ********************************************************************** 2065 ;*DADD - TEST F 2066 ;* 2067 ;* THE FOLLOWING TESTS VERIFY THAT THE DADD INSTRUCTION HANDLES 2068 ;* THE SIGN OF THE RESULT PROPERLY (COPYING THE SIGN INTO THE 2069 ;* HIGH ORDER BIT OF EACH WORD OF THE DOUBLEWORD RESULT. THE 2070 ;* TESTS ADD VARIOUS COMBINATIONS OF INCONSISTENT SIGNS IN THE 2071 ;* ADDEND AND AUGEND AND VERIFY THAT THE SIGNS OF THE RESULT 2072 ;* ARE CORRECT. 2073 ;* 2074 ;* THERE ARE 5 SETS OF TEST: (1) 0 + P/N = P/N 2075 ;* (2) N + N = N 2076 ;* (3) P + P = P 2077 ;* (4) N + P = N 2078 ;* (5) N + P = P 2079 ;* WHERE N-NEGATIVE NUMBER 2080 ;* P-POSITIVE NUMBER 2081 ; ********************************************************************** 2082 2083 ; ********************************************************************** 2084 ; ---------- DADD - TEST F-1: 0 + P/N = P/N ---------- 2085 ; ********************************************************************** 2086 2087 033053 CNUM=ACONF1-4 2088 000000 REP=0 ;RESULT FOR FIRST 3 TESTS 2089 2090 REPEAT 6,< 2091 ; ************************************************ 2092 2093 LOC=. ;ERROR RETURN ADDRESS 2094 REP=REP+1 ;REP - REPETITION COUNT 2095 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2096 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR FOR ADDL ERROR PRINT 2097 DMOVE AC1,CNUM ;INIT AUGEND 2098 JFCL 17,.+1 ;CLEAR PC FLAGS 2099 DADD AC1,CNUM+2 ;ADD N + P = 0,1 2100 PCSAVE 2101 RLEFT=0-IFG REP-3,<1> ;LEFT WORD OF RESULT 2102 RRIGHT=1-IFG REP-3,<2> ;RIGHT WORD OF RESULT 2103 CHECKA (LOC,F1,RLEFT,RRIGHT) 2104 TFLAG ([0],F1) 2105 ; ************************************************ 2106 > 2107 2108 ; ************************************************ 2109 2110 031632 LOC=. ;ERROR RETURN ADDRESS 2111 000001 REP=REP+1 ;REP - REPETITION COUNT 2112 033057 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2113 031632 200 15 0 00 041304 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR FOR ADDL ERROR PRINT 2114 031633 120 01 0 00 033057 DMOVE AC1,CNUM ;INIT AUGEND 2115 031634 255 17 0 00 031635 JFCL 17,.+1 ;CLEAR PC FLAGS 2116 031635 114 01 0 00 033061 DADD AC1,CNUM+2 ;ADD N + P = 0,1 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-1 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0074 2117 PCSAVE^ 2118 031636 264 00 0 00 031637 JSR .+1 ;STORE PC 2119 031637 FLAGL=. ;LOCATION OF PC 2120 031637 000000 000000 0 ;PC 2121 ^ 2122 000000 RLEFT=0-IFG REP-3,<1> ;LEFT WORD OF RESULT 2123 000001 RRIGHT=1-IFG REP-3,<2> ;RIGHT WORD OF RESULT 2124 CHECKA (LOC,F1,RLEFT,RRIGHT)^ 2125 2126 031640 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2127 031641 312 01 0 00 041020 CAME AC1,[RLEFT] ;IS LEFT HALF OF RESULT CORRECT? 2128 031642 254 00 0 00 031646 JRST ..0077 ;NO - GO TO ERROR HANDLING 2129 031643 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2130 031644 316 02 0 00 041127 CAMN AC1+1,[RRIGHT] ;IS RIGHT HALF CORRECT? 2131 031645 254 00 0 00 031651 JRST ..0100+1 ;YES - DONT DO ERROR HANDLING 2132 ; EXCEPT FOR ERLOOP 2133 2134 031646 200 14 0 13 000001 ..0077: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2135 031647 200 13 0 13 041126 MOVE SCR1,[EXP RLEFT,RRIGHT](SCR1) ;GET CORRECT RESULT 2136 031650 ..0100: ERROR (LOC,14,SCR1,SCR2,,TEST F1 - RESULT IS INCORRECT,APRINT)^SALL 2137 031650 036 14 0 00 041312 2138 031651 255 00 0 00 000000 2139 ^ 2140 ^ 2141 TFLAG ([0],F1)^ 2142 2143 031652 200 13 0 00 031637 MOVE SCR1,FLAGL ;GET FLAGS 2144 031653 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2145 031654 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2146 031655 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2147 ERROR (LOC,13,SCR2,FLAGL,,TEST F1 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2148 2149 031656 036 13 0 00 041325 2150 031657 255 00 0 00 000000 2151 ^ 2152 ^ 2153 ; ************************************************ 2154 2155 2156 ; ************************************************ 2157 2158 031660 LOC=. ;ERROR RETURN ADDRESS 2159 000002 REP=REP+1 ;REP - REPETITION COUNT 2160 033063 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2161 031660 200 15 0 00 041330 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR FOR ADDL ERROR PRINT 2162 031661 120 01 0 00 033063 DMOVE AC1,CNUM ;INIT AUGEND 2163 031662 255 17 0 00 031663 JFCL 17,.+1 ;CLEAR PC FLAGS 2164 031663 114 01 0 00 033065 DADD AC1,CNUM+2 ;ADD N + P = 0,1 2165 PCSAVE^ 2166 031664 264 00 0 00 031665 JSR .+1 ;STORE PC 2167 031665 FLAGL=. ;LOCATION OF PC 2168 031665 000000 000000 0 ;PC 2169 ^ 2170 000000 RLEFT=0-IFG REP-3,<1> ;LEFT WORD OF RESULT 2171 000001 RRIGHT=1-IFG REP-3,<2> ;RIGHT WORD OF RESULT DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-2 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0075 2172 CHECKA (LOC,F1,RLEFT,RRIGHT)^ 2173 2174 031666 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2175 031667 312 01 0 00 041020 CAME AC1,[RLEFT] ;IS LEFT HALF OF RESULT CORRECT? 2176 031670 254 00 0 00 031674 JRST ..0101 ;NO - GO TO ERROR HANDLING 2177 031671 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2178 031672 316 02 0 00 041127 CAMN AC1+1,[RRIGHT] ;IS RIGHT HALF CORRECT? 2179 031673 254 00 0 00 031677 JRST ..0102+1 ;YES - DONT DO ERROR HANDLING 2180 ; EXCEPT FOR ERLOOP 2181 2182 031674 200 14 0 13 000001 ..0101: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2183 031675 200 13 0 13 041126 MOVE SCR1,[EXP RLEFT,RRIGHT](SCR1) ;GET CORRECT RESULT 2184 031676 ..0102: ERROR (LOC,14,SCR1,SCR2,,TEST F1 - RESULT IS INCORRECT,APRINT)^SALL 2185 031676 036 14 0 00 041312 2186 031677 255 00 0 00 000000 2187 ^ 2188 ^ 2189 TFLAG ([0],F1)^ 2190 2191 031700 200 13 0 00 031665 MOVE SCR1,FLAGL ;GET FLAGS 2192 031701 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2193 031702 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2194 031703 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2195 ERROR (LOC,13,SCR2,FLAGL,,TEST F1 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2196 2197 031704 036 13 0 00 041331 2198 031705 255 00 0 00 000000 2199 ^ 2200 ^ 2201 ; ************************************************ 2202 2203 2204 ; ************************************************ 2205 2206 031706 LOC=. ;ERROR RETURN ADDRESS 2207 000003 REP=REP+1 ;REP - REPETITION COUNT 2208 033067 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2209 031706 200 15 0 00 041334 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR FOR ADDL ERROR PRINT 2210 031707 120 01 0 00 033067 DMOVE AC1,CNUM ;INIT AUGEND 2211 031710 255 17 0 00 031711 JFCL 17,.+1 ;CLEAR PC FLAGS 2212 031711 114 01 0 00 033071 DADD AC1,CNUM+2 ;ADD N + P = 0,1 2213 PCSAVE^ 2214 031712 264 00 0 00 031713 JSR .+1 ;STORE PC 2215 031713 FLAGL=. ;LOCATION OF PC 2216 031713 000000 000000 0 ;PC 2217 ^ 2218 000000 RLEFT=0-IFG REP-3,<1> ;LEFT WORD OF RESULT 2219 000001 RRIGHT=1-IFG REP-3,<2> ;RIGHT WORD OF RESULT 2220 CHECKA (LOC,F1,RLEFT,RRIGHT)^ 2221 2222 031714 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2223 031715 312 01 0 00 041020 CAME AC1,[RLEFT] ;IS LEFT HALF OF RESULT CORRECT? 2224 031716 254 00 0 00 031722 JRST ..0103 ;NO - GO TO ERROR HANDLING 2225 031717 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2226 031720 316 02 0 00 041127 CAMN AC1+1,[RRIGHT] ;IS RIGHT HALF CORRECT? DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-3 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0076 2227 031721 254 00 0 00 031725 JRST ..0104+1 ;YES - DONT DO ERROR HANDLING 2228 ; EXCEPT FOR ERLOOP 2229 2230 031722 200 14 0 13 000001 ..0103: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2231 031723 200 13 0 13 041126 MOVE SCR1,[EXP RLEFT,RRIGHT](SCR1) ;GET CORRECT RESULT 2232 031724 ..0104: ERROR (LOC,14,SCR1,SCR2,,TEST F1 - RESULT IS INCORRECT,APRINT)^SALL 2233 031724 036 14 0 00 041312 2234 031725 255 00 0 00 000000 2235 ^ 2236 ^ 2237 TFLAG ([0],F1)^ 2238 2239 031726 200 13 0 00 031713 MOVE SCR1,FLAGL ;GET FLAGS 2240 031727 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2241 031730 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2242 031731 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2243 ERROR (LOC,13,SCR2,FLAGL,,TEST F1 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2244 2245 031732 036 13 0 00 041335 2246 031733 255 00 0 00 000000 2247 ^ 2248 ^ 2249 ; ************************************************ 2250 2251 2252 ; ************************************************ 2253 2254 031734 LOC=. ;ERROR RETURN ADDRESS 2255 000004 REP=REP+1 ;REP - REPETITION COUNT 2256 033073 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2257 031734 200 15 0 00 041340 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR FOR ADDL ERROR PRINT 2258 031735 120 01 0 00 033073 DMOVE AC1,CNUM ;INIT AUGEND 2259 031736 255 17 0 00 031737 JFCL 17,.+1 ;CLEAR PC FLAGS 2260 031737 114 01 0 00 033075 DADD AC1,CNUM+2 ;ADD N + P = 0,1 2261 PCSAVE^ 2262 031740 264 00 0 00 031741 JSR .+1 ;STORE PC 2263 031741 FLAGL=. ;LOCATION OF PC 2264 031741 000000 000000 0 ;PC 2265 ^ 2266 777777 777777 RLEFT=0-IFG REP-3,<1> ;LEFT WORD OF RESULT 2267 777777 777777 RRIGHT=1-IFG REP-3,<2> ;RIGHT WORD OF RESULT 2268 CHECKA (LOC,F1,RLEFT,RRIGHT)^ 2269 2270 031742 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2271 031743 312 01 0 00 041166 CAME AC1,[RLEFT] ;IS LEFT HALF OF RESULT CORRECT? 2272 031744 254 00 0 00 031750 JRST ..0105 ;NO - GO TO ERROR HANDLING 2273 031745 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2274 031746 316 02 0 00 041166 CAMN AC1+1,[RRIGHT] ;IS RIGHT HALF CORRECT? 2275 031747 254 00 0 00 031753 JRST ..0106+1 ;YES - DONT DO ERROR HANDLING 2276 ; EXCEPT FOR ERLOOP 2277 2278 031750 200 14 0 13 000001 ..0105: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2279 031751 200 13 0 13 041341 MOVE SCR1,[EXP RLEFT,RRIGHT](SCR1) ;GET CORRECT RESULT 2280 031752 ..0106: ERROR (LOC,14,SCR1,SCR2,,TEST F1 - RESULT IS INCORRECT,APRINT)^SALL 2281 031752 036 14 0 00 041312 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-4 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0077 2282 031753 255 00 0 00 000000 2283 ^ 2284 ^ 2285 TFLAG ([0],F1)^ 2286 2287 031754 200 13 0 00 031741 MOVE SCR1,FLAGL ;GET FLAGS 2288 031755 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2289 031756 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2290 031757 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2291 ERROR (LOC,13,SCR2,FLAGL,,TEST F1 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2292 2293 031760 036 13 0 00 041343 2294 031761 255 00 0 00 000000 2295 ^ 2296 ^ 2297 ; ************************************************ 2298 2299 2300 ; ************************************************ 2301 2302 031762 LOC=. ;ERROR RETURN ADDRESS 2303 000005 REP=REP+1 ;REP - REPETITION COUNT 2304 033077 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2305 031762 200 15 0 00 041346 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR FOR ADDL ERROR PRINT 2306 031763 120 01 0 00 033077 DMOVE AC1,CNUM ;INIT AUGEND 2307 031764 255 17 0 00 031765 JFCL 17,.+1 ;CLEAR PC FLAGS 2308 031765 114 01 0 00 033101 DADD AC1,CNUM+2 ;ADD N + P = 0,1 2309 PCSAVE^ 2310 031766 264 00 0 00 031767 JSR .+1 ;STORE PC 2311 031767 FLAGL=. ;LOCATION OF PC 2312 031767 000000 000000 0 ;PC 2313 ^ 2314 777777 777777 RLEFT=0-IFG REP-3,<1> ;LEFT WORD OF RESULT 2315 777777 777777 RRIGHT=1-IFG REP-3,<2> ;RIGHT WORD OF RESULT 2316 CHECKA (LOC,F1,RLEFT,RRIGHT)^ 2317 2318 031770 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2319 031771 312 01 0 00 041166 CAME AC1,[RLEFT] ;IS LEFT HALF OF RESULT CORRECT? 2320 031772 254 00 0 00 031776 JRST ..0107 ;NO - GO TO ERROR HANDLING 2321 031773 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2322 031774 316 02 0 00 041166 CAMN AC1+1,[RRIGHT] ;IS RIGHT HALF CORRECT? 2323 031775 254 00 0 00 032001 JRST ..0110+1 ;YES - DONT DO ERROR HANDLING 2324 ; EXCEPT FOR ERLOOP 2325 2326 031776 200 14 0 13 000001 ..0107: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2327 031777 200 13 0 13 041341 MOVE SCR1,[EXP RLEFT,RRIGHT](SCR1) ;GET CORRECT RESULT 2328 032000 ..0110: ERROR (LOC,14,SCR1,SCR2,,TEST F1 - RESULT IS INCORRECT,APRINT)^SALL 2329 032000 036 14 0 00 041312 2330 032001 255 00 0 00 000000 2331 ^ 2332 ^ 2333 TFLAG ([0],F1)^ 2334 2335 032002 200 13 0 00 031767 MOVE SCR1,FLAGL ;GET FLAGS 2336 032003 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-5 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0078 2337 032004 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2338 032005 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2339 ERROR (LOC,13,SCR2,FLAGL,,TEST F1 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2340 2341 032006 036 13 0 00 041347 2342 032007 255 00 0 00 000000 2343 ^ 2344 ^ 2345 ; ************************************************ 2346 2347 2348 ; ************************************************ 2349 2350 032010 LOC=. ;ERROR RETURN ADDRESS 2351 000006 REP=REP+1 ;REP - REPETITION COUNT 2352 033103 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2353 032010 200 15 0 00 041352 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR FOR ADDL ERROR PRINT 2354 032011 120 01 0 00 033103 DMOVE AC1,CNUM ;INIT AUGEND 2355 032012 255 17 0 00 032013 JFCL 17,.+1 ;CLEAR PC FLAGS 2356 032013 114 01 0 00 033105 DADD AC1,CNUM+2 ;ADD N + P = 0,1 2357 PCSAVE^ 2358 032014 264 00 0 00 032015 JSR .+1 ;STORE PC 2359 032015 FLAGL=. ;LOCATION OF PC 2360 032015 000000 000000 0 ;PC 2361 ^ 2362 777777 777777 RLEFT=0-IFG REP-3,<1> ;LEFT WORD OF RESULT 2363 777777 777777 RRIGHT=1-IFG REP-3,<2> ;RIGHT WORD OF RESULT 2364 CHECKA (LOC,F1,RLEFT,RRIGHT)^ 2365 2366 032016 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2367 032017 312 01 0 00 041166 CAME AC1,[RLEFT] ;IS LEFT HALF OF RESULT CORRECT? 2368 032020 254 00 0 00 032024 JRST ..0111 ;NO - GO TO ERROR HANDLING 2369 032021 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2370 032022 316 02 0 00 041166 CAMN AC1+1,[RRIGHT] ;IS RIGHT HALF CORRECT? 2371 032023 254 00 0 00 032027 JRST ..0112+1 ;YES - DONT DO ERROR HANDLING 2372 ; EXCEPT FOR ERLOOP 2373 2374 032024 200 14 0 13 000001 ..0111: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2375 032025 200 13 0 13 041341 MOVE SCR1,[EXP RLEFT,RRIGHT](SCR1) ;GET CORRECT RESULT 2376 032026 ..0112: ERROR (LOC,14,SCR1,SCR2,,TEST F1 - RESULT IS INCORRECT,APRINT)^SALL 2377 032026 036 14 0 00 041312 2378 032027 255 00 0 00 000000 2379 ^ 2380 ^ 2381 TFLAG ([0],F1)^ 2382 2383 032030 200 13 0 00 032015 MOVE SCR1,FLAGL ;GET FLAGS 2384 032031 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2385 032032 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2386 032033 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2387 ERROR (LOC,13,SCR2,FLAGL,,TEST F1 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2388 2389 032034 036 13 0 00 041353 2390 032035 255 00 0 00 000000 2391 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-6 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0079 2392 ^ 2393 ; ************************************************ 2394 2395 ; ********************************************************************** 2396 ; ---------- DADD - TEST F-2: N + N = N ---------- 2397 ; ********************************************************************** 2398 2399 033103 CNUM=ACONF2-4 2400 2401 REPEAT 6,< 2402 ; ************************************************ 2403 2404 LOC=. ;ERROR RETURN ADDRESS 2405 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2406 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2407 DMOVE AC1,CNUM ;INIT AUGEND 2408 JFCL 17,.+1 ;CLEAR PC FLAGS 2409 DADD AC1,CNUM+2 ;ADD N + N = 77..76,77..76 2410 PCSAVE 2411 CHECKA (LOC,F2,777777777776,777777777776) 2412 TFLAG ([^B0110B3],F2) 2413 ; ************************************************ 2414 > 2415 2416 ; ************************************************ 2417 2418 032036 LOC=. ;ERROR RETURN ADDRESS 2419 033107 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2420 032036 200 15 0 00 041356 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2421 032037 120 01 0 00 033107 DMOVE AC1,CNUM ;INIT AUGEND 2422 032040 255 17 0 00 032041 JFCL 17,.+1 ;CLEAR PC FLAGS 2423 032041 114 01 0 00 033111 DADD AC1,CNUM+2 ;ADD N + N = 77..76,77..76 2424 PCSAVE^ 2425 032042 264 00 0 00 032043 JSR .+1 ;STORE PC 2426 032043 FLAGL=. ;LOCATION OF PC 2427 032043 000000 000000 0 ;PC 2428 ^ 2429 CHECKA (LOC,F2,777777777776,777777777776)^ 2430 2431 032044 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2432 032045 312 01 0 00 041167 CAME AC1,[777777777776] ;IS LEFT HALF OF RESULT CORRECT? 2433 032046 254 00 0 00 032052 JRST ..0113 ;NO - GO TO ERROR HANDLING 2434 032047 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2435 032050 316 02 0 00 041167 CAMN AC1+1,[777777777776] ;IS RIGHT HALF CORRECT? 2436 032051 254 00 0 00 032055 JRST ..0114+1 ;YES - DONT DO ERROR HANDLING 2437 ; EXCEPT FOR ERLOOP 2438 2439 032052 200 14 0 13 000001 ..0113: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2440 032053 200 13 0 13 041357 MOVE SCR1,[EXP 777777777776,777777777776](SCR1) ;GET CORRECT RESULT 2441 032054 ..0114: ERROR (LOC,14,SCR1,SCR2,,TEST F2 - RESULT IS INCORRECT,APRINT)^SALL 2442 032054 036 14 0 00 041366 2443 032055 255 00 0 00 000000 2444 ^ 2445 ^ 2446 TFLAG ([^B0110B3],F2)^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-7 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0080 2447 2448 032056 200 13 0 00 032043 MOVE SCR1,FLAGL ;GET FLAGS 2449 032057 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 2450 032060 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2451 032061 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2452 ERROR (LOC,13,SCR2,FLAGL,,TEST F2 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2453 2454 032062 036 13 0 00 041402 2455 032063 255 00 0 00 000000 2456 ^ 2457 ^ 2458 ; ************************************************ 2459 2460 2461 ; ************************************************ 2462 2463 032064 LOC=. ;ERROR RETURN ADDRESS 2464 033113 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2465 032064 200 15 0 00 041405 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2466 032065 120 01 0 00 033113 DMOVE AC1,CNUM ;INIT AUGEND 2467 032066 255 17 0 00 032067 JFCL 17,.+1 ;CLEAR PC FLAGS 2468 032067 114 01 0 00 033115 DADD AC1,CNUM+2 ;ADD N + N = 77..76,77..76 2469 PCSAVE^ 2470 032070 264 00 0 00 032071 JSR .+1 ;STORE PC 2471 032071 FLAGL=. ;LOCATION OF PC 2472 032071 000000 000000 0 ;PC 2473 ^ 2474 CHECKA (LOC,F2,777777777776,777777777776)^ 2475 2476 032072 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2477 032073 312 01 0 00 041167 CAME AC1,[777777777776] ;IS LEFT HALF OF RESULT CORRECT? 2478 032074 254 00 0 00 032100 JRST ..0115 ;NO - GO TO ERROR HANDLING 2479 032075 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2480 032076 316 02 0 00 041167 CAMN AC1+1,[777777777776] ;IS RIGHT HALF CORRECT? 2481 032077 254 00 0 00 032103 JRST ..0116+1 ;YES - DONT DO ERROR HANDLING 2482 ; EXCEPT FOR ERLOOP 2483 2484 032100 200 14 0 13 000001 ..0115: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2485 032101 200 13 0 13 041357 MOVE SCR1,[EXP 777777777776,777777777776](SCR1) ;GET CORRECT RESULT 2486 032102 ..0116: ERROR (LOC,14,SCR1,SCR2,,TEST F2 - RESULT IS INCORRECT,APRINT)^SALL 2487 032102 036 14 0 00 041366 2488 032103 255 00 0 00 000000 2489 ^ 2490 ^ 2491 TFLAG ([^B0110B3],F2)^ 2492 2493 032104 200 13 0 00 032071 MOVE SCR1,FLAGL ;GET FLAGS 2494 032105 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 2495 032106 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2496 032107 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2497 ERROR (LOC,13,SCR2,FLAGL,,TEST F2 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2498 2499 032110 036 13 0 00 041406 2500 032111 255 00 0 00 000000 2501 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-8 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0081 2502 ^ 2503 ; ************************************************ 2504 2505 2506 ; ************************************************ 2507 2508 032112 LOC=. ;ERROR RETURN ADDRESS 2509 033117 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2510 032112 200 15 0 00 041411 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2511 032113 120 01 0 00 033117 DMOVE AC1,CNUM ;INIT AUGEND 2512 032114 255 17 0 00 032115 JFCL 17,.+1 ;CLEAR PC FLAGS 2513 032115 114 01 0 00 033121 DADD AC1,CNUM+2 ;ADD N + N = 77..76,77..76 2514 PCSAVE^ 2515 032116 264 00 0 00 032117 JSR .+1 ;STORE PC 2516 032117 FLAGL=. ;LOCATION OF PC 2517 032117 000000 000000 0 ;PC 2518 ^ 2519 CHECKA (LOC,F2,777777777776,777777777776)^ 2520 2521 032120 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2522 032121 312 01 0 00 041167 CAME AC1,[777777777776] ;IS LEFT HALF OF RESULT CORRECT? 2523 032122 254 00 0 00 032126 JRST ..0117 ;NO - GO TO ERROR HANDLING 2524 032123 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2525 032124 316 02 0 00 041167 CAMN AC1+1,[777777777776] ;IS RIGHT HALF CORRECT? 2526 032125 254 00 0 00 032131 JRST ..0120+1 ;YES - DONT DO ERROR HANDLING 2527 ; EXCEPT FOR ERLOOP 2528 2529 032126 200 14 0 13 000001 ..0117: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2530 032127 200 13 0 13 041357 MOVE SCR1,[EXP 777777777776,777777777776](SCR1) ;GET CORRECT RESULT 2531 032130 ..0120: ERROR (LOC,14,SCR1,SCR2,,TEST F2 - RESULT IS INCORRECT,APRINT)^SALL 2532 032130 036 14 0 00 041366 2533 032131 255 00 0 00 000000 2534 ^ 2535 ^ 2536 TFLAG ([^B0110B3],F2)^ 2537 2538 032132 200 13 0 00 032117 MOVE SCR1,FLAGL ;GET FLAGS 2539 032133 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 2540 032134 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2541 032135 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2542 ERROR (LOC,13,SCR2,FLAGL,,TEST F2 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2543 2544 032136 036 13 0 00 041412 2545 032137 255 00 0 00 000000 2546 ^ 2547 ^ 2548 ; ************************************************ 2549 2550 2551 ; ************************************************ 2552 2553 032140 LOC=. ;ERROR RETURN ADDRESS 2554 033123 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2555 032140 200 15 0 00 041415 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2556 032141 120 01 0 00 033123 DMOVE AC1,CNUM ;INIT AUGEND DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-9 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0082 2557 032142 255 17 0 00 032143 JFCL 17,.+1 ;CLEAR PC FLAGS 2558 032143 114 01 0 00 033125 DADD AC1,CNUM+2 ;ADD N + N = 77..76,77..76 2559 PCSAVE^ 2560 032144 264 00 0 00 032145 JSR .+1 ;STORE PC 2561 032145 FLAGL=. ;LOCATION OF PC 2562 032145 000000 000000 0 ;PC 2563 ^ 2564 CHECKA (LOC,F2,777777777776,777777777776)^ 2565 2566 032146 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2567 032147 312 01 0 00 041167 CAME AC1,[777777777776] ;IS LEFT HALF OF RESULT CORRECT? 2568 032150 254 00 0 00 032154 JRST ..0121 ;NO - GO TO ERROR HANDLING 2569 032151 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2570 032152 316 02 0 00 041167 CAMN AC1+1,[777777777776] ;IS RIGHT HALF CORRECT? 2571 032153 254 00 0 00 032157 JRST ..0122+1 ;YES - DONT DO ERROR HANDLING 2572 ; EXCEPT FOR ERLOOP 2573 2574 032154 200 14 0 13 000001 ..0121: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2575 032155 200 13 0 13 041357 MOVE SCR1,[EXP 777777777776,777777777776](SCR1) ;GET CORRECT RESULT 2576 032156 ..0122: ERROR (LOC,14,SCR1,SCR2,,TEST F2 - RESULT IS INCORRECT,APRINT)^SALL 2577 032156 036 14 0 00 041366 2578 032157 255 00 0 00 000000 2579 ^ 2580 ^ 2581 TFLAG ([^B0110B3],F2)^ 2582 2583 032160 200 13 0 00 032145 MOVE SCR1,FLAGL ;GET FLAGS 2584 032161 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 2585 032162 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2586 032163 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2587 ERROR (LOC,13,SCR2,FLAGL,,TEST F2 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2588 2589 032164 036 13 0 00 041416 2590 032165 255 00 0 00 000000 2591 ^ 2592 ^ 2593 ; ************************************************ 2594 2595 2596 ; ************************************************ 2597 2598 032166 LOC=. ;ERROR RETURN ADDRESS 2599 033127 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2600 032166 200 15 0 00 041421 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2601 032167 120 01 0 00 033127 DMOVE AC1,CNUM ;INIT AUGEND 2602 032170 255 17 0 00 032171 JFCL 17,.+1 ;CLEAR PC FLAGS 2603 032171 114 01 0 00 033131 DADD AC1,CNUM+2 ;ADD N + N = 77..76,77..76 2604 PCSAVE^ 2605 032172 264 00 0 00 032173 JSR .+1 ;STORE PC 2606 032173 FLAGL=. ;LOCATION OF PC 2607 032173 000000 000000 0 ;PC 2608 ^ 2609 CHECKA (LOC,F2,777777777776,777777777776)^ 2610 2611 032174 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-10 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0083 2612 032175 312 01 0 00 041167 CAME AC1,[777777777776] ;IS LEFT HALF OF RESULT CORRECT? 2613 032176 254 00 0 00 032202 JRST ..0123 ;NO - GO TO ERROR HANDLING 2614 032177 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2615 032200 316 02 0 00 041167 CAMN AC1+1,[777777777776] ;IS RIGHT HALF CORRECT? 2616 032201 254 00 0 00 032205 JRST ..0124+1 ;YES - DONT DO ERROR HANDLING 2617 ; EXCEPT FOR ERLOOP 2618 2619 032202 200 14 0 13 000001 ..0123: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2620 032203 200 13 0 13 041357 MOVE SCR1,[EXP 777777777776,777777777776](SCR1) ;GET CORRECT RESULT 2621 032204 ..0124: ERROR (LOC,14,SCR1,SCR2,,TEST F2 - RESULT IS INCORRECT,APRINT)^SALL 2622 032204 036 14 0 00 041366 2623 032205 255 00 0 00 000000 2624 ^ 2625 ^ 2626 TFLAG ([^B0110B3],F2)^ 2627 2628 032206 200 13 0 00 032173 MOVE SCR1,FLAGL ;GET FLAGS 2629 032207 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 2630 032210 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2631 032211 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2632 ERROR (LOC,13,SCR2,FLAGL,,TEST F2 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2633 2634 032212 036 13 0 00 041422 2635 032213 255 00 0 00 000000 2636 ^ 2637 ^ 2638 ; ************************************************ 2639 2640 2641 ; ************************************************ 2642 2643 032214 LOC=. ;ERROR RETURN ADDRESS 2644 033133 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2645 032214 200 15 0 00 041425 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2646 032215 120 01 0 00 033133 DMOVE AC1,CNUM ;INIT AUGEND 2647 032216 255 17 0 00 032217 JFCL 17,.+1 ;CLEAR PC FLAGS 2648 032217 114 01 0 00 033135 DADD AC1,CNUM+2 ;ADD N + N = 77..76,77..76 2649 PCSAVE^ 2650 032220 264 00 0 00 032221 JSR .+1 ;STORE PC 2651 032221 FLAGL=. ;LOCATION OF PC 2652 032221 000000 000000 0 ;PC 2653 ^ 2654 CHECKA (LOC,F2,777777777776,777777777776)^ 2655 2656 032222 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2657 032223 312 01 0 00 041167 CAME AC1,[777777777776] ;IS LEFT HALF OF RESULT CORRECT? 2658 032224 254 00 0 00 032230 JRST ..0125 ;NO - GO TO ERROR HANDLING 2659 032225 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2660 032226 316 02 0 00 041167 CAMN AC1+1,[777777777776] ;IS RIGHT HALF CORRECT? 2661 032227 254 00 0 00 032233 JRST ..0126+1 ;YES - DONT DO ERROR HANDLING 2662 ; EXCEPT FOR ERLOOP 2663 2664 032230 200 14 0 13 000001 ..0125: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2665 032231 200 13 0 13 041357 MOVE SCR1,[EXP 777777777776,777777777776](SCR1) ;GET CORRECT RESULT 2666 032232 ..0126: ERROR (LOC,14,SCR1,SCR2,,TEST F2 - RESULT IS INCORRECT,APRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-11 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0084 2667 032232 036 14 0 00 041366 2668 032233 255 00 0 00 000000 2669 ^ 2670 ^ 2671 TFLAG ([^B0110B3],F2)^ 2672 2673 032234 200 13 0 00 032221 MOVE SCR1,FLAGL ;GET FLAGS 2674 032235 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 2675 032236 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2676 032237 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2677 ERROR (LOC,13,SCR2,FLAGL,,TEST F2 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2678 2679 032240 036 13 0 00 041426 2680 032241 255 00 0 00 000000 2681 ^ 2682 ^ 2683 ; ************************************************ 2684 2685 ; ********************************************************************** 2686 ; ---------- DADD - TEST F-3: P + P = P ---------- 2687 ; ********************************************************************** 2688 2689 033133 CNUM=ACONF3-4 2690 2691 REPEAT 6,< 2692 ; ************************************************ 2693 2694 LOC=. ;ERROR RETURN ADDRESS 2695 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2696 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2697 DMOVE AC1,CNUM ;INIT AUGEND 2698 JFCL 17,.+1 ;CLEAR PC FLAGS 2699 DADD AC1,CNUM+2 ;ADD N + P = 1,1 2700 PCSAVE 2701 CHECKA (LOC,F3,1,1) 2702 TFLAG ([0],F3) 2703 ; ************************************************ 2704 > 2705 2706 ; ************************************************ 2707 2708 032242 LOC=. ;ERROR RETURN ADDRESS 2709 033137 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2710 032242 200 15 0 00 041431 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2711 032243 120 01 0 00 033137 DMOVE AC1,CNUM ;INIT AUGEND 2712 032244 255 17 0 00 032245 JFCL 17,.+1 ;CLEAR PC FLAGS 2713 032245 114 01 0 00 033141 DADD AC1,CNUM+2 ;ADD N + P = 1,1 2714 PCSAVE^ 2715 032246 264 00 0 00 032247 JSR .+1 ;STORE PC 2716 032247 FLAGL=. ;LOCATION OF PC 2717 032247 000000 000000 0 ;PC 2718 ^ 2719 CHECKA (LOC,F3,1,1)^ 2720 2721 032250 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-12 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0085 2722 032251 312 01 0 00 041127 CAME AC1,[1] ;IS LEFT HALF OF RESULT CORRECT? 2723 032252 254 00 0 00 032256 JRST ..0127 ;NO - GO TO ERROR HANDLING 2724 032253 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2725 032254 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 2726 032255 254 00 0 00 032261 JRST ..0130+1 ;YES - DONT DO ERROR HANDLING 2727 ; EXCEPT FOR ERLOOP 2728 2729 032256 200 14 0 13 000001 ..0127: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2730 032257 200 13 0 13 041432 MOVE SCR1,[EXP 1,1](SCR1) ;GET CORRECT RESULT 2731 032260 ..0130: ERROR (LOC,14,SCR1,SCR2,,TEST F3 - RESULT IS INCORRECT,APRINT)^SALL 2732 032260 036 14 0 00 041441 2733 032261 255 00 0 00 000000 2734 ^ 2735 ^ 2736 TFLAG ([0],F3)^ 2737 2738 032262 200 13 0 00 032247 MOVE SCR1,FLAGL ;GET FLAGS 2739 032263 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2740 032264 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2741 032265 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2742 ERROR (LOC,13,SCR2,FLAGL,,TEST F3 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2743 2744 032266 036 13 0 00 041454 2745 032267 255 00 0 00 000000 2746 ^ 2747 ^ 2748 ; ************************************************ 2749 2750 2751 ; ************************************************ 2752 2753 032270 LOC=. ;ERROR RETURN ADDRESS 2754 033143 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2755 032270 200 15 0 00 041457 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2756 032271 120 01 0 00 033143 DMOVE AC1,CNUM ;INIT AUGEND 2757 032272 255 17 0 00 032273 JFCL 17,.+1 ;CLEAR PC FLAGS 2758 032273 114 01 0 00 033145 DADD AC1,CNUM+2 ;ADD N + P = 1,1 2759 PCSAVE^ 2760 032274 264 00 0 00 032275 JSR .+1 ;STORE PC 2761 032275 FLAGL=. ;LOCATION OF PC 2762 032275 000000 000000 0 ;PC 2763 ^ 2764 CHECKA (LOC,F3,1,1)^ 2765 2766 032276 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2767 032277 312 01 0 00 041127 CAME AC1,[1] ;IS LEFT HALF OF RESULT CORRECT? 2768 032300 254 00 0 00 032304 JRST ..0131 ;NO - GO TO ERROR HANDLING 2769 032301 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2770 032302 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 2771 032303 254 00 0 00 032307 JRST ..0132+1 ;YES - DONT DO ERROR HANDLING 2772 ; EXCEPT FOR ERLOOP 2773 2774 032304 200 14 0 13 000001 ..0131: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2775 032305 200 13 0 13 041432 MOVE SCR1,[EXP 1,1](SCR1) ;GET CORRECT RESULT 2776 032306 ..0132: ERROR (LOC,14,SCR1,SCR2,,TEST F3 - RESULT IS INCORRECT,APRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-13 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0086 2777 032306 036 14 0 00 041441 2778 032307 255 00 0 00 000000 2779 ^ 2780 ^ 2781 TFLAG ([0],F3)^ 2782 2783 032310 200 13 0 00 032275 MOVE SCR1,FLAGL ;GET FLAGS 2784 032311 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2785 032312 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2786 032313 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2787 ERROR (LOC,13,SCR2,FLAGL,,TEST F3 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2788 2789 032314 036 13 0 00 041460 2790 032315 255 00 0 00 000000 2791 ^ 2792 ^ 2793 ; ************************************************ 2794 2795 2796 ; ************************************************ 2797 2798 032316 LOC=. ;ERROR RETURN ADDRESS 2799 033147 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2800 032316 200 15 0 00 041463 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2801 032317 120 01 0 00 033147 DMOVE AC1,CNUM ;INIT AUGEND 2802 032320 255 17 0 00 032321 JFCL 17,.+1 ;CLEAR PC FLAGS 2803 032321 114 01 0 00 033151 DADD AC1,CNUM+2 ;ADD N + P = 1,1 2804 PCSAVE^ 2805 032322 264 00 0 00 032323 JSR .+1 ;STORE PC 2806 032323 FLAGL=. ;LOCATION OF PC 2807 032323 000000 000000 0 ;PC 2808 ^ 2809 CHECKA (LOC,F3,1,1)^ 2810 2811 032324 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2812 032325 312 01 0 00 041127 CAME AC1,[1] ;IS LEFT HALF OF RESULT CORRECT? 2813 032326 254 00 0 00 032332 JRST ..0133 ;NO - GO TO ERROR HANDLING 2814 032327 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2815 032330 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 2816 032331 254 00 0 00 032335 JRST ..0134+1 ;YES - DONT DO ERROR HANDLING 2817 ; EXCEPT FOR ERLOOP 2818 2819 032332 200 14 0 13 000001 ..0133: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2820 032333 200 13 0 13 041432 MOVE SCR1,[EXP 1,1](SCR1) ;GET CORRECT RESULT 2821 032334 ..0134: ERROR (LOC,14,SCR1,SCR2,,TEST F3 - RESULT IS INCORRECT,APRINT)^SALL 2822 032334 036 14 0 00 041441 2823 032335 255 00 0 00 000000 2824 ^ 2825 ^ 2826 TFLAG ([0],F3)^ 2827 2828 032336 200 13 0 00 032323 MOVE SCR1,FLAGL ;GET FLAGS 2829 032337 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2830 032340 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2831 032341 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-14 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0087 2832 ERROR (LOC,13,SCR2,FLAGL,,TEST F3 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2833 2834 032342 036 13 0 00 041464 2835 032343 255 00 0 00 000000 2836 ^ 2837 ^ 2838 ; ************************************************ 2839 2840 2841 ; ************************************************ 2842 2843 032344 LOC=. ;ERROR RETURN ADDRESS 2844 033153 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2845 032344 200 15 0 00 041467 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2846 032345 120 01 0 00 033153 DMOVE AC1,CNUM ;INIT AUGEND 2847 032346 255 17 0 00 032347 JFCL 17,.+1 ;CLEAR PC FLAGS 2848 032347 114 01 0 00 033155 DADD AC1,CNUM+2 ;ADD N + P = 1,1 2849 PCSAVE^ 2850 032350 264 00 0 00 032351 JSR .+1 ;STORE PC 2851 032351 FLAGL=. ;LOCATION OF PC 2852 032351 000000 000000 0 ;PC 2853 ^ 2854 CHECKA (LOC,F3,1,1)^ 2855 2856 032352 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2857 032353 312 01 0 00 041127 CAME AC1,[1] ;IS LEFT HALF OF RESULT CORRECT? 2858 032354 254 00 0 00 032360 JRST ..0135 ;NO - GO TO ERROR HANDLING 2859 032355 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2860 032356 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 2861 032357 254 00 0 00 032363 JRST ..0136+1 ;YES - DONT DO ERROR HANDLING 2862 ; EXCEPT FOR ERLOOP 2863 2864 032360 200 14 0 13 000001 ..0135: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2865 032361 200 13 0 13 041432 MOVE SCR1,[EXP 1,1](SCR1) ;GET CORRECT RESULT 2866 032362 ..0136: ERROR (LOC,14,SCR1,SCR2,,TEST F3 - RESULT IS INCORRECT,APRINT)^SALL 2867 032362 036 14 0 00 041441 2868 032363 255 00 0 00 000000 2869 ^ 2870 ^ 2871 TFLAG ([0],F3)^ 2872 2873 032364 200 13 0 00 032351 MOVE SCR1,FLAGL ;GET FLAGS 2874 032365 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2875 032366 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2876 032367 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2877 ERROR (LOC,13,SCR2,FLAGL,,TEST F3 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2878 2879 032370 036 13 0 00 041470 2880 032371 255 00 0 00 000000 2881 ^ 2882 ^ 2883 ; ************************************************ 2884 2885 2886 ; ************************************************ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-15 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0088 2887 2888 032372 LOC=. ;ERROR RETURN ADDRESS 2889 033157 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2890 032372 200 15 0 00 041473 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2891 032373 120 01 0 00 033157 DMOVE AC1,CNUM ;INIT AUGEND 2892 032374 255 17 0 00 032375 JFCL 17,.+1 ;CLEAR PC FLAGS 2893 032375 114 01 0 00 033161 DADD AC1,CNUM+2 ;ADD N + P = 1,1 2894 PCSAVE^ 2895 032376 264 00 0 00 032377 JSR .+1 ;STORE PC 2896 032377 FLAGL=. ;LOCATION OF PC 2897 032377 000000 000000 0 ;PC 2898 ^ 2899 CHECKA (LOC,F3,1,1)^ 2900 2901 032400 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2902 032401 312 01 0 00 041127 CAME AC1,[1] ;IS LEFT HALF OF RESULT CORRECT? 2903 032402 254 00 0 00 032406 JRST ..0137 ;NO - GO TO ERROR HANDLING 2904 032403 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2905 032404 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 2906 032405 254 00 0 00 032411 JRST ..0140+1 ;YES - DONT DO ERROR HANDLING 2907 ; EXCEPT FOR ERLOOP 2908 2909 032406 200 14 0 13 000001 ..0137: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2910 032407 200 13 0 13 041432 MOVE SCR1,[EXP 1,1](SCR1) ;GET CORRECT RESULT 2911 032410 ..0140: ERROR (LOC,14,SCR1,SCR2,,TEST F3 - RESULT IS INCORRECT,APRINT)^SALL 2912 032410 036 14 0 00 041441 2913 032411 255 00 0 00 000000 2914 ^ 2915 ^ 2916 TFLAG ([0],F3)^ 2917 2918 032412 200 13 0 00 032377 MOVE SCR1,FLAGL ;GET FLAGS 2919 032413 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2920 032414 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2921 032415 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2922 ERROR (LOC,13,SCR2,FLAGL,,TEST F3 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2923 2924 032416 036 13 0 00 041474 2925 032417 255 00 0 00 000000 2926 ^ 2927 ^ 2928 ; ************************************************ 2929 2930 2931 ; ************************************************ 2932 2933 032420 LOC=. ;ERROR RETURN ADDRESS 2934 033163 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2935 032420 200 15 0 00 041477 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2936 032421 120 01 0 00 033163 DMOVE AC1,CNUM ;INIT AUGEND 2937 032422 255 17 0 00 032423 JFCL 17,.+1 ;CLEAR PC FLAGS 2938 032423 114 01 0 00 033165 DADD AC1,CNUM+2 ;ADD N + P = 1,1 2939 PCSAVE^ 2940 032424 264 00 0 00 032425 JSR .+1 ;STORE PC 2941 032425 FLAGL=. ;LOCATION OF PC DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-16 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0089 2942 032425 000000 000000 0 ;PC 2943 ^ 2944 CHECKA (LOC,F3,1,1)^ 2945 2946 032426 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 2947 032427 312 01 0 00 041127 CAME AC1,[1] ;IS LEFT HALF OF RESULT CORRECT? 2948 032430 254 00 0 00 032434 JRST ..0141 ;NO - GO TO ERROR HANDLING 2949 032431 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 2950 032432 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 2951 032433 254 00 0 00 032437 JRST ..0142+1 ;YES - DONT DO ERROR HANDLING 2952 ; EXCEPT FOR ERLOOP 2953 2954 032434 200 14 0 13 000001 ..0141: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 2955 032435 200 13 0 13 041432 MOVE SCR1,[EXP 1,1](SCR1) ;GET CORRECT RESULT 2956 032436 ..0142: ERROR (LOC,14,SCR1,SCR2,,TEST F3 - RESULT IS INCORRECT,APRINT)^SALL 2957 032436 036 14 0 00 041441 2958 032437 255 00 0 00 000000 2959 ^ 2960 ^ 2961 TFLAG ([0],F3)^ 2962 2963 032440 200 13 0 00 032425 MOVE SCR1,FLAGL ;GET FLAGS 2964 032441 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 2965 032442 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 2966 032443 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 2967 ERROR (LOC,13,SCR2,FLAGL,,TEST F3 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 2968 2969 032444 036 13 0 00 041500 2970 032445 255 00 0 00 000000 2971 ^ 2972 ^ 2973 ; ************************************************ 2974 2975 ; ********************************************************************** 2976 ; ---------- DADD - TEST F-4: N + P = -1,-1 ---------- 2977 ; ********************************************************************** 2978 2979 033163 CNUM=ACONF4-4 2980 2981 REPEAT 6,< 2982 ; ************************************************ 2983 2984 LOC=. ;ERROR RETURN ADDRESS 2985 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 2986 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 2987 DMOVE AC1,CNUM ;INIT AUGEND 2988 JFCL 17,.+1 ;CLEAR PC FLAGS 2989 DADD AC1,CNUM+2 ;ADD N + P = -1,-1 2990 PCSAVE 2991 CHECKA (LOC,F4,-1,-1) 2992 TFLAG ([0],F4) 2993 ; ************************************************ 2994 > 2995 2996 ; ************************************************ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-17 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0090 2997 2998 032446 LOC=. ;ERROR RETURN ADDRESS 2999 033167 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3000 032446 200 15 0 00 041503 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3001 032447 120 01 0 00 033167 DMOVE AC1,CNUM ;INIT AUGEND 3002 032450 255 17 0 00 032451 JFCL 17,.+1 ;CLEAR PC FLAGS 3003 032451 114 01 0 00 033171 DADD AC1,CNUM+2 ;ADD N + P = -1,-1 3004 PCSAVE^ 3005 032452 264 00 0 00 032453 JSR .+1 ;STORE PC 3006 032453 FLAGL=. ;LOCATION OF PC 3007 032453 000000 000000 0 ;PC 3008 ^ 3009 CHECKA (LOC,F4,-1,-1)^ 3010 3011 032454 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3012 032455 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 3013 032456 254 00 0 00 032462 JRST ..0143 ;NO - GO TO ERROR HANDLING 3014 032457 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3015 032460 316 02 0 00 041166 CAMN AC1+1,[-1] ;IS RIGHT HALF CORRECT? 3016 032461 254 00 0 00 032465 JRST ..0144+1 ;YES - DONT DO ERROR HANDLING 3017 ; EXCEPT FOR ERLOOP 3018 3019 032462 200 14 0 13 000001 ..0143: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3020 032463 200 13 0 13 041341 MOVE SCR1,[EXP -1,-1](SCR1) ;GET CORRECT RESULT 3021 032464 ..0144: ERROR (LOC,14,SCR1,SCR2,,TEST F4 - RESULT IS INCORRECT,APRINT)^SALL 3022 032464 036 14 0 00 041511 3023 032465 255 00 0 00 000000 3024 ^ 3025 ^ 3026 TFLAG ([0],F4)^ 3027 3028 032466 200 13 0 00 032453 MOVE SCR1,FLAGL ;GET FLAGS 3029 032467 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 3030 032470 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3031 032471 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3032 ERROR (LOC,13,SCR2,FLAGL,,TEST F4 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3033 3034 032472 036 13 0 00 041524 3035 032473 255 00 0 00 000000 3036 ^ 3037 ^ 3038 ; ************************************************ 3039 3040 3041 ; ************************************************ 3042 3043 032474 LOC=. ;ERROR RETURN ADDRESS 3044 033173 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3045 032474 200 15 0 00 041527 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3046 032475 120 01 0 00 033173 DMOVE AC1,CNUM ;INIT AUGEND 3047 032476 255 17 0 00 032477 JFCL 17,.+1 ;CLEAR PC FLAGS 3048 032477 114 01 0 00 033175 DADD AC1,CNUM+2 ;ADD N + P = -1,-1 3049 PCSAVE^ 3050 032500 264 00 0 00 032501 JSR .+1 ;STORE PC 3051 032501 FLAGL=. ;LOCATION OF PC DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-18 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0091 3052 032501 000000 000000 0 ;PC 3053 ^ 3054 CHECKA (LOC,F4,-1,-1)^ 3055 3056 032502 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3057 032503 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 3058 032504 254 00 0 00 032510 JRST ..0145 ;NO - GO TO ERROR HANDLING 3059 032505 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3060 032506 316 02 0 00 041166 CAMN AC1+1,[-1] ;IS RIGHT HALF CORRECT? 3061 032507 254 00 0 00 032513 JRST ..0146+1 ;YES - DONT DO ERROR HANDLING 3062 ; EXCEPT FOR ERLOOP 3063 3064 032510 200 14 0 13 000001 ..0145: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3065 032511 200 13 0 13 041341 MOVE SCR1,[EXP -1,-1](SCR1) ;GET CORRECT RESULT 3066 032512 ..0146: ERROR (LOC,14,SCR1,SCR2,,TEST F4 - RESULT IS INCORRECT,APRINT)^SALL 3067 032512 036 14 0 00 041511 3068 032513 255 00 0 00 000000 3069 ^ 3070 ^ 3071 TFLAG ([0],F4)^ 3072 3073 032514 200 13 0 00 032501 MOVE SCR1,FLAGL ;GET FLAGS 3074 032515 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 3075 032516 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3076 032517 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3077 ERROR (LOC,13,SCR2,FLAGL,,TEST F4 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3078 3079 032520 036 13 0 00 041530 3080 032521 255 00 0 00 000000 3081 ^ 3082 ^ 3083 ; ************************************************ 3084 3085 3086 ; ************************************************ 3087 3088 032522 LOC=. ;ERROR RETURN ADDRESS 3089 033177 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3090 032522 200 15 0 00 041533 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3091 032523 120 01 0 00 033177 DMOVE AC1,CNUM ;INIT AUGEND 3092 032524 255 17 0 00 032525 JFCL 17,.+1 ;CLEAR PC FLAGS 3093 032525 114 01 0 00 033201 DADD AC1,CNUM+2 ;ADD N + P = -1,-1 3094 PCSAVE^ 3095 032526 264 00 0 00 032527 JSR .+1 ;STORE PC 3096 032527 FLAGL=. ;LOCATION OF PC 3097 032527 000000 000000 0 ;PC 3098 ^ 3099 CHECKA (LOC,F4,-1,-1)^ 3100 3101 032530 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3102 032531 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 3103 032532 254 00 0 00 032536 JRST ..0147 ;NO - GO TO ERROR HANDLING 3104 032533 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3105 032534 316 02 0 00 041166 CAMN AC1+1,[-1] ;IS RIGHT HALF CORRECT? 3106 032535 254 00 0 00 032541 JRST ..0150+1 ;YES - DONT DO ERROR HANDLING DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-19 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0092 3107 ; EXCEPT FOR ERLOOP 3108 3109 032536 200 14 0 13 000001 ..0147: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3110 032537 200 13 0 13 041341 MOVE SCR1,[EXP -1,-1](SCR1) ;GET CORRECT RESULT 3111 032540 ..0150: ERROR (LOC,14,SCR1,SCR2,,TEST F4 - RESULT IS INCORRECT,APRINT)^SALL 3112 032540 036 14 0 00 041511 3113 032541 255 00 0 00 000000 3114 ^ 3115 ^ 3116 TFLAG ([0],F4)^ 3117 3118 032542 200 13 0 00 032527 MOVE SCR1,FLAGL ;GET FLAGS 3119 032543 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 3120 032544 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3121 032545 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3122 ERROR (LOC,13,SCR2,FLAGL,,TEST F4 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3123 3124 032546 036 13 0 00 041534 3125 032547 255 00 0 00 000000 3126 ^ 3127 ^ 3128 ; ************************************************ 3129 3130 3131 ; ************************************************ 3132 3133 032550 LOC=. ;ERROR RETURN ADDRESS 3134 033203 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3135 032550 200 15 0 00 041537 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3136 032551 120 01 0 00 033203 DMOVE AC1,CNUM ;INIT AUGEND 3137 032552 255 17 0 00 032553 JFCL 17,.+1 ;CLEAR PC FLAGS 3138 032553 114 01 0 00 033205 DADD AC1,CNUM+2 ;ADD N + P = -1,-1 3139 PCSAVE^ 3140 032554 264 00 0 00 032555 JSR .+1 ;STORE PC 3141 032555 FLAGL=. ;LOCATION OF PC 3142 032555 000000 000000 0 ;PC 3143 ^ 3144 CHECKA (LOC,F4,-1,-1)^ 3145 3146 032556 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3147 032557 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 3148 032560 254 00 0 00 032564 JRST ..0151 ;NO - GO TO ERROR HANDLING 3149 032561 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3150 032562 316 02 0 00 041166 CAMN AC1+1,[-1] ;IS RIGHT HALF CORRECT? 3151 032563 254 00 0 00 032567 JRST ..0152+1 ;YES - DONT DO ERROR HANDLING 3152 ; EXCEPT FOR ERLOOP 3153 3154 032564 200 14 0 13 000001 ..0151: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3155 032565 200 13 0 13 041341 MOVE SCR1,[EXP -1,-1](SCR1) ;GET CORRECT RESULT 3156 032566 ..0152: ERROR (LOC,14,SCR1,SCR2,,TEST F4 - RESULT IS INCORRECT,APRINT)^SALL 3157 032566 036 14 0 00 041511 3158 032567 255 00 0 00 000000 3159 ^ 3160 ^ 3161 TFLAG ([0],F4)^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-20 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0093 3162 3163 032570 200 13 0 00 032555 MOVE SCR1,FLAGL ;GET FLAGS 3164 032571 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 3165 032572 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3166 032573 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3167 ERROR (LOC,13,SCR2,FLAGL,,TEST F4 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3168 3169 032574 036 13 0 00 041540 3170 032575 255 00 0 00 000000 3171 ^ 3172 ^ 3173 ; ************************************************ 3174 3175 3176 ; ************************************************ 3177 3178 032576 LOC=. ;ERROR RETURN ADDRESS 3179 033207 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3180 032576 200 15 0 00 041543 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3181 032577 120 01 0 00 033207 DMOVE AC1,CNUM ;INIT AUGEND 3182 032600 255 17 0 00 032601 JFCL 17,.+1 ;CLEAR PC FLAGS 3183 032601 114 01 0 00 033211 DADD AC1,CNUM+2 ;ADD N + P = -1,-1 3184 PCSAVE^ 3185 032602 264 00 0 00 032603 JSR .+1 ;STORE PC 3186 032603 FLAGL=. ;LOCATION OF PC 3187 032603 000000 000000 0 ;PC 3188 ^ 3189 CHECKA (LOC,F4,-1,-1)^ 3190 3191 032604 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3192 032605 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 3193 032606 254 00 0 00 032612 JRST ..0153 ;NO - GO TO ERROR HANDLING 3194 032607 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3195 032610 316 02 0 00 041166 CAMN AC1+1,[-1] ;IS RIGHT HALF CORRECT? 3196 032611 254 00 0 00 032615 JRST ..0154+1 ;YES - DONT DO ERROR HANDLING 3197 ; EXCEPT FOR ERLOOP 3198 3199 032612 200 14 0 13 000001 ..0153: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3200 032613 200 13 0 13 041341 MOVE SCR1,[EXP -1,-1](SCR1) ;GET CORRECT RESULT 3201 032614 ..0154: ERROR (LOC,14,SCR1,SCR2,,TEST F4 - RESULT IS INCORRECT,APRINT)^SALL 3202 032614 036 14 0 00 041511 3203 032615 255 00 0 00 000000 3204 ^ 3205 ^ 3206 TFLAG ([0],F4)^ 3207 3208 032616 200 13 0 00 032603 MOVE SCR1,FLAGL ;GET FLAGS 3209 032617 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 3210 032620 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3211 032621 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3212 ERROR (LOC,13,SCR2,FLAGL,,TEST F4 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3213 3214 032622 036 13 0 00 041544 3215 032623 255 00 0 00 000000 3216 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-21 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0094 3217 ^ 3218 ; ************************************************ 3219 3220 3221 ; ************************************************ 3222 3223 032624 LOC=. ;ERROR RETURN ADDRESS 3224 033213 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3225 032624 200 15 0 00 041547 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3226 032625 120 01 0 00 033213 DMOVE AC1,CNUM ;INIT AUGEND 3227 032626 255 17 0 00 032627 JFCL 17,.+1 ;CLEAR PC FLAGS 3228 032627 114 01 0 00 033215 DADD AC1,CNUM+2 ;ADD N + P = -1,-1 3229 PCSAVE^ 3230 032630 264 00 0 00 032631 JSR .+1 ;STORE PC 3231 032631 FLAGL=. ;LOCATION OF PC 3232 032631 000000 000000 0 ;PC 3233 ^ 3234 CHECKA (LOC,F4,-1,-1)^ 3235 3236 032632 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3237 032633 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 3238 032634 254 00 0 00 032640 JRST ..0155 ;NO - GO TO ERROR HANDLING 3239 032635 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3240 032636 316 02 0 00 041166 CAMN AC1+1,[-1] ;IS RIGHT HALF CORRECT? 3241 032637 254 00 0 00 032643 JRST ..0156+1 ;YES - DONT DO ERROR HANDLING 3242 ; EXCEPT FOR ERLOOP 3243 3244 032640 200 14 0 13 000001 ..0155: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3245 032641 200 13 0 13 041341 MOVE SCR1,[EXP -1,-1](SCR1) ;GET CORRECT RESULT 3246 032642 ..0156: ERROR (LOC,14,SCR1,SCR2,,TEST F4 - RESULT IS INCORRECT,APRINT)^SALL 3247 032642 036 14 0 00 041511 3248 032643 255 00 0 00 000000 3249 ^ 3250 ^ 3251 TFLAG ([0],F4)^ 3252 3253 032644 200 13 0 00 032631 MOVE SCR1,FLAGL ;GET FLAGS 3254 032645 200 14 0 00 041020 MOVE SCR2,[0] ;SCR2 - CORRECT FLAGS 3255 032646 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3256 032647 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3257 ERROR (LOC,13,SCR2,FLAGL,,TEST F4 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3258 3259 032650 036 13 0 00 041550 3260 032651 255 00 0 00 000000 3261 ^ 3262 ^ 3263 ; ************************************************ 3264 3265 ; ********************************************************************** 3266 ; ---------- DADD - TEST F-5: N + P = 0,1 ---------- 3267 ; ********************************************************************** 3268 3269 033213 CNUM=ACONF5-4 3270 3271 REPEAT 6,< DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-22 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0095 3272 ; ************************************************ 3273 3274 LOC=. ;ERROR RETURN ADDRESS 3275 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3276 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3277 DMOVE AC1,CNUM ;INIT AUGEND 3278 JFCL 17,.+1 ;CLEAR PC FLAGS 3279 DADD AC1,CNUM+2 ;ADD N + P = 0,1 3280 PCSAVE 3281 CHECKA (LOC,F5,0,1) 3282 TFLAG ([^B0110B3],F5) 3283 ; ************************************************ 3284 > 3285 3286 ; ************************************************ 3287 3288 032652 LOC=. ;ERROR RETURN ADDRESS 3289 033217 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3290 032652 200 15 0 00 041553 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3291 032653 120 01 0 00 033217 DMOVE AC1,CNUM ;INIT AUGEND 3292 032654 255 17 0 00 032655 JFCL 17,.+1 ;CLEAR PC FLAGS 3293 032655 114 01 0 00 033221 DADD AC1,CNUM+2 ;ADD N + P = 0,1 3294 PCSAVE^ 3295 032656 264 00 0 00 032657 JSR .+1 ;STORE PC 3296 032657 FLAGL=. ;LOCATION OF PC 3297 032657 000000 000000 0 ;PC 3298 ^ 3299 CHECKA (LOC,F5,0,1)^ 3300 3301 032660 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3302 032661 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 3303 032662 254 00 0 00 032666 JRST ..0157 ;NO - GO TO ERROR HANDLING 3304 032663 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3305 032664 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 3306 032665 254 00 0 00 032671 JRST ..0160+1 ;YES - DONT DO ERROR HANDLING 3307 ; EXCEPT FOR ERLOOP 3308 3309 032666 200 14 0 13 000001 ..0157: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3310 032667 200 13 0 13 041126 MOVE SCR1,[EXP 0,1](SCR1) ;GET CORRECT RESULT 3311 032670 ..0160: ERROR (LOC,14,SCR1,SCR2,,TEST F5 - RESULT IS INCORRECT,APRINT)^SALL 3312 032670 036 14 0 00 041561 3313 032671 255 00 0 00 000000 3314 ^ 3315 ^ 3316 TFLAG ([^B0110B3],F5)^ 3317 3318 032672 200 13 0 00 032657 MOVE SCR1,FLAGL ;GET FLAGS 3319 032673 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 3320 032674 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3321 032675 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3322 ERROR (LOC,13,SCR2,FLAGL,,TEST F5 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3323 3324 032676 036 13 0 00 041574 3325 032677 255 00 0 00 000000 3326 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-23 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0096 3327 ^ 3328 ; ************************************************ 3329 3330 3331 ; ************************************************ 3332 3333 032700 LOC=. ;ERROR RETURN ADDRESS 3334 033223 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3335 032700 200 15 0 00 041577 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3336 032701 120 01 0 00 033223 DMOVE AC1,CNUM ;INIT AUGEND 3337 032702 255 17 0 00 032703 JFCL 17,.+1 ;CLEAR PC FLAGS 3338 032703 114 01 0 00 033225 DADD AC1,CNUM+2 ;ADD N + P = 0,1 3339 PCSAVE^ 3340 032704 264 00 0 00 032705 JSR .+1 ;STORE PC 3341 032705 FLAGL=. ;LOCATION OF PC 3342 032705 000000 000000 0 ;PC 3343 ^ 3344 CHECKA (LOC,F5,0,1)^ 3345 3346 032706 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3347 032707 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 3348 032710 254 00 0 00 032714 JRST ..0161 ;NO - GO TO ERROR HANDLING 3349 032711 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3350 032712 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 3351 032713 254 00 0 00 032717 JRST ..0162+1 ;YES - DONT DO ERROR HANDLING 3352 ; EXCEPT FOR ERLOOP 3353 3354 032714 200 14 0 13 000001 ..0161: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3355 032715 200 13 0 13 041126 MOVE SCR1,[EXP 0,1](SCR1) ;GET CORRECT RESULT 3356 032716 ..0162: ERROR (LOC,14,SCR1,SCR2,,TEST F5 - RESULT IS INCORRECT,APRINT)^SALL 3357 032716 036 14 0 00 041561 3358 032717 255 00 0 00 000000 3359 ^ 3360 ^ 3361 TFLAG ([^B0110B3],F5)^ 3362 3363 032720 200 13 0 00 032705 MOVE SCR1,FLAGL ;GET FLAGS 3364 032721 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 3365 032722 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3366 032723 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3367 ERROR (LOC,13,SCR2,FLAGL,,TEST F5 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3368 3369 032724 036 13 0 00 041600 3370 032725 255 00 0 00 000000 3371 ^ 3372 ^ 3373 ; ************************************************ 3374 3375 3376 ; ************************************************ 3377 3378 032726 LOC=. ;ERROR RETURN ADDRESS 3379 033227 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3380 032726 200 15 0 00 041603 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3381 032727 120 01 0 00 033227 DMOVE AC1,CNUM ;INIT AUGEND DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-24 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0097 3382 032730 255 17 0 00 032731 JFCL 17,.+1 ;CLEAR PC FLAGS 3383 032731 114 01 0 00 033231 DADD AC1,CNUM+2 ;ADD N + P = 0,1 3384 PCSAVE^ 3385 032732 264 00 0 00 032733 JSR .+1 ;STORE PC 3386 032733 FLAGL=. ;LOCATION OF PC 3387 032733 000000 000000 0 ;PC 3388 ^ 3389 CHECKA (LOC,F5,0,1)^ 3390 3391 032734 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3392 032735 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 3393 032736 254 00 0 00 032742 JRST ..0163 ;NO - GO TO ERROR HANDLING 3394 032737 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3395 032740 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 3396 032741 254 00 0 00 032745 JRST ..0164+1 ;YES - DONT DO ERROR HANDLING 3397 ; EXCEPT FOR ERLOOP 3398 3399 032742 200 14 0 13 000001 ..0163: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3400 032743 200 13 0 13 041126 MOVE SCR1,[EXP 0,1](SCR1) ;GET CORRECT RESULT 3401 032744 ..0164: ERROR (LOC,14,SCR1,SCR2,,TEST F5 - RESULT IS INCORRECT,APRINT)^SALL 3402 032744 036 14 0 00 041561 3403 032745 255 00 0 00 000000 3404 ^ 3405 ^ 3406 TFLAG ([^B0110B3],F5)^ 3407 3408 032746 200 13 0 00 032733 MOVE SCR1,FLAGL ;GET FLAGS 3409 032747 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 3410 032750 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3411 032751 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3412 ERROR (LOC,13,SCR2,FLAGL,,TEST F5 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3413 3414 032752 036 13 0 00 041604 3415 032753 255 00 0 00 000000 3416 ^ 3417 ^ 3418 ; ************************************************ 3419 3420 3421 ; ************************************************ 3422 3423 032754 LOC=. ;ERROR RETURN ADDRESS 3424 033233 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3425 032754 200 15 0 00 041607 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3426 032755 120 01 0 00 033233 DMOVE AC1,CNUM ;INIT AUGEND 3427 032756 255 17 0 00 032757 JFCL 17,.+1 ;CLEAR PC FLAGS 3428 032757 114 01 0 00 033235 DADD AC1,CNUM+2 ;ADD N + P = 0,1 3429 PCSAVE^ 3430 032760 264 00 0 00 032761 JSR .+1 ;STORE PC 3431 032761 FLAGL=. ;LOCATION OF PC 3432 032761 000000 000000 0 ;PC 3433 ^ 3434 CHECKA (LOC,F5,0,1)^ 3435 3436 032762 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-25 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0098 3437 032763 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 3438 032764 254 00 0 00 032770 JRST ..0165 ;NO - GO TO ERROR HANDLING 3439 032765 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3440 032766 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 3441 032767 254 00 0 00 032773 JRST ..0166+1 ;YES - DONT DO ERROR HANDLING 3442 ; EXCEPT FOR ERLOOP 3443 3444 032770 200 14 0 13 000001 ..0165: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3445 032771 200 13 0 13 041126 MOVE SCR1,[EXP 0,1](SCR1) ;GET CORRECT RESULT 3446 032772 ..0166: ERROR (LOC,14,SCR1,SCR2,,TEST F5 - RESULT IS INCORRECT,APRINT)^SALL 3447 032772 036 14 0 00 041561 3448 032773 255 00 0 00 000000 3449 ^ 3450 ^ 3451 TFLAG ([^B0110B3],F5)^ 3452 3453 032774 200 13 0 00 032761 MOVE SCR1,FLAGL ;GET FLAGS 3454 032775 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 3455 032776 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3456 032777 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3457 ERROR (LOC,13,SCR2,FLAGL,,TEST F5 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3458 3459 033000 036 13 0 00 041610 3460 033001 255 00 0 00 000000 3461 ^ 3462 ^ 3463 ; ************************************************ 3464 3465 3466 ; ************************************************ 3467 3468 033002 LOC=. ;ERROR RETURN ADDRESS 3469 033237 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3470 033002 200 15 0 00 041613 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3471 033003 120 01 0 00 033237 DMOVE AC1,CNUM ;INIT AUGEND 3472 033004 255 17 0 00 033005 JFCL 17,.+1 ;CLEAR PC FLAGS 3473 033005 114 01 0 00 033241 DADD AC1,CNUM+2 ;ADD N + P = 0,1 3474 PCSAVE^ 3475 033006 264 00 0 00 033007 JSR .+1 ;STORE PC 3476 033007 FLAGL=. ;LOCATION OF PC 3477 033007 000000 000000 0 ;PC 3478 ^ 3479 CHECKA (LOC,F5,0,1)^ 3480 3481 033010 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3482 033011 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 3483 033012 254 00 0 00 033016 JRST ..0167 ;NO - GO TO ERROR HANDLING 3484 033013 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3485 033014 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 3486 033015 254 00 0 00 033021 JRST ..0170+1 ;YES - DONT DO ERROR HANDLING 3487 ; EXCEPT FOR ERLOOP 3488 3489 033016 200 14 0 13 000001 ..0167: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3490 033017 200 13 0 13 041126 MOVE SCR1,[EXP 0,1](SCR1) ;GET CORRECT RESULT 3491 033020 ..0170: ERROR (LOC,14,SCR1,SCR2,,TEST F5 - RESULT IS INCORRECT,APRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-26 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0099 3492 033020 036 14 0 00 041561 3493 033021 255 00 0 00 000000 3494 ^ 3495 ^ 3496 TFLAG ([^B0110B3],F5)^ 3497 3498 033022 200 13 0 00 033007 MOVE SCR1,FLAGL ;GET FLAGS 3499 033023 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 3500 033024 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3501 033025 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3502 ERROR (LOC,13,SCR2,FLAGL,,TEST F5 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3503 3504 033026 036 13 0 00 041614 3505 033027 255 00 0 00 000000 3506 ^ 3507 ^ 3508 ; ************************************************ 3509 3510 3511 ; ************************************************ 3512 3513 033030 LOC=. ;ERROR RETURN ADDRESS 3514 033243 CNUM=CNUM+4 ;ADDRESS OF TEST DATA 3515 033030 200 15 0 00 041617 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3516 033031 120 01 0 00 033243 DMOVE AC1,CNUM ;INIT AUGEND 3517 033032 255 17 0 00 033033 JFCL 17,.+1 ;CLEAR PC FLAGS 3518 033033 114 01 0 00 033245 DADD AC1,CNUM+2 ;ADD N + P = 0,1 3519 PCSAVE^ 3520 033034 264 00 0 00 033035 JSR .+1 ;STORE PC 3521 033035 FLAGL=. ;LOCATION OF PC 3522 033035 000000 000000 0 ;PC 3523 ^ 3524 CHECKA (LOC,F5,0,1)^ 3525 3526 033036 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3527 033037 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 3528 033040 254 00 0 00 033044 JRST ..0171 ;NO - GO TO ERROR HANDLING 3529 033041 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3530 033042 316 02 0 00 041127 CAMN AC1+1,[1] ;IS RIGHT HALF CORRECT? 3531 033043 254 00 0 00 033047 JRST ..0172+1 ;YES - DONT DO ERROR HANDLING 3532 ; EXCEPT FOR ERLOOP 3533 3534 033044 200 14 0 13 000001 ..0171: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3535 033045 200 13 0 13 041126 MOVE SCR1,[EXP 0,1](SCR1) ;GET CORRECT RESULT 3536 033046 ..0172: ERROR (LOC,14,SCR1,SCR2,,TEST F5 - RESULT IS INCORRECT,APRINT)^SALL 3537 033046 036 14 0 00 041561 3538 033047 255 00 0 00 000000 3539 ^ 3540 ^ 3541 TFLAG ([^B0110B3],F5)^ 3542 3543 033050 200 13 0 00 033035 MOVE SCR1,FLAGL ;GET FLAGS 3544 033051 200 14 0 00 041371 MOVE SCR2,[^B0110B3] ;SCR2 - CORRECT FLAGS 3545 033052 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3546 033053 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 8-27 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0100 3547 ERROR (LOC,13,SCR2,FLAGL,,TEST F5 - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3548 3549 033054 036 13 0 00 041620 3550 033055 255 00 0 00 000000 3551 ^ 3552 ^ 3553 ; ************************************************ 3554 3555 033056 254 00 0 00 033247 JRST AENDF ;SKIP OVER DATA DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 9 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0101 3556 3557 033057 000000 000000 ACONF1: EXP 0,0,0,1B0+1 3558 033060 000000 000000 3559 033061 000000 000000 3560 033062 400000 000001 3561 033063 000000 000000 EXP 0,1B0,0,1 3562 033064 400000 000000 3563 033065 000000 000000 3564 033066 000000 000001 3565 033067 000000 000000 EXP 0,1B0,0,1B0+1 3566 033070 400000 000000 3567 033071 000000 000000 3568 033072 400000 000001 3569 033073 000000 000000 EXP 0,0,-1,377777777777 3570 033074 000000 000000 3571 033075 777777 777777 3572 033076 377777 777777 3573 033077 000000 000000 EXP 0,1B0,-1,377777777777 3574 033100 400000 000000 3575 033101 777777 777777 3576 033102 377777 777777 3577 033103 000000 000000 EXP 0,1B0,-1,-1 3578 033104 400000 000000 3579 033105 777777 777777 3580 033106 777777 777777 3581 033107 777777 777777 ACONF2: EXP -1,377777777777,-2,-1 3582 033110 377777 777777 3583 033111 777777 777776 3584 033112 777777 777777 3585 033113 777777 777777 EXP -1,377777777777,-2,377777777777 3586 033114 377777 777777 3587 033115 777777 777776 3588 033116 377777 777777 3589 033117 777777 777777 EXP -1,-1,-2,377777777777 3590 033120 777777 777777 3591 033121 777777 777776 3592 033122 377777 777777 3593 033123 777777 777776 EXP -2,-1,-1,377777777777 3594 033124 777777 777777 3595 033125 777777 777777 3596 033126 377777 777777 3597 033127 777777 777776 EXP -2,377777777777,-1,377777777777 3598 033130 377777 777777 3599 033131 777777 777777 3600 033132 377777 777777 3601 033133 777777 777776 EXP -2,377777777777,-1,-1 3602 033134 377777 777777 3603 033135 777777 777777 3604 033136 777777 777777 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 10 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0102 3605 3606 033137 000000 000000 ACONF3: EXP 0,1B0+1,1,0 3607 033140 400000 000001 3608 033141 000000 000001 3609 033142 000000 000000 3610 033143 000000 000000 EXP 0,1B0+1,1,1B0 3611 033144 400000 000001 3612 033145 000000 000001 3613 033146 400000 000000 3614 033147 000000 000000 EXP 0,1,1,1B0 3615 033150 000000 000001 3616 033151 000000 000001 3617 033152 400000 000000 3618 033153 000000 000001 EXP 1,0,0,1B0+1 3619 033154 000000 000000 3620 033155 000000 000000 3621 033156 400000 000001 3622 033157 000000 000001 EXP 1,1B0,0,1B0+1 3623 033160 400000 000000 3624 033161 000000 000000 3625 033162 400000 000001 3626 033163 000000 000001 EXP 1,1B0,0,1 3627 033164 400000 000000 3628 033165 000000 000000 3629 033166 000000 000001 3630 033167 777777 777777 ACONF4: EXP -1,377777777776,0,1 3631 033170 377777 777776 3632 033171 000000 000000 3633 033172 000000 000001 3634 033173 777777 777777 EXP -1,377777777776,0,1B0+1 3635 033174 377777 777776 3636 033175 000000 000000 3637 033176 400000 000001 3638 033177 777777 777777 EXP -1,-2,0,1B0+1 3639 033200 777777 777776 3640 033201 000000 000000 3641 033202 400000 000001 3642 033203 000000 000000 EXP 0,1,-1,377777777776 3643 033204 000000 000001 3644 033205 777777 777777 3645 033206 377777 777776 3646 033207 000000 000000 EXP 0,1B0+1,-1,377777777776 3647 033210 400000 000001 3648 033211 777777 777777 3649 033212 377777 777776 3650 033213 000000 000000 EXP 0,1B0+1,-1,-2 3651 033214 400000 000001 3652 033215 777777 777777 3653 033216 777777 777776 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 11 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST F SEQ 0103 3654 3655 033217 777777 777777 ACONF5: EXP -1,377777777777,0,2 3656 033220 377777 777777 3657 033221 000000 000000 3658 033222 000000 000002 3659 033223 777777 777777 EXP -1,377777777777,0,1B0+2 3660 033224 377777 777777 3661 033225 000000 000000 3662 033226 400000 000002 3663 033227 777777 777777 EXP -1,-1,0,1B0+2 3664 033230 777777 777777 3665 033231 000000 000000 3666 033232 400000 000002 3667 033233 000000 000000 EXP 0,2,-1,377777777777 3668 033234 000000 000002 3669 033235 777777 777777 3670 033236 377777 777777 3671 033237 000000 000000 EXP 0,1B0+2,-1,377777777777 3672 033240 400000 000002 3673 033241 777777 777777 3674 033242 377777 777777 3675 033243 000000 000000 EXP 0,1B0+2,-1,-1 3676 033244 400000 000002 3677 033245 777777 777777 3678 033246 777777 777777 3679 033247 AENDF: DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 12 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST G SEQ 0104 3680 SUBTTL DADD - TEST G 3681 3682 ; ********************************************************************** 3683 ;*DADD - TEST G 3684 ;* 3685 ;* 2**N + (2**70 - 2**N) = 1000... (AROV & CARRY 1 SET) 3686 ;* (2**70 - 2**N) + 2**N = 1000... (AROV & CARRY 1 SET) 3687 ;* -2**N + (-2**70 + 2**N - 1) = 0111... (AROV & CARRY 0 SET) 3688 ;* (-2**70 + 2**N - 1) + -2**N = 0111... (AROV & CARRY 0 SET) 3689 ;* 3690 ;* THEST TESTS CHECK THE SETTING OF AROV & CARRY 1 AND AROV & 3691 ;* CARRY 0 FLAGS. CHECKED FOR BITS 0,34,36,70. 3692 ; ********************************************************************** 3693 3694 ; ********************************************************************** 3695 ;* THE FOLLOWING SECTION OF CODE IS REPEATED 8 TIMES. THE FIRST 3696 ;* 4 TESTS FLOAT A 1 ACROSS A DOUBLEWORD IN BITS 0,35,36,71. 3697 ;* THIS NUMBER IS THEN ADDED TO THE SMALLEST POSITIVE INTEGER 3698 ;* WHICH WILL PRODUCE AN OVERFLOW - THE RESULT IS A DOUBLEWORD 3699 ;* OF 0S WITH 1 IN THE SIGN BIT - WITH OVERFLOW & CARRY 1 SET. 3700 ;* THE NEXT 4 TESTS FLOAT A 0 ACROSS A DOUBLEWORD IN BITS 1, 3701 ;* 35,36,71 (A NEGATIVE NUMBER). THIS NUMBER IS ADDED TO THE 3702 ;* SMALLEST NEGATIVE INTEGER WHICH WILL PRODUCE AN OVERFLOW - 3703 ;* THE RESULT IS A DOUBLEWORD OF 1S WITH A 0 IN THE SIGN BIT - 3704 ;* WITH OVERFLOW AND CARRY 0 SET. 3705 ;* THE DOUBLEWORDS USED IN THIS TEST ARE LOCATED IN THE LIST 3706 ;* 'CONST2'. 3707 ; ********************************************************************** 3708 3709 033522 CNUM=ACONG-6 ;POINTER TO THE DOUBLEWORDS IN 3710 ; THE RESULT 3711 500000 000000 FLAGS=^B1010B3 ;AROV,CRY0,CRY1,FOV 3712 3713 REPEAT ^D8,< 3714 ; ************************************************ 3715 3716 CNUM=CNUM+6 ;CNUM POINTS TO THE TEST DATA 3717 LOC=. ;ERROR LOOP RETURN ADDRESS 3718 IFE ACONG-CNUM+^D24, ;FLAGS FOR SECOND 4 CASES 3719 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3720 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0/1 3721 JFCL 17,.+1 ;CLEAR PC FLAGS 3722 DADD AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 3723 PCSAVE 3724 CHECKB (LOC,G,CNUM+4) 3725 TFLAG ([FLAGS],G) 3726 ; ************************************************ 3727 > 3728 3729 ; ************************************************ 3730 3731 033530 CNUM=CNUM+6 ;CNUM POINTS TO THE TEST DATA 3732 033247 LOC=. ;ERROR LOOP RETURN ADDRESS 3733 IFE ACONG-CNUM+^D24, ;FLAGS FOR SECOND 4 CASES 3734 033247 200 15 0 00 041623 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 12-1 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST G SEQ 0105 3735 033250 120 01 0 00 033530 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0/1 3736 033251 255 17 0 00 033252 JFCL 17,.+1 ;CLEAR PC FLAGS 3737 033252 114 01 0 00 033532 DADD AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 3738 PCSAVE^ 3739 033253 264 00 0 00 033254 JSR .+1 ;STORE PC 3740 033254 FLAGL=. ;LOCATION OF PC 3741 033254 000000 000000 0 ;PC 3742 ^ 3743 CHECKB (LOC,G,CNUM+4)^ 3744 3745 033255 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3746 033256 312 01 0 00 033534 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 3747 033257 254 00 0 00 033263 JRST ..0173 ;NO - GO TO ERROR HANDLING 3748 033260 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3749 033261 316 02 0 00 033535 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 3750 033262 254 00 0 00 033266 JRST ..0174+1 ;YES - DONT DO ERROR HANDLING 3751 ; EXCEPT FOR ERLOOP 3752 3753 033263 200 14 0 13 000001 ..0173: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3754 033264 200 13 0 13 033534 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 3755 033265 ..0174: ERROR (LOC,14,SCR1,SCR2,,TEST G - RESULT IS INCORRECT,APRINT)^SALL 3756 033265 036 14 0 00 041631 3757 033266 255 00 0 00 000000 3758 ^ 3759 ^ 3760 TFLAG ([FLAGS],G)^ 3761 3762 033267 200 13 0 00 033254 MOVE SCR1,FLAGL ;GET FLAGS 3763 033270 200 14 0 00 041634 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 3764 033271 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3765 033272 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3766 ERROR (LOC,13,SCR2,FLAGL,,TEST G - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3767 033273 036 13 0 00 041644 3768 033274 255 00 0 00 000000 3769 ^ 3770 ^ 3771 ; ************************************************ 3772 3773 3774 ; ************************************************ 3775 3776 033536 CNUM=CNUM+6 ;CNUM POINTS TO THE TEST DATA 3777 033275 LOC=. ;ERROR LOOP RETURN ADDRESS 3778 IFE ACONG-CNUM+^D24, ;FLAGS FOR SECOND 4 CASES 3779 033275 200 15 0 00 041647 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3780 033276 120 01 0 00 033536 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0/1 3781 033277 255 17 0 00 033300 JFCL 17,.+1 ;CLEAR PC FLAGS 3782 033300 114 01 0 00 033540 DADD AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 3783 PCSAVE^ 3784 033301 264 00 0 00 033302 JSR .+1 ;STORE PC 3785 033302 FLAGL=. ;LOCATION OF PC 3786 033302 000000 000000 0 ;PC 3787 ^ 3788 CHECKB (LOC,G,CNUM+4)^ 3789 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 12-2 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST G SEQ 0106 3790 033303 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3791 033304 312 01 0 00 033542 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 3792 033305 254 00 0 00 033311 JRST ..0175 ;NO - GO TO ERROR HANDLING 3793 033306 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3794 033307 316 02 0 00 033543 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 3795 033310 254 00 0 00 033314 JRST ..0176+1 ;YES - DONT DO ERROR HANDLING 3796 ; EXCEPT FOR ERLOOP 3797 3798 033311 200 14 0 13 000001 ..0175: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3799 033312 200 13 0 13 033542 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 3800 033313 ..0176: ERROR (LOC,14,SCR1,SCR2,,TEST G - RESULT IS INCORRECT,APRINT)^SALL 3801 033313 036 14 0 00 041631 3802 033314 255 00 0 00 000000 3803 ^ 3804 ^ 3805 TFLAG ([FLAGS],G)^ 3806 3807 033315 200 13 0 00 033302 MOVE SCR1,FLAGL ;GET FLAGS 3808 033316 200 14 0 00 041634 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 3809 033317 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3810 033320 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3811 ERROR (LOC,13,SCR2,FLAGL,,TEST G - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3812 033321 036 13 0 00 041650 3813 033322 255 00 0 00 000000 3814 ^ 3815 ^ 3816 ; ************************************************ 3817 3818 3819 ; ************************************************ 3820 3821 033544 CNUM=CNUM+6 ;CNUM POINTS TO THE TEST DATA 3822 033323 LOC=. ;ERROR LOOP RETURN ADDRESS 3823 IFE ACONG-CNUM+^D24, ;FLAGS FOR SECOND 4 CASES 3824 033323 200 15 0 00 041653 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3825 033324 120 01 0 00 033544 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0/1 3826 033325 255 17 0 00 033326 JFCL 17,.+1 ;CLEAR PC FLAGS 3827 033326 114 01 0 00 033546 DADD AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 3828 PCSAVE^ 3829 033327 264 00 0 00 033330 JSR .+1 ;STORE PC 3830 033330 FLAGL=. ;LOCATION OF PC 3831 033330 000000 000000 0 ;PC 3832 ^ 3833 CHECKB (LOC,G,CNUM+4)^ 3834 3835 033331 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3836 033332 312 01 0 00 033550 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 3837 033333 254 00 0 00 033337 JRST ..0177 ;NO - GO TO ERROR HANDLING 3838 033334 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3839 033335 316 02 0 00 033551 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 3840 033336 254 00 0 00 033342 JRST ..0200+1 ;YES - DONT DO ERROR HANDLING 3841 ; EXCEPT FOR ERLOOP 3842 3843 033337 200 14 0 13 000001 ..0177: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3844 033340 200 13 0 13 033550 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 12-3 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST G SEQ 0107 3845 033341 ..0200: ERROR (LOC,14,SCR1,SCR2,,TEST G - RESULT IS INCORRECT,APRINT)^SALL 3846 033341 036 14 0 00 041631 3847 033342 255 00 0 00 000000 3848 ^ 3849 ^ 3850 TFLAG ([FLAGS],G)^ 3851 3852 033343 200 13 0 00 033330 MOVE SCR1,FLAGL ;GET FLAGS 3853 033344 200 14 0 00 041634 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 3854 033345 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3855 033346 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3856 ERROR (LOC,13,SCR2,FLAGL,,TEST G - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3857 033347 036 13 0 00 041654 3858 033350 255 00 0 00 000000 3859 ^ 3860 ^ 3861 ; ************************************************ 3862 3863 3864 ; ************************************************ 3865 3866 033552 CNUM=CNUM+6 ;CNUM POINTS TO THE TEST DATA 3867 033351 LOC=. ;ERROR LOOP RETURN ADDRESS 3868 IFE ACONG-CNUM+^D24, ;FLAGS FOR SECOND 4 CASES 3869 033351 200 15 0 00 041657 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3870 033352 120 01 0 00 033552 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0/1 3871 033353 255 17 0 00 033354 JFCL 17,.+1 ;CLEAR PC FLAGS 3872 033354 114 01 0 00 033554 DADD AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 3873 PCSAVE^ 3874 033355 264 00 0 00 033356 JSR .+1 ;STORE PC 3875 033356 FLAGL=. ;LOCATION OF PC 3876 033356 000000 000000 0 ;PC 3877 ^ 3878 CHECKB (LOC,G,CNUM+4)^ 3879 3880 033357 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3881 033360 312 01 0 00 033556 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 3882 033361 254 00 0 00 033365 JRST ..0201 ;NO - GO TO ERROR HANDLING 3883 033362 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3884 033363 316 02 0 00 033557 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 3885 033364 254 00 0 00 033370 JRST ..0202+1 ;YES - DONT DO ERROR HANDLING 3886 ; EXCEPT FOR ERLOOP 3887 3888 033365 200 14 0 13 000001 ..0201: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3889 033366 200 13 0 13 033556 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 3890 033367 ..0202: ERROR (LOC,14,SCR1,SCR2,,TEST G - RESULT IS INCORRECT,APRINT)^SALL 3891 033367 036 14 0 00 041631 3892 033370 255 00 0 00 000000 3893 ^ 3894 ^ 3895 TFLAG ([FLAGS],G)^ 3896 3897 033371 200 13 0 00 033356 MOVE SCR1,FLAGL ;GET FLAGS 3898 033372 200 14 0 00 041634 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 3899 033373 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 12-4 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST G SEQ 0108 3900 033374 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3901 ERROR (LOC,13,SCR2,FLAGL,,TEST G - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3902 033375 036 13 0 00 041660 3903 033376 255 00 0 00 000000 3904 ^ 3905 ^ 3906 ; ************************************************ 3907 3908 3909 ; ************************************************ 3910 3911 033560 CNUM=CNUM+6 ;CNUM POINTS TO THE TEST DATA 3912 033377 LOC=. ;ERROR LOOP RETURN ADDRESS 3913 600000 000000 IFE ACONG-CNUM+^D24, ;FLAGS FOR SECOND 4 CASES 3914 033377 200 15 0 00 041663 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3915 033400 120 01 0 00 033560 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0/1 3916 033401 255 17 0 00 033402 JFCL 17,.+1 ;CLEAR PC FLAGS 3917 033402 114 01 0 00 033562 DADD AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 3918 PCSAVE^ 3919 033403 264 00 0 00 033404 JSR .+1 ;STORE PC 3920 033404 FLAGL=. ;LOCATION OF PC 3921 033404 000000 000000 0 ;PC 3922 ^ 3923 CHECKB (LOC,G,CNUM+4)^ 3924 3925 033405 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3926 033406 312 01 0 00 033564 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 3927 033407 254 00 0 00 033413 JRST ..0203 ;NO - GO TO ERROR HANDLING 3928 033410 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3929 033411 316 02 0 00 033565 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 3930 033412 254 00 0 00 033416 JRST ..0204+1 ;YES - DONT DO ERROR HANDLING 3931 ; EXCEPT FOR ERLOOP 3932 3933 033413 200 14 0 13 000001 ..0203: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3934 033414 200 13 0 13 033564 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 3935 033415 ..0204: ERROR (LOC,14,SCR1,SCR2,,TEST G - RESULT IS INCORRECT,APRINT)^SALL 3936 033415 036 14 0 00 041631 3937 033416 255 00 0 00 000000 3938 ^ 3939 ^ 3940 TFLAG ([FLAGS],G)^ 3941 3942 033417 200 13 0 00 033404 MOVE SCR1,FLAGL ;GET FLAGS 3943 033420 200 14 0 00 041664 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 3944 033421 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3945 033422 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3946 ERROR (LOC,13,SCR2,FLAGL,,TEST G - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3947 033423 036 13 0 00 041665 3948 033424 255 00 0 00 000000 3949 ^ 3950 ^ 3951 ; ************************************************ 3952 3953 3954 ; ************************************************ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 12-5 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST G SEQ 0109 3955 3956 033566 CNUM=CNUM+6 ;CNUM POINTS TO THE TEST DATA 3957 033425 LOC=. ;ERROR LOOP RETURN ADDRESS 3958 IFE ACONG-CNUM+^D24, ;FLAGS FOR SECOND 4 CASES 3959 033425 200 15 0 00 041670 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 3960 033426 120 01 0 00 033566 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0/1 3961 033427 255 17 0 00 033430 JFCL 17,.+1 ;CLEAR PC FLAGS 3962 033430 114 01 0 00 033570 DADD AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 3963 PCSAVE^ 3964 033431 264 00 0 00 033432 JSR .+1 ;STORE PC 3965 033432 FLAGL=. ;LOCATION OF PC 3966 033432 000000 000000 0 ;PC 3967 ^ 3968 CHECKB (LOC,G,CNUM+4)^ 3969 3970 033433 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 3971 033434 312 01 0 00 033572 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 3972 033435 254 00 0 00 033441 JRST ..0205 ;NO - GO TO ERROR HANDLING 3973 033436 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 3974 033437 316 02 0 00 033573 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 3975 033440 254 00 0 00 033444 JRST ..0206+1 ;YES - DONT DO ERROR HANDLING 3976 ; EXCEPT FOR ERLOOP 3977 3978 033441 200 14 0 13 000001 ..0205: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 3979 033442 200 13 0 13 033572 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 3980 033443 ..0206: ERROR (LOC,14,SCR1,SCR2,,TEST G - RESULT IS INCORRECT,APRINT)^SALL 3981 033443 036 14 0 00 041631 3982 033444 255 00 0 00 000000 3983 ^ 3984 ^ 3985 TFLAG ([FLAGS],G)^ 3986 3987 033445 200 13 0 00 033432 MOVE SCR1,FLAGL ;GET FLAGS 3988 033446 200 14 0 00 041664 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 3989 033447 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 3990 033450 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 3991 ERROR (LOC,13,SCR2,FLAGL,,TEST G - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 3992 033451 036 13 0 00 041671 3993 033452 255 00 0 00 000000 3994 ^ 3995 ^ 3996 ; ************************************************ 3997 3998 3999 ; ************************************************ 4000 4001 033574 CNUM=CNUM+6 ;CNUM POINTS TO THE TEST DATA 4002 033453 LOC=. ;ERROR LOOP RETURN ADDRESS 4003 IFE ACONG-CNUM+^D24, ;FLAGS FOR SECOND 4 CASES 4004 033453 200 15 0 00 041674 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 4005 033454 120 01 0 00 033574 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0/1 4006 033455 255 17 0 00 033456 JFCL 17,.+1 ;CLEAR PC FLAGS 4007 033456 114 01 0 00 033576 DADD AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 4008 PCSAVE^ 4009 033457 264 00 0 00 033460 JSR .+1 ;STORE PC DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 12-6 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST G SEQ 0110 4010 033460 FLAGL=. ;LOCATION OF PC 4011 033460 000000 000000 0 ;PC 4012 ^ 4013 CHECKB (LOC,G,CNUM+4)^ 4014 4015 033461 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4016 033462 312 01 0 00 033600 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4017 033463 254 00 0 00 033467 JRST ..0207 ;NO - GO TO ERROR HANDLING 4018 033464 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4019 033465 316 02 0 00 033601 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4020 033466 254 00 0 00 033472 JRST ..0210+1 ;YES - DONT DO ERROR HANDLING 4021 ; EXCEPT FOR ERLOOP 4022 4023 033467 200 14 0 13 000001 ..0207: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4024 033470 200 13 0 13 033600 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4025 033471 ..0210: ERROR (LOC,14,SCR1,SCR2,,TEST G - RESULT IS INCORRECT,APRINT)^SALL 4026 033471 036 14 0 00 041631 4027 033472 255 00 0 00 000000 4028 ^ 4029 ^ 4030 TFLAG ([FLAGS],G)^ 4031 4032 033473 200 13 0 00 033460 MOVE SCR1,FLAGL ;GET FLAGS 4033 033474 200 14 0 00 041664 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 4034 033475 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 4035 033476 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 4036 ERROR (LOC,13,SCR2,FLAGL,,TEST G - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 4037 033477 036 13 0 00 041675 4038 033500 255 00 0 00 000000 4039 ^ 4040 ^ 4041 ; ************************************************ 4042 4043 4044 ; ************************************************ 4045 4046 033602 CNUM=CNUM+6 ;CNUM POINTS TO THE TEST DATA 4047 033501 LOC=. ;ERROR LOOP RETURN ADDRESS 4048 IFE ACONG-CNUM+^D24, ;FLAGS FOR SECOND 4 CASES 4049 033501 200 15 0 00 041700 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 4050 033502 120 01 0 00 033602 DMOVE AC1,CNUM ;INIT AUGEND TO FLOATING 0/1 4051 033503 255 17 0 00 033504 JFCL 17,.+1 ;CLEAR PC FLAGS 4052 033504 114 01 0 00 033604 DADD AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 4053 PCSAVE^ 4054 033505 264 00 0 00 033506 JSR .+1 ;STORE PC 4055 033506 FLAGL=. ;LOCATION OF PC 4056 033506 000000 000000 0 ;PC 4057 ^ 4058 CHECKB (LOC,G,CNUM+4)^ 4059 4060 033507 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4061 033510 312 01 0 00 033606 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4062 033511 254 00 0 00 033515 JRST ..0211 ;NO - GO TO ERROR HANDLING 4063 033512 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4064 033513 316 02 0 00 033607 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 12-7 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST G SEQ 0111 4065 033514 254 00 0 00 033520 JRST ..0212+1 ;YES - DONT DO ERROR HANDLING 4066 ; EXCEPT FOR ERLOOP 4067 4068 033515 200 14 0 13 000001 ..0211: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4069 033516 200 13 0 13 033606 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4070 033517 ..0212: ERROR (LOC,14,SCR1,SCR2,,TEST G - RESULT IS INCORRECT,APRINT)^SALL 4071 033517 036 14 0 00 041631 4072 033520 255 00 0 00 000000 4073 ^ 4074 ^ 4075 TFLAG ([FLAGS],G)^ 4076 4077 033521 200 13 0 00 033506 MOVE SCR1,FLAGL ;GET FLAGS 4078 033522 200 14 0 00 041664 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 4079 033523 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 4080 033524 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 4081 ERROR (LOC,13,SCR2,FLAGL,,TEST G - PC FLAGS INCORRECT (LEFT 4 BITS),APRINT)^SALL 4082 033525 036 13 0 00 041701 4083 033526 255 00 0 00 000000 4084 ^ 4085 ^ 4086 ; ************************************************ 4087 4088 033527 254 00 0 00 033610 JRST AENDG ;SKIP OVER DATA DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 13 DSKCFM MAC 26-Sep-79 15:49 DADD - TEST G SEQ 0112 4089 4090 ; ********************************************************************** 4091 ; 8 SETS OF 3 DOUBLEWORDS (AUDEND,ADDEND,RESULT) 4092 ; ********************************************************************** 4093 4094 033530 200000 000000 ACONG: EXP 1B1,0,1B1,0,1B0,1B0 4095 033531 000000 000000 4096 033532 200000 000000 4097 033533 000000 000000 4098 033534 400000 000000 4099 033535 400000 000000 4100 033536 000000 000001 EXP 1,0,377777777777,0,1B0,1B0 4101 033537 000000 000000 4102 033540 377777 777777 4103 033541 000000 000000 4104 033542 400000 000000 4105 033543 400000 000000 4106 033544 000000 000000 EXP 0,1B1,377777777777,1B1,1B0,1B0 4107 033545 200000 000000 4108 033546 377777 777777 4109 033547 200000 000000 4110 033550 400000 000000 4111 033551 400000 000000 4112 033552 000000 000000 EXP 0,1,377777777777,377777777777,1B0,1B0 4113 033553 000000 000001 4114 033554 377777 777777 4115 033555 377777 777777 4116 033556 400000 000000 4117 033557 400000 000000 4118 033560 400000 000000 EXP 1B0,1B0,-1,-1,377777777777,377777777777 4119 033561 400000 000000 4120 033562 777777 777777 4121 033563 777777 777777 4122 033564 377777 777777 4123 033565 377777 777777 4124 033566 400000 000000 EXP 1B0,-1,-1,1B0,377777777777,377777777777 4125 033567 777777 777777 4126 033570 777777 777777 4127 033571 400000 000000 4128 033572 377777 777777 4129 033573 377777 777777 4130 033574 400000 000001 EXP 1B0+1,1B0,-2,1B0,377777777777,0 4131 033575 400000 000000 4132 033576 777777 777776 4133 033577 400000 000000 4134 033600 377777 777777 4135 033601 000000 000000 4136 033602 777777 777777 EXP -1,-1,1B0,1B0,377777777777,377777777777 4137 033603 777777 777777 4138 033604 400000 000000 4139 033605 400000 000000 4140 033606 377777 777777 4141 033607 377777 777777 4142 033610 AENDG: DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 14 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST A SEQ 0113 4143 SUBTTL DSUB - TEST A 4144 SALL 4145 041704 T=SIXBTZ 4146 LALL 4147 ; ********************************************************************** 4148 ;*DSUB - TEST A 4149 ;* 4150 ;* 0,# - 0,0 = 0,# GENERAL TESTING TO SEE THAT 4151 ;* #,0 - 0,0 = #,0 DSUB CAN HANDLE DOUBLEWORDS 4152 ;* #,# - 0,0 = #,# 4153 ;* 0,0 - 0,# = -(0,#) 4154 ;* 0,0 - #,0 = -(#,0) 4155 ;* 0,0 - #,# = -(#,#) 4156 ; ********************************************************************** 4157 4158 ; ********************************************************************** 4159 ; ---------- DSUB (0,#) - (0,0) = (0,#) ---------- 4160 ; ********************************************************************** 4161 4162 033610 200 15 0 00 041024 STEST1: MOVE SCR3,[[EXP 0,NUM],,[EXP 0,0]] ;ADDR FOR SPRINT 4163 033611 120 01 0 00 041020 DMOVE AC1,[EXP 0,NUM] ;INIT MINUEND TO (0,#) 4164 033612 115 01 0 00 041022 DSUB AC1,[EXP 0,0] ;SUB (0,#)-(0,0) 4165 CHECKS (STEST1,A1,0,NUM)^ 4166 4167 033613 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4168 033614 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 4169 033615 254 00 0 00 033621 JRST ..0213 ;NO - GO TO ERROR HANDLING 4170 033616 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4171 033617 316 02 0 00 041021 CAMN AC1+1,[NUM] ;IS RIGHT HALF CORRECT? 4172 033620 254 00 0 00 033624 JRST ..0214+1 ;YES - DONT DO ERROR HANDLING 4173 ; EXCEPT FOR ERLOOP 4174 4175 033621 200 14 0 13 000001 ..0213: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4176 033622 200 13 0 13 041020 MOVE SCR1,[EXP 0,NUM](SCR1) ;GET CORRECT RESULT 4177 033623 ..0214: ERROR (STEST1,14,SCR1,SCR2,,TEST A1 - RESULT IS INCORRECT,SPRINT)^SALL 4178 033623 036 14 0 00 041706 4179 033624 255 00 0 00 000000 4180 ^ 4181 ^ 4182 4183 ; ********************************************************************** 4184 ; ---------- DSUB (#,0) - (0,0) = (#,0) ---------- 4185 ; ********************************************************************** 4186 4187 033625 200 15 0 00 041036 STEST2: MOVE SCR3,[[EXP NUM,0],,[EXP 0,0]] ;ADDR FOR SPRINT 4188 033626 120 01 0 00 041021 DMOVE AC1,[EXP NUM,0] ;INIT MINUEND TO (#,0) 4189 033627 115 01 0 00 041022 DSUB AC1,[EXP 0,0] ;SUB (#,0)-(0,0) 4190 CHECKS (STEST2,A2,NUM,0)^ 4191 4192 033630 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4193 033631 312 01 0 00 041021 CAME AC1,[NUM] ;IS LEFT HALF OF RESULT CORRECT? 4194 033632 254 00 0 00 033636 JRST ..0215 ;NO - GO TO ERROR HANDLING 4195 033633 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4196 033634 316 02 0 00 041020 CAMN AC1+1,[0] ;IS RIGHT HALF CORRECT? 4197 033635 254 00 0 00 033641 JRST ..0216+1 ;YES - DONT DO ERROR HANDLING DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 14-1 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST A SEQ 0114 4198 ; EXCEPT FOR ERLOOP 4199 4200 033636 200 14 0 13 000001 ..0215: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4201 033637 200 13 0 13 041021 MOVE SCR1,[EXP NUM,0](SCR1) ;GET CORRECT RESULT 4202 033640 ..0216: ERROR (STEST2,14,SCR1,SCR2,,TEST A2 - RESULT IS INCORRECT,SPRINT)^SALL 4203 033640 036 14 0 00 041711 4204 033641 255 00 0 00 000000 4205 ^ 4206 ^ 4207 4208 ; ********************************************************************** 4209 ; ---------- DSUB (#,#) - (0,0) = (#,#) ---------- 4210 ; ********************************************************************** 4211 4212 033642 200 15 0 00 041051 STEST3: MOVE SCR3,[[EXP NUM,NUM],,[EXP 0,0]] ;ADDR FOR SPRINT 4213 033643 120 01 0 00 041047 DMOVE AC1,[EXP NUM,NUM] ;INIT MINUEND TO (#,#) 4214 033644 115 01 0 00 041022 DSUB AC1,[EXP 0,0] ;SUB (#,#)-(0,0) 4215 CHECKS (STEST3,A3,NUM,NUM)^ 4216 4217 033645 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4218 033646 312 01 0 00 041021 CAME AC1,[NUM] ;IS LEFT HALF OF RESULT CORRECT? 4219 033647 254 00 0 00 033653 JRST ..0217 ;NO - GO TO ERROR HANDLING 4220 033650 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4221 033651 316 02 0 00 041021 CAMN AC1+1,[NUM] ;IS RIGHT HALF CORRECT? 4222 033652 254 00 0 00 033656 JRST ..0220+1 ;YES - DONT DO ERROR HANDLING 4223 ; EXCEPT FOR ERLOOP 4224 4225 033653 200 14 0 13 000001 ..0217: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4226 033654 200 13 0 13 041047 MOVE SCR1,[EXP NUM,NUM](SCR1) ;GET CORRECT RESULT 4227 033655 ..0220: ERROR (STEST3,14,SCR1,SCR2,,TEST A3 - RESULT IS INCORRECT,SPRINT)^SALL 4228 033655 036 14 0 00 041714 4229 033656 255 00 0 00 000000 4230 ^ 4231 ^ 4232 4233 ; ********************************************************************** 4234 ; ---------- DSUB (0,0) - (0,#) = (-1,-#) ---------- 4235 ; ********************************************************************** 4236 4237 033657 200 15 0 00 041062 STEST4: MOVE SCR3,[[EXP 0,0],,[EXP 0,NUM]] ;ADDR FOR SPRINT 4238 033660 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT MINUEND TO (0,0) 4239 033661 115 01 0 00 041020 DSUB AC1,[EXP 0,NUM] ;SUB (0,0) - (0,#) 4240 CHECKS (STEST4,A4,-1,-NUM)^ 4241 4242 033662 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4243 033663 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 4244 033664 254 00 0 00 033670 JRST ..0221 ;NO - GO TO ERROR HANDLING 4245 033665 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4246 033666 316 02 0 00 041717 CAMN AC1+1,[-NUM] ;IS RIGHT HALF CORRECT? 4247 033667 254 00 0 00 033673 JRST ..0222+1 ;YES - DONT DO ERROR HANDLING 4248 ; EXCEPT FOR ERLOOP 4249 4250 033670 200 14 0 13 000001 ..0221: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4251 033671 200 13 0 13 041720 MOVE SCR1,[EXP -1,-NUM](SCR1) ;GET CORRECT RESULT 4252 033672 ..0222: ERROR (STEST4,14,SCR1,SCR2,,TEST A4 - RESULT IS INCORRECT,SPRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 14-2 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST A SEQ 0115 4253 033672 036 14 0 00 041722 4254 033673 255 00 0 00 000000 4255 ^ 4256 ^ 4257 4258 ; ********************************************************************** 4259 ; ---------- DSUB (0,0) - (#,0) = (-#,0) ---------- 4260 ; ********************************************************************** 4261 4262 033674 200 15 0 00 041073 STEST5: MOVE SCR3,[[EXP 0,0],,[EXP NUM,0]] ;ADDR FOR SPRINT 4263 033675 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT MINUEND TO (0,0) 4264 033676 115 01 0 00 041021 DSUB AC1,[EXP NUM,0] ;SUB (0,0) - (#,0) 4265 CHECKS (STEST5,A5,-NUM,400000000000)^ 4266 4267 033677 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4268 033700 312 01 0 00 041717 CAME AC1,[-NUM] ;IS LEFT HALF OF RESULT CORRECT? 4269 033701 254 00 0 00 033705 JRST ..0223 ;NO - GO TO ERROR HANDLING 4270 033702 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4271 033703 316 02 0 00 041725 CAMN AC1+1,[400000000000] ;IS RIGHT HALF CORRECT? 4272 033704 254 00 0 00 033710 JRST ..0224+1 ;YES - DONT DO ERROR HANDLING 4273 ; EXCEPT FOR ERLOOP 4274 4275 033705 200 14 0 13 000001 ..0223: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4276 033706 200 13 0 13 041726 MOVE SCR1,[EXP -NUM,400000000000](SCR1) ;GET CORRECT RESULT 4277 033707 ..0224: ERROR (STEST5,14,SCR1,SCR2,,TEST A5 - RESULT IS INCORRECT,SPRINT)^SALL 4278 033707 036 14 0 00 041730 4279 033710 255 00 0 00 000000 4280 ^ 4281 ^ 4282 4283 ; ********************************************************************** 4284 ; ---------- DSUB (0,0) - (#,#) = -(#,#) ---------- 4285 ; ********************************************************************** 4286 4287 033711 200 15 0 00 041104 STEST6: MOVE SCR3,[[EXP 0,0],,[EXP NUM,NUM]] ;ADDR FOR SPRINT 4288 033712 403 01 0 00 000002 SETZB AC1,AC1+1 ;INIT MINUEND TO (0,0) 4289 033713 115 01 0 00 041047 DSUB AC1,[EXP NUM,NUM] ;SUB (0,0)-(#,#) 4290 CHECKS (STEST6,A6,-NUM-1,-NUM)^ 4291 4292 033714 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4293 033715 312 01 0 00 041733 CAME AC1,[-NUM-1] ;IS LEFT HALF OF RESULT CORRECT? 4294 033716 254 00 0 00 033722 JRST ..0225 ;NO - GO TO ERROR HANDLING 4295 033717 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4296 033720 316 02 0 00 041717 CAMN AC1+1,[-NUM] ;IS RIGHT HALF CORRECT? 4297 033721 254 00 0 00 033725 JRST ..0226+1 ;YES - DONT DO ERROR HANDLING 4298 ; EXCEPT FOR ERLOOP 4299 4300 033722 200 14 0 13 000001 ..0225: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4301 033723 200 13 0 13 041733 MOVE SCR1,[EXP -NUM-1,-NUM](SCR1) ;GET CORRECT RESULT 4302 033724 ..0226: ERROR (STEST6,14,SCR1,SCR2,,TEST A6 - RESULT IS INCORRECT,SPRINT)^SALL 4303 033724 036 14 0 00 041735 4304 033725 255 00 0 00 000000 4305 ^ 4306 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 15 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST B SEQ 0116 4307 SUBTTL DSUB - TEST B 4308 4309 ; ********************************************************************** 4310 ;*DSUB - TEST B 4311 ;* 4312 ;* TEST ALL PERMUTATIONS OF 0,1,-1 IN THE MINUEND AND 4313 ;* SUBTRAHEND -- TEST: 4314 ;* 0,0 - 0,0 0,1 - 0,0 0,-1 - 0,0 .... 4315 ;* 0,0 - 0,1 0,1 - 0,1 0,-1 - 0,1 .... 4316 ;* 0,0 - 0,-1 0,1 - 0,-1 0,-1 - 0,-1 .... 4317 ;* 0,0 - 1,0 .... .... .... 4318 ;* 0,0 - 1,1 .... .... .... 4319 ;* 0,0 - 1,-1 .... .... .... 4320 ;* 0,0 - -1,0 .... .... .... 4321 ;* 0,0 - -1,1 .... .... .... 4322 ;* 0,0 - -1,-1 .... .... .... 4323 ; ********************************************************************** 4324 4325 ; ********************************************************************** 4326 ;* THESE COMBINATIONS TEST THE ABILITY OF THE DSUB TO HANDLE 4327 ;* BORROWS FROM THE NEXT WORD AND SIGNS CHANGING. THE RESULT 4328 ;* IS VERIFIED AND THE PC FLAGS ARE CHECKED TO SEE THAT THEY 4329 ;* ARE SET PROPERLY. 4330 ; ********************************************************************** 4331 4332 ; ********************************************************************** 4333 ;*PROCEDURE - (1) SET UP A POINTER 'MINU' TO SEQUENCE THE MINUEND 4334 ;* (2) LOOP ON MINUEND 4335 ;* (3) SET UP A POINTER 'SUBTR' TO SEQUENCE THE SUBTRAHEND 4336 ;* (4) LOOP ON SUBTRAHEND 4337 ;* (5) CALCULATE THE EXPECTED RESULT OF THE DSUB 4338 ;* (6) DO DSUB 4339 ;* (7) COMPARE RESULTS - ACTUAL VS. EXPECTED 4340 ;* (8) TEST FLAGS 4341 ;* (9) CONTINUE AT (4) 4342 ; ********************************************************************** 4343 4344 000003 MINU=AC1+2 ;MINU - POINTS TO MINUEND 4345 000004 SUBTR=MINU+1 ;SUBTR - POINTS TO SUBTRAHEND 4346 000012 SCR0=SCR0 ;SCR0 - SCRATCH ACS 4347 4348 ; ********************************************************************** 4349 ;INITIALIZE LOOPS - OUTERMOST ON MINUEND 4350 ; INNERMOST ON SUBTRAHEND 4351 ; ********************************************************************** 4352 4353 033726 200 03 0 00 041740 MOVE MINU,[-^D10,,SUBT-2] ;LEFT HALF - # WORDS IN LIST + 1 4354 ;RIGHT HALF - ADDRESS OF LIST 4355 033727 350 00 0 00 000003 OLOOP: AOS MINU ;ADD 2 TO ADDRESS (DOUBLEWORD) 4356 033730 252 03 0 00 034040 AOBJP MINU,BDONE ;ALL DONE WHEN COUNT = 0 4357 033731 552 03 0 00 034036 HRRZM MINU,IMINU ;SET UP MINU INDIRECT ADDR 4358 033732 200 04 0 00 041740 MOVE SUBTR,[-^D10,,SUBT-2] ;LEFT HALF - # WORDS IN LIST + 1 4359 ;RIGHT HALF - ADDRESS OF LIST 4360 033733 350 00 0 00 000004 ILOOP: AOS SUBTR ;ADD 2 TO ADDRESS (DOUBLEWORD) 4361 033734 252 04 0 00 033727 AOBJP SUBTR,OLOOP ;DONE WITH INNER LOOP WHEN COUNT DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 15-1 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST B SEQ 0117 4362 ; REACHES 0 - BACK TO OUTER LOOP 4363 033735 552 04 0 00 034037 HRRZM SUBTR,ISUBTR ;SET UP SUBTR INDIRECT ADDR 4364 033736 514 15 0 00 000003 HRLZ SCR3,MINU ;SCR3 - ADDR FOR ADDL ERROR PRINT 4365 033737 540 15 0 00 000004 HRR SCR3,SUBTR ; (MINU,,SUBTR) 4366 4367 ; ********************************************************************** 4368 ;ACTUAL TEST SECTION (STEPS 1-7 OF ABOVE DESCRIPTION) 4369 ; ********************************************************************** 4370 4371 033740 120 01 1 00 034036 BTESTB: DMOVE AC1,@IMINU ;GET MINUEND 4372 033741 120 12 1 00 034037 DMOVE SCR0,@ISUBTR ;GET SUBTRAHEND TO CALC EXPECTED 4373 033742 450 12 0 00 000000 SETCA SCR0, ;1-S COMPLEMENT OF LEFT WORD 4374 033743 450 13 0 00 000000 SETCA SCR1, ;1-S COMPLEMENT OF RIGHT WORD 4375 033744 114 12 0 00 000001 DADD SCR0,AC1 ;RESULT-1 (USED 1'S COMPLEMENT) 4376 033745 114 12 0 00 041126 DADD SCR0,[EXP 0,1] ;GET RESULT 4377 033746 255 17 0 00 033747 JFCL 17,.+1 ;CLEAR PC FLAGS 4378 033747 400 14 0 00 000000 SETZ SCR2, ;POINTER TO INCORRECT WORD IN RESULT 4379 4380 033750 115 01 1 00 034037 DSUB AC1,@ISUBTR ;DO THE SUBTRACTION 4381 4382 PCSAVE^ 4383 033751 264 00 0 00 033752 JSR .+1 ;STORE PC 4384 033752 FLAGL=. ;LOCATION OF PC 4385 033752 000000 000000 0 ;PC 4386 ^ 4387 033753 312 01 0 00 000012 CAME AC1,SCR0 ;LEFT WORD CORRECT? 4388 033754 254 00 0 00 033760 JRST BERROR 4389 033755 201 14 0 00 000001 MOVEI SCR2,1 ;POINTER TO INCORRECT WORD IN RESULT 4390 033756 316 02 0 00 000013 CAMN AC1+1,SCR1 ;RIGHT WORD CORRECT? 4391 033757 254 00 0 00 033764 JRST BFLAG ;YES - NOW TEST PC FLAGS 4392 4393 033760 200 12 0 14 000012 BERROR: MOVE SCR0,SCR0(SCR2) ;GET CORRECT RESULT FOR ADDL PRINT 4394 033761 200 13 0 14 000001 MOVE SCR1,AC1(SCR2) ;GET ACTUAL (INCORRECT) RESULT 4395 ERROR (BTESTB ,14,SCR0,SCR1,,TEST B - RESULT INCORRECT,SPRINT)^SALL 4396 033762 036 14 0 00 041746 4397 033763 255 00 0 00 000000 4398 ^ 4399 4400 033764 550 14 0 00 033752 BFLAG: HRRZ SCR2,FLAGL ;SCR2 - PC WITH 0000 FLAGS 4401 033765 120 12 1 00 034037 DMOVE SCR0,@ISUBTR ;GET SUBTRAHEND 4402 033766 444 12 1 00 034036 EQV SCR0,@IMINU ;LEFT BIT IS 1 IF SIGNS SAME 4403 033767 603 12 0 00 400000 TLNE SCR0,400000 ;IS LEFT BIT A 1? (SIGNS SAME) 4404 033770 254 00 0 00 033775 JRST BSAME ;YES - GO COMPARE MINU VS. SUBTR 4405 033771 331 00 1 00 034036 SKIPL @IMINU ;NO - IS MINUEND < 0 4406 033772 254 00 0 00 034005 JRST BDONEI ;NO - CORRECT FLAGS ARE 0000 4407 4408 033773 505 14 0 00 300000 BFSET: HRLI SCR2,300000 ;YES - CORRECT FLAGS ARE 0110 4409 033774 254 00 0 00 034005 JRST BDONEI ;CORRECT FLAGS CALC IS DONE 4410 4411 033775 120 12 1 00 034036 BSAME: DMOVE SCR0,@IMINU ;SIGNS ARE SAME - GET MINUEND 4412 033776 315 12 1 00 034037 CAMGE SCR0,@ISUBTR ;MINUEND >= SUBTRA? (LEFT WORD) 4413 033777 254 00 0 00 034005 JRST BDONEI ;NO - FLAGS ARE 0000 4414 034000 312 12 1 00 034037 CAME SCR0,@ISUBTR ;MINUEND = SUBTRA? (LEFT WORD) 4415 034001 254 00 0 00 033773 JRST BFSET ;NO - MIN > SUBTR - FLAGS 0110 4416 034002 350 00 0 00 034037 AOS ISUBTR ;1ST WORDS ARE = SO LOOK AT 2ND DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 15-2 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST B SEQ 0118 4417 034003 311 13 1 00 034037 CAML SCR1,@ISUBTR ;MINUEND < SUBTRAHEND? 4418 034004 254 00 0 00 033773 JRST BFSET ;NO - FLAGS ARE 0110 4419 4420 034005 BDONEI: TFLAG (SCR2,B,SPRINT,BTESTB)^ 4421 4422 034005 200 13 0 00 033752 MOVE SCR1,FLAGL ;GET FLAGS 4423 034006 200 14 0 00 000014 MOVE SCR2,SCR2 ;SCR2 - CORRECT FLAGS 4424 034007 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 4425 034010 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 4426 ERROR (BTESTB,13,SCR2,FLAGL,,TEST B - PC FLAGS INCORRECT (LEFT 4 BITS),SPRINT)^SA 4427 LL 4428 034011 036 13 0 00 041760 4429 034012 255 00 0 00 000000 4430 ^ 4431 ^ 4432 034013 254 00 0 00 033733 JRST ILOOP ;END OF TEST - GOTO NEXT ONE 4433 4434 034014 000000 000000 SUBT: EXP 0,0,0,1,0,377777777777 4435 034015 000000 000000 4436 034016 000000 000000 4437 034017 000000 000001 4438 034020 000000 000000 4439 034021 377777 777777 4440 034022 000000 000001 EXP 1,0,1,1,1,377777777777 4441 034023 000000 000000 4442 034024 000000 000001 4443 034025 000000 000001 4444 034026 000000 000001 4445 034027 377777 777777 4446 034030 777777 777777 EXP -1,1B0,-1,1B0+1,-1,-1 4447 034031 400000 000000 4448 034032 777777 777777 4449 034033 400000 000001 4450 034034 777777 777777 4451 034035 777777 777777 4452 034036 000000 000000 IMINU: 0 4453 034037 000000 000000 ISUBTR: 0 4454 034040 BDONE: DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0119 4455 SUBTTL DSUB - TEST C 4456 4457 ; ********************************************************************** 4458 ;*DSUB - TEST C 4459 ;* 4460 ;* THE FOLLOWING TESTS VERIFY THAT THE DSUB INSTRUCTION HANDLES 4461 ;* THE SIGN OF THE RESULT PROPERLY (COPYING THE SIGN INTO THE 4462 ;* HIGH ORDER BIT OF EACH WORD OF THE DOUBLEWORD RESULT. THE 4463 ;* TESTS SUBTRACT VARIOUS COMBINATIONS OF INCONSISTENT SIGNS 4464 ;* IN THE SUBTRAHEND AND MINUEND AND VERIFY THAT THE SIGNS OF 4465 ;* THE RESULT ARE CORRECT. 4466 ;* 4467 ;* THERE ARE 5 SETS OF TEST: (1) 0 - P/N = N/P 4468 ;* (2) N - N = P/N 4469 ;* (3) P - P = N/P 4470 ;* (4) N - P = N/P 4471 ;* (5) N - P = N/P 4472 ;* WHERE N-NEGATIVE NUMBER 4473 ;* P-POSITIVE NUMBER 4474 ; ********************************************************************** 4475 4476 ; ********************************************************************** 4477 ; ---------- DSUB - TEST C-1: 0 - P/N = N/P ---------- 4478 ; ********************************************************************** 4479 4480 034641 CNUM=SCONC1-6 4481 4482 REPEAT 6,< 4483 ; ************************************************ 4484 4485 LOC=. ;ERROR RETURN ADDRESS 4486 CNUM=CNUM+6 ;ADDRESS OF TEST DATA 4487 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4488 DMOVE AC1,CNUM ;INIT MINUEND 4489 DSUB AC1,CNUM+2 ;SUB N - P 4490 CHECKT (LOC,C1,CNUM+4) 4491 ; ************************************************ 4492 > 4493 4494 ; ************************************************ 4495 4496 034040 LOC=. ;ERROR RETURN ADDRESS 4497 034647 CNUM=CNUM+6 ;ADDRESS OF TEST DATA 4498 034040 200 15 0 00 041763 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4499 034041 120 01 0 00 034647 DMOVE AC1,CNUM ;INIT MINUEND 4500 034042 115 01 0 00 034651 DSUB AC1,CNUM+2 ;SUB N - P 4501 CHECKT (LOC,C1,CNUM+4)^ 4502 4503 034043 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4504 034044 312 01 0 00 034653 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4505 034045 254 00 0 00 034051 JRST ..0227 ;NO - GO TO ERROR HANDLING 4506 034046 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4507 034047 316 02 0 00 034654 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4508 034050 254 00 0 00 034054 JRST ..0230+1 ;YES - DONT DO ERROR HANDLING 4509 ; EXCEPT FOR ERLOOP DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-1 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0120 4510 4511 034051 200 14 0 13 000001 ..0227: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4512 034052 200 13 0 13 034653 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4513 034053 ..0230: ERROR (LOC,14,SCR1,SCR2,,TEST C1 - RESULT IS INCORRECT,SPRINT)^SALL 4514 034053 036 14 0 00 041771 4515 034054 255 00 0 00 000000 4516 ^ 4517 ^ 4518 ; ************************************************ 4519 4520 4521 ; ************************************************ 4522 4523 034055 LOC=. ;ERROR RETURN ADDRESS 4524 034655 CNUM=CNUM+6 ;ADDRESS OF TEST DATA 4525 034055 200 15 0 00 041774 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4526 034056 120 01 0 00 034655 DMOVE AC1,CNUM ;INIT MINUEND 4527 034057 115 01 0 00 034657 DSUB AC1,CNUM+2 ;SUB N - P 4528 CHECKT (LOC,C1,CNUM+4)^ 4529 4530 034060 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4531 034061 312 01 0 00 034661 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4532 034062 254 00 0 00 034066 JRST ..0231 ;NO - GO TO ERROR HANDLING 4533 034063 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4534 034064 316 02 0 00 034662 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4535 034065 254 00 0 00 034071 JRST ..0232+1 ;YES - DONT DO ERROR HANDLING 4536 ; EXCEPT FOR ERLOOP 4537 4538 034066 200 14 0 13 000001 ..0231: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4539 034067 200 13 0 13 034661 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4540 034070 ..0232: ERROR (LOC,14,SCR1,SCR2,,TEST C1 - RESULT IS INCORRECT,SPRINT)^SALL 4541 034070 036 14 0 00 041771 4542 034071 255 00 0 00 000000 4543 ^ 4544 ^ 4545 ; ************************************************ 4546 4547 4548 ; ************************************************ 4549 4550 034072 LOC=. ;ERROR RETURN ADDRESS 4551 034663 CNUM=CNUM+6 ;ADDRESS OF TEST DATA 4552 034072 200 15 0 00 041775 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4553 034073 120 01 0 00 034663 DMOVE AC1,CNUM ;INIT MINUEND 4554 034074 115 01 0 00 034665 DSUB AC1,CNUM+2 ;SUB N - P 4555 CHECKT (LOC,C1,CNUM+4)^ 4556 4557 034075 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4558 034076 312 01 0 00 034667 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4559 034077 254 00 0 00 034103 JRST ..0233 ;NO - GO TO ERROR HANDLING 4560 034100 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4561 034101 316 02 0 00 034670 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4562 034102 254 00 0 00 034106 JRST ..0234+1 ;YES - DONT DO ERROR HANDLING 4563 ; EXCEPT FOR ERLOOP 4564 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-2 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0121 4565 034103 200 14 0 13 000001 ..0233: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4566 034104 200 13 0 13 034667 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4567 034105 ..0234: ERROR (LOC,14,SCR1,SCR2,,TEST C1 - RESULT IS INCORRECT,SPRINT)^SALL 4568 034105 036 14 0 00 041771 4569 034106 255 00 0 00 000000 4570 ^ 4571 ^ 4572 ; ************************************************ 4573 4574 4575 ; ************************************************ 4576 4577 034107 LOC=. ;ERROR RETURN ADDRESS 4578 034671 CNUM=CNUM+6 ;ADDRESS OF TEST DATA 4579 034107 200 15 0 00 041776 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4580 034110 120 01 0 00 034671 DMOVE AC1,CNUM ;INIT MINUEND 4581 034111 115 01 0 00 034673 DSUB AC1,CNUM+2 ;SUB N - P 4582 CHECKT (LOC,C1,CNUM+4)^ 4583 4584 034112 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4585 034113 312 01 0 00 034675 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4586 034114 254 00 0 00 034120 JRST ..0235 ;NO - GO TO ERROR HANDLING 4587 034115 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4588 034116 316 02 0 00 034676 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4589 034117 254 00 0 00 034123 JRST ..0236+1 ;YES - DONT DO ERROR HANDLING 4590 ; EXCEPT FOR ERLOOP 4591 4592 034120 200 14 0 13 000001 ..0235: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4593 034121 200 13 0 13 034675 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4594 034122 ..0236: ERROR (LOC,14,SCR1,SCR2,,TEST C1 - RESULT IS INCORRECT,SPRINT)^SALL 4595 034122 036 14 0 00 041771 4596 034123 255 00 0 00 000000 4597 ^ 4598 ^ 4599 ; ************************************************ 4600 4601 4602 ; ************************************************ 4603 4604 034124 LOC=. ;ERROR RETURN ADDRESS 4605 034677 CNUM=CNUM+6 ;ADDRESS OF TEST DATA 4606 034124 200 15 0 00 041777 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4607 034125 120 01 0 00 034677 DMOVE AC1,CNUM ;INIT MINUEND 4608 034126 115 01 0 00 034701 DSUB AC1,CNUM+2 ;SUB N - P 4609 CHECKT (LOC,C1,CNUM+4)^ 4610 4611 034127 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4612 034130 312 01 0 00 034703 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4613 034131 254 00 0 00 034135 JRST ..0237 ;NO - GO TO ERROR HANDLING 4614 034132 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4615 034133 316 02 0 00 034704 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4616 034134 254 00 0 00 034140 JRST ..0240+1 ;YES - DONT DO ERROR HANDLING 4617 ; EXCEPT FOR ERLOOP 4618 4619 034135 200 14 0 13 000001 ..0237: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-3 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0122 4620 034136 200 13 0 13 034703 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4621 034137 ..0240: ERROR (LOC,14,SCR1,SCR2,,TEST C1 - RESULT IS INCORRECT,SPRINT)^SALL 4622 034137 036 14 0 00 041771 4623 034140 255 00 0 00 000000 4624 ^ 4625 ^ 4626 ; ************************************************ 4627 4628 4629 ; ************************************************ 4630 4631 034141 LOC=. ;ERROR RETURN ADDRESS 4632 034705 CNUM=CNUM+6 ;ADDRESS OF TEST DATA 4633 034141 200 15 0 00 042000 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4634 034142 120 01 0 00 034705 DMOVE AC1,CNUM ;INIT MINUEND 4635 034143 115 01 0 00 034707 DSUB AC1,CNUM+2 ;SUB N - P 4636 CHECKT (LOC,C1,CNUM+4)^ 4637 4638 034144 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4639 034145 312 01 0 00 034711 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4640 034146 254 00 0 00 034152 JRST ..0241 ;NO - GO TO ERROR HANDLING 4641 034147 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4642 034150 316 02 0 00 034712 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4643 034151 254 00 0 00 034155 JRST ..0242+1 ;YES - DONT DO ERROR HANDLING 4644 ; EXCEPT FOR ERLOOP 4645 4646 034152 200 14 0 13 000001 ..0241: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4647 034153 200 13 0 13 034711 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4648 034154 ..0242: ERROR (LOC,14,SCR1,SCR2,,TEST C1 - RESULT IS INCORRECT,SPRINT)^SALL 4649 034154 036 14 0 00 041771 4650 034155 255 00 0 00 000000 4651 ^ 4652 ^ 4653 ; ************************************************ 4654 4655 ; ********************************************************************** 4656 ; ---------- DSUB - TEST C-2: N - N = P/N ---------- 4657 ; ********************************************************************** 4658 4659 034705 CNUM=SCONC2-6 4660 4661 REPEAT 6,< 4662 ; ************************************************ 4663 4664 LOC=. ;ERROR RETURN ADDRESS 4665 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4666 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4667 DMOVE AC1,CNUM ;INIT MINUEND 4668 DSUB AC1,CNUM+2 ;SUB N - N 4669 CHECKT (LOC,C2,CNUM+4) 4670 ; ************************************************ 4671 > 4672 4673 ; ************************************************ 4674 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-4 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0123 4675 034156 LOC=. ;ERROR RETURN ADDRESS 4676 034713 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4677 034156 200 15 0 00 042001 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4678 034157 120 01 0 00 034713 DMOVE AC1,CNUM ;INIT MINUEND 4679 034160 115 01 0 00 034715 DSUB AC1,CNUM+2 ;SUB N - N 4680 CHECKT (LOC,C2,CNUM+4)^ 4681 4682 034161 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4683 034162 312 01 0 00 034717 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4684 034163 254 00 0 00 034167 JRST ..0243 ;NO - GO TO ERROR HANDLING 4685 034164 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4686 034165 316 02 0 00 034720 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4687 034166 254 00 0 00 034172 JRST ..0244+1 ;YES - DONT DO ERROR HANDLING 4688 ; EXCEPT FOR ERLOOP 4689 4690 034167 200 14 0 13 000001 ..0243: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4691 034170 200 13 0 13 034717 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4692 034171 ..0244: ERROR (LOC,14,SCR1,SCR2,,TEST C2 - RESULT IS INCORRECT,SPRINT)^SALL 4693 034171 036 14 0 00 042007 4694 034172 255 00 0 00 000000 4695 ^ 4696 ^ 4697 ; ************************************************ 4698 4699 4700 ; ************************************************ 4701 4702 034173 LOC=. ;ERROR RETURN ADDRESS 4703 034721 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4704 034173 200 15 0 00 042012 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4705 034174 120 01 0 00 034721 DMOVE AC1,CNUM ;INIT MINUEND 4706 034175 115 01 0 00 034723 DSUB AC1,CNUM+2 ;SUB N - N 4707 CHECKT (LOC,C2,CNUM+4)^ 4708 4709 034176 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4710 034177 312 01 0 00 034725 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4711 034200 254 00 0 00 034204 JRST ..0245 ;NO - GO TO ERROR HANDLING 4712 034201 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4713 034202 316 02 0 00 034726 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4714 034203 254 00 0 00 034207 JRST ..0246+1 ;YES - DONT DO ERROR HANDLING 4715 ; EXCEPT FOR ERLOOP 4716 4717 034204 200 14 0 13 000001 ..0245: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4718 034205 200 13 0 13 034725 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4719 034206 ..0246: ERROR (LOC,14,SCR1,SCR2,,TEST C2 - RESULT IS INCORRECT,SPRINT)^SALL 4720 034206 036 14 0 00 042007 4721 034207 255 00 0 00 000000 4722 ^ 4723 ^ 4724 ; ************************************************ 4725 4726 4727 ; ************************************************ 4728 4729 034210 LOC=. ;ERROR RETURN ADDRESS DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-5 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0124 4730 034727 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4731 034210 200 15 0 00 042013 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4732 034211 120 01 0 00 034727 DMOVE AC1,CNUM ;INIT MINUEND 4733 034212 115 01 0 00 034731 DSUB AC1,CNUM+2 ;SUB N - N 4734 CHECKT (LOC,C2,CNUM+4)^ 4735 4736 034213 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4737 034214 312 01 0 00 034733 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4738 034215 254 00 0 00 034221 JRST ..0247 ;NO - GO TO ERROR HANDLING 4739 034216 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4740 034217 316 02 0 00 034734 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4741 034220 254 00 0 00 034224 JRST ..0250+1 ;YES - DONT DO ERROR HANDLING 4742 ; EXCEPT FOR ERLOOP 4743 4744 034221 200 14 0 13 000001 ..0247: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4745 034222 200 13 0 13 034733 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4746 034223 ..0250: ERROR (LOC,14,SCR1,SCR2,,TEST C2 - RESULT IS INCORRECT,SPRINT)^SALL 4747 034223 036 14 0 00 042007 4748 034224 255 00 0 00 000000 4749 ^ 4750 ^ 4751 ; ************************************************ 4752 4753 4754 ; ************************************************ 4755 4756 034225 LOC=. ;ERROR RETURN ADDRESS 4757 034735 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4758 034225 200 15 0 00 042014 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4759 034226 120 01 0 00 034735 DMOVE AC1,CNUM ;INIT MINUEND 4760 034227 115 01 0 00 034737 DSUB AC1,CNUM+2 ;SUB N - N 4761 CHECKT (LOC,C2,CNUM+4)^ 4762 4763 034230 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4764 034231 312 01 0 00 034741 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4765 034232 254 00 0 00 034236 JRST ..0251 ;NO - GO TO ERROR HANDLING 4766 034233 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4767 034234 316 02 0 00 034742 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4768 034235 254 00 0 00 034241 JRST ..0252+1 ;YES - DONT DO ERROR HANDLING 4769 ; EXCEPT FOR ERLOOP 4770 4771 034236 200 14 0 13 000001 ..0251: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4772 034237 200 13 0 13 034741 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4773 034240 ..0252: ERROR (LOC,14,SCR1,SCR2,,TEST C2 - RESULT IS INCORRECT,SPRINT)^SALL 4774 034240 036 14 0 00 042007 4775 034241 255 00 0 00 000000 4776 ^ 4777 ^ 4778 ; ************************************************ 4779 4780 4781 ; ************************************************ 4782 4783 034242 LOC=. ;ERROR RETURN ADDRESS 4784 034743 CNUM=CNUM+6 ;SUBRESS OF TEST DATA DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-6 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0125 4785 034242 200 15 0 00 042015 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4786 034243 120 01 0 00 034743 DMOVE AC1,CNUM ;INIT MINUEND 4787 034244 115 01 0 00 034745 DSUB AC1,CNUM+2 ;SUB N - N 4788 CHECKT (LOC,C2,CNUM+4)^ 4789 4790 034245 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4791 034246 312 01 0 00 034747 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4792 034247 254 00 0 00 034253 JRST ..0253 ;NO - GO TO ERROR HANDLING 4793 034250 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4794 034251 316 02 0 00 034750 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4795 034252 254 00 0 00 034256 JRST ..0254+1 ;YES - DONT DO ERROR HANDLING 4796 ; EXCEPT FOR ERLOOP 4797 4798 034253 200 14 0 13 000001 ..0253: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4799 034254 200 13 0 13 034747 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4800 034255 ..0254: ERROR (LOC,14,SCR1,SCR2,,TEST C2 - RESULT IS INCORRECT,SPRINT)^SALL 4801 034255 036 14 0 00 042007 4802 034256 255 00 0 00 000000 4803 ^ 4804 ^ 4805 ; ************************************************ 4806 4807 4808 ; ************************************************ 4809 4810 034257 LOC=. ;ERROR RETURN ADDRESS 4811 034751 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4812 034257 200 15 0 00 042016 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4813 034260 120 01 0 00 034751 DMOVE AC1,CNUM ;INIT MINUEND 4814 034261 115 01 0 00 034753 DSUB AC1,CNUM+2 ;SUB N - N 4815 CHECKT (LOC,C2,CNUM+4)^ 4816 4817 034262 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4818 034263 312 01 0 00 034755 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4819 034264 254 00 0 00 034270 JRST ..0255 ;NO - GO TO ERROR HANDLING 4820 034265 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4821 034266 316 02 0 00 034756 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4822 034267 254 00 0 00 034273 JRST ..0256+1 ;YES - DONT DO ERROR HANDLING 4823 ; EXCEPT FOR ERLOOP 4824 4825 034270 200 14 0 13 000001 ..0255: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4826 034271 200 13 0 13 034755 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4827 034272 ..0256: ERROR (LOC,14,SCR1,SCR2,,TEST C2 - RESULT IS INCORRECT,SPRINT)^SALL 4828 034272 036 14 0 00 042007 4829 034273 255 00 0 00 000000 4830 ^ 4831 ^ 4832 ; ************************************************ 4833 4834 ; ********************************************************************** 4835 ; ---------- DSUB - TEST C-3: P - P = N/P ---------- 4836 ; ********************************************************************** 4837 4838 034751 CNUM=SCONC3-6 4839 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-7 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0126 4840 REPEAT 6,< 4841 ; ************************************************ 4842 4843 LOC=. ;ERROR RETURN ADDRESS 4844 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4845 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4846 DMOVE AC1,CNUM ;INIT MINUEND 4847 DSUB AC1,CNUM+2 ;SUB N - P 4848 CHECKT (LOC,C3,CNUM+4) 4849 ; ************************************************ 4850 > 4851 4852 ; ************************************************ 4853 4854 034274 LOC=. ;ERROR RETURN ADDRESS 4855 034757 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4856 034274 200 15 0 00 042017 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4857 034275 120 01 0 00 034757 DMOVE AC1,CNUM ;INIT MINUEND 4858 034276 115 01 0 00 034761 DSUB AC1,CNUM+2 ;SUB N - P 4859 CHECKT (LOC,C3,CNUM+4)^ 4860 4861 034277 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4862 034300 312 01 0 00 034763 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4863 034301 254 00 0 00 034305 JRST ..0257 ;NO - GO TO ERROR HANDLING 4864 034302 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4865 034303 316 02 0 00 034764 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4866 034304 254 00 0 00 034310 JRST ..0260+1 ;YES - DONT DO ERROR HANDLING 4867 ; EXCEPT FOR ERLOOP 4868 4869 034305 200 14 0 13 000001 ..0257: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4870 034306 200 13 0 13 034763 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4871 034307 ..0260: ERROR (LOC,14,SCR1,SCR2,,TEST C3 - RESULT IS INCORRECT,SPRINT)^SALL 4872 034307 036 14 0 00 042025 4873 034310 255 00 0 00 000000 4874 ^ 4875 ^ 4876 ; ************************************************ 4877 4878 4879 ; ************************************************ 4880 4881 034311 LOC=. ;ERROR RETURN ADDRESS 4882 034765 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4883 034311 200 15 0 00 042030 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4884 034312 120 01 0 00 034765 DMOVE AC1,CNUM ;INIT MINUEND 4885 034313 115 01 0 00 034767 DSUB AC1,CNUM+2 ;SUB N - P 4886 CHECKT (LOC,C3,CNUM+4)^ 4887 4888 034314 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4889 034315 312 01 0 00 034771 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4890 034316 254 00 0 00 034322 JRST ..0261 ;NO - GO TO ERROR HANDLING 4891 034317 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4892 034320 316 02 0 00 034772 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4893 034321 254 00 0 00 034325 JRST ..0262+1 ;YES - DONT DO ERROR HANDLING 4894 ; EXCEPT FOR ERLOOP DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-8 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0127 4895 4896 034322 200 14 0 13 000001 ..0261: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4897 034323 200 13 0 13 034771 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4898 034324 ..0262: ERROR (LOC,14,SCR1,SCR2,,TEST C3 - RESULT IS INCORRECT,SPRINT)^SALL 4899 034324 036 14 0 00 042025 4900 034325 255 00 0 00 000000 4901 ^ 4902 ^ 4903 ; ************************************************ 4904 4905 4906 ; ************************************************ 4907 4908 034326 LOC=. ;ERROR RETURN ADDRESS 4909 034773 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4910 034326 200 15 0 00 042031 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4911 034327 120 01 0 00 034773 DMOVE AC1,CNUM ;INIT MINUEND 4912 034330 115 01 0 00 034775 DSUB AC1,CNUM+2 ;SUB N - P 4913 CHECKT (LOC,C3,CNUM+4)^ 4914 4915 034331 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4916 034332 312 01 0 00 034777 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4917 034333 254 00 0 00 034337 JRST ..0263 ;NO - GO TO ERROR HANDLING 4918 034334 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4919 034335 316 02 0 00 035000 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4920 034336 254 00 0 00 034342 JRST ..0264+1 ;YES - DONT DO ERROR HANDLING 4921 ; EXCEPT FOR ERLOOP 4922 4923 034337 200 14 0 13 000001 ..0263: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4924 034340 200 13 0 13 034777 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4925 034341 ..0264: ERROR (LOC,14,SCR1,SCR2,,TEST C3 - RESULT IS INCORRECT,SPRINT)^SALL 4926 034341 036 14 0 00 042025 4927 034342 255 00 0 00 000000 4928 ^ 4929 ^ 4930 ; ************************************************ 4931 4932 4933 ; ************************************************ 4934 4935 034343 LOC=. ;ERROR RETURN ADDRESS 4936 035001 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4937 034343 200 15 0 00 042032 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4938 034344 120 01 0 00 035001 DMOVE AC1,CNUM ;INIT MINUEND 4939 034345 115 01 0 00 035003 DSUB AC1,CNUM+2 ;SUB N - P 4940 CHECKT (LOC,C3,CNUM+4)^ 4941 4942 034346 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4943 034347 312 01 0 00 035005 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4944 034350 254 00 0 00 034354 JRST ..0265 ;NO - GO TO ERROR HANDLING 4945 034351 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4946 034352 316 02 0 00 035006 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4947 034353 254 00 0 00 034357 JRST ..0266+1 ;YES - DONT DO ERROR HANDLING 4948 ; EXCEPT FOR ERLOOP 4949 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-9 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0128 4950 034354 200 14 0 13 000001 ..0265: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4951 034355 200 13 0 13 035005 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4952 034356 ..0266: ERROR (LOC,14,SCR1,SCR2,,TEST C3 - RESULT IS INCORRECT,SPRINT)^SALL 4953 034356 036 14 0 00 042025 4954 034357 255 00 0 00 000000 4955 ^ 4956 ^ 4957 ; ************************************************ 4958 4959 4960 ; ************************************************ 4961 4962 034360 LOC=. ;ERROR RETURN ADDRESS 4963 035007 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4964 034360 200 15 0 00 042033 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4965 034361 120 01 0 00 035007 DMOVE AC1,CNUM ;INIT MINUEND 4966 034362 115 01 0 00 035011 DSUB AC1,CNUM+2 ;SUB N - P 4967 CHECKT (LOC,C3,CNUM+4)^ 4968 4969 034363 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4970 034364 312 01 0 00 035013 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4971 034365 254 00 0 00 034371 JRST ..0267 ;NO - GO TO ERROR HANDLING 4972 034366 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 4973 034367 316 02 0 00 035014 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 4974 034370 254 00 0 00 034374 JRST ..0270+1 ;YES - DONT DO ERROR HANDLING 4975 ; EXCEPT FOR ERLOOP 4976 4977 034371 200 14 0 13 000001 ..0267: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 4978 034372 200 13 0 13 035013 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 4979 034373 ..0270: ERROR (LOC,14,SCR1,SCR2,,TEST C3 - RESULT IS INCORRECT,SPRINT)^SALL 4980 034373 036 14 0 00 042025 4981 034374 255 00 0 00 000000 4982 ^ 4983 ^ 4984 ; ************************************************ 4985 4986 4987 ; ************************************************ 4988 4989 034375 LOC=. ;ERROR RETURN ADDRESS 4990 035015 CNUM=CNUM+6 ;SUBRESS OF TEST DATA 4991 034375 200 15 0 00 042034 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 4992 034376 120 01 0 00 035015 DMOVE AC1,CNUM ;INIT MINUEND 4993 034377 115 01 0 00 035017 DSUB AC1,CNUM+2 ;SUB N - P 4994 CHECKT (LOC,C3,CNUM+4)^ 4995 4996 034400 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 4997 034401 312 01 0 00 035021 CAME AC1,CNUM+4 ;IS LEFT HALF OF RESULT CORRECT? 4998 034402 254 00 0 00 034406 JRST ..0271 ;NO - GO TO ERROR HANDLING 4999 034403 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5000 034404 316 02 0 00 035022 CAMN AC1+1,CNUM+4+1 ;IS RIGHT HALF CORRECT? 5001 034405 254 00 0 00 034411 JRST ..0272+1 ;YES - DONT DO ERROR HANDLING 5002 ; EXCEPT FOR ERLOOP 5003 5004 034406 200 14 0 13 000001 ..0271: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-10 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0129 5005 034407 200 13 0 13 035021 MOVE SCR1,CNUM+4(SCR1) ;GET CORRECT WORD OF RESULT 5006 034410 ..0272: ERROR (LOC,14,SCR1,SCR2,,TEST C3 - RESULT IS INCORRECT,SPRINT)^SALL 5007 034410 036 14 0 00 042025 5008 034411 255 00 0 00 000000 5009 ^ 5010 ^ 5011 ; ************************************************ 5012 5013 ; ********************************************************************** 5014 ; ---------- DSUB - TEST C-4: N - P = -3 ---------- 5015 ; ********************************************************************** 5016 5017 035017 CNUM=SCONC4-4 5018 5019 REPEAT 6,< 5020 ; ************************************************ 5021 5022 LOC=. ;ERROR RETURN ADDRESS 5023 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5024 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5025 DMOVE AC1,CNUM ;INIT MINUEND 5026 DSUB AC1,CNUM+2 ;SUB N - P = -3 5027 CHECKS (LOC,C4,-1,-3) 5028 ; ************************************************ 5029 > 5030 5031 ; ************************************************ 5032 5033 034412 LOC=. ;ERROR RETURN ADDRESS 5034 035023 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5035 034412 200 15 0 00 042035 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5036 034413 120 01 0 00 035023 DMOVE AC1,CNUM ;INIT MINUEND 5037 034414 115 01 0 00 035025 DSUB AC1,CNUM+2 ;SUB N - P = -3 5038 CHECKS (LOC,C4,-1,-3)^ 5039 5040 034415 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5041 034416 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 5042 034417 254 00 0 00 034423 JRST ..0273 ;NO - GO TO ERROR HANDLING 5043 034420 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5044 034421 316 02 0 00 042036 CAMN AC1+1,[-3] ;IS RIGHT HALF CORRECT? 5045 034422 254 00 0 00 034426 JRST ..0274+1 ;YES - DONT DO ERROR HANDLING 5046 ; EXCEPT FOR ERLOOP 5047 5048 034423 200 14 0 13 000001 ..0273: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5049 034424 200 13 0 13 042037 MOVE SCR1,[EXP -1,-3](SCR1) ;GET CORRECT RESULT 5050 034425 ..0274: ERROR (LOC,14,SCR1,SCR2,,TEST C4 - RESULT IS INCORRECT,SPRINT)^SALL 5051 034425 036 14 0 00 042046 5052 034426 255 00 0 00 000000 5053 ^ 5054 ^ 5055 ; ************************************************ 5056 5057 5058 ; ************************************************ 5059 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-11 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0130 5060 034427 LOC=. ;ERROR RETURN ADDRESS 5061 035027 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5062 034427 200 15 0 00 042051 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5063 034430 120 01 0 00 035027 DMOVE AC1,CNUM ;INIT MINUEND 5064 034431 115 01 0 00 035031 DSUB AC1,CNUM+2 ;SUB N - P = -3 5065 CHECKS (LOC,C4,-1,-3)^ 5066 5067 034432 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5068 034433 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 5069 034434 254 00 0 00 034440 JRST ..0275 ;NO - GO TO ERROR HANDLING 5070 034435 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5071 034436 316 02 0 00 042036 CAMN AC1+1,[-3] ;IS RIGHT HALF CORRECT? 5072 034437 254 00 0 00 034443 JRST ..0276+1 ;YES - DONT DO ERROR HANDLING 5073 ; EXCEPT FOR ERLOOP 5074 5075 034440 200 14 0 13 000001 ..0275: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5076 034441 200 13 0 13 042037 MOVE SCR1,[EXP -1,-3](SCR1) ;GET CORRECT RESULT 5077 034442 ..0276: ERROR (LOC,14,SCR1,SCR2,,TEST C4 - RESULT IS INCORRECT,SPRINT)^SALL 5078 034442 036 14 0 00 042046 5079 034443 255 00 0 00 000000 5080 ^ 5081 ^ 5082 ; ************************************************ 5083 5084 5085 ; ************************************************ 5086 5087 034444 LOC=. ;ERROR RETURN ADDRESS 5088 035033 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5089 034444 200 15 0 00 042052 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5090 034445 120 01 0 00 035033 DMOVE AC1,CNUM ;INIT MINUEND 5091 034446 115 01 0 00 035035 DSUB AC1,CNUM+2 ;SUB N - P = -3 5092 CHECKS (LOC,C4,-1,-3)^ 5093 5094 034447 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5095 034450 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 5096 034451 254 00 0 00 034455 JRST ..0277 ;NO - GO TO ERROR HANDLING 5097 034452 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5098 034453 316 02 0 00 042036 CAMN AC1+1,[-3] ;IS RIGHT HALF CORRECT? 5099 034454 254 00 0 00 034460 JRST ..0300+1 ;YES - DONT DO ERROR HANDLING 5100 ; EXCEPT FOR ERLOOP 5101 5102 034455 200 14 0 13 000001 ..0277: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5103 034456 200 13 0 13 042037 MOVE SCR1,[EXP -1,-3](SCR1) ;GET CORRECT RESULT 5104 034457 ..0300: ERROR (LOC,14,SCR1,SCR2,,TEST C4 - RESULT IS INCORRECT,SPRINT)^SALL 5105 034457 036 14 0 00 042046 5106 034460 255 00 0 00 000000 5107 ^ 5108 ^ 5109 ; ************************************************ 5110 5111 5112 ; ************************************************ 5113 5114 034461 LOC=. ;ERROR RETURN ADDRESS DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-12 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0131 5115 035037 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5116 034461 200 15 0 00 042053 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5117 034462 120 01 0 00 035037 DMOVE AC1,CNUM ;INIT MINUEND 5118 034463 115 01 0 00 035041 DSUB AC1,CNUM+2 ;SUB N - P = -3 5119 CHECKS (LOC,C4,-1,-3)^ 5120 5121 034464 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5122 034465 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 5123 034466 254 00 0 00 034472 JRST ..0301 ;NO - GO TO ERROR HANDLING 5124 034467 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5125 034470 316 02 0 00 042036 CAMN AC1+1,[-3] ;IS RIGHT HALF CORRECT? 5126 034471 254 00 0 00 034475 JRST ..0302+1 ;YES - DONT DO ERROR HANDLING 5127 ; EXCEPT FOR ERLOOP 5128 5129 034472 200 14 0 13 000001 ..0301: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5130 034473 200 13 0 13 042037 MOVE SCR1,[EXP -1,-3](SCR1) ;GET CORRECT RESULT 5131 034474 ..0302: ERROR (LOC,14,SCR1,SCR2,,TEST C4 - RESULT IS INCORRECT,SPRINT)^SALL 5132 034474 036 14 0 00 042046 5133 034475 255 00 0 00 000000 5134 ^ 5135 ^ 5136 ; ************************************************ 5137 5138 5139 ; ************************************************ 5140 5141 034476 LOC=. ;ERROR RETURN ADDRESS 5142 035043 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5143 034476 200 15 0 00 042054 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5144 034477 120 01 0 00 035043 DMOVE AC1,CNUM ;INIT MINUEND 5145 034500 115 01 0 00 035045 DSUB AC1,CNUM+2 ;SUB N - P = -3 5146 CHECKS (LOC,C4,-1,-3)^ 5147 5148 034501 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5149 034502 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 5150 034503 254 00 0 00 034507 JRST ..0303 ;NO - GO TO ERROR HANDLING 5151 034504 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5152 034505 316 02 0 00 042036 CAMN AC1+1,[-3] ;IS RIGHT HALF CORRECT? 5153 034506 254 00 0 00 034512 JRST ..0304+1 ;YES - DONT DO ERROR HANDLING 5154 ; EXCEPT FOR ERLOOP 5155 5156 034507 200 14 0 13 000001 ..0303: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5157 034510 200 13 0 13 042037 MOVE SCR1,[EXP -1,-3](SCR1) ;GET CORRECT RESULT 5158 034511 ..0304: ERROR (LOC,14,SCR1,SCR2,,TEST C4 - RESULT IS INCORRECT,SPRINT)^SALL 5159 034511 036 14 0 00 042046 5160 034512 255 00 0 00 000000 5161 ^ 5162 ^ 5163 ; ************************************************ 5164 5165 5166 ; ************************************************ 5167 5168 034513 LOC=. ;ERROR RETURN ADDRESS 5169 035047 CNUM=CNUM+4 ;SUBRESS OF TEST DATA DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-13 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0132 5170 034513 200 15 0 00 042055 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5171 034514 120 01 0 00 035047 DMOVE AC1,CNUM ;INIT MINUEND 5172 034515 115 01 0 00 035051 DSUB AC1,CNUM+2 ;SUB N - P = -3 5173 CHECKS (LOC,C4,-1,-3)^ 5174 5175 034516 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5176 034517 312 01 0 00 041166 CAME AC1,[-1] ;IS LEFT HALF OF RESULT CORRECT? 5177 034520 254 00 0 00 034524 JRST ..0305 ;NO - GO TO ERROR HANDLING 5178 034521 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5179 034522 316 02 0 00 042036 CAMN AC1+1,[-3] ;IS RIGHT HALF CORRECT? 5180 034523 254 00 0 00 034527 JRST ..0306+1 ;YES - DONT DO ERROR HANDLING 5181 ; EXCEPT FOR ERLOOP 5182 5183 034524 200 14 0 13 000001 ..0305: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5184 034525 200 13 0 13 042037 MOVE SCR1,[EXP -1,-3](SCR1) ;GET CORRECT RESULT 5185 034526 ..0306: ERROR (LOC,14,SCR1,SCR2,,TEST C4 - RESULT IS INCORRECT,SPRINT)^SALL 5186 034526 036 14 0 00 042046 5187 034527 255 00 0 00 000000 5188 ^ 5189 ^ 5190 ; ************************************************ 5191 5192 ; ********************************************************************** 5193 ; ---------- DSUB - TEST C-5: P - N = 3 ---------- 5194 ; ********************************************************************** 5195 5196 035047 CNUM=SCONC5-4 5197 5198 REPEAT 6,< 5199 ; ************************************************ 5200 5201 LOC=. ;ERROR RETURN ADDRESS 5202 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5203 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5204 DMOVE AC1,CNUM ;INIT MINUEND 5205 DSUB AC1,CNUM+2 ;SUB N - P = 3 5206 CHECKS (LOC,C5,0,3) 5207 ; ************************************************ 5208 > 5209 5210 ; ************************************************ 5211 5212 034530 LOC=. ;ERROR RETURN ADDRESS 5213 035053 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5214 034530 200 15 0 00 042056 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5215 034531 120 01 0 00 035053 DMOVE AC1,CNUM ;INIT MINUEND 5216 034532 115 01 0 00 035055 DSUB AC1,CNUM+2 ;SUB N - P = 3 5217 CHECKS (LOC,C5,0,3)^ 5218 5219 034533 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5220 034534 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 5221 034535 254 00 0 00 034541 JRST ..0307 ;NO - GO TO ERROR HANDLING 5222 034536 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5223 034537 316 02 0 00 042057 CAMN AC1+1,[3] ;IS RIGHT HALF CORRECT? 5224 034540 254 00 0 00 034544 JRST ..0310+1 ;YES - DONT DO ERROR HANDLING DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-14 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0133 5225 ; EXCEPT FOR ERLOOP 5226 5227 034541 200 14 0 13 000001 ..0307: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5228 034542 200 13 0 13 042060 MOVE SCR1,[EXP 0,3](SCR1) ;GET CORRECT RESULT 5229 034543 ..0310: ERROR (LOC,14,SCR1,SCR2,,TEST C5 - RESULT IS INCORRECT,SPRINT)^SALL 5230 034543 036 14 0 00 042067 5231 034544 255 00 0 00 000000 5232 ^ 5233 ^ 5234 ; ************************************************ 5235 5236 5237 ; ************************************************ 5238 5239 034545 LOC=. ;ERROR RETURN ADDRESS 5240 035057 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5241 034545 200 15 0 00 042072 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5242 034546 120 01 0 00 035057 DMOVE AC1,CNUM ;INIT MINUEND 5243 034547 115 01 0 00 035061 DSUB AC1,CNUM+2 ;SUB N - P = 3 5244 CHECKS (LOC,C5,0,3)^ 5245 5246 034550 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5247 034551 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 5248 034552 254 00 0 00 034556 JRST ..0311 ;NO - GO TO ERROR HANDLING 5249 034553 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5250 034554 316 02 0 00 042057 CAMN AC1+1,[3] ;IS RIGHT HALF CORRECT? 5251 034555 254 00 0 00 034561 JRST ..0312+1 ;YES - DONT DO ERROR HANDLING 5252 ; EXCEPT FOR ERLOOP 5253 5254 034556 200 14 0 13 000001 ..0311: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5255 034557 200 13 0 13 042060 MOVE SCR1,[EXP 0,3](SCR1) ;GET CORRECT RESULT 5256 034560 ..0312: ERROR (LOC,14,SCR1,SCR2,,TEST C5 - RESULT IS INCORRECT,SPRINT)^SALL 5257 034560 036 14 0 00 042067 5258 034561 255 00 0 00 000000 5259 ^ 5260 ^ 5261 ; ************************************************ 5262 5263 5264 ; ************************************************ 5265 5266 034562 LOC=. ;ERROR RETURN ADDRESS 5267 035063 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5268 034562 200 15 0 00 042073 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5269 034563 120 01 0 00 035063 DMOVE AC1,CNUM ;INIT MINUEND 5270 034564 115 01 0 00 035065 DSUB AC1,CNUM+2 ;SUB N - P = 3 5271 CHECKS (LOC,C5,0,3)^ 5272 5273 034565 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5274 034566 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 5275 034567 254 00 0 00 034573 JRST ..0313 ;NO - GO TO ERROR HANDLING 5276 034570 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5277 034571 316 02 0 00 042057 CAMN AC1+1,[3] ;IS RIGHT HALF CORRECT? 5278 034572 254 00 0 00 034576 JRST ..0314+1 ;YES - DONT DO ERROR HANDLING 5279 ; EXCEPT FOR ERLOOP DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-15 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0134 5280 5281 034573 200 14 0 13 000001 ..0313: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5282 034574 200 13 0 13 042060 MOVE SCR1,[EXP 0,3](SCR1) ;GET CORRECT RESULT 5283 034575 ..0314: ERROR (LOC,14,SCR1,SCR2,,TEST C5 - RESULT IS INCORRECT,SPRINT)^SALL 5284 034575 036 14 0 00 042067 5285 034576 255 00 0 00 000000 5286 ^ 5287 ^ 5288 ; ************************************************ 5289 5290 5291 ; ************************************************ 5292 5293 034577 LOC=. ;ERROR RETURN ADDRESS 5294 035067 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5295 034577 200 15 0 00 042074 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5296 034600 120 01 0 00 035067 DMOVE AC1,CNUM ;INIT MINUEND 5297 034601 115 01 0 00 035071 DSUB AC1,CNUM+2 ;SUB N - P = 3 5298 CHECKS (LOC,C5,0,3)^ 5299 5300 034602 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5301 034603 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 5302 034604 254 00 0 00 034610 JRST ..0315 ;NO - GO TO ERROR HANDLING 5303 034605 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5304 034606 316 02 0 00 042057 CAMN AC1+1,[3] ;IS RIGHT HALF CORRECT? 5305 034607 254 00 0 00 034613 JRST ..0316+1 ;YES - DONT DO ERROR HANDLING 5306 ; EXCEPT FOR ERLOOP 5307 5308 034610 200 14 0 13 000001 ..0315: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5309 034611 200 13 0 13 042060 MOVE SCR1,[EXP 0,3](SCR1) ;GET CORRECT RESULT 5310 034612 ..0316: ERROR (LOC,14,SCR1,SCR2,,TEST C5 - RESULT IS INCORRECT,SPRINT)^SALL 5311 034612 036 14 0 00 042067 5312 034613 255 00 0 00 000000 5313 ^ 5314 ^ 5315 ; ************************************************ 5316 5317 5318 ; ************************************************ 5319 5320 034614 LOC=. ;ERROR RETURN ADDRESS 5321 035073 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5322 034614 200 15 0 00 042075 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5323 034615 120 01 0 00 035073 DMOVE AC1,CNUM ;INIT MINUEND 5324 034616 115 01 0 00 035075 DSUB AC1,CNUM+2 ;SUB N - P = 3 5325 CHECKS (LOC,C5,0,3)^ 5326 5327 034617 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5328 034620 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 5329 034621 254 00 0 00 034625 JRST ..0317 ;NO - GO TO ERROR HANDLING 5330 034622 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5331 034623 316 02 0 00 042057 CAMN AC1+1,[3] ;IS RIGHT HALF CORRECT? 5332 034624 254 00 0 00 034630 JRST ..0320+1 ;YES - DONT DO ERROR HANDLING 5333 ; EXCEPT FOR ERLOOP 5334 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-16 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0135 5335 034625 200 14 0 13 000001 ..0317: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5336 034626 200 13 0 13 042060 MOVE SCR1,[EXP 0,3](SCR1) ;GET CORRECT RESULT 5337 034627 ..0320: ERROR (LOC,14,SCR1,SCR2,,TEST C5 - RESULT IS INCORRECT,SPRINT)^SALL 5338 034627 036 14 0 00 042067 5339 034630 255 00 0 00 000000 5340 ^ 5341 ^ 5342 ; ************************************************ 5343 5344 5345 ; ************************************************ 5346 5347 034631 LOC=. ;ERROR RETURN ADDRESS 5348 035077 CNUM=CNUM+4 ;SUBRESS OF TEST DATA 5349 034631 200 15 0 00 042076 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5350 034632 120 01 0 00 035077 DMOVE AC1,CNUM ;INIT MINUEND 5351 034633 115 01 0 00 035101 DSUB AC1,CNUM+2 ;SUB N - P = 3 5352 CHECKS (LOC,C5,0,3)^ 5353 5354 034634 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5355 034635 312 01 0 00 041020 CAME AC1,[0] ;IS LEFT HALF OF RESULT CORRECT? 5356 034636 254 00 0 00 034642 JRST ..0321 ;NO - GO TO ERROR HANDLING 5357 034637 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5358 034640 316 02 0 00 042057 CAMN AC1+1,[3] ;IS RIGHT HALF CORRECT? 5359 034641 254 00 0 00 034645 JRST ..0322+1 ;YES - DONT DO ERROR HANDLING 5360 ; EXCEPT FOR ERLOOP 5361 5362 034642 200 14 0 13 000001 ..0321: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5363 034643 200 13 0 13 042060 MOVE SCR1,[EXP 0,3](SCR1) ;GET CORRECT RESULT 5364 034644 ..0322: ERROR (LOC,14,SCR1,SCR2,,TEST C5 - RESULT IS INCORRECT,SPRINT)^SALL 5365 034644 036 14 0 00 042067 5366 034645 255 00 0 00 000000 5367 ^ 5368 ^ 5369 ; ************************************************ 5370 5371 034646 254 00 0 00 035103 JRST SENDC ;SKIP OVER DATA 5372 5373 034647 000000 000000 SCONC1: EXP 0,0,0,1B0,0,0 5374 034650 000000 000000 5375 034651 000000 000000 5376 034652 400000 000000 5377 034653 000000 000000 5378 034654 000000 000000 5379 034655 000000 000000 EXP 0,1B0,0,1,-1,-1 5380 034656 400000 000000 5381 034657 000000 000000 5382 034660 000000 000001 5383 034661 777777 777777 5384 034662 777777 777777 5385 034663 000000 000000 EXP 0,1B0,0,1B0+1,-1,-1 5386 034664 400000 000000 5387 034665 000000 000000 5388 034666 400000 000001 5389 034667 777777 777777 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-17 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0136 5390 034670 777777 777777 5391 034671 000000 000000 EXP 0,0,-1,377777777777,0,1 5392 034672 000000 000000 5393 034673 777777 777777 5394 034674 377777 777777 5395 034675 000000 000000 5396 034676 000000 000001 5397 034677 000000 000000 EXP 0,1B0,-1,377777777777,0,1 5398 034700 400000 000000 5399 034701 777777 777777 5400 034702 377777 777777 5401 034703 000000 000000 5402 034704 000000 000001 5403 034705 000000 000000 EXP 0,1B0,-1,-1,0,1 5404 034706 400000 000000 5405 034707 777777 777777 5406 034710 777777 777777 5407 034711 000000 000000 5408 034712 000000 000001 5409 5410 034713 777777 777777 SCONC2: EXP -1,377777777777,-2,-1,1,0 5411 034714 377777 777777 5412 034715 777777 777776 5413 034716 777777 777777 5414 034717 000000 000001 5415 034720 000000 000000 5416 034721 777777 777777 EXP -1,377777777777,-2,377777777777,1,0 5417 034722 377777 777777 5418 034723 777777 777776 5419 034724 377777 777777 5420 034725 000000 000001 5421 034726 000000 000000 5422 034727 777777 777777 EXP -1,-1,-2,377777777777,1,0 5423 034730 777777 777777 5424 034731 777777 777776 5425 034732 377777 777777 5426 034733 000000 000001 5427 034734 000000 000000 5428 034735 777777 777776 EXP -2,-1,-1,377777777777,-1,1B0 5429 034736 777777 777777 5430 034737 777777 777777 5431 034740 377777 777777 5432 034741 777777 777777 5433 034742 400000 000000 5434 034743 777777 777776 EXP -2,377777777777,-1,377777777777,-1,1B0 5435 034744 377777 777777 5436 034745 777777 777777 5437 034746 377777 777777 5438 034747 777777 777777 5439 034750 400000 000000 5440 034751 777777 777776 EXP -2,377777777777,-1,-1,-1,1B0 5441 034752 377777 777777 5442 034753 777777 777777 5443 034754 777777 777777 5444 034755 777777 777777 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-18 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0137 5445 034756 400000 000000 5446 5447 034757 000000 000000 SCONC3: EXP 0,1B0+1,1,0,-1,1B0+1 5448 034760 400000 000001 5449 034761 000000 000001 5450 034762 000000 000000 5451 034763 777777 777777 5452 034764 400000 000001 5453 034765 000000 000000 EXP 0,1B0+1,1,1B0,-1,1B0+1 5454 034766 400000 000001 5455 034767 000000 000001 5456 034770 400000 000000 5457 034771 777777 777777 5458 034772 400000 000001 5459 034773 000000 000000 EXP 0,1,1,1B0,-1,1B0+1 5460 034774 000000 000001 5461 034775 000000 000001 5462 034776 400000 000000 5463 034777 777777 777777 5464 035000 400000 000001 5465 035001 000000 000001 EXP 1,0,0,1B0+1,0,377777777777 5466 035002 000000 000000 5467 035003 000000 000000 5468 035004 400000 000001 5469 035005 000000 000000 5470 035006 377777 777777 5471 035007 000000 000001 EXP 1,1B0,0,1B0+1,0,377777777777 5472 035010 400000 000000 5473 035011 000000 000000 5474 035012 400000 000001 5475 035013 000000 000000 5476 035014 377777 777777 5477 035015 000000 000001 EXP 1,1B0,0,1,0,377777777777 5478 035016 400000 000000 5479 035017 000000 000000 5480 035020 000000 000001 5481 035021 000000 000000 5482 035022 377777 777777 5483 5484 035023 777777 777777 SCONC4: EXP -1,377777777776,0,1 5485 035024 377777 777776 5486 035025 000000 000000 5487 035026 000000 000001 5488 035027 777777 777777 EXP -1,377777777776,0,1B0+1 5489 035030 377777 777776 5490 035031 000000 000000 5491 035032 400000 000001 5492 035033 777777 777777 EXP -1,-2,0,1B0+1 5493 035034 777777 777776 5494 035035 000000 000000 5495 035036 400000 000001 5496 035037 777777 777777 EXP -1,377777777777,0,2 5497 035040 377777 777777 5498 035041 000000 000000 5499 035042 000000 000002 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 16-19 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST C SEQ 0138 5500 035043 777777 777777 EXP -1,377777777777,0,1B0+2 5501 035044 377777 777777 5502 035045 000000 000000 5503 035046 400000 000002 5504 035047 777777 777777 EXP -1,-1,0,1B0+2 5505 035050 777777 777777 5506 035051 000000 000000 5507 035052 400000 000002 5508 035053 000000 000000 SCONC5: EXP 0,1,-1,377777777776 5509 035054 000000 000001 5510 035055 777777 777777 5511 035056 377777 777776 5512 035057 000000 000000 EXP 0,1B0+1,-1,377777777776 5513 035060 400000 000001 5514 035061 777777 777777 5515 035062 377777 777776 5516 035063 000000 000000 EXP 0,1B0+1,-1,-2 5517 035064 400000 000001 5518 035065 777777 777777 5519 035066 777777 777776 5520 035067 000000 000000 EXP 0,2,-1,377777777777 5521 035070 000000 000002 5522 035071 777777 777777 5523 035072 377777 777777 5524 035073 000000 000000 EXP 0,1B0+2,-1,377777777777 5525 035074 400000 000002 5526 035075 777777 777777 5527 035076 377777 777777 5528 035077 000000 000000 EXP 0,1B0+2,-1,-1 5529 035100 400000 000002 5530 035101 777777 777777 5531 035102 777777 777777 5532 035103 SENDC: DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 17 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST D SEQ 0139 5533 SUBTTL DSUB - TEST D 5534 5535 ; ********************************************************************** 5536 ;*DSUB - TEST D 5537 ;* 5538 ;* 2**N - (-2**70 + 2**N) = 1000... (AROV & CARRY 1 SET) 5539 ;* (-2**70 + 2**N) - 2**N = 1000... (AROV & CARRY 1 SET) 5540 ;* -2**N - (2**70 - 2**N + 1) = 0111... (AROV & CARRY 0 SET) 5541 ;* (2**70 - 2**N + 1) - -2**N = 0111... (AROV & CARRY 0 SET) 5542 ; ********************************************************************** 5543 5544 ; ********************************************************************** 5545 ;* THE FOLLOWING SECTION OF CODE IS REPEATED 8 TIMES. THE FIRST 5546 ;* 4 TESTS FLOAT A 1 ACROSS A DOUBLEWORD IN BITS 1,35,37,71. 5547 ;* FROM THIS NUMBER IS SUBTRACTED THE SMALLEST (MAGNITUDE) 5548 ;* NEGATIVE INTEGER WHICH WILL PRODUCE AN OVERFLOW - THE RESULT 5549 ;* IS A DOUBLEWORD OF 0'S WITH 1 IN THE SIGN BIT - WITH OVERFLOW 5550 ;* & CARRY 1 SET. THE NEXT 4 TESTS FLOAT A 0 ACROSS A DOUBLE- 5551 ;* WORD IN BITS 1,35,37,71 (A NEG NUMBER). FROM THIS NUMBER IS 5552 ;* SUBTRACTED THE SMALLEST POSITIVE INTEGER WHICH WILL PRODUCE 5553 ;* AN OVERFLOW - THE RESULT IS A DOUBLEWORD OF 1S WITH A 0 IN 5554 ;* THE SIGN BIT - WITH OVERFLOW AND CARRY 0 SET. 5555 ;* THE DOUBLEWORDS USED IN THIS TEST ARE LOCATED IN THE LIST 5556 ;* 'SCOND'. 5557 ; ********************************************************************** 5558 5559 035370 CNUM=SCOND-4 ;POINTER TO THE DOUBLEWORDS TO 5560 ; BE SUBTRACTED 5561 000000 REP=0 ;REPETITION COUNT 5562 400000 000000 RESULT=1B0 ;1B0 FOR 1ST 4 / 377.. FOR 2ND 4 5563 500000 000000 FLAGS=^B1010B3 ;AROV,CRY0,CRY1,FOV 5564 5565 REPEAT ^D8,< 5566 ; ************************************************ 5567 5568 LOC=. ;ERROR LOOP RETURN ADDRESS 5569 CNUM=CNUM+4 ;POINT TO THE TEST CASE 5570 REP=REP+1 ;REPETITION COUNT 5571 IFG REP-4, ;LARGEST POSITIVE NUMBER 5573 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5574 DMOVE AC1,CNUM ;INIT MINUEND TO FLOATING 0/1 5575 JFCL 17,.+1 ;CLEAR PC FLAGS 5576 DSUB AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 5577 PCSAVE 5578 CHECKS (LOC,D,RESULT,RESULT) 5579 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 5580 TFLAG ([FLAGS],D,SPRINT) 5581 ; ************************************************ 5582 > 5583 5584 ; ************************************************ 5585 5586 035103 LOC=. ;ERROR LOOP RETURN ADDRESS 5587 035374 CNUM=CNUM+4 ;POINT TO THE TEST CASE DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 17-1 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST D SEQ 0140 5588 000001 REP=REP+1 ;REPETITION COUNT 5589 IFG REP-4, ;LARGEST POSITIVE NUMBER 5591 035103 200 15 0 00 042077 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5592 035104 120 01 0 00 035374 DMOVE AC1,CNUM ;INIT MINUEND TO FLOATING 0/1 5593 035105 255 17 0 00 035106 JFCL 17,.+1 ;CLEAR PC FLAGS 5594 035106 115 01 0 00 035376 DSUB AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 5595 PCSAVE^ 5596 035107 264 00 0 00 035110 JSR .+1 ;STORE PC 5597 035110 FLAGL=. ;LOCATION OF PC 5598 035110 000000 000000 0 ;PC 5599 ^ 5600 CHECKS (LOC,D,RESULT,RESULT)^ 5601 5602 035111 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5603 035112 312 01 0 00 041725 CAME AC1,[RESULT] ;IS LEFT HALF OF RESULT CORRECT? 5604 035113 254 00 0 00 035117 JRST ..0323 ;NO - GO TO ERROR HANDLING 5605 035114 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5606 035115 316 02 0 00 041725 CAMN AC1+1,[RESULT] ;IS RIGHT HALF CORRECT? 5607 035116 254 00 0 00 035122 JRST ..0324+1 ;YES - DONT DO ERROR HANDLING 5608 ; EXCEPT FOR ERLOOP 5609 5610 035117 200 14 0 13 000001 ..0323: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5611 035120 200 13 0 13 042100 MOVE SCR1,[EXP RESULT,RESULT](SCR1) ;GET CORRECT RESULT 5612 035121 ..0324: ERROR (LOC,14,SCR1,SCR2,,TEST D - RESULT IS INCORRECT,SPRINT)^SALL 5613 035121 036 14 0 00 042107 5614 035122 255 00 0 00 000000 5615 ^ 5616 ^ 5617 035123 200 15 0 00 042077 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 5618 TFLAG ([FLAGS],D,SPRINT)^ 5619 5620 035124 200 13 0 00 035110 MOVE SCR1,FLAGL ;GET FLAGS 5621 035125 200 14 0 00 041634 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 5622 035126 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 5623 035127 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 5624 ERROR (LOC,13,SCR2,FLAGL,,TEST D - PC FLAGS INCORRECT (LEFT 4 BITS),SPRINT)^SALL 5625 035130 036 13 0 00 042121 5626 035131 255 00 0 00 000000 5627 ^ 5628 ^ 5629 ; ************************************************ 5630 5631 5632 ; ************************************************ 5633 5634 035132 LOC=. ;ERROR LOOP RETURN ADDRESS 5635 035400 CNUM=CNUM+4 ;POINT TO THE TEST CASE 5636 000002 REP=REP+1 ;REPETITION COUNT 5637 IFG REP-4, ;LARGEST POSITIVE NUMBER 5639 035132 200 15 0 00 042124 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5640 035133 120 01 0 00 035400 DMOVE AC1,CNUM ;INIT MINUEND TO FLOATING 0/1 5641 035134 255 17 0 00 035135 JFCL 17,.+1 ;CLEAR PC FLAGS 5642 035135 115 01 0 00 035402 DSUB AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 17-2 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST D SEQ 0141 5643 PCSAVE^ 5644 035136 264 00 0 00 035137 JSR .+1 ;STORE PC 5645 035137 FLAGL=. ;LOCATION OF PC 5646 035137 000000 000000 0 ;PC 5647 ^ 5648 CHECKS (LOC,D,RESULT,RESULT)^ 5649 5650 035140 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5651 035141 312 01 0 00 041725 CAME AC1,[RESULT] ;IS LEFT HALF OF RESULT CORRECT? 5652 035142 254 00 0 00 035146 JRST ..0325 ;NO - GO TO ERROR HANDLING 5653 035143 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5654 035144 316 02 0 00 041725 CAMN AC1+1,[RESULT] ;IS RIGHT HALF CORRECT? 5655 035145 254 00 0 00 035151 JRST ..0326+1 ;YES - DONT DO ERROR HANDLING 5656 ; EXCEPT FOR ERLOOP 5657 5658 035146 200 14 0 13 000001 ..0325: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5659 035147 200 13 0 13 042100 MOVE SCR1,[EXP RESULT,RESULT](SCR1) ;GET CORRECT RESULT 5660 035150 ..0326: ERROR (LOC,14,SCR1,SCR2,,TEST D - RESULT IS INCORRECT,SPRINT)^SALL 5661 035150 036 14 0 00 042107 5662 035151 255 00 0 00 000000 5663 ^ 5664 ^ 5665 035152 200 15 0 00 042124 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 5666 TFLAG ([FLAGS],D,SPRINT)^ 5667 5668 035153 200 13 0 00 035137 MOVE SCR1,FLAGL ;GET FLAGS 5669 035154 200 14 0 00 041634 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 5670 035155 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 5671 035156 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 5672 ERROR (LOC,13,SCR2,FLAGL,,TEST D - PC FLAGS INCORRECT (LEFT 4 BITS),SPRINT)^SALL 5673 035157 036 13 0 00 042125 5674 035160 255 00 0 00 000000 5675 ^ 5676 ^ 5677 ; ************************************************ 5678 5679 5680 ; ************************************************ 5681 5682 035161 LOC=. ;ERROR LOOP RETURN ADDRESS 5683 035404 CNUM=CNUM+4 ;POINT TO THE TEST CASE 5684 000003 REP=REP+1 ;REPETITION COUNT 5685 IFG REP-4, ;LARGEST POSITIVE NUMBER 5687 035161 200 15 0 00 042130 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5688 035162 120 01 0 00 035404 DMOVE AC1,CNUM ;INIT MINUEND TO FLOATING 0/1 5689 035163 255 17 0 00 035164 JFCL 17,.+1 ;CLEAR PC FLAGS 5690 035164 115 01 0 00 035406 DSUB AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 5691 PCSAVE^ 5692 035165 264 00 0 00 035166 JSR .+1 ;STORE PC 5693 035166 FLAGL=. ;LOCATION OF PC 5694 035166 000000 000000 0 ;PC 5695 ^ 5696 CHECKS (LOC,D,RESULT,RESULT)^ 5697 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 17-3 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST D SEQ 0142 5698 035167 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5699 035170 312 01 0 00 041725 CAME AC1,[RESULT] ;IS LEFT HALF OF RESULT CORRECT? 5700 035171 254 00 0 00 035175 JRST ..0327 ;NO - GO TO ERROR HANDLING 5701 035172 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5702 035173 316 02 0 00 041725 CAMN AC1+1,[RESULT] ;IS RIGHT HALF CORRECT? 5703 035174 254 00 0 00 035200 JRST ..0330+1 ;YES - DONT DO ERROR HANDLING 5704 ; EXCEPT FOR ERLOOP 5705 5706 035175 200 14 0 13 000001 ..0327: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5707 035176 200 13 0 13 042100 MOVE SCR1,[EXP RESULT,RESULT](SCR1) ;GET CORRECT RESULT 5708 035177 ..0330: ERROR (LOC,14,SCR1,SCR2,,TEST D - RESULT IS INCORRECT,SPRINT)^SALL 5709 035177 036 14 0 00 042107 5710 035200 255 00 0 00 000000 5711 ^ 5712 ^ 5713 035201 200 15 0 00 042130 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 5714 TFLAG ([FLAGS],D,SPRINT)^ 5715 5716 035202 200 13 0 00 035166 MOVE SCR1,FLAGL ;GET FLAGS 5717 035203 200 14 0 00 041634 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 5718 035204 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 5719 035205 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 5720 ERROR (LOC,13,SCR2,FLAGL,,TEST D - PC FLAGS INCORRECT (LEFT 4 BITS),SPRINT)^SALL 5721 035206 036 13 0 00 042131 5722 035207 255 00 0 00 000000 5723 ^ 5724 ^ 5725 ; ************************************************ 5726 5727 5728 ; ************************************************ 5729 5730 035210 LOC=. ;ERROR LOOP RETURN ADDRESS 5731 035410 CNUM=CNUM+4 ;POINT TO THE TEST CASE 5732 000004 REP=REP+1 ;REPETITION COUNT 5733 IFG REP-4, ;LARGEST POSITIVE NUMBER 5735 035210 200 15 0 00 042134 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5736 035211 120 01 0 00 035410 DMOVE AC1,CNUM ;INIT MINUEND TO FLOATING 0/1 5737 035212 255 17 0 00 035213 JFCL 17,.+1 ;CLEAR PC FLAGS 5738 035213 115 01 0 00 035412 DSUB AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 5739 PCSAVE^ 5740 035214 264 00 0 00 035215 JSR .+1 ;STORE PC 5741 035215 FLAGL=. ;LOCATION OF PC 5742 035215 000000 000000 0 ;PC 5743 ^ 5744 CHECKS (LOC,D,RESULT,RESULT)^ 5745 5746 035216 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5747 035217 312 01 0 00 041725 CAME AC1,[RESULT] ;IS LEFT HALF OF RESULT CORRECT? 5748 035220 254 00 0 00 035224 JRST ..0331 ;NO - GO TO ERROR HANDLING 5749 035221 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5750 035222 316 02 0 00 041725 CAMN AC1+1,[RESULT] ;IS RIGHT HALF CORRECT? 5751 035223 254 00 0 00 035227 JRST ..0332+1 ;YES - DONT DO ERROR HANDLING 5752 ; EXCEPT FOR ERLOOP DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 17-4 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST D SEQ 0143 5753 5754 035224 200 14 0 13 000001 ..0331: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5755 035225 200 13 0 13 042100 MOVE SCR1,[EXP RESULT,RESULT](SCR1) ;GET CORRECT RESULT 5756 035226 ..0332: ERROR (LOC,14,SCR1,SCR2,,TEST D - RESULT IS INCORRECT,SPRINT)^SALL 5757 035226 036 14 0 00 042107 5758 035227 255 00 0 00 000000 5759 ^ 5760 ^ 5761 035230 200 15 0 00 042134 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 5762 TFLAG ([FLAGS],D,SPRINT)^ 5763 5764 035231 200 13 0 00 035215 MOVE SCR1,FLAGL ;GET FLAGS 5765 035232 200 14 0 00 041634 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 5766 035233 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 5767 035234 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 5768 ERROR (LOC,13,SCR2,FLAGL,,TEST D - PC FLAGS INCORRECT (LEFT 4 BITS),SPRINT)^SALL 5769 035235 036 13 0 00 042135 5770 035236 255 00 0 00 000000 5771 ^ 5772 ^ 5773 ; ************************************************ 5774 5775 5776 ; ************************************************ 5777 5778 035237 LOC=. ;ERROR LOOP RETURN ADDRESS 5779 035414 CNUM=CNUM+4 ;POINT TO THE TEST CASE 5780 000005 REP=REP+1 ;REPETITION COUNT 5781 600000 000000 IFG REP-4, ;LARGEST POSITIVE NUMBER 5783 035237 200 15 0 00 042140 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5784 035240 120 01 0 00 035414 DMOVE AC1,CNUM ;INIT MINUEND TO FLOATING 0/1 5785 035241 255 17 0 00 035242 JFCL 17,.+1 ;CLEAR PC FLAGS 5786 035242 115 01 0 00 035416 DSUB AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 5787 PCSAVE^ 5788 035243 264 00 0 00 035244 JSR .+1 ;STORE PC 5789 035244 FLAGL=. ;LOCATION OF PC 5790 035244 000000 000000 0 ;PC 5791 ^ 5792 CHECKS (LOC,D,RESULT,RESULT)^ 5793 5794 035245 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5795 035246 312 01 0 00 042141 CAME AC1,[RESULT] ;IS LEFT HALF OF RESULT CORRECT? 5796 035247 254 00 0 00 035253 JRST ..0333 ;NO - GO TO ERROR HANDLING 5797 035250 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5798 035251 316 02 0 00 042141 CAMN AC1+1,[RESULT] ;IS RIGHT HALF CORRECT? 5799 035252 254 00 0 00 035256 JRST ..0334+1 ;YES - DONT DO ERROR HANDLING 5800 ; EXCEPT FOR ERLOOP 5801 5802 035253 200 14 0 13 000001 ..0333: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5803 035254 200 13 0 13 042141 MOVE SCR1,[EXP RESULT,RESULT](SCR1) ;GET CORRECT RESULT 5804 035255 ..0334: ERROR (LOC,14,SCR1,SCR2,,TEST D - RESULT IS INCORRECT,SPRINT)^SALL 5805 035255 036 14 0 00 042107 5806 035256 255 00 0 00 000000 5807 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 17-5 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST D SEQ 0144 5808 ^ 5809 035257 200 15 0 00 042140 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 5810 TFLAG ([FLAGS],D,SPRINT)^ 5811 5812 035260 200 13 0 00 035244 MOVE SCR1,FLAGL ;GET FLAGS 5813 035261 200 14 0 00 041664 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 5814 035262 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 5815 035263 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 5816 ERROR (LOC,13,SCR2,FLAGL,,TEST D - PC FLAGS INCORRECT (LEFT 4 BITS),SPRINT)^SALL 5817 035264 036 13 0 00 042143 5818 035265 255 00 0 00 000000 5819 ^ 5820 ^ 5821 ; ************************************************ 5822 5823 5824 ; ************************************************ 5825 5826 035266 LOC=. ;ERROR LOOP RETURN ADDRESS 5827 035420 CNUM=CNUM+4 ;POINT TO THE TEST CASE 5828 000006 REP=REP+1 ;REPETITION COUNT 5829 600000 000000 IFG REP-4, ;LARGEST POSITIVE NUMBER 5831 035266 200 15 0 00 042146 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5832 035267 120 01 0 00 035420 DMOVE AC1,CNUM ;INIT MINUEND TO FLOATING 0/1 5833 035270 255 17 0 00 035271 JFCL 17,.+1 ;CLEAR PC FLAGS 5834 035271 115 01 0 00 035422 DSUB AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 5835 PCSAVE^ 5836 035272 264 00 0 00 035273 JSR .+1 ;STORE PC 5837 035273 FLAGL=. ;LOCATION OF PC 5838 035273 000000 000000 0 ;PC 5839 ^ 5840 CHECKS (LOC,D,RESULT,RESULT)^ 5841 5842 035274 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5843 035275 312 01 0 00 042141 CAME AC1,[RESULT] ;IS LEFT HALF OF RESULT CORRECT? 5844 035276 254 00 0 00 035302 JRST ..0335 ;NO - GO TO ERROR HANDLING 5845 035277 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5846 035300 316 02 0 00 042141 CAMN AC1+1,[RESULT] ;IS RIGHT HALF CORRECT? 5847 035301 254 00 0 00 035305 JRST ..0336+1 ;YES - DONT DO ERROR HANDLING 5848 ; EXCEPT FOR ERLOOP 5849 5850 035302 200 14 0 13 000001 ..0335: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5851 035303 200 13 0 13 042141 MOVE SCR1,[EXP RESULT,RESULT](SCR1) ;GET CORRECT RESULT 5852 035304 ..0336: ERROR (LOC,14,SCR1,SCR2,,TEST D - RESULT IS INCORRECT,SPRINT)^SALL 5853 035304 036 14 0 00 042107 5854 035305 255 00 0 00 000000 5855 ^ 5856 ^ 5857 035306 200 15 0 00 042146 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 5858 TFLAG ([FLAGS],D,SPRINT)^ 5859 5860 035307 200 13 0 00 035273 MOVE SCR1,FLAGL ;GET FLAGS 5861 035310 200 14 0 00 041664 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 5862 035311 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 17-6 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST D SEQ 0145 5863 035312 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 5864 ERROR (LOC,13,SCR2,FLAGL,,TEST D - PC FLAGS INCORRECT (LEFT 4 BITS),SPRINT)^SALL 5865 035313 036 13 0 00 042147 5866 035314 255 00 0 00 000000 5867 ^ 5868 ^ 5869 ; ************************************************ 5870 5871 5872 ; ************************************************ 5873 5874 035315 LOC=. ;ERROR LOOP RETURN ADDRESS 5875 035424 CNUM=CNUM+4 ;POINT TO THE TEST CASE 5876 000007 REP=REP+1 ;REPETITION COUNT 5877 600000 000000 IFG REP-4, ;LARGEST POSITIVE NUMBER 5879 035315 200 15 0 00 042152 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5880 035316 120 01 0 00 035424 DMOVE AC1,CNUM ;INIT MINUEND TO FLOATING 0/1 5881 035317 255 17 0 00 035320 JFCL 17,.+1 ;CLEAR PC FLAGS 5882 035320 115 01 0 00 035426 DSUB AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 5883 PCSAVE^ 5884 035321 264 00 0 00 035322 JSR .+1 ;STORE PC 5885 035322 FLAGL=. ;LOCATION OF PC 5886 035322 000000 000000 0 ;PC 5887 ^ 5888 CHECKS (LOC,D,RESULT,RESULT)^ 5889 5890 035323 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5891 035324 312 01 0 00 042141 CAME AC1,[RESULT] ;IS LEFT HALF OF RESULT CORRECT? 5892 035325 254 00 0 00 035331 JRST ..0337 ;NO - GO TO ERROR HANDLING 5893 035326 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5894 035327 316 02 0 00 042141 CAMN AC1+1,[RESULT] ;IS RIGHT HALF CORRECT? 5895 035330 254 00 0 00 035334 JRST ..0340+1 ;YES - DONT DO ERROR HANDLING 5896 ; EXCEPT FOR ERLOOP 5897 5898 035331 200 14 0 13 000001 ..0337: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5899 035332 200 13 0 13 042141 MOVE SCR1,[EXP RESULT,RESULT](SCR1) ;GET CORRECT RESULT 5900 035333 ..0340: ERROR (LOC,14,SCR1,SCR2,,TEST D - RESULT IS INCORRECT,SPRINT)^SALL 5901 035333 036 14 0 00 042107 5902 035334 255 00 0 00 000000 5903 ^ 5904 ^ 5905 035335 200 15 0 00 042152 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 5906 TFLAG ([FLAGS],D,SPRINT)^ 5907 5908 035336 200 13 0 00 035322 MOVE SCR1,FLAGL ;GET FLAGS 5909 035337 200 14 0 00 041664 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 5910 035340 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 5911 035341 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 5912 ERROR (LOC,13,SCR2,FLAGL,,TEST D - PC FLAGS INCORRECT (LEFT 4 BITS),SPRINT)^SALL 5913 035342 036 13 0 00 042153 5914 035343 255 00 0 00 000000 5915 ^ 5916 ^ 5917 ; ************************************************ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 17-7 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST D SEQ 0146 5918 5919 5920 ; ************************************************ 5921 5922 035344 LOC=. ;ERROR LOOP RETURN ADDRESS 5923 035430 CNUM=CNUM+4 ;POINT TO THE TEST CASE 5924 000010 REP=REP+1 ;REPETITION COUNT 5925 600000 000000 IFG REP-4, ;LARGEST POSITIVE NUMBER 5927 035344 200 15 0 00 042156 MOVE SCR3,[CNUM,,CNUM+2] ;ADDRESS OF ADDL ERROR PRINT 5928 035345 120 01 0 00 035430 DMOVE AC1,CNUM ;INIT MINUEND TO FLOATING 0/1 5929 035346 255 17 0 00 035347 JFCL 17,.+1 ;CLEAR PC FLAGS 5930 035347 115 01 0 00 035432 DSUB AC1,CNUM+2 ;MAKE IT OVERFLOW (POS OR NEG) 5931 PCSAVE^ 5932 035350 264 00 0 00 035351 JSR .+1 ;STORE PC 5933 035351 FLAGL=. ;LOCATION OF PC 5934 035351 000000 000000 0 ;PC 5935 ^ 5936 CHECKS (LOC,D,RESULT,RESULT)^ 5937 5938 035352 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD IN ERROR 5939 035353 312 01 0 00 042141 CAME AC1,[RESULT] ;IS LEFT HALF OF RESULT CORRECT? 5940 035354 254 00 0 00 035360 JRST ..0341 ;NO - GO TO ERROR HANDLING 5941 035355 201 13 0 00 000001 MOVEI SCR1,1 ;YES, POINTER TO RIGHT HALF 5942 035356 316 02 0 00 042141 CAMN AC1+1,[RESULT] ;IS RIGHT HALF CORRECT? 5943 035357 254 00 0 00 035363 JRST ..0342+1 ;YES - DONT DO ERROR HANDLING 5944 ; EXCEPT FOR ERLOOP 5945 5946 035360 200 14 0 13 000001 ..0341: MOVE SCR2,AC1(SCR1) ;GET ACTUAL WORD OF RESULT 5947 035361 200 13 0 13 042141 MOVE SCR1,[EXP RESULT,RESULT](SCR1) ;GET CORRECT RESULT 5948 035362 ..0342: ERROR (LOC,14,SCR1,SCR2,,TEST D - RESULT IS INCORRECT,SPRINT)^SALL 5949 035362 036 14 0 00 042107 5950 035363 255 00 0 00 000000 5951 ^ 5952 ^ 5953 035364 200 15 0 00 042156 MOVE SCR3,[CNUM,,CNUM+2] ;SCR3 - ADDR OF ADDL ERROR PRINT 5954 TFLAG ([FLAGS],D,SPRINT)^ 5955 5956 035365 200 13 0 00 035351 MOVE SCR1,FLAGL ;GET FLAGS 5957 035366 200 14 0 00 041664 MOVE SCR2,[FLAGS] ;SCR2 - CORRECT FLAGS 5958 035367 430 13 0 00 000014 XOR SCR1,SCR2 ;SET ALL MATCHING BITS TO 0 5959 035370 603 13 0 00 740000 TLNE SCR1,740000 ;TEST IF MATCH CORRECTLY 5960 ERROR (LOC,13,SCR2,FLAGL,,TEST D - PC FLAGS INCORRECT (LEFT 4 BITS),SPRINT)^SALL 5961 035371 036 13 0 00 042157 5962 035372 200 17 0 00 030303 5963 ^ 5964 ^ 5965 ; ************************************************ 5966 5967 035373 254 00 0 00 035434 JRST SENDD ;SKIP OVER DATA 5968 5969 ; ********************************************************************** 5970 ; 8 SETS OF 3 DOUBLEWORDS (MINUEND,SUBTRAHEND,RESULT) 5971 ; ********************************************************************** 5972 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 17-8 DSKCFM MAC 26-Sep-79 15:49 DSUB - TEST D SEQ 0147 5973 035374 200000 000000 SCOND: EXP 1B1,0,^B11B1,0 5974 035375 000000 000000 5975 035376 600000 000000 5976 035377 000000 000000 5977 035400 000000 000001 EXP 1,0,1B0+1,0 5978 035401 000000 000000 5979 035402 400000 000001 5980 035403 000000 000000 5981 035404 000000 000000 EXP 0,1B1,1B0,1B1 5982 035405 200000 000000 5983 035406 400000 000000 5984 035407 200000 000000 5985 035410 000000 000000 EXP 0,1,1B0,1 5986 035411 000000 000001 5987 035412 400000 000000 5988 035413 000000 000001 5989 035414 577777 777777 EXP 577777777777,-1,1B1,0 5990 035415 777777 777777 5991 035416 200000 000000 5992 035417 000000 000000 5993 035420 777777 777776 EXP 777777777776,-1,377777777777,0 5994 035421 777777 777777 5995 035422 377777 777777 5996 035423 000000 000000 5997 035424 777777 777777 EXP -1,577777777777,377777777777,^B11B1 5998 035425 577777 777777 5999 035426 377777 777777 6000 035427 600000 000000 6001 035430 777777 777777 EXP -1,-2,377777777777,-1 6002 035431 777777 777776 6003 035432 377777 777777 6004 035433 777777 777777 6005 035434 SENDD: DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 18 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST A SEQ 0148 6006 SUBTTL DMUL - TEST A 6007 SALL 6008 042162 T=SIXBTZ 6009 LALL 6010 ; ********************************************************************** 6011 ;*DMUL - TEST A 6012 ;* 6013 ;* 0,# * 0 = 0 0 * 0,# = 0 THESE ARE GENERAL TESTS TO 6014 ;* #,0 * 0 = 0 0 * #,0 = 0 ASCERTAIN THAT THE DMUL CAN 6015 ;* #,# * 0 = 0 0 * #,# = 0 HANDLE DOUBLEWORDS. THE ACS 6016 ;* -1,-# * 0 = 0 0 * -1,-# = 0 WILL CONTAIN THE RESULT ARE 6017 ;* -#,0 * 0 = 0 0 * -#,0 = 0 FILLED WITH GARBAGE AND THE 6018 ;* -#,-# * 0 = 0 0 * -#,-# = 0 RESULT IS CHECKED TO SEE THAT 6019 ;* 0,0 * 0 = 0 DMUL PRODUCES A 4-WORD LONG 6020 ;* RESULT IN THE ACS. 6021 ; ********************************************************************** 6022 6023 ; ********************************************************************** 6024 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6025 ; ********************************************************************** 6026 6027 MULT (A,0,NUM)^ 6028 6029 ; --- MULTIPLICAND = (0,NUM) 6030 ; --- MULTIPLIER === (0,0) 6031 ; --- RESULT ======= (0,0,0,0) 6032 6033 035434 200 01 0 00 042174 ..0343: MOVE AC1,[[EXP 0,NUM,0,0,0,0,0,0],,MCAND] 6034 035435 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6035 035436 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6036 ERROR (..0343,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6037 035437 036 14 0 00 042204 6038 035440 255 00 0 00 000000 6039 ^ 6040 ^ 6041 6042 ; ********************************************************************** 6043 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6044 ; ********************************************************************** 6045 6046 MULT (A,NUM)^ 6047 6048 ; --- MULTIPLICAND = (NUM,0) 6049 ; --- MULTIPLIER === (0,0) 6050 ; --- RESULT ======= (0,0,0,0) 6051 6052 035441 200 01 0 00 042217 ..0344: MOVE AC1,[[EXP NUM,0,0,0,0,0,0,0],,MCAND] 6053 035442 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6054 035443 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6055 ERROR (..0344,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6056 035444 036 14 0 00 042204 6057 035445 255 00 0 00 000000 6058 ^ 6059 ^ 6060 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 18-1 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST A SEQ 0149 6061 ; ********************************************************************** 6062 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6063 ; ********************************************************************** 6064 6065 MULT (A,NUM,NUM)^ 6066 6067 ; --- MULTIPLICAND = (NUM,NUM) 6068 ; --- MULTIPLIER === (0,0) 6069 ; --- RESULT ======= (0,0,0,0) 6070 6071 035446 200 01 0 00 042230 ..0345: MOVE AC1,[[EXP NUM,NUM,0,0,0,0,0,0],,MCAND] 6072 035447 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6073 035450 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6074 ERROR (..0345,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6075 035451 036 14 0 00 042204 6076 035452 255 00 0 00 000000 6077 ^ 6078 ^ 6079 6080 ; ********************************************************************** 6081 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6082 ; ********************************************************************** 6083 6084 MULT (A,0,0,0,NUM)^ 6085 6086 ; --- MULTIPLICAND = (0,0) 6087 ; --- MULTIPLIER === (0,NUM) 6088 ; --- RESULT ======= (0,0,0,0) 6089 6090 035453 200 01 0 00 042241 ..0346: MOVE AC1,[[EXP 0,0,0,NUM,0,0,0,0],,MCAND] 6091 035454 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6092 035455 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6093 ERROR (..0346,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6094 035456 036 14 0 00 042204 6095 035457 255 00 0 00 000000 6096 ^ 6097 ^ 6098 6099 ; ********************************************************************** 6100 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6101 ; ********************************************************************** 6102 6103 MULT (A,0,0,NUM)^ 6104 6105 ; --- MULTIPLICAND = (0,0) 6106 ; --- MULTIPLIER === (NUM,0) 6107 ; --- RESULT ======= (0,0,0,0) 6108 6109 035460 200 01 0 00 042252 ..0347: MOVE AC1,[[EXP 0,0,NUM,0,0,0,0,0],,MCAND] 6110 035461 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6111 035462 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6112 ERROR (..0347,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6113 035463 036 14 0 00 042204 6114 035464 255 00 0 00 000000 6115 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 18-2 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST A SEQ 0150 6116 ^ 6117 6118 ; ********************************************************************** 6119 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6120 ; ********************************************************************** 6121 6122 MULT (A,0,0,NUM,NUM)^ 6123 6124 ; --- MULTIPLICAND = (0,0) 6125 ; --- MULTIPLIER === (NUM,NUM) 6126 ; --- RESULT ======= (0,0,0,0) 6127 6128 035465 200 01 0 00 042263 ..0350: MOVE AC1,[[EXP 0,0,NUM,NUM,0,0,0,0],,MCAND] 6129 035466 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6130 035467 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6131 ERROR (..0350,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6132 035470 036 14 0 00 042204 6133 035471 255 00 0 00 000000 6134 ^ 6135 ^ 6136 6137 ; ********************************************************************** 6138 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6139 ; ********************************************************************** 6140 6141 MULT (A,-1,-NUM)^ 6142 6143 ; --- MULTIPLICAND = (-1,-NUM) 6144 ; --- MULTIPLIER === (0,0) 6145 ; --- RESULT ======= (0,0,0,0) 6146 6147 035472 200 01 0 00 042274 ..0351: MOVE AC1,[[EXP -1,-NUM,0,0,0,0,0,0],,MCAND] 6148 035473 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6149 035474 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6150 ERROR (..0351,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6151 035475 036 14 0 00 042204 6152 035476 255 00 0 00 000000 6153 ^ 6154 ^ 6155 6156 ; ********************************************************************** 6157 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6158 ; ********************************************************************** 6159 6160 MULT (A,-NUM,-1)^ 6161 6162 ; --- MULTIPLICAND = (-NUM,-1) 6163 ; --- MULTIPLIER === (0,0) 6164 ; --- RESULT ======= (0,0,0,0) 6165 6166 035477 200 01 0 00 042305 ..0352: MOVE AC1,[[EXP -NUM,-1,0,0,0,0,0,0],,MCAND] 6167 035500 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6168 035501 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6169 ERROR (..0352,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6170 035502 036 14 0 00 042204 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 18-3 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST A SEQ 0151 6171 035503 255 00 0 00 000000 6172 ^ 6173 ^ 6174 6175 ; ********************************************************************** 6176 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6177 ; ********************************************************************** 6178 6179 MULT (A,-NUM,-NUM)^ 6180 6181 ; --- MULTIPLICAND = (-NUM,-NUM) 6182 ; --- MULTIPLIER === (0,0) 6183 ; --- RESULT ======= (0,0,0,0) 6184 6185 035504 200 01 0 00 042316 ..0353: MOVE AC1,[[EXP -NUM,-NUM,0,0,0,0,0,0],,MCAND] 6186 035505 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6187 035506 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6188 ERROR (..0353,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6189 035507 036 14 0 00 042204 6190 035510 255 00 0 00 000000 6191 ^ 6192 ^ 6193 6194 ; ********************************************************************** 6195 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6196 ; ********************************************************************** 6197 6198 MULT (A,0,0,-1,-NUM)^ 6199 6200 ; --- MULTIPLICAND = (0,0) 6201 ; --- MULTIPLIER === (-1,-NUM) 6202 ; --- RESULT ======= (0,0,0,0) 6203 6204 035511 200 01 0 00 042327 ..0354: MOVE AC1,[[EXP 0,0,-1,-NUM,0,0,0,0],,MCAND] 6205 035512 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6206 035513 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6207 ERROR (..0354,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6208 035514 036 14 0 00 042204 6209 035515 255 00 0 00 000000 6210 ^ 6211 ^ 6212 6213 ; ********************************************************************** 6214 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6215 ; ********************************************************************** 6216 6217 MULT (A,0,0,-NUM,-1)^ 6218 6219 ; --- MULTIPLICAND = (0,0) 6220 ; --- MULTIPLIER === (-NUM,-1) 6221 ; --- RESULT ======= (0,0,0,0) 6222 6223 035516 200 01 0 00 042340 ..0355: MOVE AC1,[[EXP 0,0,-NUM,-1,0,0,0,0],,MCAND] 6224 035517 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6225 035520 260 17 0 00 040451 GO MSUBR ;GO DO TEST DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 18-4 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST A SEQ 0152 6226 ERROR (..0355,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6227 035521 036 14 0 00 042204 6228 035522 255 00 0 00 000000 6229 ^ 6230 ^ 6231 6232 ; ********************************************************************** 6233 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6234 ; ********************************************************************** 6235 6236 MULT (A,0,0,-NUM,-NUM)^ 6237 6238 ; --- MULTIPLICAND = (0,0) 6239 ; --- MULTIPLIER === (-NUM,-NUM) 6240 ; --- RESULT ======= (0,0,0,0) 6241 6242 035523 200 01 0 00 042351 ..0356: MOVE AC1,[[EXP 0,0,-NUM,-NUM,0,0,0,0],,MCAND] 6243 035524 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6244 035525 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6245 ERROR (..0356,14,SCR1,SCR2,,TEST A - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6246 035526 036 14 0 00 042204 6247 035527 255 00 0 00 000000 6248 ^ 6249 ^ 6250 6251 ; ********************************************************************** 6252 ; ---------- DMUL - TEST A - # * 0 = 0 ---------- 6253 ; ********************************************************************** 6254 6255 MULT^ 6256 6257 ; --- MULTIPLICAND = (0,0) 6258 ; --- MULTIPLIER === (0,0) 6259 ; --- RESULT ======= (0,0,0,0) 6260 6261 035530 200 01 0 00 042362 ..0357: MOVE AC1,[[EXP 0,0,0,0,0,0,0,0],,MCAND] 6262 035531 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6263 035532 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6264 ERROR (..0357,14,SCR1,SCR2,,TEST - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6265 035533 036 14 0 00 042372 6266 035534 255 00 0 00 000000 6267 ^ 6268 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 19 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST B SEQ 0153 6269 SUBTTL DMUL - TEST B 6270 6271 ; ********************************************************************** 6272 ;*DMUL - TEST B 6273 ;* 6274 ;* 0,# * 1 = 0,# THESE TEST THE DMUL ON A SLIGHTLY 6275 ;* #,0 * 1 = #,0 STEEPER GRADIENT. THIS WILL VERIFY 6276 ;* #,# * 1 = #,# THAT THE DMUL HANDLES DOUBLEWORDS AND 6277 ;* -1,-# * 1 = -1,-# A NON-ZERO MULTIPLIER. THESE TESTS ARE 6278 ;* -#,-1 * 1 = -#,-1 REPEATED WITH THE MULTIPLICAND AND THE 6279 ;* -#,-# * 1 = -#,-# MULTIPLIER REVERSED. 6280 ; ********************************************************************** 6281 6282 ; ********************************************************************** 6283 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6284 ; ********************************************************************** 6285 6286 MULT (B,0,NUM,0,1,0,0,0,NUM)^ 6287 6288 ; --- MULTIPLICAND = (0,NUM) 6289 ; --- MULTIPLIER === (0,1) 6290 ; --- RESULT ======= (0,0,0,NUM) 6291 6292 035535 200 01 0 00 042405 ..0360: MOVE AC1,[[EXP 0,NUM,0,1,0,0,0,NUM],,MCAND] 6293 035536 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6294 035537 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6295 ERROR (..0360,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6296 035540 036 14 0 00 042415 6297 035541 255 00 0 00 000000 6298 ^ 6299 ^ 6300 6301 ; ********************************************************************** 6302 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6303 ; ********************************************************************** 6304 6305 MULT (B,NUM,0,0,1,0,0,NUM)^ 6306 6307 ; --- MULTIPLICAND = (NUM,0) 6308 ; --- MULTIPLIER === (0,1) 6309 ; --- RESULT ======= (0,0,NUM,0) 6310 6311 035542 200 01 0 00 042430 ..0361: MOVE AC1,[[EXP NUM,0,0,1,0,0,NUM,0],,MCAND] 6312 035543 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6313 035544 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6314 ERROR (..0361,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6315 035545 036 14 0 00 042415 6316 035546 255 00 0 00 000000 6317 ^ 6318 ^ 6319 6320 ; ********************************************************************** 6321 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6322 ; ********************************************************************** 6323 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 19-1 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST B SEQ 0154 6324 MULT (B,NUM,NUM,0,1,0,0,NUM,NUM)^ 6325 6326 ; --- MULTIPLICAND = (NUM,NUM) 6327 ; --- MULTIPLIER === (0,1) 6328 ; --- RESULT ======= (0,0,NUM,NUM) 6329 6330 035547 200 01 0 00 042441 ..0362: MOVE AC1,[[EXP NUM,NUM,0,1,0,0,NUM,NUM],,MCAND] 6331 035550 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6332 035551 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6333 ERROR (..0362,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6334 035552 036 14 0 00 042415 6335 035553 255 00 0 00 000000 6336 ^ 6337 ^ 6338 6339 ; ********************************************************************** 6340 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6341 ; ********************************************************************** 6342 6343 MULT (B,0,1,0,NUM,0,0,0,NUM)^ 6344 6345 ; --- MULTIPLICAND = (0,1) 6346 ; --- MULTIPLIER === (0,NUM) 6347 ; --- RESULT ======= (0,0,0,NUM) 6348 6349 035554 200 01 0 00 042452 ..0363: MOVE AC1,[[EXP 0,1,0,NUM,0,0,0,NUM],,MCAND] 6350 035555 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6351 035556 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6352 ERROR (..0363,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6353 035557 036 14 0 00 042415 6354 035560 255 00 0 00 000000 6355 ^ 6356 ^ 6357 6358 ; ********************************************************************** 6359 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6360 ; ********************************************************************** 6361 6362 MULT (B,0,1,NUM,0,0,0,NUM)^ 6363 6364 ; --- MULTIPLICAND = (0,1) 6365 ; --- MULTIPLIER === (NUM,0) 6366 ; --- RESULT ======= (0,0,NUM,0) 6367 6368 035561 200 01 0 00 042463 ..0364: MOVE AC1,[[EXP 0,1,NUM,0,0,0,NUM,0],,MCAND] 6369 035562 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6370 035563 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6371 ERROR (..0364,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6372 035564 036 14 0 00 042415 6373 035565 255 00 0 00 000000 6374 ^ 6375 ^ 6376 6377 ; ********************************************************************** 6378 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 19-2 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST B SEQ 0155 6379 ; ********************************************************************** 6380 6381 MULT (B,0,1,NUM,NUM,0,0,NUM,NUM)^ 6382 6383 ; --- MULTIPLICAND = (0,1) 6384 ; --- MULTIPLIER === (NUM,NUM) 6385 ; --- RESULT ======= (0,0,NUM,NUM) 6386 6387 035566 200 01 0 00 042474 ..0365: MOVE AC1,[[EXP 0,1,NUM,NUM,0,0,NUM,NUM],,MCAND] 6388 035567 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6389 035570 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6390 ERROR (..0365,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6391 035571 036 14 0 00 042415 6392 035572 255 00 0 00 000000 6393 ^ 6394 ^ 6395 6396 ; ********************************************************************** 6397 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6398 ; ********************************************************************** 6399 6400 MULT (B,-1,-NUM,0,1,-1,-1,-1,-NUM)^ 6401 6402 ; --- MULTIPLICAND = (-1,-NUM) 6403 ; --- MULTIPLIER === (0,1) 6404 ; --- RESULT ======= (-1,-1,-1,-NUM) 6405 6406 035573 200 01 0 00 042505 ..0366: MOVE AC1,[[EXP -1,-NUM,0,1,-1,-1,-1,-NUM],,MCAND] 6407 035574 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6408 035575 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6409 ERROR (..0366,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6410 035576 036 14 0 00 042415 6411 035577 255 00 0 00 000000 6412 ^ 6413 ^ 6414 6415 ; ********************************************************************** 6416 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6417 ; ********************************************************************** 6418 6419 MULT (B,-NUM,-1,0,1,-1,-1,-NUM,-1)^ 6420 6421 ; --- MULTIPLICAND = (-NUM,-1) 6422 ; --- MULTIPLIER === (0,1) 6423 ; --- RESULT ======= (-1,-1,-NUM,-1) 6424 6425 035600 200 01 0 00 042516 ..0367: MOVE AC1,[[EXP -NUM,-1,0,1,-1,-1,-NUM,-1],,MCAND] 6426 035601 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6427 035602 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6428 ERROR (..0367,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6429 035603 036 14 0 00 042415 6430 035604 255 00 0 00 000000 6431 ^ 6432 ^ 6433 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 19-3 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST B SEQ 0156 6434 ; ********************************************************************** 6435 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6436 ; ********************************************************************** 6437 6438 MULT (B,-NUM,-NUM,0,1,-1,-1,-NUM,-NUM)^ 6439 6440 ; --- MULTIPLICAND = (-NUM,-NUM) 6441 ; --- MULTIPLIER === (0,1) 6442 ; --- RESULT ======= (-1,-1,-NUM,-NUM) 6443 6444 035605 200 01 0 00 042527 ..0370: MOVE AC1,[[EXP -NUM,-NUM,0,1,-1,-1,-NUM,-NUM],,MCAND] 6445 035606 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6446 035607 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6447 ERROR (..0370,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6448 035610 036 14 0 00 042415 6449 035611 255 00 0 00 000000 6450 ^ 6451 ^ 6452 6453 ; ********************************************************************** 6454 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6455 ; ********************************************************************** 6456 6457 MULT (B,0,1,-1,-NUM,-1,-1,-1,-NUM)^ 6458 6459 ; --- MULTIPLICAND = (0,1) 6460 ; --- MULTIPLIER === (-1,-NUM) 6461 ; --- RESULT ======= (-1,-1,-1,-NUM) 6462 6463 035612 200 01 0 00 042540 ..0371: MOVE AC1,[[EXP 0,1,-1,-NUM,-1,-1,-1,-NUM],,MCAND] 6464 035613 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6465 035614 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6466 ERROR (..0371,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6467 035615 036 14 0 00 042415 6468 035616 255 00 0 00 000000 6469 ^ 6470 ^ 6471 6472 ; ********************************************************************** 6473 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6474 ; ********************************************************************** 6475 6476 MULT (B,0,1,-NUM,-1,-1,-1,-NUM,-1)^ 6477 6478 ; --- MULTIPLICAND = (0,1) 6479 ; --- MULTIPLIER === (-NUM,-1) 6480 ; --- RESULT ======= (-1,-1,-NUM,-1) 6481 6482 035617 200 01 0 00 042551 ..0372: MOVE AC1,[[EXP 0,1,-NUM,-1,-1,-1,-NUM,-1],,MCAND] 6483 035620 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6484 035621 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6485 ERROR (..0372,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6486 035622 036 14 0 00 042415 6487 035623 255 00 0 00 000000 6488 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 19-4 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST B SEQ 0157 6489 ^ 6490 6491 ; ********************************************************************** 6492 ; ---------- DMUL - TEST B - # * 1 = 1 ---------- 6493 ; ********************************************************************** 6494 6495 MULT (B,0,1,-NUM,-NUM,-1,-1,-NUM,-NUM)^ 6496 6497 ; --- MULTIPLICAND = (0,1) 6498 ; --- MULTIPLIER === (-NUM,-NUM) 6499 ; --- RESULT ======= (-1,-1,-NUM,-NUM) 6500 6501 035624 200 01 0 00 042562 ..0373: MOVE AC1,[[EXP 0,1,-NUM,-NUM,-1,-1,-NUM,-NUM],,MCAND] 6502 035625 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6503 035626 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6504 ERROR (..0373,14,SCR1,SCR2,,TEST B - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6505 035627 036 14 0 00 042415 6506 035630 255 00 0 00 000000 6507 ^ 6508 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0158 6509 SUBTTL DMUL - TEST C 6510 6511 ; ********************************************************************** 6512 ;*DMUL - TEST C 6513 ;* 6514 ;* 0,1777.. * 2 THESE TESTS VERIFY THAT BITS ARE 6515 ;* 0,3777.. * 2 SHIFTED ACROSS WORD BOUNDARIES. A WORD 6516 ;* 1777..,3777.. * 2 OF ONES IS MULTIPLIED BY A FLOATING 1 6517 ;* 3777..,3777.. * 2 WHICH WILL CAUSE A SHIFT ACROSS WORD 6518 ;* 0,3777.. * 1,0 BOUNDARIES OR NOT. THE TEST VERIFIES 6519 ;* 1,3777.. * 1,0 THAT THE SHIFT IS DONE PROPERLY FOR 6520 ;* 3777..,3777.. * 1,0 BOUNDARY CONDITIONS. 6521 ;* 0,1777.. * 2,0 IN EACH TEST THE PC FLAGS ARE TESTED 6522 ;* 0,3777.. * 2,0 SINCE THERE ARE NO OVERFLOW CONDITIONS 6523 ;* 3777..,3777.. * 2,0 THE LEFTMOST BIT OF THE PC SHOULD BE 6524 ;* 0 (NO AROV). 6525 ;* THESE TESTS ARE REPEATED WITH MULT- 6526 ;* PLICAND AND MULTIPLIER REVERSED. 6527 ; ********************************************************************** 6528 6529 ; ********************************************************************** 6530 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6531 ; ********************************************************************** 6532 6533 MULTF (C,0,177777777777,0,2,0,0,0,377777777776)^ 6534 6535 ; --- MULTIPLICAND = (0,177777777777) 6536 ; --- MULTIPLIER === (0,2) 6537 ; --- RESULT ======= (0,0,0,377777777776) 6538 6539 035631 200 01 0 00 042573 ..0374: MOVE AC1,[[EXP 0,177777777777,0,2,0,0,0,377777777776],,MCAND] 6540 035632 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6541 035633 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6542 ERROR (..0374,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6543 035634 036 14 0 00 042603 6544 035635 255 00 0 00 000000 6545 ^ 6546 6547 035636 200 14 0 00 040457 ..0375: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6548 035637 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6549 ERROR (..0374,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6550 LL 6551 035640 036 13 0 00 042615 6552 035641 255 00 0 00 000000 6553 ^ 6554 ^ 6555 6556 ; ********************************************************************** 6557 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6558 ; ********************************************************************** 6559 6560 MULTF (C,0,377777777777,0,2,0,0,1,377777777776)^ 6561 6562 ; --- MULTIPLICAND = (0,377777777777) 6563 ; --- MULTIPLIER === (0,2) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-1 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0159 6564 ; --- RESULT ======= (0,0,1,377777777776) 6565 6566 035642 200 01 0 00 042630 ..0376: MOVE AC1,[[EXP 0,377777777777,0,2,0,0,1,377777777776],,MCAND] 6567 035643 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6568 035644 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6569 ERROR (..0376,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6570 035645 036 14 0 00 042603 6571 035646 255 00 0 00 000000 6572 ^ 6573 6574 035647 200 14 0 00 040457 ..0377: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6575 035650 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6576 ERROR (..0376,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6577 LL 6578 035651 036 13 0 00 042615 6579 035652 255 00 0 00 000000 6580 ^ 6581 ^ 6582 6583 ; ********************************************************************** 6584 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6585 ; ********************************************************************** 6586 6587 MULTF (C,177777777777,377777777777,0,2,0,0,377777777777,377777777776)^ 6588 6589 ; --- MULTIPLICAND = (177777777777,377777777777) 6590 ; --- MULTIPLIER === (0,2) 6591 ; --- RESULT ======= (0,0,377777777777,377777777776) 6592 6593 ..0400: MOVE AC1,[[EXP 177777777777,377777777777,0,2,0,0,377777777777,377777777776],,MCA 6594 035653 200 01 0 00 042641 ND] 6595 035654 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6596 035655 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6597 ERROR (..0400,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6598 035656 036 14 0 00 042603 6599 035657 255 00 0 00 000000 6600 ^ 6601 6602 035660 200 14 0 00 040457 ..0401: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6603 035661 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6604 ERROR (..0400,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6605 LL 6606 035662 036 13 0 00 042615 6607 035663 255 00 0 00 000000 6608 ^ 6609 ^ 6610 6611 ; ********************************************************************** 6612 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6613 ; ********************************************************************** 6614 6615 MULTF (C,377777777777,377777777777,0,2,0,1,377777777777,377777777776)^ 6616 6617 ; --- MULTIPLICAND = (377777777777,377777777777) 6618 ; --- MULTIPLIER === (0,2) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-2 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0160 6619 ; --- RESULT ======= (0,1,377777777777,377777777776) 6620 6621 ..0402: MOVE AC1,[[EXP 377777777777,377777777777,0,2,0,1,377777777777,377777777776],,MCA 6622 035664 200 01 0 00 042652 ND] 6623 035665 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6624 035666 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6625 ERROR (..0402,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6626 035667 036 14 0 00 042603 6627 035670 255 00 0 00 000000 6628 ^ 6629 6630 035671 200 14 0 00 040457 ..0403: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6631 035672 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6632 ERROR (..0402,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6633 LL 6634 035673 036 13 0 00 042615 6635 035674 255 00 0 00 000000 6636 ^ 6637 ^ 6638 6639 ; ********************************************************************** 6640 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6641 ; ********************************************************************** 6642 6643 MULTF (C,0,377777777777,1,0,0,0,377777777777)^ 6644 6645 ; --- MULTIPLICAND = (0,377777777777) 6646 ; --- MULTIPLIER === (1,0) 6647 ; --- RESULT ======= (0,0,377777777777,0) 6648 6649 035675 200 01 0 00 042663 ..0404: MOVE AC1,[[EXP 0,377777777777,1,0,0,0,377777777777,0],,MCAND] 6650 035676 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6651 035677 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6652 ERROR (..0404,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6653 035700 036 14 0 00 042603 6654 035701 255 00 0 00 000000 6655 ^ 6656 6657 035702 200 14 0 00 040457 ..0405: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6658 035703 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6659 ERROR (..0404,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6660 LL 6661 035704 036 13 0 00 042615 6662 035705 255 00 0 00 000000 6663 ^ 6664 ^ 6665 6666 ; ********************************************************************** 6667 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6668 ; ********************************************************************** 6669 6670 MULTF (C,1,377777777777,1,0,0,1,377777777777)^ 6671 6672 ; --- MULTIPLICAND = (1,377777777777) 6673 ; --- MULTIPLIER === (1,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-3 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0161 6674 ; --- RESULT ======= (0,1,377777777777,0) 6675 6676 035706 200 01 0 00 042674 ..0406: MOVE AC1,[[EXP 1,377777777777,1,0,0,1,377777777777,0],,MCAND] 6677 035707 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6678 035710 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6679 ERROR (..0406,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6680 035711 036 14 0 00 042603 6681 035712 255 00 0 00 000000 6682 ^ 6683 6684 035713 200 14 0 00 040457 ..0407: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6685 035714 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6686 ERROR (..0406,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6687 LL 6688 035715 036 13 0 00 042615 6689 035716 255 00 0 00 000000 6690 ^ 6691 ^ 6692 6693 ; ********************************************************************** 6694 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6695 ; ********************************************************************** 6696 6697 MULTF (C,377777777777,377777777777,1,0,0,377777777777,377777777777)^ 6698 6699 ; --- MULTIPLICAND = (377777777777,377777777777) 6700 ; --- MULTIPLIER === (1,0) 6701 ; --- RESULT ======= (0,377777777777,377777777777,0) 6702 6703 ..0410: MOVE AC1,[[EXP 377777777777,377777777777,1,0,0,377777777777,377777777777,0],,MCA 6704 035717 200 01 0 00 042705 ND] 6705 035720 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6706 035721 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6707 ERROR (..0410,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6708 035722 036 14 0 00 042603 6709 035723 255 00 0 00 000000 6710 ^ 6711 6712 035724 200 14 0 00 040457 ..0411: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6713 035725 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6714 ERROR (..0410,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6715 LL 6716 035726 036 13 0 00 042615 6717 035727 255 00 0 00 000000 6718 ^ 6719 ^ 6720 6721 ; ********************************************************************** 6722 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6723 ; ********************************************************************** 6724 6725 MULTF (C,0,177777777777,2,0,0,0,377777777776)^ 6726 6727 ; --- MULTIPLICAND = (0,177777777777) 6728 ; --- MULTIPLIER === (2,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-4 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0162 6729 ; --- RESULT ======= (0,0,377777777776,0) 6730 6731 035730 200 01 0 00 042716 ..0412: MOVE AC1,[[EXP 0,177777777777,2,0,0,0,377777777776,0],,MCAND] 6732 035731 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6733 035732 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6734 ERROR (..0412,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6735 035733 036 14 0 00 042603 6736 035734 255 00 0 00 000000 6737 ^ 6738 6739 035735 200 14 0 00 040457 ..0413: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6740 035736 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6741 ERROR (..0412,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6742 LL 6743 035737 036 13 0 00 042615 6744 035740 255 00 0 00 000000 6745 ^ 6746 ^ 6747 6748 ; ********************************************************************** 6749 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6750 ; ********************************************************************** 6751 6752 MULTF (C,0,377777777777,2,0,0,1,377777777776)^ 6753 6754 ; --- MULTIPLICAND = (0,377777777777) 6755 ; --- MULTIPLIER === (2,0) 6756 ; --- RESULT ======= (0,1,377777777776,0) 6757 6758 035741 200 01 0 00 042727 ..0414: MOVE AC1,[[EXP 0,377777777777,2,0,0,1,377777777776,0],,MCAND] 6759 035742 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6760 035743 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6761 ERROR (..0414,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6762 035744 036 14 0 00 042603 6763 035745 255 00 0 00 000000 6764 ^ 6765 6766 035746 200 14 0 00 040457 ..0415: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6767 035747 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6768 ERROR (..0414,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6769 LL 6770 035750 036 13 0 00 042615 6771 035751 255 00 0 00 000000 6772 ^ 6773 ^ 6774 6775 ; ********************************************************************** 6776 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6777 ; ********************************************************************** 6778 6779 MULTF (C,377777777777,377777777777,2,0,1,377777777777,377777777776)^ 6780 6781 ; --- MULTIPLICAND = (377777777777,377777777777) 6782 ; --- MULTIPLIER === (2,0) 6783 ; --- RESULT ======= (1,377777777777,377777777776,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-5 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0163 6784 6785 ..0416: MOVE AC1,[[EXP 377777777777,377777777777,2,0,1,377777777777,377777777776,0],,MCA 6786 035752 200 01 0 00 042740 ND] 6787 035753 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6788 035754 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6789 ERROR (..0416,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6790 035755 036 14 0 00 042603 6791 035756 255 00 0 00 000000 6792 ^ 6793 6794 035757 200 14 0 00 040457 ..0417: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6795 035760 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6796 ERROR (..0416,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6797 LL 6798 035761 036 13 0 00 042615 6799 035762 255 00 0 00 000000 6800 ^ 6801 ^ 6802 6803 ; ********************************************************************** 6804 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6805 ; ********************************************************************** 6806 6807 MULTF (C,0,2,0,177777777777,0,0,0,377777777776)^ 6808 6809 ; --- MULTIPLICAND = (0,2) 6810 ; --- MULTIPLIER === (0,177777777777) 6811 ; --- RESULT ======= (0,0,0,377777777776) 6812 6813 035763 200 01 0 00 042751 ..0420: MOVE AC1,[[EXP 0,2,0,177777777777,0,0,0,377777777776],,MCAND] 6814 035764 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6815 035765 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6816 ERROR (..0420,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6817 035766 036 14 0 00 042603 6818 035767 255 00 0 00 000000 6819 ^ 6820 6821 035770 200 14 0 00 040457 ..0421: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6822 035771 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6823 ERROR (..0420,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6824 LL 6825 035772 036 13 0 00 042615 6826 035773 255 00 0 00 000000 6827 ^ 6828 ^ 6829 6830 ; ********************************************************************** 6831 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6832 ; ********************************************************************** 6833 6834 MULTF (C,0,2,0,377777777777,0,0,1,377777777776)^ 6835 6836 ; --- MULTIPLICAND = (0,2) 6837 ; --- MULTIPLIER === (0,377777777777) 6838 ; --- RESULT ======= (0,0,1,377777777776) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-6 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0164 6839 6840 035774 200 01 0 00 042762 ..0422: MOVE AC1,[[EXP 0,2,0,377777777777,0,0,1,377777777776],,MCAND] 6841 035775 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6842 035776 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6843 ERROR (..0422,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6844 035777 036 14 0 00 042603 6845 036000 255 00 0 00 000000 6846 ^ 6847 6848 036001 200 14 0 00 040457 ..0423: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6849 036002 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6850 ERROR (..0422,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6851 LL 6852 036003 036 13 0 00 042615 6853 036004 255 00 0 00 000000 6854 ^ 6855 ^ 6856 6857 ; ********************************************************************** 6858 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6859 ; ********************************************************************** 6860 6861 MULTF (C,0,2,177777777777,377777777777,0,0,377777777777,377777777776)^ 6862 6863 ; --- MULTIPLICAND = (0,2) 6864 ; --- MULTIPLIER === (177777777777,377777777777) 6865 ; --- RESULT ======= (0,0,377777777777,377777777776) 6866 6867 ..0424: MOVE AC1,[[EXP 0,2,177777777777,377777777777,0,0,377777777777,377777777776],,MCA 6868 036005 200 01 0 00 042773 ND] 6869 036006 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6870 036007 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6871 ERROR (..0424,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6872 036010 036 14 0 00 042603 6873 036011 255 00 0 00 000000 6874 ^ 6875 6876 036012 200 14 0 00 040457 ..0425: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6877 036013 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6878 ERROR (..0424,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6879 LL 6880 036014 036 13 0 00 042615 6881 036015 255 00 0 00 000000 6882 ^ 6883 ^ 6884 6885 ; ********************************************************************** 6886 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6887 ; ********************************************************************** 6888 6889 MULTF (C,0,2,377777777777,377777777777,0,1,377777777777,377777777776)^ 6890 6891 ; --- MULTIPLICAND = (0,2) 6892 ; --- MULTIPLIER === (377777777777,377777777777) 6893 ; --- RESULT ======= (0,1,377777777777,377777777776) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-7 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0165 6894 6895 ..0426: MOVE AC1,[[EXP 0,2,377777777777,377777777777,0,1,377777777777,377777777776],,MCA 6896 036016 200 01 0 00 043004 ND] 6897 036017 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6898 036020 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6899 ERROR (..0426,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6900 036021 036 14 0 00 042603 6901 036022 255 00 0 00 000000 6902 ^ 6903 6904 036023 200 14 0 00 040457 ..0427: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6905 036024 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6906 ERROR (..0426,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6907 LL 6908 036025 036 13 0 00 042615 6909 036026 255 00 0 00 000000 6910 ^ 6911 ^ 6912 6913 ; ********************************************************************** 6914 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6915 ; ********************************************************************** 6916 6917 MULTF (C,1,0,0,377777777777,0,0,377777777777)^ 6918 6919 ; --- MULTIPLICAND = (1,0) 6920 ; --- MULTIPLIER === (0,377777777777) 6921 ; --- RESULT ======= (0,0,377777777777,0) 6922 6923 036027 200 01 0 00 043015 ..0430: MOVE AC1,[[EXP 1,0,0,377777777777,0,0,377777777777,0],,MCAND] 6924 036030 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6925 036031 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6926 ERROR (..0430,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6927 036032 036 14 0 00 042603 6928 036033 255 00 0 00 000000 6929 ^ 6930 6931 036034 200 14 0 00 040457 ..0431: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6932 036035 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6933 ERROR (..0430,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6934 LL 6935 036036 036 13 0 00 042615 6936 036037 255 00 0 00 000000 6937 ^ 6938 ^ 6939 6940 ; ********************************************************************** 6941 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6942 ; ********************************************************************** 6943 6944 MULTF (C,1,0,1,377777777777,0,1,377777777777)^ 6945 6946 ; --- MULTIPLICAND = (1,0) 6947 ; --- MULTIPLIER === (1,377777777777) 6948 ; --- RESULT ======= (0,1,377777777777,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-8 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0166 6949 6950 036040 200 01 0 00 043026 ..0432: MOVE AC1,[[EXP 1,0,1,377777777777,0,1,377777777777,0],,MCAND] 6951 036041 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6952 036042 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6953 ERROR (..0432,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6954 036043 036 14 0 00 042603 6955 036044 255 00 0 00 000000 6956 ^ 6957 6958 036045 200 14 0 00 040457 ..0433: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6959 036046 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6960 ERROR (..0432,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6961 LL 6962 036047 036 13 0 00 042615 6963 036050 255 00 0 00 000000 6964 ^ 6965 ^ 6966 6967 ; ********************************************************************** 6968 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6969 ; ********************************************************************** 6970 6971 MULTF (C,1,0,377777777777,377777777777,0,377777777777,377777777777)^ 6972 6973 ; --- MULTIPLICAND = (1,0) 6974 ; --- MULTIPLIER === (377777777777,377777777777) 6975 ; --- RESULT ======= (0,377777777777,377777777777,0) 6976 6977 ..0434: MOVE AC1,[[EXP 1,0,377777777777,377777777777,0,377777777777,377777777777,0],,MCA 6978 036051 200 01 0 00 043037 ND] 6979 036052 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 6980 036053 260 17 0 00 040451 GO MSUBR ;GO DO TEST 6981 ERROR (..0434,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 6982 036054 036 14 0 00 042603 6983 036055 255 00 0 00 000000 6984 ^ 6985 6986 036056 200 14 0 00 040457 ..0435: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 6987 036057 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 6988 ERROR (..0434,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 6989 LL 6990 036060 036 13 0 00 042615 6991 036061 255 00 0 00 000000 6992 ^ 6993 ^ 6994 6995 ; ********************************************************************** 6996 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 6997 ; ********************************************************************** 6998 6999 MULTF (C,2,0,0,177777777777,0,0,377777777776)^ 7000 7001 ; --- MULTIPLICAND = (2,0) 7002 ; --- MULTIPLIER === (0,177777777777) 7003 ; --- RESULT ======= (0,0,377777777776,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-9 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0167 7004 7005 036062 200 01 0 00 043050 ..0436: MOVE AC1,[[EXP 2,0,0,177777777777,0,0,377777777776,0],,MCAND] 7006 036063 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7007 036064 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7008 ERROR (..0436,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7009 036065 036 14 0 00 042603 7010 036066 255 00 0 00 000000 7011 ^ 7012 7013 036067 200 14 0 00 040457 ..0437: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7014 036070 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7015 ERROR (..0436,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7016 LL 7017 036071 036 13 0 00 042615 7018 036072 255 00 0 00 000000 7019 ^ 7020 ^ 7021 7022 ; ********************************************************************** 7023 ; ---------- DMUL - TEST C - SHIFT 1'S ACROSS WORD BOUNDARIES ---------- 7024 ; ********************************************************************** 7025 7026 MULTF (C,2,0,0,377777777777,0,1,377777777776)^ 7027 7028 ; --- MULTIPLICAND = (2,0) 7029 ; --- MULTIPLIER === (0,377777777777) 7030 ; --- RESULT ======= (0,1,377777777776,0) 7031 7032 036073 200 01 0 00 043061 ..0440: MOVE AC1,[[EXP 2,0,0,377777777777,0,1,377777777776,0],,MCAND] 7033 036074 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7034 036075 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7035 ERROR (..0440,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7036 036076 036 14 0 00 042603 7037 036077 255 00 0 00 000000 7038 ^ 7039 7040 036100 200 14 0 00 040457 ..0441: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7041 036101 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7042 ERROR (..0440,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7043 LL 7044 036102 036 13 0 00 042615 7045 036103 255 00 0 00 000000 7046 ^ 7047 ^ 7048 7049 ; ********************************************************************** 7050 ; ---------- DMUL - TEST C - SHIFT ACROSS WORD BOUNDARIES ---------- 7051 ; ********************************************************************** 7052 7053 MULTF (C,2,0,377777777777,377777777777,1,377777777777,377777777776)^ 7054 7055 ; --- MULTIPLICAND = (2,0) 7056 ; --- MULTIPLIER === (377777777777,377777777777) 7057 ; --- RESULT ======= (1,377777777777,377777777776,0) 7058 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 20-10 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST C SEQ 0168 7059 ..0442: MOVE AC1,[[EXP 2,0,377777777777,377777777777,1,377777777777,377777777776,0],,MCA 7060 036104 200 01 0 00 043072 ND] 7061 036105 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7062 036106 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7063 ERROR (..0442,14,SCR1,SCR2,,TEST C - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7064 036107 036 14 0 00 042603 7065 036110 255 00 0 00 000000 7066 ^ 7067 7068 036111 200 14 0 00 040457 ..0443: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7069 036112 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7070 ERROR (..0442,13,SCR2,MFLOC,,TEST C - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7071 LL 7072 036113 036 13 0 00 042615 7073 036114 255 00 0 00 000000 7074 ^ 7075 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0169 7076 SUBTTL DMUL - TEST D 7077 7078 ; ********************************************************************** 7079 ;*DMUL - TEST D 7080 ;* 7081 ;* 7777..,6000.. * 2 THESE TESTS VERIFY THAT BITS ARE 7082 ;* 7777..,4000.. * 2 SHIFTED ACROSS WORD BOUNDARIES. A WORD 7083 ;* 6000..,4000.. * 2 OF ONES IS MULTIPLIED BY A FLOATING 1 7084 ;* 4000..,4000.. * 2 WHICH WILL CAUSE A SHIFT ACROSS WORD 7085 ;* 777..,400.. * 1,0 BOUNDARIES OR NOT. THE TEST VERIFIES 7086 ;* ..776,400.. * 1,0 THAT THE SHIFT IS DONE PROPERLY FOR 7087 ;* 400..,400.. * 1,0 BOUNDARY CONDITIONS. 7088 ;* 777..,600.. * 2,0 IN EACH TEST THE PC FLAGS ARE TESTED 7089 ;* 777..,400.. * 2,0 SINCE THERE ARE NO OVERFLOW CONDITIONS 7090 ;* 400..,400.. * 2,0 THE LEFTMOST BIT OF THE PC SHOULD BE 7091 ;* 0 (NO AROV). 7092 ;* THESE TESTS ARE REPEATED WITH MULT- 7093 ;* PLICAND AND MULTIPLIER REVERSED. 7094 ; ********************************************************************** 7095 7096 ; ********************************************************************** 7097 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7098 ; ********************************************************************** 7099 7100 MULTF (D,-1,600000000000,0,2,-1,-1,-1,400000000000)^ 7101 7102 ; --- MULTIPLICAND = (-1,600000000000) 7103 ; --- MULTIPLIER === (0,2) 7104 ; --- RESULT ======= (-1,-1,-1,400000000000) 7105 7106 036115 200 01 0 00 043103 ..0444: MOVE AC1,[[EXP -1,600000000000,0,2,-1,-1,-1,400000000000],,MCAND] 7107 036116 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7108 036117 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7109 ERROR (..0444,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7110 036120 036 14 0 00 043113 7111 036121 255 00 0 00 000000 7112 ^ 7113 7114 036122 200 14 0 00 040457 ..0445: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7115 036123 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7116 ERROR (..0444,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7117 LL 7118 036124 036 13 0 00 043125 7119 036125 255 00 0 00 000000 7120 ^ 7121 ^ 7122 7123 ; ********************************************************************** 7124 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7125 ; ********************************************************************** 7126 7127 MULTF (D,-1,400000000000,0,2,-1,-1,-2,400000000000)^ 7128 7129 ; --- MULTIPLICAND = (-1,400000000000) 7130 ; --- MULTIPLIER === (0,2) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-1 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0170 7131 ; --- RESULT ======= (-1,-1,-2,400000000000) 7132 7133 036126 200 01 0 00 043140 ..0446: MOVE AC1,[[EXP -1,400000000000,0,2,-1,-1,-2,400000000000],,MCAND] 7134 036127 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7135 036130 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7136 ERROR (..0446,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7137 036131 036 14 0 00 043113 7138 036132 255 00 0 00 000000 7139 ^ 7140 7141 036133 200 14 0 00 040457 ..0447: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7142 036134 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7143 ERROR (..0446,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7144 LL 7145 036135 036 13 0 00 043125 7146 036136 255 00 0 00 000000 7147 ^ 7148 ^ 7149 7150 ; ********************************************************************** 7151 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7152 ; ********************************************************************** 7153 7154 MULTF (D,600000000000,400000000000,0,2,-1,-1,400000000000,400000000000)^ 7155 7156 ; --- MULTIPLICAND = (600000000000,400000000000) 7157 ; --- MULTIPLIER === (0,2) 7158 ; --- RESULT ======= (-1,-1,400000000000,400000000000) 7159 7160 ..0450: MOVE AC1,[[EXP 600000000000,400000000000,0,2,-1,-1,400000000000,400000000000],,M 7161 036137 200 01 0 00 043151 CAND] 7162 036140 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7163 036141 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7164 ERROR (..0450,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7165 036142 036 14 0 00 043113 7166 036143 255 00 0 00 000000 7167 ^ 7168 7169 036144 200 14 0 00 040457 ..0451: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7170 036145 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7171 ERROR (..0450,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7172 LL 7173 036146 036 13 0 00 043125 7174 036147 255 00 0 00 000000 7175 ^ 7176 ^ 7177 7178 ; ********************************************************************** 7179 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7180 ; ********************************************************************** 7181 7182 MULTF (D,400000000000,400000000000,0,2,-1,-2,400000000000,400000000000)^ 7183 7184 ; --- MULTIPLICAND = (400000000000,400000000000) 7185 ; --- MULTIPLIER === (0,2) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-2 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0171 7186 ; --- RESULT ======= (-1,-2,400000000000,400000000000) 7187 7188 ..0452: MOVE AC1,[[EXP 400000000000,400000000000,0,2,-1,-2,400000000000,400000000000],,M 7189 036150 200 01 0 00 043162 CAND] 7190 036151 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7191 036152 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7192 ERROR (..0452,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7193 036153 036 14 0 00 043113 7194 036154 255 00 0 00 000000 7195 ^ 7196 7197 036155 200 14 0 00 040457 ..0453: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7198 036156 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7199 ERROR (..0452,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7200 LL 7201 036157 036 13 0 00 043125 7202 036160 255 00 0 00 000000 7203 ^ 7204 ^ 7205 7206 ; ********************************************************************** 7207 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7208 ; ********************************************************************** 7209 7210 MULTF (D,-1,400000000000,1,0,-1,-1,400000000000,400000000000)^ 7211 7212 ; --- MULTIPLICAND = (-1,400000000000) 7213 ; --- MULTIPLIER === (1,0) 7214 ; --- RESULT ======= (-1,-1,400000000000,400000000000) 7215 7216 036161 200 01 0 00 043173 ..0454: MOVE AC1,[[EXP -1,400000000000,1,0,-1,-1,400000000000,400000000000],,MCAND] 7217 036162 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7218 036163 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7219 ERROR (..0454,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7220 036164 036 14 0 00 043113 7221 036165 255 00 0 00 000000 7222 ^ 7223 7224 036166 200 14 0 00 040457 ..0455: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7225 036167 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7226 ERROR (..0454,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7227 LL 7228 036170 036 13 0 00 043125 7229 036171 255 00 0 00 000000 7230 ^ 7231 ^ 7232 7233 ; ********************************************************************** 7234 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7235 ; ********************************************************************** 7236 7237 MULTF (D,-2,400000000000,1,0,-1,-2,400000000000,400000000000)^ 7238 7239 ; --- MULTIPLICAND = (-2,400000000000) 7240 ; --- MULTIPLIER === (1,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-3 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0172 7241 ; --- RESULT ======= (-1,-2,400000000000,400000000000) 7242 7243 036172 200 01 0 00 043204 ..0456: MOVE AC1,[[EXP -2,400000000000,1,0,-1,-2,400000000000,400000000000],,MCAND] 7244 036173 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7245 036174 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7246 ERROR (..0456,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7247 036175 036 14 0 00 043113 7248 036176 255 00 0 00 000000 7249 ^ 7250 7251 036177 200 14 0 00 040457 ..0457: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7252 036200 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7253 ERROR (..0456,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7254 LL 7255 036201 036 13 0 00 043125 7256 036202 255 00 0 00 000000 7257 ^ 7258 ^ 7259 7260 ; ********************************************************************** 7261 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7262 ; ********************************************************************** 7263 7264 MULTF (D,400000000000,400000000000,1,0,-1,400000000000,400000000000,400000000000) 7265 ^ 7266 7267 ; --- MULTIPLICAND = (400000000000,400000000000) 7268 ; --- MULTIPLIER === (1,0) 7269 ; --- RESULT ======= (-1,400000000000,400000000000,400000000000) 7270 7271 ..0460: MOVE AC1,[[EXP 400000000000,400000000000,1,0,-1,400000000000,400000000000,400000 7272 036203 200 01 0 00 043215 000000],,MCAND] 7273 036204 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7274 036205 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7275 ERROR (..0460,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7276 036206 036 14 0 00 043113 7277 036207 255 00 0 00 000000 7278 ^ 7279 7280 036210 200 14 0 00 040457 ..0461: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7281 036211 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7282 ERROR (..0460,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7283 LL 7284 036212 036 13 0 00 043125 7285 036213 255 00 0 00 000000 7286 ^ 7287 ^ 7288 7289 ; ********************************************************************** 7290 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7291 ; ********************************************************************** 7292 7293 MULTF (D,-1,600000000000,2,0,-1,-1,400000000000,400000000000)^ 7294 7295 ; --- MULTIPLICAND = (-1,600000000000) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-4 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0173 7296 ; --- MULTIPLIER === (2,0) 7297 ; --- RESULT ======= (-1,-1,400000000000,400000000000) 7298 7299 036214 200 01 0 00 043226 ..0462: MOVE AC1,[[EXP -1,600000000000,2,0,-1,-1,400000000000,400000000000],,MCAND] 7300 036215 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7301 036216 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7302 ERROR (..0462,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7303 036217 036 14 0 00 043113 7304 036220 255 00 0 00 000000 7305 ^ 7306 7307 036221 200 14 0 00 040457 ..0463: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7308 036222 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7309 ERROR (..0462,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7310 LL 7311 036223 036 13 0 00 043125 7312 036224 255 00 0 00 000000 7313 ^ 7314 ^ 7315 7316 ; ********************************************************************** 7317 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7318 ; ********************************************************************** 7319 7320 MULTF (D,-1,400000000000,2,0,-1,-2,400000000000,400000000000)^ 7321 7322 ; --- MULTIPLICAND = (-1,400000000000) 7323 ; --- MULTIPLIER === (2,0) 7324 ; --- RESULT ======= (-1,-2,400000000000,400000000000) 7325 7326 036225 200 01 0 00 043237 ..0464: MOVE AC1,[[EXP -1,400000000000,2,0,-1,-2,400000000000,400000000000],,MCAND] 7327 036226 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7328 036227 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7329 ERROR (..0464,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7330 036230 036 14 0 00 043113 7331 036231 255 00 0 00 000000 7332 ^ 7333 7334 036232 200 14 0 00 040457 ..0465: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7335 036233 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7336 ERROR (..0464,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7337 LL 7338 036234 036 13 0 00 043125 7339 036235 255 00 0 00 000000 7340 ^ 7341 ^ 7342 7343 ; ********************************************************************** 7344 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7345 ; ********************************************************************** 7346 7347 MULTF (D,400000000000,400000000000,2,0,-2,400000000000,400000000000,400000000000) 7348 ^ 7349 7350 ; --- MULTIPLICAND = (400000000000,400000000000) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-5 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0174 7351 ; --- MULTIPLIER === (2,0) 7352 ; --- RESULT ======= (-2,400000000000,400000000000,400000000000) 7353 7354 ..0466: MOVE AC1,[[EXP 400000000000,400000000000,2,0,-2,400000000000,400000000000,400000 7355 036236 200 01 0 00 043250 000000],,MCAND] 7356 036237 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7357 036240 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7358 ERROR (..0466,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7359 036241 036 14 0 00 043113 7360 036242 255 00 0 00 000000 7361 ^ 7362 7363 036243 200 14 0 00 040457 ..0467: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7364 036244 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7365 ERROR (..0466,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7366 LL 7367 036245 036 13 0 00 043125 7368 036246 255 00 0 00 000000 7369 ^ 7370 ^ 7371 7372 ; ********************************************************************** 7373 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7374 ; ********************************************************************** 7375 7376 MULTF (D,0,2,-1,600000000000,-1,-1,-1,400000000000)^ 7377 7378 ; --- MULTIPLICAND = (0,2) 7379 ; --- MULTIPLIER === (-1,600000000000) 7380 ; --- RESULT ======= (-1,-1,-1,400000000000) 7381 7382 036247 200 01 0 00 043261 ..0470: MOVE AC1,[[EXP 0,2,-1,600000000000,-1,-1,-1,400000000000],,MCAND] 7383 036250 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7384 036251 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7385 ERROR (..0470,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7386 036252 036 14 0 00 043113 7387 036253 255 00 0 00 000000 7388 ^ 7389 7390 036254 200 14 0 00 040457 ..0471: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7391 036255 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7392 ERROR (..0470,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7393 LL 7394 036256 036 13 0 00 043125 7395 036257 255 00 0 00 000000 7396 ^ 7397 ^ 7398 7399 ; ********************************************************************** 7400 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7401 ; ********************************************************************** 7402 7403 MULTF (D,0,2,-1,400000000000,-1,-1,-2,400000000000)^ 7404 7405 ; --- MULTIPLICAND = (0,2) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-6 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0175 7406 ; --- MULTIPLIER === (-1,400000000000) 7407 ; --- RESULT ======= (-1,-1,-2,400000000000) 7408 7409 036260 200 01 0 00 043272 ..0472: MOVE AC1,[[EXP 0,2,-1,400000000000,-1,-1,-2,400000000000],,MCAND] 7410 036261 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7411 036262 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7412 ERROR (..0472,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7413 036263 036 14 0 00 043113 7414 036264 255 00 0 00 000000 7415 ^ 7416 7417 036265 200 14 0 00 040457 ..0473: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7418 036266 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7419 ERROR (..0472,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7420 LL 7421 036267 036 13 0 00 043125 7422 036270 255 00 0 00 000000 7423 ^ 7424 ^ 7425 7426 ; ********************************************************************** 7427 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7428 ; ********************************************************************** 7429 7430 MULTF (D,0,2,600000000000,400000000000,-1,-1,400000000000,400000000000)^ 7431 7432 ; --- MULTIPLICAND = (0,2) 7433 ; --- MULTIPLIER === (600000000000,400000000000) 7434 ; --- RESULT ======= (-1,-1,400000000000,400000000000) 7435 7436 ..0474: MOVE AC1,[[EXP 0,2,600000000000,400000000000,-1,-1,400000000000,400000000000],,M 7437 036271 200 01 0 00 043303 CAND] 7438 036272 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7439 036273 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7440 ERROR (..0474,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7441 036274 036 14 0 00 043113 7442 036275 255 00 0 00 000000 7443 ^ 7444 7445 036276 200 14 0 00 040457 ..0475: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7446 036277 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7447 ERROR (..0474,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7448 LL 7449 036300 036 13 0 00 043125 7450 036301 255 00 0 00 000000 7451 ^ 7452 ^ 7453 7454 ; ********************************************************************** 7455 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7456 ; ********************************************************************** 7457 7458 MULTF (D,0,2,400000000000,400000000000,-1,-2,400000000000,400000000000)^ 7459 7460 ; --- MULTIPLICAND = (0,2) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-7 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0176 7461 ; --- MULTIPLIER === (400000000000,400000000000) 7462 ; --- RESULT ======= (-1,-2,400000000000,400000000000) 7463 7464 ..0476: MOVE AC1,[[EXP 0,2,400000000000,400000000000,-1,-2,400000000000,400000000000],,M 7465 036302 200 01 0 00 043314 CAND] 7466 036303 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7467 036304 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7468 ERROR (..0476,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7469 036305 036 14 0 00 043113 7470 036306 255 00 0 00 000000 7471 ^ 7472 7473 036307 200 14 0 00 040457 ..0477: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7474 036310 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7475 ERROR (..0476,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7476 LL 7477 036311 036 13 0 00 043125 7478 036312 255 00 0 00 000000 7479 ^ 7480 ^ 7481 7482 ; ********************************************************************** 7483 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7484 ; ********************************************************************** 7485 7486 MULTF (D,1,0,-1,400000000000,-1,-1,400000000000,400000000000)^ 7487 7488 ; --- MULTIPLICAND = (1,0) 7489 ; --- MULTIPLIER === (-1,400000000000) 7490 ; --- RESULT ======= (-1,-1,400000000000,400000000000) 7491 7492 036313 200 01 0 00 043325 ..0500: MOVE AC1,[[EXP 1,0,-1,400000000000,-1,-1,400000000000,400000000000],,MCAND] 7493 036314 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7494 036315 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7495 ERROR (..0500,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7496 036316 036 14 0 00 043113 7497 036317 255 00 0 00 000000 7498 ^ 7499 7500 036320 200 14 0 00 040457 ..0501: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7501 036321 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7502 ERROR (..0500,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7503 LL 7504 036322 036 13 0 00 043125 7505 036323 255 00 0 00 000000 7506 ^ 7507 ^ 7508 7509 ; ********************************************************************** 7510 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7511 ; ********************************************************************** 7512 7513 MULTF (D,1,0,-2,400000000000,-1,-2,400000000000,400000000000)^ 7514 7515 ; --- MULTIPLICAND = (1,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-8 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0177 7516 ; --- MULTIPLIER === (-2,400000000000) 7517 ; --- RESULT ======= (-1,-2,400000000000,400000000000) 7518 7519 036324 200 01 0 00 043336 ..0502: MOVE AC1,[[EXP 1,0,-2,400000000000,-1,-2,400000000000,400000000000],,MCAND] 7520 036325 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7521 036326 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7522 ERROR (..0502,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7523 036327 036 14 0 00 043113 7524 036330 255 00 0 00 000000 7525 ^ 7526 7527 036331 200 14 0 00 040457 ..0503: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7528 036332 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7529 ERROR (..0502,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7530 LL 7531 036333 036 13 0 00 043125 7532 036334 255 00 0 00 000000 7533 ^ 7534 ^ 7535 7536 ; ********************************************************************** 7537 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7538 ; ********************************************************************** 7539 7540 MULTF (D,1,0,400000000000,400000000000,-1,400000000000,400000000000,400000000000) 7541 ^ 7542 7543 ; --- MULTIPLICAND = (1,0) 7544 ; --- MULTIPLIER === (400000000000,400000000000) 7545 ; --- RESULT ======= (-1,400000000000,400000000000,400000000000) 7546 7547 ..0504: MOVE AC1,[[EXP 1,0,400000000000,400000000000,-1,400000000000,400000000000,400000 7548 036335 200 01 0 00 043347 000000],,MCAND] 7549 036336 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7550 036337 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7551 ERROR (..0504,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7552 036340 036 14 0 00 043113 7553 036341 255 00 0 00 000000 7554 ^ 7555 7556 036342 200 14 0 00 040457 ..0505: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7557 036343 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7558 ERROR (..0504,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7559 LL 7560 036344 036 13 0 00 043125 7561 036345 255 00 0 00 000000 7562 ^ 7563 ^ 7564 7565 ; ********************************************************************** 7566 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7567 ; ********************************************************************** 7568 7569 MULTF (D,2,0,-1,600000000000,-1,-1,400000000000,400000000000)^ 7570 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-9 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0178 7571 ; --- MULTIPLICAND = (2,0) 7572 ; --- MULTIPLIER === (-1,600000000000) 7573 ; --- RESULT ======= (-1,-1,400000000000,400000000000) 7574 7575 036346 200 01 0 00 043360 ..0506: MOVE AC1,[[EXP 2,0,-1,600000000000,-1,-1,400000000000,400000000000],,MCAND] 7576 036347 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7577 036350 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7578 ERROR (..0506,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7579 036351 036 14 0 00 043113 7580 036352 255 00 0 00 000000 7581 ^ 7582 7583 036353 200 14 0 00 040457 ..0507: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7584 036354 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7585 ERROR (..0506,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7586 LL 7587 036355 036 13 0 00 043125 7588 036356 255 00 0 00 000000 7589 ^ 7590 ^ 7591 7592 ; ********************************************************************** 7593 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7594 ; ********************************************************************** 7595 7596 MULTF (D,2,0,-1,400000000000,-1,-2,400000000000,400000000000)^ 7597 7598 ; --- MULTIPLICAND = (2,0) 7599 ; --- MULTIPLIER === (-1,400000000000) 7600 ; --- RESULT ======= (-1,-2,400000000000,400000000000) 7601 7602 036357 200 01 0 00 043371 ..0510: MOVE AC1,[[EXP 2,0,-1,400000000000,-1,-2,400000000000,400000000000],,MCAND] 7603 036360 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7604 036361 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7605 ERROR (..0510,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7606 036362 036 14 0 00 043113 7607 036363 255 00 0 00 000000 7608 ^ 7609 7610 036364 200 14 0 00 040457 ..0511: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7611 036365 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7612 ERROR (..0510,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7613 LL 7614 036366 036 13 0 00 043125 7615 036367 255 00 0 00 000000 7616 ^ 7617 ^ 7618 7619 ; ********************************************************************** 7620 ; ---------- DMUL - TEST D - SHIFT 0'S ACROSS WORD BOUNDARIES ---------- 7621 ; ********************************************************************** 7622 7623 MULTF (D,2,0,400000000000,400000000000,-2,400000000000,400000000000,400000000000) 7624 ^ 7625 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 21-10 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST D SEQ 0179 7626 ; --- MULTIPLICAND = (2,0) 7627 ; --- MULTIPLIER === (400000000000,400000000000) 7628 ; --- RESULT ======= (-2,400000000000,400000000000,400000000000) 7629 7630 ..0512: MOVE AC1,[[EXP 2,0,400000000000,400000000000,-2,400000000000,400000000000,400000 7631 036370 200 01 0 00 043402 000000],,MCAND] 7632 036371 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7633 036372 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7634 ERROR (..0512,14,SCR1,SCR2,,TEST D - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7635 036373 036 14 0 00 043113 7636 036374 255 00 0 00 000000 7637 ^ 7638 7639 036375 200 14 0 00 040457 ..0513: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7640 036376 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7641 ERROR (..0512,13,SCR2,MFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7642 LL 7643 036377 036 13 0 00 043125 7644 036400 255 00 0 00 000000 7645 ^ 7646 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 22 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST E (OVERFLOW) SEQ 0180 7647 SUBTTL DMUL - TEST E (OVERFLOW) 7648 7649 ; ********************************************************************** 7650 ;*DMUL - TEST E 7651 ;* 7652 ;* -2^70 * -2^70 THIS IS THE ONLY CASE THAT CAN SET 7653 ;* THE AROV FLAG. THIS TEST VERIFIES THE 7654 ;* RESULT AND CHECKS THE SETTING OF THE 7655 ;* AROV FLAG. 7656 ;* 7657 ;* ------- MULTIPLICAND = (4000...,4000...) 7658 ;* ------- MULTIPLIER === (4000...,4000...) 7659 ;* ------- RESULT ======= (4000...,4000...,4000...,4000...) 7660 ; ********************************************************************** 7661 7662 036401 LOC=. 7663 7664 036401 120 01 0 00 042100 DMOVE AC1,[EXP 1B0,1B0] ;INIT MULTIPLICAND 7665 036402 120 03 0 00 043403 DMOVE AC1+2,[EXP 525252525252,252525252525] ;PUT GARBAGE IN 7666 ; RIGHT HALF OF RESULT 7667 036403 400 13 0 00 000000 SETZ SCR1, ;POINTER TO WHICH WORD INCORRECT 7668 036404 255 17 0 00 036405 JFCL 17,.+1 ;CLEAR FLAGS 7669 036405 116 01 0 00 000001 DMUL AC1,AC1 ;MULTIPLY 7670 PCSAVE^ 7671 036406 264 00 0 00 036407 JSR .+1 ;STORE PC 7672 036407 FLAGL=. ;LOCATION OF PC 7673 036407 000000 000000 0 ;PC 7674 ^ 7675 036410 312 01 0 00 041725 CAME AC1,[1B0] ;1ST WORD OF RESULT OK? 7676 036411 254 00 0 00 036423 JRST MOVERR ;NO - GO DO ERROR PRINTOUT 7677 036412 201 13 0 00 000001 MOVEI SCR1,1 ;POINT TO 2ND WORD 7678 036413 312 02 0 00 041725 CAME AC1+1,[1B0] ;2ND WORD OF RESULT OK? 7679 036414 254 00 0 00 036423 JRST MOVERR ;NO - GO DO ERROR PRINTOUT 7680 036415 201 13 0 00 000002 MOVEI SCR1,2 ;POINT TO 3RD WORD 7681 036416 312 03 0 00 041725 CAME AC1+2,[1B0] ;3RD WORD OF RESULT OK? 7682 036417 254 00 0 00 036423 JRST MOVERR ;NO - GO DO ERROR PRINTOUT 7683 036420 201 13 0 00 000003 MOVEI SCR1,3 ;POINT TO 4TH WORD 7684 036421 316 04 0 00 041725 CAMN AC1+3,[1B0] ;4TH WORD OF RESULT OK? 7685 036422 254 00 0 00 036426 JRST MOVOK ;YES - GO CHECK AROV FLAGS 7686 036423 200 13 0 13 000001 MOVERR: MOVE SCR1,AC1(SCR1) ;GET INCORRECT WORD 7687 ERROR (LOC,13,[1B0],SCR1,,TEST E - RESULT INCORRECT,MPRINT)^SALL 7688 036424 036 13 0 00 043412 7689 036425 255 00 0 00 000000 7690 ^ 7691 036426 255 10 0 00 036432 MOVOK: JOV MOVRR+1 ;TEST OVERFLOW - SHOULD BE ON 7692 036427 201 15 0 00 042100 MOVEI SCR3,[EXP 1B0,1B0] ;ADDRESS OF OPERANDS FOR ADDL 7693 036430 504 15 0 00 000015 HRL SCR3,SCR3 ; ERROR PRINT ROUTINE 7694 036431 MOVRR: ERROR (LOC,13,AC1,FLAGL,,TEST E - PC FLAGS INCORRECT - LEFT 4 BITS,MPRINT)^SALL 7695 036431 036 13 0 00 043424 7696 036432 255 00 0 00 000000 7697 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 23 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST F - TEST NEGATIVE OPERANDS SEQ 0181 7698 SUBTTL DMUL - TEST F - TEST NEGATIVE OPERANDS 7699 7700 ; ********************************************************************** 7701 ;*DMUL - TEST F 7702 ;* 7703 ;* -2 * -3 THESE TESTS VERIFY THAT THE DMUL HANDLES 7704 ;* -2,0 * -3 THE SIGNS PROPERLY WHEN MULTIPLYING 7705 ;* -2 * -3,0 OPERANDS WHICH ARE BOTH NEGATIVE. TESTS 7706 ;* -2,0 * -3,0 B,C,D TESTED THE COMBINATIONS POS*POS, 7707 ;* POS*NEG AND NEG*POS BUT NOT NEG*NEG. THE 7708 ;* AROV FLAG IS ALSO TESTED TO ASCERTAIN 7709 ;* THAT IT WAS NOT SET. 7710 ; ********************************************************************** 7711 7712 ; ********************************************************************** 7713 ; ---------- DMUL TEST F - TEST NEGATIVE OPERANDS ---------- 7714 ; ********************************************************************** 7715 7716 MULTF (F,-1,-2,-1,-3,0,0,0,6)^ 7717 7718 ; --- MULTIPLICAND = (-1,-2) 7719 ; --- MULTIPLIER === (-1,-3) 7720 ; --- RESULT ======= (0,0,0,6) 7721 7722 036433 200 01 0 00 043437 ..0514: MOVE AC1,[[EXP -1,-2,-1,-3,0,0,0,6],,MCAND] 7723 036434 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7724 036435 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7725 ERROR (..0514,14,SCR1,SCR2,,TEST F - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7726 036436 036 14 0 00 043447 7727 036437 255 00 0 00 000000 7728 ^ 7729 7730 036440 200 14 0 00 040457 ..0515: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7731 036441 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7732 ERROR (..0514,13,SCR2,MFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7733 LL 7734 036442 036 13 0 00 043461 7735 036443 255 00 0 00 000000 7736 ^ 7737 ^ 7738 7739 ; ********************************************************************** 7740 ; ---------- DMUL TEST F - TEST NEGATIVE OPERANDS ---------- 7741 ; ********************************************************************** 7742 7743 MULTF (F,-2,400000000000,-1,-3,0,0,6)^ 7744 7745 ; --- MULTIPLICAND = (-2,400000000000) 7746 ; --- MULTIPLIER === (-1,-3) 7747 ; --- RESULT ======= (0,0,6,0) 7748 7749 036444 200 01 0 00 043474 ..0516: MOVE AC1,[[EXP -2,400000000000,-1,-3,0,0,6,0],,MCAND] 7750 036445 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7751 036446 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7752 ERROR (..0516,14,SCR1,SCR2,,TEST F - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 23-1 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST F - TEST NEGATIVE OPERANDS SEQ 0182 7753 036447 036 14 0 00 043447 7754 036450 255 00 0 00 000000 7755 ^ 7756 7757 036451 200 14 0 00 040457 ..0517: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7758 036452 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7759 ERROR (..0516,13,SCR2,MFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7760 LL 7761 036453 036 13 0 00 043461 7762 036454 255 00 0 00 000000 7763 ^ 7764 ^ 7765 7766 ; ********************************************************************** 7767 ; ---------- DMUL TEST F - TEST NEGATIVE OPERANDS ---------- 7768 ; ********************************************************************** 7769 7770 MULTF (F,-1,-2,-3,400000000000,0,0,6)^ 7771 7772 ; --- MULTIPLICAND = (-1,-2) 7773 ; --- MULTIPLIER === (-3,400000000000) 7774 ; --- RESULT ======= (0,0,6,0) 7775 7776 036455 200 01 0 00 043505 ..0520: MOVE AC1,[[EXP -1,-2,-3,400000000000,0,0,6,0],,MCAND] 7777 036456 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7778 036457 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7779 ERROR (..0520,14,SCR1,SCR2,,TEST F - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7780 036460 036 14 0 00 043447 7781 036461 255 00 0 00 000000 7782 ^ 7783 7784 036462 200 14 0 00 040457 ..0521: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7785 036463 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7786 ERROR (..0520,13,SCR2,MFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7787 LL 7788 036464 036 13 0 00 043461 7789 036465 255 00 0 00 000000 7790 ^ 7791 ^ 7792 7793 ; ********************************************************************** 7794 ; ---------- DMUL TEST F - TEST NEGATIVE OPERANDS ---------- 7795 ; ********************************************************************** 7796 7797 MULTF (F,-2,400000000000,-3,400000000000,0,6)^ 7798 7799 ; --- MULTIPLICAND = (-2,400000000000) 7800 ; --- MULTIPLIER === (-3,400000000000) 7801 ; --- RESULT ======= (0,6,0,0) 7802 7803 036466 200 01 0 00 043516 ..0522: MOVE AC1,[[EXP -2,400000000000,-3,400000000000,0,6,0,0],,MCAND] 7804 036467 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7805 036470 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7806 ERROR (..0522,14,SCR1,SCR2,,TEST F - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7807 036471 036 14 0 00 043447 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 23-2 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST F - TEST NEGATIVE OPERANDS SEQ 0183 7808 036472 255 00 0 00 000000 7809 ^ 7810 7811 036473 200 14 0 00 040457 ..0523: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7812 036474 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7813 ERROR (..0522,13,SCR2,MFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7814 LL 7815 036475 036 13 0 00 043461 7816 036476 255 00 0 00 000000 7817 ^ 7818 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0184 7819 SUBTTL DMUL - TEST G 7820 7821 ; ********************************************************************** 7822 ;*DMUL - TEST G 7823 ;* 7824 ;* 2 * 3 2,0 * 3,0 THESE TESTS MULTIPLY NUMBERS WHICH HAVE 7825 ;* 2 * -3 2,0 * -3,0 INCONSISTENT SIGNS AMONGST THE WORDS OF 7826 ;* -2 * 3 -2,-1 * 3,0 EACH OPERAND. THE FLAGS IS ALSO TESTED 7827 ;* -2 * -3 -2,-1 * -3,0 TO VERIFY THAT IT IS NOT SET. 7828 ; ********************************************************************** 7829 7830 ; ********************************************************************** 7831 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 7832 ; ********************************************************************** 7833 7834 MULTF (G,0,2,0,400000000003,0,0,0,6)^ 7835 7836 ; --- MULTIPLICAND = (0,2) 7837 ; --- MULTIPLIER === (0,400000000003) 7838 ; --- RESULT ======= (0,0,0,6) 7839 7840 036477 200 01 0 00 043527 ..0524: MOVE AC1,[[EXP 0,2,0,400000000003,0,0,0,6],,MCAND] 7841 036500 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7842 036501 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7843 ERROR (..0524,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7844 036502 036 14 0 00 043537 7845 036503 255 00 0 00 000000 7846 ^ 7847 7848 036504 200 14 0 00 040457 ..0525: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7849 036505 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7850 ERROR (..0524,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7851 LL 7852 036506 036 13 0 00 043551 7853 036507 255 00 0 00 000000 7854 ^ 7855 ^ 7856 7857 ; ********************************************************************** 7858 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 7859 ; ********************************************************************** 7860 7861 MULTF (G,0,400000000002,0,400000000003,0,0,0,6)^ 7862 7863 ; --- MULTIPLICAND = (0,400000000002) 7864 ; --- MULTIPLIER === (0,400000000003) 7865 ; --- RESULT ======= (0,0,0,6) 7866 7867 036510 200 01 0 00 043564 ..0526: MOVE AC1,[[EXP 0,400000000002,0,400000000003,0,0,0,6],,MCAND] 7868 036511 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7869 036512 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7870 ERROR (..0526,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7871 036513 036 14 0 00 043537 7872 036514 255 00 0 00 000000 7873 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-1 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0185 7874 7875 036515 200 14 0 00 040457 ..0527: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7876 036516 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7877 ERROR (..0526,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7878 LL 7879 036517 036 13 0 00 043551 7880 036520 255 00 0 00 000000 7881 ^ 7882 ^ 7883 7884 ; ********************************************************************** 7885 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 7886 ; ********************************************************************** 7887 7888 MULTF (G,0,400000000002,0,3,0,0,0,6)^ 7889 7890 ; --- MULTIPLICAND = (0,400000000002) 7891 ; --- MULTIPLIER === (0,3) 7892 ; --- RESULT ======= (0,0,0,6) 7893 7894 036521 200 01 0 00 043575 ..0530: MOVE AC1,[[EXP 0,400000000002,0,3,0,0,0,6],,MCAND] 7895 036522 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7896 036523 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7897 ERROR (..0530,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7898 036524 036 14 0 00 043537 7899 036525 255 00 0 00 000000 7900 ^ 7901 7902 036526 200 14 0 00 040457 ..0531: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7903 036527 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7904 ERROR (..0530,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7905 LL 7906 036530 036 13 0 00 043551 7907 036531 255 00 0 00 000000 7908 ^ 7909 ^ 7910 7911 ; ********************************************************************** 7912 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 7913 ; ********************************************************************** 7914 7915 MULTF (G,0,2,-1,377777777775,-1,-1,-1,-6)^ 7916 7917 ; --- MULTIPLICAND = (0,2) 7918 ; --- MULTIPLIER === (-1,377777777775) 7919 ; --- RESULT ======= (-1,-1,-1,-6) 7920 7921 036532 200 01 0 00 043606 ..0532: MOVE AC1,[[EXP 0,2,-1,377777777775,-1,-1,-1,-6],,MCAND] 7922 036533 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7923 036534 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7924 ERROR (..0532,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7925 036535 036 14 0 00 043537 7926 036536 255 00 0 00 000000 7927 ^ 7928 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-2 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0186 7929 036537 200 14 0 00 040457 ..0533: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7930 036540 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7931 ERROR (..0532,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7932 LL 7933 036541 036 13 0 00 043551 7934 036542 255 00 0 00 000000 7935 ^ 7936 ^ 7937 7938 ; ********************************************************************** 7939 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 7940 ; ********************************************************************** 7941 7942 MULTF (G,0,400000000002,-1,377777777775,-1,-1,-1,-6)^ 7943 7944 ; --- MULTIPLICAND = (0,400000000002) 7945 ; --- MULTIPLIER === (-1,377777777775) 7946 ; --- RESULT ======= (-1,-1,-1,-6) 7947 7948 036543 200 01 0 00 043617 ..0534: MOVE AC1,[[EXP 0,400000000002,-1,377777777775,-1,-1,-1,-6],,MCAND] 7949 036544 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7950 036545 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7951 ERROR (..0534,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7952 036546 036 14 0 00 043537 7953 036547 255 00 0 00 000000 7954 ^ 7955 7956 036550 200 14 0 00 040457 ..0535: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 7957 036551 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7958 ERROR (..0534,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7959 LL 7960 036552 036 13 0 00 043551 7961 036553 255 00 0 00 000000 7962 ^ 7963 ^ 7964 7965 ; ********************************************************************** 7966 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 7967 ; ********************************************************************** 7968 7969 MULTF (G,0,400000000002,-1,-3,-1,-1,-1,-6)^ 7970 7971 ; --- MULTIPLICAND = (0,400000000002) 7972 ; --- MULTIPLIER === (-1,-3) 7973 ; --- RESULT ======= (-1,-1,-1,-6) 7974 7975 036554 200 01 0 00 043630 ..0536: MOVE AC1,[[EXP 0,400000000002,-1,-3,-1,-1,-1,-6],,MCAND] 7976 036555 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 7977 036556 260 17 0 00 040451 GO MSUBR ;GO DO TEST 7978 ERROR (..0536,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 7979 036557 036 14 0 00 043537 7980 036560 255 00 0 00 000000 7981 ^ 7982 7983 036561 200 14 0 00 040457 ..0537: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-3 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0187 7984 036562 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 7985 ERROR (..0536,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 7986 LL 7987 036563 036 13 0 00 043551 7988 036564 255 00 0 00 000000 7989 ^ 7990 ^ 7991 7992 ; ********************************************************************** 7993 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 7994 ; ********************************************************************** 7995 7996 MULTF (G,-1,-2,0,400000000003,-1,-1,-1,-6)^ 7997 7998 ; --- MULTIPLICAND = (-1,-2) 7999 ; --- MULTIPLIER === (0,400000000003) 8000 ; --- RESULT ======= (-1,-1,-1,-6) 8001 8002 036565 200 01 0 00 043641 ..0540: MOVE AC1,[[EXP -1,-2,0,400000000003,-1,-1,-1,-6],,MCAND] 8003 036566 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8004 036567 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8005 ERROR (..0540,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8006 036570 036 14 0 00 043537 8007 036571 255 00 0 00 000000 8008 ^ 8009 8010 036572 200 14 0 00 040457 ..0541: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8011 036573 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8012 ERROR (..0540,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8013 LL 8014 036574 036 13 0 00 043551 8015 036575 255 00 0 00 000000 8016 ^ 8017 ^ 8018 8019 ; ********************************************************************** 8020 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8021 ; ********************************************************************** 8022 8023 MULTF (G,-1,377777777776,0,400000000003,-1,-1,-1,-6)^ 8024 8025 ; --- MULTIPLICAND = (-1,377777777776) 8026 ; --- MULTIPLIER === (0,400000000003) 8027 ; --- RESULT ======= (-1,-1,-1,-6) 8028 8029 036576 200 01 0 00 043652 ..0542: MOVE AC1,[[EXP -1,377777777776,0,400000000003,-1,-1,-1,-6],,MCAND] 8030 036577 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8031 036600 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8032 ERROR (..0542,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8033 036601 036 14 0 00 043537 8034 036602 255 00 0 00 000000 8035 ^ 8036 8037 036603 200 14 0 00 040457 ..0543: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8038 036604 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-4 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0188 8039 ERROR (..0542,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8040 LL 8041 036605 036 13 0 00 043551 8042 036606 255 00 0 00 000000 8043 ^ 8044 ^ 8045 8046 ; ********************************************************************** 8047 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8048 ; ********************************************************************** 8049 8050 MULTF (G,-1,377777777776,0,3,-1,-1,-1,-6)^ 8051 8052 ; --- MULTIPLICAND = (-1,377777777776) 8053 ; --- MULTIPLIER === (0,3) 8054 ; --- RESULT ======= (-1,-1,-1,-6) 8055 8056 036607 200 01 0 00 043663 ..0544: MOVE AC1,[[EXP -1,377777777776,0,3,-1,-1,-1,-6],,MCAND] 8057 036610 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8058 036611 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8059 ERROR (..0544,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8060 036612 036 14 0 00 043537 8061 036613 255 00 0 00 000000 8062 ^ 8063 8064 036614 200 14 0 00 040457 ..0545: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8065 036615 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8066 ERROR (..0544,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8067 LL 8068 036616 036 13 0 00 043551 8069 036617 255 00 0 00 000000 8070 ^ 8071 ^ 8072 8073 ; ********************************************************************** 8074 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8075 ; ********************************************************************** 8076 8077 MULTF (G,-1,-2,-1,377777777775,0,0,0,6)^ 8078 8079 ; --- MULTIPLICAND = (-1,-2) 8080 ; --- MULTIPLIER === (-1,377777777775) 8081 ; --- RESULT ======= (0,0,0,6) 8082 8083 036620 200 01 0 00 043674 ..0546: MOVE AC1,[[EXP -1,-2,-1,377777777775,0,0,0,6],,MCAND] 8084 036621 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8085 036622 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8086 ERROR (..0546,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8087 036623 036 14 0 00 043537 8088 036624 255 00 0 00 000000 8089 ^ 8090 8091 036625 200 14 0 00 040457 ..0547: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8092 036626 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8093 ERROR (..0546,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-5 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0189 8094 LL 8095 036627 036 13 0 00 043551 8096 036630 255 00 0 00 000000 8097 ^ 8098 ^ 8099 8100 ; ********************************************************************** 8101 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8102 ; ********************************************************************** 8103 8104 MULTF (G,-1,377777777776,-1,377777777775,0,0,0,6)^ 8105 8106 ; --- MULTIPLICAND = (-1,377777777776) 8107 ; --- MULTIPLIER === (-1,377777777775) 8108 ; --- RESULT ======= (0,0,0,6) 8109 8110 036631 200 01 0 00 043705 ..0550: MOVE AC1,[[EXP -1,377777777776,-1,377777777775,0,0,0,6],,MCAND] 8111 036632 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8112 036633 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8113 ERROR (..0550,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8114 036634 036 14 0 00 043537 8115 036635 255 00 0 00 000000 8116 ^ 8117 8118 036636 200 14 0 00 040457 ..0551: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8119 036637 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8120 ERROR (..0550,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8121 LL 8122 036640 036 13 0 00 043551 8123 036641 255 00 0 00 000000 8124 ^ 8125 ^ 8126 8127 ; ********************************************************************** 8128 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8129 ; ********************************************************************** 8130 8131 MULTF (G,-1,377777777776,-1,-3,0,0,0,6)^ 8132 8133 ; --- MULTIPLICAND = (-1,377777777776) 8134 ; --- MULTIPLIER === (-1,-3) 8135 ; --- RESULT ======= (0,0,0,6) 8136 8137 036642 200 01 0 00 043716 ..0552: MOVE AC1,[[EXP -1,377777777776,-1,-3,0,0,0,6],,MCAND] 8138 036643 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8139 036644 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8140 ERROR (..0552,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8141 036645 036 14 0 00 043537 8142 036646 255 00 0 00 000000 8143 ^ 8144 8145 036647 200 14 0 00 040457 ..0553: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8146 036650 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8147 ERROR (..0552,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8148 LL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-6 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0190 8149 036651 036 13 0 00 043551 8150 036652 255 00 0 00 000000 8151 ^ 8152 ^ 8153 8154 ; ********************************************************************** 8155 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8156 ; ********************************************************************** 8157 8158 MULTF (G,2,0,3,400000000000,0,6)^ 8159 8160 ; --- MULTIPLICAND = (2,0) 8161 ; --- MULTIPLIER === (3,400000000000) 8162 ; --- RESULT ======= (0,6,0,0) 8163 8164 036653 200 01 0 00 043727 ..0554: MOVE AC1,[[EXP 2,0,3,400000000000,0,6,0,0],,MCAND] 8165 036654 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8166 036655 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8167 ERROR (..0554,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8168 036656 036 14 0 00 043537 8169 036657 255 00 0 00 000000 8170 ^ 8171 8172 036660 200 14 0 00 040457 ..0555: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8173 036661 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8174 ERROR (..0554,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8175 LL 8176 036662 036 13 0 00 043551 8177 036663 255 00 0 00 000000 8178 ^ 8179 ^ 8180 8181 ; ********************************************************************** 8182 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8183 ; ********************************************************************** 8184 8185 MULTF (G,2,400000000000,3,400000000000,0,6)^ 8186 8187 ; --- MULTIPLICAND = (2,400000000000) 8188 ; --- MULTIPLIER === (3,400000000000) 8189 ; --- RESULT ======= (0,6,0,0) 8190 8191 036664 200 01 0 00 043740 ..0556: MOVE AC1,[[EXP 2,400000000000,3,400000000000,0,6,0,0],,MCAND] 8192 036665 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8193 036666 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8194 ERROR (..0556,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8195 036667 036 14 0 00 043537 8196 036670 255 00 0 00 000000 8197 ^ 8198 8199 036671 200 14 0 00 040457 ..0557: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8200 036672 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8201 ERROR (..0556,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8202 LL 8203 036673 036 13 0 00 043551 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-7 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0191 8204 036674 255 00 0 00 000000 8205 ^ 8206 ^ 8207 8208 ; ********************************************************************** 8209 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8210 ; ********************************************************************** 8211 8212 MULTF (G,2,400000000000,3,0,0,6,0)^ 8213 8214 ; --- MULTIPLICAND = (2,400000000000) 8215 ; --- MULTIPLIER === (3,0) 8216 ; --- RESULT ======= (0,6,0,0) 8217 8218 036675 200 01 0 00 043751 ..0560: MOVE AC1,[[EXP 2,400000000000,3,0,0,6,0,0],,MCAND] 8219 036676 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8220 036677 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8221 ERROR (..0560,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8222 036700 036 14 0 00 043537 8223 036701 255 00 0 00 000000 8224 ^ 8225 8226 036702 200 14 0 00 040457 ..0561: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8227 036703 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8228 ERROR (..0560,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8229 LL 8230 036704 036 13 0 00 043551 8231 036705 255 00 0 00 000000 8232 ^ 8233 ^ 8234 8235 ; ********************************************************************** 8236 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8237 ; ********************************************************************** 8238 8239 MULTF (G,2,0,-3,0,-1,-6,400000000000,400000000000)^ 8240 8241 ; --- MULTIPLICAND = (2,0) 8242 ; --- MULTIPLIER === (-3,0) 8243 ; --- RESULT ======= (-1,-6,400000000000,400000000000) 8244 8245 036706 200 01 0 00 043762 ..0562: MOVE AC1,[[EXP 2,0,-3,0,-1,-6,400000000000,400000000000],,MCAND] 8246 036707 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8247 036710 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8248 ERROR (..0562,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8249 036711 036 14 0 00 043537 8250 036712 255 00 0 00 000000 8251 ^ 8252 8253 036713 200 14 0 00 040457 ..0563: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8254 036714 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8255 ERROR (..0562,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8256 LL 8257 036715 036 13 0 00 043551 8258 036716 255 00 0 00 000000 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-8 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0192 8259 ^ 8260 ^ 8261 8262 ; ********************************************************************** 8263 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8264 ; ********************************************************************** 8265 8266 MULTF (G,2,400000000000,-3,0,-1,-6,400000000000,400000000000)^ 8267 8268 ; --- MULTIPLICAND = (2,400000000000) 8269 ; --- MULTIPLIER === (-3,0) 8270 ; --- RESULT ======= (-1,-6,400000000000,400000000000) 8271 8272 036717 200 01 0 00 043773 ..0564: MOVE AC1,[[EXP 2,400000000000,-3,0,-1,-6,400000000000,400000000000],,MCAND] 8273 036720 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8274 036721 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8275 ERROR (..0564,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8276 036722 036 14 0 00 043537 8277 036723 255 00 0 00 000000 8278 ^ 8279 8280 036724 200 14 0 00 040457 ..0565: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8281 036725 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8282 ERROR (..0564,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8283 LL 8284 036726 036 13 0 00 043551 8285 036727 255 00 0 00 000000 8286 ^ 8287 ^ 8288 8289 ; ********************************************************************** 8290 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8291 ; ********************************************************************** 8292 8293 MULTF (G,2,400000000000,-3,400000000000,-1,-6,400000000000,400000000000)^ 8294 8295 ; --- MULTIPLICAND = (2,400000000000) 8296 ; --- MULTIPLIER === (-3,400000000000) 8297 ; --- RESULT ======= (-1,-6,400000000000,400000000000) 8298 8299 ..0566: MOVE AC1,[[EXP 2,400000000000,-3,400000000000,-1,-6,400000000000,400000000000],, 8300 036730 200 01 0 00 044004 MCAND] 8301 036731 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8302 036732 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8303 ERROR (..0566,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8304 036733 036 14 0 00 043537 8305 036734 255 00 0 00 000000 8306 ^ 8307 8308 036735 200 14 0 00 040457 ..0567: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8309 036736 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8310 ERROR (..0566,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8311 LL 8312 036737 036 13 0 00 043551 8313 036740 255 00 0 00 000000 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-9 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0193 8314 ^ 8315 ^ 8316 8317 ; ********************************************************************** 8318 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8319 ; ********************************************************************** 8320 8321 MULTF (G,-2,400000000000,3,400000000000,-1,-6,400000000000,400000000000)^ 8322 8323 ; --- MULTIPLICAND = (-2,400000000000) 8324 ; --- MULTIPLIER === (3,400000000000) 8325 ; --- RESULT ======= (-1,-6,400000000000,400000000000) 8326 8327 ..0570: MOVE AC1,[[EXP -2,400000000000,3,400000000000,-1,-6,400000000000,400000000000],, 8328 036741 200 01 0 00 044015 MCAND] 8329 036742 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8330 036743 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8331 ERROR (..0570,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8332 036744 036 14 0 00 043537 8333 036745 255 00 0 00 000000 8334 ^ 8335 8336 036746 200 14 0 00 040457 ..0571: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8337 036747 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8338 ERROR (..0570,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8339 LL 8340 036750 036 13 0 00 043551 8341 036751 255 00 0 00 000000 8342 ^ 8343 ^ 8344 8345 ; ********************************************************************** 8346 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8347 ; ********************************************************************** 8348 8349 MULTF (G,-2,0,3,400000000000,-1,-6,400000000000,400000000000)^ 8350 8351 ; --- MULTIPLICAND = (-2,0) 8352 ; --- MULTIPLIER === (3,400000000000) 8353 ; --- RESULT ======= (-1,-6,400000000000,400000000000) 8354 8355 036752 200 01 0 00 044026 ..0572: MOVE AC1,[[EXP -2,0,3,400000000000,-1,-6,400000000000,400000000000],,MCAND] 8356 036753 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8357 036754 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8358 ERROR (..0572,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8359 036755 036 14 0 00 043537 8360 036756 255 00 0 00 000000 8361 ^ 8362 8363 036757 200 14 0 00 040457 ..0573: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8364 036760 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8365 ERROR (..0572,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8366 LL 8367 036761 036 13 0 00 043551 8368 036762 255 00 0 00 000000 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-10 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0194 8369 ^ 8370 ^ 8371 8372 ; ********************************************************************** 8373 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8374 ; ********************************************************************** 8375 8376 MULTF (G,-2,0,3,0,-1,-6,400000000000,400000000000)^ 8377 8378 ; --- MULTIPLICAND = (-2,0) 8379 ; --- MULTIPLIER === (3,0) 8380 ; --- RESULT ======= (-1,-6,400000000000,400000000000) 8381 8382 036763 200 01 0 00 044037 ..0574: MOVE AC1,[[EXP -2,0,3,0,-1,-6,400000000000,400000000000],,MCAND] 8383 036764 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8384 036765 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8385 ERROR (..0574,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8386 036766 036 14 0 00 043537 8387 036767 255 00 0 00 000000 8388 ^ 8389 8390 036770 200 14 0 00 040457 ..0575: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8391 036771 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8392 ERROR (..0574,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8393 LL 8394 036772 036 13 0 00 043551 8395 036773 255 00 0 00 000000 8396 ^ 8397 ^ 8398 8399 ; ********************************************************************** 8400 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8401 ; ********************************************************************** 8402 8403 MULTF (G,-2,400000000000,-3,0,0,6)^ 8404 8405 ; --- MULTIPLICAND = (-2,400000000000) 8406 ; --- MULTIPLIER === (-3,0) 8407 ; --- RESULT ======= (0,6,0,0) 8408 8409 036774 200 01 0 00 044050 ..0576: MOVE AC1,[[EXP -2,400000000000,-3,0,0,6,0,0],,MCAND] 8410 036775 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8411 036776 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8412 ERROR (..0576,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8413 036777 036 14 0 00 043537 8414 037000 255 00 0 00 000000 8415 ^ 8416 8417 037001 200 14 0 00 040457 ..0577: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8418 037002 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8419 ERROR (..0576,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8420 LL 8421 037003 036 13 0 00 043551 8422 037004 255 00 0 00 000000 8423 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 24-11 DSKCFM MAC 26-Sep-79 15:49 DMUL - TEST G SEQ 0195 8424 ^ 8425 8426 ; ********************************************************************** 8427 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8428 ; ********************************************************************** 8429 8430 MULTF (G,-2,0,-3,0,0,6)^ 8431 8432 ; --- MULTIPLICAND = (-2,0) 8433 ; --- MULTIPLIER === (-3,0) 8434 ; --- RESULT ======= (0,6,0,0) 8435 8436 037005 200 01 0 00 044061 ..0600: MOVE AC1,[[EXP -2,0,-3,0,0,6,0,0],,MCAND] 8437 037006 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8438 037007 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8439 ERROR (..0600,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8440 037010 036 14 0 00 043537 8441 037011 255 00 0 00 000000 8442 ^ 8443 8444 037012 200 14 0 00 040457 ..0601: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8445 037013 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8446 ERROR (..0600,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8447 LL 8448 037014 036 13 0 00 043551 8449 037015 255 00 0 00 000000 8450 ^ 8451 ^ 8452 8453 ; ********************************************************************** 8454 ; ---------- DMUL - TEST G - INCONSISTENT SIGNS ---------- 8455 ; ********************************************************************** 8456 8457 MULTF (G,-2,0,-3,400000000000,0,6)^ 8458 8459 ; --- MULTIPLICAND = (-2,0) 8460 ; --- MULTIPLIER === (-3,400000000000) 8461 ; --- RESULT ======= (0,6,0,0) 8462 8463 037016 200 01 0 00 044072 ..0602: MOVE AC1,[[EXP -2,0,-3,400000000000,0,6,0,0],,MCAND] 8464 037017 251 01 0 00 040511 BLT AC1,MRES+3 ;SET UP OPERANDS FOR SUBROUTINE 8465 037020 260 17 0 00 040451 GO MSUBR ;GO DO TEST 8466 ERROR (..0602,14,SCR1,SCR2,,TEST G - RESULT CALCULATED INCORRECTLY,MPRINT)^SALL 8467 037021 036 14 0 00 043537 8468 037022 255 00 0 00 000000 8469 ^ 8470 8471 037023 200 14 0 00 040457 ..0603: MOVE SCR2,MFLOC ;GET PC - TO TEST PC FLAGS 8472 037024 623 14 0 00 400000 TLZE SCR2,AROV ;CALC OK PC (NO - AROV) & TEST 8473 ERROR (..0602,13,SCR2,MFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0 TO 4,MPRINT)^SA 8474 LL 8475 037025 036 13 0 00 043551 8476 037026 255 00 0 00 000000 8477 ^ 8478 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 25 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST A SEQ 0196 8479 SUBTTL DDIV - TEST A 8480 SALL 8481 044073 T=SIXBTZ 8482 LALL 8483 ; ********************************************************************** 8484 ;*DDIV - TEST A 8485 ;* 8486 ;* (0,0,0,#) / 1 THESE BASIC TESTS VERIFY THAT THE DDIV 8487 ;* (0,0,#,0) / 1 HANDLES A QUADRUPLE WORD DIVIDEND. FOR 8488 ;* EACH TEST ALL PERMUTATIONS OF POSITIVE 8489 ;* AND NEGATIVE OPERANDS ARE TESTED. 8490 ; ********************************************************************** 8491 8492 ; ********************************************************************** 8493 ; ---------- DDIV - TEST A - (0,0,0,#) / 1 ---------- 8494 ; ********************************************************************** 8495 8496 PDIV (A,0,0,0,NUM,0,1,0,NUM)^ 8497 8498 ; --- DIVIDEND == (0,0,0,NUM) 8499 ; --- DIVISOR === (0,1) 8500 ; --- QUOTIENT == (0,NUM) 8501 ; --- REMAINDER = (0,0) 8502 8503 037027 200 01 0 00 044107 ..0604: MOVE AC1,[[EXP 0,0,0,NUM,0,1,0,NUM,0,0],,PDEND] 8504 037030 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8505 037031 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8506 ERROR (..0604,14,SCR1,SCR2,,TEST A - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8507 037032 036 14 0 00 044117 8508 037033 255 00 0 00 000000 8509 ^ 8510 ^ 8511 8512 ; ********************************************************************** 8513 ; ---------- DDIV - TEST A - (0,0,#,0) / 1 ---------- 8514 ; ********************************************************************** 8515 8516 PDIV (A,0,0,NUM,0,0,1,NUM,0)^ 8517 8518 ; --- DIVIDEND == (0,0,NUM,0) 8519 ; --- DIVISOR === (0,1) 8520 ; --- QUOTIENT == (NUM,0) 8521 ; --- REMAINDER = (0,0) 8522 8523 037034 200 01 0 00 044134 ..0605: MOVE AC1,[[EXP 0,0,NUM,0,0,1,NUM,0,0,0],,PDEND] 8524 037035 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8525 037036 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8526 ERROR (..0605,14,SCR1,SCR2,,TEST A - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8527 037037 036 14 0 00 044117 8528 037040 255 00 0 00 000000 8529 ^ 8530 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 26 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST B SEQ 0197 8531 SUBTTL DDIV - TEST B 8532 8533 ; ********************************************************************** 8534 ;*DDIV - TEST B 8535 ;* 8536 ;* (0,0,0,#) / # THESE TESTS PERFORM SOME CASES MORE 8537 ;* (0,0,#,0) / (#,0) DIFFICULT THAN (A). PERMUTATIONS OF 8538 ;* POSITIVE AND NEGATIVE OPERANDS ARE 8539 ;* TESTED. 8540 ; ********************************************************************** 8541 8542 ; ********************************************************************** 8543 ; ---------- DDIV - TEST B - (0,0,0,#) / # ---------- 8544 ; ********************************************************************** 8545 8546 PDIV (B,0,0,0,NUM,0,NUM,0,1)^ 8547 8548 ; --- DIVIDEND == (0,0,0,NUM) 8549 ; --- DIVISOR === (0,NUM) 8550 ; --- QUOTIENT == (0,1) 8551 ; --- REMAINDER = (0,0) 8552 8553 037041 200 01 0 00 044147 ..0606: MOVE AC1,[[EXP 0,0,0,NUM,0,NUM,0,1,0,0],,PDEND] 8554 037042 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8555 037043 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8556 ERROR (..0606,14,SCR1,SCR2,,TEST B - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8557 037044 036 14 0 00 044157 8558 037045 255 00 0 00 000000 8559 ^ 8560 ^ 8561 8562 ; ********************************************************************** 8563 ; ---------- DDIV - TEST B - (0,0,#,0) / #,0 ---------- 8564 ; ********************************************************************** 8565 8566 PDIV (B,0,0,NUM,0,NUM,0,0,1)^ 8567 8568 ; --- DIVIDEND == (0,0,NUM,0) 8569 ; --- DIVISOR === (NUM,0) 8570 ; --- QUOTIENT == (0,1) 8571 ; --- REMAINDER = (0,0) 8572 8573 037046 200 01 0 00 044174 ..0607: MOVE AC1,[[EXP 0,0,NUM,0,NUM,0,0,1,0,0],,PDEND] 8574 037047 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8575 037050 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8576 ERROR (..0607,14,SCR1,SCR2,,TEST B - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8577 037051 036 14 0 00 044157 8578 037052 255 00 0 00 000000 8579 ^ 8580 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 27 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST C SEQ 0198 8581 SUBTTL DDIV - TEST C 8582 8583 ; ********************************************************************** 8584 ;*DDIV - TEST C 8585 ;* 8586 ;* (0,0,0,1) (0,0,1,0) (0,0,1,0) (0,1,0,0) (0,1,0,0) (1,0,0,0) 8587 ;* ------- ------- ------- ------- ------- ------- 8588 ;* 2 2 2,0 2 2,0 2,0 8589 ;* 8590 ;* THESE TESTS PERFORM DIVISIONS WHICH RESULT IN A SHIFT OF THE 8591 ;* THE DIVIDEND ACROSS WORD BOUNDARIES. 8592 ;* THESE TESTS ARE REPEATED FOR THE VARIOUS PERMUTATIONS OF 8593 ;* POSITIVE AND NEGATIVE OPERANDS. 8594 ; ********************************************************************** 8595 8596 ; ********************************************************************** 8597 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8598 ; ********************************************************************** 8599 8600 PDIV (C,0,0,0,1,0,2,0,0,0,1)^ 8601 8602 ; --- DIVIDEND == (0,0,0,1) 8603 ; --- DIVISOR === (0,2) 8604 ; --- QUOTIENT == (0,0) 8605 ; --- REMAINDER = (0,1) 8606 8607 037053 200 01 0 00 044207 ..0610: MOVE AC1,[[EXP 0,0,0,1,0,2,0,0,0,1],,PDEND] 8608 037054 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8609 037055 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8610 ERROR (..0610,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8611 037056 036 14 0 00 044217 8612 037057 255 00 0 00 000000 8613 ^ 8614 ^ 8615 8616 ; ********************************************************************** 8617 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8618 ; ********************************************************************** 8619 8620 PDIV (C,0,0,1,0,0,2,0,200000000000,0,0)^ 8621 8622 ; --- DIVIDEND == (0,0,1,0) 8623 ; --- DIVISOR === (0,2) 8624 ; --- QUOTIENT == (0,200000000000) 8625 ; --- REMAINDER = (0,0) 8626 8627 037060 200 01 0 00 044234 ..0611: MOVE AC1,[[EXP 0,0,1,0,0,2,0,200000000000,0,0],,PDEND] 8628 037061 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8629 037062 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8630 ERROR (..0611,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8631 037063 036 14 0 00 044217 8632 037064 255 00 0 00 000000 8633 ^ 8634 ^ 8635 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 27-1 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST C SEQ 0199 8636 ; ********************************************************************** 8637 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8638 ; ********************************************************************** 8639 8640 PDIV (C,0,0,1,0,2,0,0,0,1,0)^ 8641 8642 ; --- DIVIDEND == (0,0,1,0) 8643 ; --- DIVISOR === (2,0) 8644 ; --- QUOTIENT == (0,0) 8645 ; --- REMAINDER = (1,0) 8646 8647 037065 200 01 0 00 044247 ..0612: MOVE AC1,[[EXP 0,0,1,0,2,0,0,0,1,0],,PDEND] 8648 037066 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8649 037067 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8650 ERROR (..0612,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8651 037070 036 14 0 00 044217 8652 037071 255 00 0 00 000000 8653 ^ 8654 ^ 8655 8656 ; ********************************************************************** 8657 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8658 ; ********************************************************************** 8659 8660 PDIV (C,0,1,0,0,0,2,200000000000,0,0,0)^ 8661 8662 ; --- DIVIDEND == (0,1,0,0) 8663 ; --- DIVISOR === (0,2) 8664 ; --- QUOTIENT == (200000000000,0) 8665 ; --- REMAINDER = (0,0) 8666 8667 037072 200 01 0 00 044262 ..0613: MOVE AC1,[[EXP 0,1,0,0,0,2,200000000000,0,0,0],,PDEND] 8668 037073 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8669 037074 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8670 ERROR (..0613,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8671 037075 036 14 0 00 044217 8672 037076 255 00 0 00 000000 8673 ^ 8674 ^ 8675 8676 ; ********************************************************************** 8677 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8678 ; ********************************************************************** 8679 8680 PDIV (C,0,1,0,0,2,0,0,200000000000,0,0)^ 8681 8682 ; --- DIVIDEND == (0,1,0,0) 8683 ; --- DIVISOR === (2,0) 8684 ; --- QUOTIENT == (0,200000000000) 8685 ; --- REMAINDER = (0,0) 8686 8687 037077 200 01 0 00 044275 ..0614: MOVE AC1,[[EXP 0,1,0,0,2,0,0,200000000000,0,0],,PDEND] 8688 037100 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8689 037101 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8690 ERROR (..0614,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 27-2 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST C SEQ 0200 8691 037102 036 14 0 00 044217 8692 037103 255 00 0 00 000000 8693 ^ 8694 ^ 8695 8696 ; ********************************************************************** 8697 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8698 ; ********************************************************************** 8699 8700 PDIV (C,1,0,0,0,2,0,200000000000,0,0,0)^ 8701 8702 ; --- DIVIDEND == (1,0,0,0) 8703 ; --- DIVISOR === (2,0) 8704 ; --- QUOTIENT == (200000000000,0) 8705 ; --- REMAINDER = (0,0) 8706 8707 037104 200 01 0 00 044310 ..0615: MOVE AC1,[[EXP 1,0,0,0,2,0,200000000000,0,0,0],,PDEND] 8708 037105 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8709 037106 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8710 ERROR (..0615,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8711 037107 036 14 0 00 044217 8712 037110 255 00 0 00 000000 8713 ^ 8714 ^ 8715 8716 ; ********************************************************************** 8717 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8718 ; ********************************************************************** 8719 8720 PDIV (C,-1,-1,-1,-1,0,2,0,0,-1,-1)^ 8721 8722 ; --- DIVIDEND == (-1,-1,-1,-1) 8723 ; --- DIVISOR === (0,2) 8724 ; --- QUOTIENT == (0,0) 8725 ; --- REMAINDER = (-1,-1) 8726 8727 037111 200 01 0 00 044323 ..0616: MOVE AC1,[[EXP -1,-1,-1,-1,0,2,0,0,-1,-1],,PDEND] 8728 037112 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8729 037113 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8730 ERROR (..0616,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8731 037114 036 14 0 00 044217 8732 037115 255 00 0 00 000000 8733 ^ 8734 ^ 8735 8736 ; ********************************************************************** 8737 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8738 ; ********************************************************************** 8739 8740 PDIV (C,-1,-1,-1,1B0,0,2,-1,600000000000,0,0)^ 8741 8742 ; --- DIVIDEND == (-1,-1,-1,1B0) 8743 ; --- DIVISOR === (0,2) 8744 ; --- QUOTIENT == (-1,600000000000) 8745 ; --- REMAINDER = (0,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 27-3 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST C SEQ 0201 8746 8747 037116 200 01 0 00 044336 ..0617: MOVE AC1,[[EXP -1,-1,-1,1B0,0,2,-1,600000000000,0,0],,PDEND] 8748 037117 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8749 037120 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8750 ERROR (..0617,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8751 037121 036 14 0 00 044217 8752 037122 255 00 0 00 000000 8753 ^ 8754 ^ 8755 8756 ; ********************************************************************** 8757 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8758 ; ********************************************************************** 8759 8760 PDIV (C,-1,-1,-1,1B0,2,0,0,0,-1,1B0)^ 8761 8762 ; --- DIVIDEND == (-1,-1,-1,1B0) 8763 ; --- DIVISOR === (2,0) 8764 ; --- QUOTIENT == (0,0) 8765 ; --- REMAINDER = (-1,1B0) 8766 8767 037123 200 01 0 00 044351 ..0620: MOVE AC1,[[EXP -1,-1,-1,1B0,2,0,0,0,-1,1B0],,PDEND] 8768 037124 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8769 037125 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8770 ERROR (..0620,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8771 037126 036 14 0 00 044217 8772 037127 255 00 0 00 000000 8773 ^ 8774 ^ 8775 8776 ; ********************************************************************** 8777 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8778 ; ********************************************************************** 8779 8780 PDIV (C,-1,-1,1B0,1B0,0,2,600000000000,1B0,0,0)^ 8781 8782 ; --- DIVIDEND == (-1,-1,1B0,1B0) 8783 ; --- DIVISOR === (0,2) 8784 ; --- QUOTIENT == (600000000000,1B0) 8785 ; --- REMAINDER = (0,0) 8786 8787 037130 200 01 0 00 044364 ..0621: MOVE AC1,[[EXP -1,-1,1B0,1B0,0,2,600000000000,1B0,0,0],,PDEND] 8788 037131 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8789 037132 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8790 ERROR (..0621,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8791 037133 036 14 0 00 044217 8792 037134 255 00 0 00 000000 8793 ^ 8794 ^ 8795 8796 ; ********************************************************************** 8797 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8798 ; ********************************************************************** 8799 8800 PDIV (C,-1,-1,1B0,1B0,2,0,-1,600000000000,0,0)^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 27-4 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST C SEQ 0202 8801 8802 ; --- DIVIDEND == (-1,-1,1B0,1B0) 8803 ; --- DIVISOR === (2,0) 8804 ; --- QUOTIENT == (-1,600000000000) 8805 ; --- REMAINDER = (0,0) 8806 8807 037135 200 01 0 00 044377 ..0622: MOVE AC1,[[EXP -1,-1,1B0,1B0,2,0,-1,600000000000,0,0],,PDEND] 8808 037136 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8809 037137 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8810 ERROR (..0622,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8811 037140 036 14 0 00 044217 8812 037141 255 00 0 00 000000 8813 ^ 8814 ^ 8815 8816 ; ********************************************************************** 8817 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8818 ; ********************************************************************** 8819 8820 PDIV (C,-1,1B0,1B0,1B0,2,0,600000000000,1B0,0,0)^ 8821 8822 ; --- DIVIDEND == (-1,1B0,1B0,1B0) 8823 ; --- DIVISOR === (2,0) 8824 ; --- QUOTIENT == (600000000000,1B0) 8825 ; --- REMAINDER = (0,0) 8826 8827 037142 200 01 0 00 044412 ..0623: MOVE AC1,[[EXP -1,1B0,1B0,1B0,2,0,600000000000,1B0,0,0],,PDEND] 8828 037143 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8829 037144 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8830 ERROR (..0623,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8831 037145 036 14 0 00 044217 8832 037146 255 00 0 00 000000 8833 ^ 8834 ^ 8835 8836 ; ********************************************************************** 8837 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8838 ; ********************************************************************** 8839 8840 PDIV (C,0,0,0,1,-1,-2,0,0,0,1)^ 8841 8842 ; --- DIVIDEND == (0,0,0,1) 8843 ; --- DIVISOR === (-1,-2) 8844 ; --- QUOTIENT == (0,0) 8845 ; --- REMAINDER = (0,1) 8846 8847 037147 200 01 0 00 044425 ..0624: MOVE AC1,[[EXP 0,0,0,1,-1,-2,0,0,0,1],,PDEND] 8848 037150 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8849 037151 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8850 ERROR (..0624,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8851 037152 036 14 0 00 044217 8852 037153 255 00 0 00 000000 8853 ^ 8854 ^ 8855 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 27-5 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST C SEQ 0203 8856 ; ********************************************************************** 8857 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8858 ; ********************************************************************** 8859 8860 PDIV (C,0,0,1,0,-1,-2,-1,600000000000,0,0)^ 8861 8862 ; --- DIVIDEND == (0,0,1,0) 8863 ; --- DIVISOR === (-1,-2) 8864 ; --- QUOTIENT == (-1,600000000000) 8865 ; --- REMAINDER = (0,0) 8866 8867 037154 200 01 0 00 044440 ..0625: MOVE AC1,[[EXP 0,0,1,0,-1,-2,-1,600000000000,0,0],,PDEND] 8868 037155 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8869 037156 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8870 ERROR (..0625,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8871 037157 036 14 0 00 044217 8872 037160 255 00 0 00 000000 8873 ^ 8874 ^ 8875 8876 ; ********************************************************************** 8877 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8878 ; ********************************************************************** 8879 8880 PDIV (C,0,0,1,0,-2,1B0,0,0,1,0)^ 8881 8882 ; --- DIVIDEND == (0,0,1,0) 8883 ; --- DIVISOR === (-2,1B0) 8884 ; --- QUOTIENT == (0,0) 8885 ; --- REMAINDER = (1,0) 8886 8887 037161 200 01 0 00 044453 ..0626: MOVE AC1,[[EXP 0,0,1,0,-2,1B0,0,0,1,0],,PDEND] 8888 037162 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8889 037163 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8890 ERROR (..0626,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8891 037164 036 14 0 00 044217 8892 037165 255 00 0 00 000000 8893 ^ 8894 ^ 8895 8896 ; ********************************************************************** 8897 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8898 ; ********************************************************************** 8899 8900 PDIV (C,0,1,0,0,-1,-2,600000000000,1B0,0,0)^ 8901 8902 ; --- DIVIDEND == (0,1,0,0) 8903 ; --- DIVISOR === (-1,-2) 8904 ; --- QUOTIENT == (600000000000,1B0) 8905 ; --- REMAINDER = (0,0) 8906 8907 037166 200 01 0 00 044466 ..0627: MOVE AC1,[[EXP 0,1,0,0,-1,-2,600000000000,1B0,0,0],,PDEND] 8908 037167 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8909 037170 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8910 ERROR (..0627,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 27-6 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST C SEQ 0204 8911 037171 036 14 0 00 044217 8912 037172 255 00 0 00 000000 8913 ^ 8914 ^ 8915 8916 ; ********************************************************************** 8917 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8918 ; ********************************************************************** 8919 8920 PDIV (C,0,1,0,0,-2,1B0,-1,600000000000,0,0)^ 8921 8922 ; --- DIVIDEND == (0,1,0,0) 8923 ; --- DIVISOR === (-2,1B0) 8924 ; --- QUOTIENT == (-1,600000000000) 8925 ; --- REMAINDER = (0,0) 8926 8927 037173 200 01 0 00 044501 ..0630: MOVE AC1,[[EXP 0,1,0,0,-2,1B0,-1,600000000000,0,0],,PDEND] 8928 037174 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8929 037175 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8930 ERROR (..0630,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8931 037176 036 14 0 00 044217 8932 037177 255 00 0 00 000000 8933 ^ 8934 ^ 8935 8936 ; ********************************************************************** 8937 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8938 ; ********************************************************************** 8939 8940 PDIV (C,1,0,0,0,-2,1B0,600000000000,1B0,0,0)^ 8941 8942 ; --- DIVIDEND == (1,0,0,0) 8943 ; --- DIVISOR === (-2,1B0) 8944 ; --- QUOTIENT == (600000000000,1B0) 8945 ; --- REMAINDER = (0,0) 8946 8947 037200 200 01 0 00 044514 ..0631: MOVE AC1,[[EXP 1,0,0,0,-2,1B0,600000000000,1B0,0,0],,PDEND] 8948 037201 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8949 037202 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8950 ERROR (..0631,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8951 037203 036 14 0 00 044217 8952 037204 255 00 0 00 000000 8953 ^ 8954 ^ 8955 8956 ; ********************************************************************** 8957 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8958 ; ********************************************************************** 8959 8960 PDIV (C,-1,-1,-1,-1,-1,-2,0,0,-1,-1)^ 8961 8962 ; --- DIVIDEND == (-1,-1,-1,-1) 8963 ; --- DIVISOR === (-1,-2) 8964 ; --- QUOTIENT == (0,0) 8965 ; --- REMAINDER = (-1,-1) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 27-7 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST C SEQ 0205 8966 8967 037205 200 01 0 00 044527 ..0632: MOVE AC1,[[EXP -1,-1,-1,-1,-1,-2,0,0,-1,-1],,PDEND] 8968 037206 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8969 037207 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8970 ERROR (..0632,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8971 037210 036 14 0 00 044217 8972 037211 255 00 0 00 000000 8973 ^ 8974 ^ 8975 8976 ; ********************************************************************** 8977 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8978 ; ********************************************************************** 8979 8980 PDIV (C,-1,-1,-1,1B0,-1,-2,0,200000000000,0,0)^ 8981 8982 ; --- DIVIDEND == (-1,-1,-1,1B0) 8983 ; --- DIVISOR === (-1,-2) 8984 ; --- QUOTIENT == (0,200000000000) 8985 ; --- REMAINDER = (0,0) 8986 8987 037212 200 01 0 00 044542 ..0633: MOVE AC1,[[EXP -1,-1,-1,1B0,-1,-2,0,200000000000,0,0],,PDEND] 8988 037213 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 8989 037214 260 17 0 00 040513 GO PSUBR ;GO DO TEST 8990 ERROR (..0633,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 8991 037215 036 14 0 00 044217 8992 037216 255 00 0 00 000000 8993 ^ 8994 ^ 8995 8996 ; ********************************************************************** 8997 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 8998 ; ********************************************************************** 8999 9000 PDIV (C,-1,-1,-1,1B0,-2,1B0,0,0,-1,1B0)^ 9001 9002 ; --- DIVIDEND == (-1,-1,-1,1B0) 9003 ; --- DIVISOR === (-2,1B0) 9004 ; --- QUOTIENT == (0,0) 9005 ; --- REMAINDER = (-1,1B0) 9006 9007 037217 200 01 0 00 044555 ..0634: MOVE AC1,[[EXP -1,-1,-1,1B0,-2,1B0,0,0,-1,1B0],,PDEND] 9008 037220 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9009 037221 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9010 ERROR (..0634,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9011 037222 036 14 0 00 044217 9012 037223 255 00 0 00 000000 9013 ^ 9014 ^ 9015 9016 ; ********************************************************************** 9017 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 9018 ; ********************************************************************** 9019 9020 PDIV (C,-1,-1,1B0,1B0,-1,-2,200000000000,0,0,0)^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 27-8 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST C SEQ 0206 9021 9022 ; --- DIVIDEND == (-1,-1,1B0,1B0) 9023 ; --- DIVISOR === (-1,-2) 9024 ; --- QUOTIENT == (200000000000,0) 9025 ; --- REMAINDER = (0,0) 9026 9027 037224 200 01 0 00 044570 ..0635: MOVE AC1,[[EXP -1,-1,1B0,1B0,-1,-2,200000000000,0,0,0],,PDEND] 9028 037225 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9029 037226 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9030 ERROR (..0635,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9031 037227 036 14 0 00 044217 9032 037230 255 00 0 00 000000 9033 ^ 9034 ^ 9035 9036 ; ********************************************************************** 9037 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 9038 ; ********************************************************************** 9039 9040 PDIV (C,-1,-1,1B0,1B0,-2,1B0,0,200000000000,0,0)^ 9041 9042 ; --- DIVIDEND == (-1,-1,1B0,1B0) 9043 ; --- DIVISOR === (-2,1B0) 9044 ; --- QUOTIENT == (0,200000000000) 9045 ; --- REMAINDER = (0,0) 9046 9047 037231 200 01 0 00 044603 ..0636: MOVE AC1,[[EXP -1,-1,1B0,1B0,-2,1B0,0,200000000000,0,0],,PDEND] 9048 037232 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9049 037233 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9050 ERROR (..0636,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9051 037234 036 14 0 00 044217 9052 037235 255 00 0 00 000000 9053 ^ 9054 ^ 9055 9056 ; ********************************************************************** 9057 ; ---------- DDIV - TEST C (GENERAL TESTING) ---------- 9058 ; ********************************************************************** 9059 9060 PDIV (C,-1,1B0,1B0,1B0,-2,1B0,200000000000,0,0,0)^ 9061 9062 ; --- DIVIDEND == (-1,1B0,1B0,1B0) 9063 ; --- DIVISOR === (-2,1B0) 9064 ; --- QUOTIENT == (200000000000,0) 9065 ; --- REMAINDER = (0,0) 9066 9067 037236 200 01 0 00 044616 ..0637: MOVE AC1,[[EXP -1,1B0,1B0,1B0,-2,1B0,200000000000,0,0,0],,PDEND] 9068 037237 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9069 037240 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9070 ERROR (..0637,14,SCR1,SCR2,,TEST C - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9071 037241 036 14 0 00 044217 9072 037242 255 00 0 00 000000 9073 ^ 9074 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 28 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST D SEQ 0207 9075 SUBTTL DDIV - TEST D 9076 9077 ; ********************************************************************** 9078 ;*DDIV - TEST D 9079 ;* 9080 ;* MISCELLANEOUS TESTING. THESE TESTS DIVIDE 2 NUMBERS AND JUST 9081 ;* CHECK TO SEE THAT THE DDIV GETS THE CORRECT ANSWERS. 9082 ; ********************************************************************** 9083 9084 111111 111111 ONE=111111111111 9085 222222 222222 TWO=222222222222 9086 333333 333333 THREE=333333333333 9087 444444 444444 FOUR=444444444444 9088 555555 555555 FIVE=555555555555 9089 9090 ; ********************************************************************** 9091 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9092 ; ********************************************************************** 9093 9094 PDIVF (D,THREE,THREE,THREE,THREE,344444444444,FOUR,365605075342,070414545131,0556 9095 32516360,373564760527)^ 9096 9097 ; --- DIVIDEND == (THREE,THREE,THREE,THREE) 9098 ; --- DIVISOR === (344444444444,FOUR) 9099 ; --- QUOTIENT == (365605075342,070414545131) 9100 ; --- REMAINDER = (055632516360,373564760527) 9101 9102 ..0640: MOVE AC1,[[EXP THREE,THREE,THREE,THREE,344444444444,FOUR,365605075342,0704145451 9103 037243 200 01 0 00 044631 31,055632516360,373564760527],,PDEND] 9104 037244 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9105 037245 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9106 ERROR (..0640,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9107 037246 036 14 0 00 044641 9108 037247 255 00 0 00 000000 9109 ^ 9110 9111 037250 200 14 0 00 040521 ..0641: MOVE SCR2,PFLOC ;GET PC 9112 037251 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9113 ERROR (..0640,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9114 LL 9115 037252 036 13 0 00 044653 9116 037253 255 00 0 00 000000 9117 ^ 9118 ^ 9119 9120 ; ********************************************************************** 9121 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9122 ; ********************************************************************** 9123 9124 PDIVF (D,THREE,FOUR,THREE,FOUR,344444444444,THREE,365605075340,247073632327,21367 9125 2200375,376365035467)^ 9126 9127 ; --- DIVIDEND == (THREE,FOUR,THREE,FOUR) 9128 ; --- DIVISOR === (344444444444,THREE) 9129 ; --- QUOTIENT == (365605075340,247073632327) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 28-1 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST D SEQ 0208 9130 ; --- REMAINDER = (213672200375,376365035467) 9131 9132 ..0642: MOVE AC1,[[EXP THREE,FOUR,THREE,FOUR,344444444444,THREE,365605075340,24707363232 9133 037254 200 01 0 00 044670 7,213672200375,376365035467],,PDEND] 9134 037255 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9135 037256 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9136 ERROR (..0642,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9137 037257 036 14 0 00 044641 9138 037260 255 00 0 00 000000 9139 ^ 9140 9141 037261 200 14 0 00 040521 ..0643: MOVE SCR2,PFLOC ;GET PC 9142 037262 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9143 ERROR (..0642,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9144 LL 9145 037263 036 13 0 00 044653 9146 037264 255 00 0 00 000000 9147 ^ 9148 ^ 9149 9150 ; ********************************************************************** 9151 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9152 ; ********************************************************************** 9153 9154 PDIVF (D,TWO,TWO,TWO,TWO,THREE,THREE,252525252525,125252525253,ONE,ONE)^ 9155 9156 ; --- DIVIDEND == (TWO,TWO,TWO,TWO) 9157 ; --- DIVISOR === (THREE,THREE) 9158 ; --- QUOTIENT == (252525252525,125252525253) 9159 ; --- REMAINDER = (ONE,ONE) 9160 9161 ..0644: MOVE AC1,[[EXP TWO,TWO,TWO,TWO,THREE,THREE,252525252525,125252525253,ONE,ONE],,P 9162 037265 200 01 0 00 044703 DEND] 9163 037266 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9164 037267 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9165 ERROR (..0644,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9166 037270 036 14 0 00 044641 9167 037271 255 00 0 00 000000 9168 ^ 9169 9170 037272 200 14 0 00 040521 ..0645: MOVE SCR2,PFLOC ;GET PC 9171 037273 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9172 ERROR (..0644,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9173 LL 9174 037274 036 13 0 00 044653 9175 037275 255 00 0 00 000000 9176 ^ 9177 ^ 9178 9179 ; ********************************************************************** 9180 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9181 ; ********************************************************************** 9182 9183 PDIVF (D,TWO,THREE,TWO,THREE,THREE,FOUR,252525252526,070707070710,004040404041,32 9184 7272727273)^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 28-2 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST D SEQ 0209 9185 9186 ; --- DIVIDEND == (TWO,THREE,TWO,THREE) 9187 ; --- DIVISOR === (THREE,FOUR) 9188 ; --- QUOTIENT == (252525252526,070707070710) 9189 ; --- REMAINDER = (004040404041,327272727273) 9190 9191 ..0646: MOVE AC1,[[EXP TWO,THREE,TWO,THREE,THREE,FOUR,252525252526,070707070710,00404040 9192 037276 200 01 0 00 044716 4041,327272727273],,PDEND] 9193 037277 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9194 037300 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9195 ERROR (..0646,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9196 037301 036 14 0 00 044641 9197 037302 255 00 0 00 000000 9198 ^ 9199 9200 037303 200 14 0 00 040521 ..0647: MOVE SCR2,PFLOC ;GET PC 9201 037304 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9202 ERROR (..0646,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9203 LL 9204 037305 036 13 0 00 044653 9205 037306 255 00 0 00 000000 9206 ^ 9207 ^ 9208 9209 ; ********************************************************************** 9210 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9211 ; ********************************************************************** 9212 9213 PDIVF (D,255555555555,FIVE,FIVE,FIVE,311111111111,ONE,335056427213,035475265746,1 9214 44375704605,004166365327)^ 9215 9216 ; --- DIVIDEND == (255555555555,FIVE,FIVE,FIVE) 9217 ; --- DIVISOR === (311111111111,ONE) 9218 ; --- QUOTIENT == (335056427213,035475265746) 9219 ; --- REMAINDER = (144375704605,004166365327) 9220 9221 ..0650: MOVE AC1,[[EXP 255555555555,FIVE,FIVE,FIVE,311111111111,ONE,335056427213,0354752 9222 037307 200 01 0 00 044731 65746,144375704605,004166365327],,PDEND] 9223 037310 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9224 037311 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9225 ERROR (..0650,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9226 037312 036 14 0 00 044641 9227 037313 255 00 0 00 000000 9228 ^ 9229 9230 037314 200 14 0 00 040521 ..0651: MOVE SCR2,PFLOC ;GET PC 9231 037315 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9232 ERROR (..0650,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9233 LL 9234 037316 036 13 0 00 044653 9235 037317 255 00 0 00 000000 9236 ^ 9237 ^ 9238 9239 ; ********************************************************************** DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 28-3 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST D SEQ 0210 9240 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9241 ; ********************************************************************** 9242 9243 PDIVF (D,255555555555,TWO,FIVE,TWO,311111111111,666666666666,335056427212,3234437 9244 57047,240023257716,107503314730)^ 9245 9246 ; --- DIVIDEND == (255555555555,TWO,FIVE,TWO) 9247 ; --- DIVISOR === (311111111111,666666666666) 9248 ; --- QUOTIENT == (335056427212,323443757047) 9249 ; --- REMAINDER = (240023257716,107503314730) 9250 9251 ..0652: MOVE AC1,[[EXP 255555555555,TWO,FIVE,TWO,311111111111,666666666666,335056427212, 9252 037320 200 01 0 00 044744 323443757047,240023257716,107503314730],,PDEND] 9253 037321 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9254 037322 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9255 ERROR (..0652,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9256 037323 036 14 0 00 044641 9257 037324 255 00 0 00 000000 9258 ^ 9259 9260 037325 200 14 0 00 040521 ..0653: MOVE SCR2,PFLOC ;GET PC 9261 037326 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9262 ERROR (..0652,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9263 LL 9264 037327 036 13 0 00 044653 9265 037330 255 00 0 00 000000 9266 ^ 9267 ^ 9268 9269 ; ********************************************************************** 9270 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9271 ; ********************************************************************** 9272 9273 123456 123456 K=123456123456 9274 PDIVF (D,K,K,K,K,234567234567,234567234567,210420323476,136703233600,055256055256 9275 ,055256055256)^ 9276 9277 ; --- DIVIDEND == (K,K,K,K) 9278 ; --- DIVISOR === (234567234567,234567234567) 9279 ; --- QUOTIENT == (210420323476,136703233600) 9280 ; --- REMAINDER = (055256055256,055256055256) 9281 9282 ..0654: MOVE AC1,[[EXP K,K,K,K,234567234567,234567234567,210420323476,136703233600,05525 9283 037331 200 01 0 00 044757 6055256,055256055256],,PDEND] 9284 037332 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9285 037333 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9286 ERROR (..0654,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9287 037334 036 14 0 00 044641 9288 037335 255 00 0 00 000000 9289 ^ 9290 9291 037336 200 14 0 00 040521 ..0655: MOVE SCR2,PFLOC ;GET PC 9292 037337 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9293 ERROR (..0654,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9294 LL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 28-4 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST D SEQ 0211 9295 037340 036 13 0 00 044653 9296 037341 255 00 0 00 000000 9297 ^ 9298 ^ 9299 9300 ; ********************************************************************** 9301 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9302 ; ********************************************************************** 9303 9304 PDIVF (D,FOUR,FOUR,FOUR,FOUR,THREE,333333333334,1B0,400000000001,511111111110,511 9305 111111110)^ 9306 9307 ; --- DIVIDEND == (FOUR,FOUR,FOUR,FOUR) 9308 ; --- DIVISOR === (THREE,333333333334) 9309 ; --- QUOTIENT == (1B0,400000000001) 9310 ; --- REMAINDER = (511111111110,511111111110) 9311 9312 ..0656: MOVE AC1,[[EXP FOUR,FOUR,FOUR,FOUR,THREE,333333333334,1B0,400000000001,511111111 9313 037342 200 01 0 00 044772 110,511111111110],,PDEND] 9314 037343 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9315 037344 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9316 ERROR (..0656,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9317 037345 036 14 0 00 044641 9318 037346 255 00 0 00 000000 9319 ^ 9320 9321 037347 200 14 0 00 040521 ..0657: MOVE SCR2,PFLOC ;GET PC 9322 037350 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9323 ERROR (..0656,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9324 LL 9325 037351 036 13 0 00 044653 9326 037352 255 00 0 00 000000 9327 ^ 9328 ^ 9329 9330 ; ********************************************************************** 9331 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9332 ; ********************************************************************** 9333 9334 PDIVF (D,FIVE,FIVE,FIVE,FIVE,FOUR,FOUR,252525252525,125252525252,606060606060,460 9335 606060605)^ 9336 9337 ; --- DIVIDEND == (FIVE,FIVE,FIVE,FIVE) 9338 ; --- DIVISOR === (FOUR,FOUR) 9339 ; --- QUOTIENT == (252525252525,125252525252) 9340 ; --- REMAINDER = (606060606060,460606060605) 9341 9342 ..0660: MOVE AC1,[[EXP FIVE,FIVE,FIVE,FIVE,FOUR,FOUR,252525252525,125252525252,606060606 9343 037353 200 01 0 00 045005 060,460606060605],,PDEND] 9344 037354 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9345 037355 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9346 ERROR (..0660,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9347 037356 036 14 0 00 044641 9348 037357 255 00 0 00 000000 9349 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 28-5 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST D SEQ 0212 9350 9351 037360 200 14 0 00 040521 ..0661: MOVE SCR2,PFLOC ;GET PC 9352 037361 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9353 ERROR (..0660,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9354 LL 9355 037362 036 13 0 00 044653 9356 037363 255 00 0 00 000000 9357 ^ 9358 ^ 9359 9360 ; ********************************************************************** 9361 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9362 ; ********************************************************************** 9363 9364 PDIVF (D,FOUR,FIVE,FOUR,FIVE,432123456765,432123456765,364320315052,247020761620, 9365 473571652245,600514541235)^ 9366 9367 ; --- DIVIDEND == (FOUR,FIVE,FOUR,FIVE) 9368 ; --- DIVISOR === (432123456765,432123456765) 9369 ; --- QUOTIENT == (364320315052,247020761620) 9370 ; --- REMAINDER = (473571652245,600514541235) 9371 9372 ..0662: MOVE AC1,[[EXP FOUR,FIVE,FOUR,FIVE,432123456765,432123456765,364320315052,247020 9373 037364 200 01 0 00 045020 761620,473571652245,600514541235],,PDEND] 9374 037365 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9375 037366 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9376 ERROR (..0662,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9377 037367 036 14 0 00 044641 9378 037370 255 00 0 00 000000 9379 ^ 9380 9381 037371 200 14 0 00 040521 ..0663: MOVE SCR2,PFLOC ;GET PC 9382 037372 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9383 ERROR (..0662,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9384 LL 9385 037373 036 13 0 00 044653 9386 037374 255 00 0 00 000000 9387 ^ 9388 ^ 9389 9390 ; ********************************************************************** 9391 ; ---------- DDIV - TEST D (MISCELLANEOUS CASES) ---------- 9392 ; ********************************************************************** 9393 9394 PDIVF (D,FIVE,TWO,FIVE,TWO,543210123456,543210123456,356736272460,271326656374,76 9395 3153710465,406655405512)^ 9396 9397 ; --- DIVIDEND == (FIVE,TWO,FIVE,TWO) 9398 ; --- DIVISOR === (543210123456,543210123456) 9399 ; --- QUOTIENT == (356736272460,271326656374) 9400 ; --- REMAINDER = (763153710465,406655405512) 9401 9402 ..0664: MOVE AC1,[[EXP FIVE,TWO,FIVE,TWO,543210123456,543210123456,356736272460,27132665 9403 037375 200 01 0 00 045033 6374,763153710465,406655405512],,PDEND] 9404 037376 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 28-6 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST D SEQ 0213 9405 037377 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9406 ERROR (..0664,14,SCR1,SCR2,,TEST D - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9407 037400 036 14 0 00 044641 9408 037401 255 00 0 00 000000 9409 ^ 9410 9411 037402 200 14 0 00 040521 ..0665: MOVE SCR2,PFLOC ;GET PC 9412 037403 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9413 ERROR (..0664,13,SCR2,PFLOC,,TEST D - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9414 LL 9415 037404 036 13 0 00 044653 9416 037405 255 00 0 00 000000 9417 ^ 9418 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 29 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST E SEQ 0214 9419 SUBTTL DDIV - TEST E 9420 9421 ; ********************************************************************** 9422 ;*DDIV - TEST E 9423 ;* 9424 ;* -4/-2 -4/2 4/-2 4/2 9425 ;* (-3,0,0,0)/(-6,0) (-3,0,0,0)/(6,0) 3/-6 3/6 9426 ;* 9427 ;* THESE TESTS VERIFY THAT THE DDIV HANDLES THE SIGN OF ITS 9428 ;* OPERANDS PROPERLY. THE SIGN BITS OF THE LOW ORDER WORDS ARE 9429 ;* INITIALLY DIFFERENT FROM THE HIGH ORDER WORD. THE SIGN SHOULD 9430 ;* BE FORMED CORRECTLY IN SPITE OF THAT. 9431 ; ********************************************************************** 9432 9433 ; ********************************************************************** 9434 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9435 ; ********************************************************************** 9436 9437 PDIVF (E,-1,377777777777,377777777777,377777777774,-1,377777777776,0,2)^ 9438 9439 ; --- DIVIDEND == (-1,377777777777,377777777777,377777777774) 9440 ; --- DIVISOR === (-1,377777777776) 9441 ; --- QUOTIENT == (0,2) 9442 ; --- REMAINDER = (0,0) 9443 9444 ..0666: MOVE AC1,[[EXP -1,377777777777,377777777777,377777777774,-1,377777777776,0,2,0,0 9445 037406 200 01 0 00 045046 ],,PDEND] 9446 037407 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9447 037410 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9448 ERROR (..0666,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9449 037411 036 14 0 00 045056 9450 037412 255 00 0 00 000000 9451 ^ 9452 9453 037413 200 14 0 00 040521 ..0667: MOVE SCR2,PFLOC ;GET PC 9454 037414 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9455 ERROR (..0666,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9456 LL 9457 037415 036 13 0 00 045070 9458 037416 255 00 0 00 000000 9459 ^ 9460 ^ 9461 9462 ; ********************************************************************** 9463 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9464 ; ********************************************************************** 9465 9466 PDIVF (E,-1,377777777777,377777777777,-4,-1,-2,0,2)^ 9467 9468 ; --- DIVIDEND == (-1,377777777777,377777777777,-4) 9469 ; --- DIVISOR === (-1,-2) 9470 ; --- QUOTIENT == (0,2) 9471 ; --- REMAINDER = (0,0) 9472 9473 037417 200 01 0 00 045105 ..0670: MOVE AC1,[[EXP -1,377777777777,377777777777,-4,-1,-2,0,2,0,0],,PDEND] DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 29-1 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST E SEQ 0215 9474 037420 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9475 037421 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9476 ERROR (..0670,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9477 037422 036 14 0 00 045056 9478 037423 255 00 0 00 000000 9479 ^ 9480 9481 037424 200 14 0 00 040521 ..0671: MOVE SCR2,PFLOC ;GET PC 9482 037425 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9483 ERROR (..0670,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9484 LL 9485 037426 036 13 0 00 045070 9486 037427 255 00 0 00 000000 9487 ^ 9488 ^ 9489 9490 ; ********************************************************************** 9491 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9492 ; ********************************************************************** 9493 9494 PDIVF (E,-1,377777777777,377777777777,377777777774,0,400000000002,-1,-2)^ 9495 9496 ; --- DIVIDEND == (-1,377777777777,377777777777,377777777774) 9497 ; --- DIVISOR === (0,400000000002) 9498 ; --- QUOTIENT == (-1,-2) 9499 ; --- REMAINDER = (0,0) 9500 9501 ..0672: MOVE AC1,[[EXP -1,377777777777,377777777777,377777777774,0,400000000002,-1,-2,0, 9502 037430 200 01 0 00 045120 0],,PDEND] 9503 037431 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9504 037432 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9505 ERROR (..0672,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9506 037433 036 14 0 00 045056 9507 037434 255 00 0 00 000000 9508 ^ 9509 9510 037435 200 14 0 00 040521 ..0673: MOVE SCR2,PFLOC ;GET PC 9511 037436 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9512 ERROR (..0672,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9513 LL 9514 037437 036 13 0 00 045070 9515 037440 255 00 0 00 000000 9516 ^ 9517 ^ 9518 9519 ; ********************************************************************** 9520 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9521 ; ********************************************************************** 9522 9523 PDIVF (E,-1,-1,-1,-4,0,400000000002,-1,-2)^ 9524 9525 ; --- DIVIDEND == (-1,-1,-1,-4) 9526 ; --- DIVISOR === (0,400000000002) 9527 ; --- QUOTIENT == (-1,-2) 9528 ; --- REMAINDER = (0,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 29-2 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST E SEQ 0216 9529 9530 037441 200 01 0 00 045133 ..0674: MOVE AC1,[[EXP -1,-1,-1,-4,0,400000000002,-1,-2,0,0],,PDEND] 9531 037442 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9532 037443 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9533 ERROR (..0674,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9534 037444 036 14 0 00 045056 9535 037445 255 00 0 00 000000 9536 ^ 9537 9538 037446 200 14 0 00 040521 ..0675: MOVE SCR2,PFLOC ;GET PC 9539 037447 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9540 ERROR (..0674,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9541 LL 9542 037450 036 13 0 00 045070 9543 037451 255 00 0 00 000000 9544 ^ 9545 ^ 9546 9547 ; ********************************************************************** 9548 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9549 ; ********************************************************************** 9550 9551 PDIVF (E,0,1B0,1B0,400000000004,-1,377777777776,-1,-2)^ 9552 9553 ; --- DIVIDEND == (0,1B0,1B0,400000000004) 9554 ; --- DIVISOR === (-1,377777777776) 9555 ; --- QUOTIENT == (-1,-2) 9556 ; --- REMAINDER = (0,0) 9557 9558 037452 200 01 0 00 045146 ..0676: MOVE AC1,[[EXP 0,1B0,1B0,400000000004,-1,377777777776,-1,-2,0,0],,PDEND] 9559 037453 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9560 037454 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9561 ERROR (..0676,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9562 037455 036 14 0 00 045056 9563 037456 255 00 0 00 000000 9564 ^ 9565 9566 037457 200 14 0 00 040521 ..0677: MOVE SCR2,PFLOC ;GET PC 9567 037460 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9568 ERROR (..0676,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9569 LL 9570 037461 036 13 0 00 045070 9571 037462 255 00 0 00 000000 9572 ^ 9573 ^ 9574 9575 ; ********************************************************************** 9576 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9577 ; ********************************************************************** 9578 9579 PDIVF (E,0,1B0,1B0,400000000004,-1,-2,-1,-2)^ 9580 9581 ; --- DIVIDEND == (0,1B0,1B0,400000000004) 9582 ; --- DIVISOR === (-1,-2) 9583 ; --- QUOTIENT == (-1,-2) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 29-3 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST E SEQ 0217 9584 ; --- REMAINDER = (0,0) 9585 9586 037463 200 01 0 00 045161 ..0700: MOVE AC1,[[EXP 0,1B0,1B0,400000000004,-1,-2,-1,-2,0,0],,PDEND] 9587 037464 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9588 037465 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9589 ERROR (..0700,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9590 037466 036 14 0 00 045056 9591 037467 255 00 0 00 000000 9592 ^ 9593 9594 037470 200 14 0 00 040521 ..0701: MOVE SCR2,PFLOC ;GET PC 9595 037471 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9596 ERROR (..0700,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9597 LL 9598 037472 036 13 0 00 045070 9599 037473 255 00 0 00 000000 9600 ^ 9601 ^ 9602 9603 ; ********************************************************************** 9604 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9605 ; ********************************************************************** 9606 9607 PDIVF (E,0,0,0,400000000004,0,2,0,2)^ 9608 9609 ; --- DIVIDEND == (0,0,0,400000000004) 9610 ; --- DIVISOR === (0,2) 9611 ; --- QUOTIENT == (0,2) 9612 ; --- REMAINDER = (0,0) 9613 9614 037474 200 01 0 00 045174 ..0702: MOVE AC1,[[EXP 0,0,0,400000000004,0,2,0,2,0,0],,PDEND] 9615 037475 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9616 037476 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9617 ERROR (..0702,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9618 037477 036 14 0 00 045056 9619 037500 255 00 0 00 000000 9620 ^ 9621 9622 037501 200 14 0 00 040521 ..0703: MOVE SCR2,PFLOC ;GET PC 9623 037502 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9624 ERROR (..0702,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9625 LL 9626 037503 036 13 0 00 045070 9627 037504 255 00 0 00 000000 9628 ^ 9629 ^ 9630 9631 ; ********************************************************************** 9632 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9633 ; ********************************************************************** 9634 9635 PDIVF (E,0,0,0,400000000004,0,400000000002,0,2)^ 9636 9637 ; --- DIVIDEND == (0,0,0,400000000004) 9638 ; --- DIVISOR === (0,400000000002) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 29-4 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST E SEQ 0218 9639 ; --- QUOTIENT == (0,2) 9640 ; --- REMAINDER = (0,0) 9641 9642 037505 200 01 0 00 045207 ..0704: MOVE AC1,[[EXP 0,0,0,400000000004,0,400000000002,0,2,0,0],,PDEND] 9643 037506 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9644 037507 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9645 ERROR (..0704,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9646 037510 036 14 0 00 045056 9647 037511 255 00 0 00 000000 9648 ^ 9649 9650 037512 200 14 0 00 040521 ..0705: MOVE SCR2,PFLOC ;GET PC 9651 037513 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9652 ERROR (..0704,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9653 LL 9654 037514 036 13 0 00 045070 9655 037515 255 00 0 00 000000 9656 ^ 9657 ^ 9658 9659 ; ********************************************************************** 9660 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9661 ; ********************************************************************** 9662 9663 PDIVF (E,-3,1B0,1B0,1B0,-6,1B0,200000000000,0)^ 9664 9665 ; --- DIVIDEND == (-3,1B0,1B0,1B0) 9666 ; --- DIVISOR === (-6,1B0) 9667 ; --- QUOTIENT == (200000000000,0) 9668 ; --- REMAINDER = (0,0) 9669 9670 037516 200 01 0 00 045222 ..0706: MOVE AC1,[[EXP -3,1B0,1B0,1B0,-6,1B0,200000000000,0,0,0],,PDEND] 9671 037517 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9672 037520 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9673 ERROR (..0706,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9674 037521 036 14 0 00 045056 9675 037522 255 00 0 00 000000 9676 ^ 9677 9678 037523 200 14 0 00 040521 ..0707: MOVE SCR2,PFLOC ;GET PC 9679 037524 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9680 ERROR (..0706,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9681 LL 9682 037525 036 13 0 00 045070 9683 037526 255 00 0 00 000000 9684 ^ 9685 ^ 9686 9687 ; ********************************************************************** 9688 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9689 ; ********************************************************************** 9690 9691 PDIVF (E,-3,1B0,1B0,0,-6,1B0,200000000000,0)^ 9692 9693 ; --- DIVIDEND == (-3,1B0,1B0,0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 29-5 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST E SEQ 0219 9694 ; --- DIVISOR === (-6,1B0) 9695 ; --- QUOTIENT == (200000000000,0) 9696 ; --- REMAINDER = (0,0) 9697 9698 037527 200 01 0 00 045235 ..0710: MOVE AC1,[[EXP -3,1B0,1B0,0,-6,1B0,200000000000,0,0,0],,PDEND] 9699 037530 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9700 037531 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9701 ERROR (..0710,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9702 037532 036 14 0 00 045056 9703 037533 255 00 0 00 000000 9704 ^ 9705 9706 037534 200 14 0 00 040521 ..0711: MOVE SCR2,PFLOC ;GET PC 9707 037535 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9708 ERROR (..0710,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9709 LL 9710 037536 036 13 0 00 045070 9711 037537 255 00 0 00 000000 9712 ^ 9713 ^ 9714 9715 ; ********************************************************************** 9716 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9717 ; ********************************************************************** 9718 9719 PDIVF (E,-3,1B0,0,0,6,0,600000000000,1B0)^ 9720 9721 ; --- DIVIDEND == (-3,1B0,0,0) 9722 ; --- DIVISOR === (6,0) 9723 ; --- QUOTIENT == (600000000000,1B0) 9724 ; --- REMAINDER = (0,0) 9725 9726 037540 200 01 0 00 045250 ..0712: MOVE AC1,[[EXP -3,1B0,0,0,6,0,600000000000,1B0,0,0],,PDEND] 9727 037541 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9728 037542 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9729 ERROR (..0712,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9730 037543 036 14 0 00 045056 9731 037544 255 00 0 00 000000 9732 ^ 9733 9734 037545 200 14 0 00 040521 ..0713: MOVE SCR2,PFLOC ;GET PC 9735 037546 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9736 ERROR (..0712,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9737 LL 9738 037547 036 13 0 00 045070 9739 037550 255 00 0 00 000000 9740 ^ 9741 ^ 9742 9743 ; ********************************************************************** 9744 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9745 ; ********************************************************************** 9746 9747 PDIVF (E,-3,0,0,0,6,1B0,600000000000,1B0)^ 9748 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 29-6 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST E SEQ 0220 9749 ; --- DIVIDEND == (-3,0,0,0) 9750 ; --- DIVISOR === (6,1B0) 9751 ; --- QUOTIENT == (600000000000,1B0) 9752 ; --- REMAINDER = (0,0) 9753 9754 037551 200 01 0 00 045263 ..0714: MOVE AC1,[[EXP -3,0,0,0,6,1B0,600000000000,1B0,0,0],,PDEND] 9755 037552 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9756 037553 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9757 ERROR (..0714,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9758 037554 036 14 0 00 045056 9759 037555 255 00 0 00 000000 9760 ^ 9761 9762 037556 200 14 0 00 040521 ..0715: MOVE SCR2,PFLOC ;GET PC 9763 037557 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9764 ERROR (..0714,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9765 LL 9766 037560 036 13 0 00 045070 9767 037561 255 00 0 00 000000 9768 ^ 9769 ^ 9770 9771 ; ********************************************************************** 9772 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9773 ; ********************************************************************** 9774 9775 PDIVF (E,3,1B0,1B0,0,-6,1B0,600000000000,1B0)^ 9776 9777 ; --- DIVIDEND == (3,1B0,1B0,0) 9778 ; --- DIVISOR === (-6,1B0) 9779 ; --- QUOTIENT == (600000000000,1B0) 9780 ; --- REMAINDER = (0,0) 9781 9782 037562 200 01 0 00 045276 ..0716: MOVE AC1,[[EXP 3,1B0,1B0,0,-6,1B0,600000000000,1B0,0,0],,PDEND] 9783 037563 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9784 037564 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9785 ERROR (..0716,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9786 037565 036 14 0 00 045056 9787 037566 255 00 0 00 000000 9788 ^ 9789 9790 037567 200 14 0 00 040521 ..0717: MOVE SCR2,PFLOC ;GET PC 9791 037570 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9792 ERROR (..0716,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9793 LL 9794 037571 036 13 0 00 045070 9795 037572 255 00 0 00 000000 9796 ^ 9797 ^ 9798 9799 ; ********************************************************************** 9800 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9801 ; ********************************************************************** 9802 9803 PDIVF (E,3,1B0,0,1B0,-6,1B0,600000000000,1B0)^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 29-7 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST E SEQ 0221 9804 9805 ; --- DIVIDEND == (3,1B0,0,1B0) 9806 ; --- DIVISOR === (-6,1B0) 9807 ; --- QUOTIENT == (600000000000,1B0) 9808 ; --- REMAINDER = (0,0) 9809 9810 037573 200 01 0 00 045311 ..0720: MOVE AC1,[[EXP 3,1B0,0,1B0,-6,1B0,600000000000,1B0,0,0],,PDEND] 9811 037574 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9812 037575 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9813 ERROR (..0720,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9814 037576 036 14 0 00 045056 9815 037577 255 00 0 00 000000 9816 ^ 9817 9818 037600 200 14 0 00 040521 ..0721: MOVE SCR2,PFLOC ;GET PC 9819 037601 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9820 ERROR (..0720,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9821 LL 9822 037602 036 13 0 00 045070 9823 037603 255 00 0 00 000000 9824 ^ 9825 ^ 9826 9827 ; ********************************************************************** 9828 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9829 ; ********************************************************************** 9830 9831 PDIVF (E,3,0,1B0,1B0,6,1B0,200000000000,0)^ 9832 9833 ; --- DIVIDEND == (3,0,1B0,1B0) 9834 ; --- DIVISOR === (6,1B0) 9835 ; --- QUOTIENT == (200000000000,0) 9836 ; --- REMAINDER = (0,0) 9837 9838 037604 200 01 0 00 045324 ..0722: MOVE AC1,[[EXP 3,0,1B0,1B0,6,1B0,200000000000,0,0,0],,PDEND] 9839 037605 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9840 037606 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9841 ERROR (..0722,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9842 037607 036 14 0 00 045056 9843 037610 255 00 0 00 000000 9844 ^ 9845 9846 037611 200 14 0 00 040521 ..0723: MOVE SCR2,PFLOC ;GET PC 9847 037612 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9848 ERROR (..0722,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9849 LL 9850 037613 036 13 0 00 045070 9851 037614 255 00 0 00 000000 9852 ^ 9853 ^ 9854 9855 ; ********************************************************************** 9856 ; ---------- DDIV - TEST E (INCONSISTENT SIGNS IN OPERANDS) ---------- 9857 ; ********************************************************************** 9858 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 29-8 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST E SEQ 0222 9859 PDIVF (E,3,1B0,1B0,1B0,6,0,200000000000,0)^ 9860 9861 ; --- DIVIDEND == (3,1B0,1B0,1B0) 9862 ; --- DIVISOR === (6,0) 9863 ; --- QUOTIENT == (200000000000,0) 9864 ; --- REMAINDER = (0,0) 9865 9866 037615 200 01 0 00 045337 ..0724: MOVE AC1,[[EXP 3,1B0,1B0,1B0,6,0,200000000000,0,0,0],,PDEND] 9867 037616 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9868 037617 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9869 ERROR (..0724,14,SCR1,SCR2,,TEST E - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9870 037620 036 14 0 00 045056 9871 037621 255 00 0 00 000000 9872 ^ 9873 9874 037622 200 14 0 00 040521 ..0725: MOVE SCR2,PFLOC ;GET PC 9875 037623 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9876 ERROR (..0724,13,SCR2,PFLOC,,TEST E - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9877 LL 9878 037624 036 13 0 00 045070 9879 037625 255 00 0 00 000000 9880 ^ 9881 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 30 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST F SEQ 0223 9882 SUBTTL DDIV - TEST F 9883 9884 ; ********************************************************************** 9885 ;*DDIV - TEST F 9886 ;* 9887 ;* 1,0,0,0 -1,0,0,0 0,-1,-1,-1 -1,0,0,1 9888 ;* ------- -------- ---------- -------- 9889 ;* 1,1 1,1 1,0 1,0 9890 ;* 9891 ;* 1,0,0,0 -1,0,0,0 0,-1,-1,-1 -1,0,0,1 9892 ;* ------- -------- ---------- -------- 9893 ;* -2,-1 -2,-1 -1,0 -1,0 9894 ;* 9895 ;* THESE TESTS VERIFY THAT THE DDIV WILL NOT GENERATE AN 9896 ;* OVERFLOW AND NO DIVIDE CONDITION WHEN THE DIVISOR IS 9897 ;* JUST LARGE ENOUGH TO NOT CAUSE ONE. 9898 ; ********************************************************************** 9899 9900 ; ********************************************************************** 9901 ; ---------- DDIV - TEST F (NOT QUITE OVERFLOW CONDITIONS) ---------- 9902 ; ********************************************************************** 9903 9904 PDIVF (F,1,0,0,0,1,1,377777777777,0,1,0)^ 9905 9906 ; --- DIVIDEND == (1,0,0,0) 9907 ; --- DIVISOR === (1,1) 9908 ; --- QUOTIENT == (377777777777,0) 9909 ; --- REMAINDER = (1,0) 9910 9911 037626 200 01 0 00 045352 ..0726: MOVE AC1,[[EXP 1,0,0,0,1,1,377777777777,0,1,0],,PDEND] 9912 037627 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9913 037630 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9914 ERROR (..0726,14,SCR1,SCR2,,TEST F - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9915 037631 036 14 0 00 045362 9916 037632 255 00 0 00 000000 9917 ^ 9918 9919 037633 200 14 0 00 040521 ..0727: MOVE SCR2,PFLOC ;GET PC 9920 037634 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9921 ERROR (..0726,13,SCR2,PFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9922 LL 9923 037635 036 13 0 00 045374 9924 037636 255 00 0 00 000000 9925 ^ 9926 ^ 9927 9928 ; ********************************************************************** 9929 ; ---------- DDIV - TEST F (NOT QUITE OVERFLOW CONDITIONS) ---------- 9930 ; ********************************************************************** 9931 9932 PDIVF (F,1,0,0,0,-2,-1,400000000001,1B0,1,0)^ 9933 9934 ; --- DIVIDEND == (1,0,0,0) 9935 ; --- DIVISOR === (-2,-1) 9936 ; --- QUOTIENT == (400000000001,1B0) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 30-1 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST F SEQ 0224 9937 ; --- REMAINDER = (1,0) 9938 9939 037637 200 01 0 00 045411 ..0730: MOVE AC1,[[EXP 1,0,0,0,-2,-1,400000000001,1B0,1,0],,PDEND] 9940 037640 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9941 037641 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9942 ERROR (..0730,14,SCR1,SCR2,,TEST F - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9943 037642 036 14 0 00 045362 9944 037643 255 00 0 00 000000 9945 ^ 9946 9947 037644 200 14 0 00 040521 ..0731: MOVE SCR2,PFLOC ;GET PC 9948 037645 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9949 ERROR (..0730,13,SCR2,PFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9950 LL 9951 037646 036 13 0 00 045374 9952 037647 255 00 0 00 000000 9953 ^ 9954 ^ 9955 9956 ; ********************************************************************** 9957 ; ---------- DDIV - TEST F (NOT QUITE OVERFLOW CONDITIONS) ---------- 9958 ; ********************************************************************** 9959 9960 PDIVF (F,-1,1B0,1B0,1B0,1,1,400000000001,1B0,-1,1B0)^ 9961 9962 ; --- DIVIDEND == (-1,1B0,1B0,1B0) 9963 ; --- DIVISOR === (1,1) 9964 ; --- QUOTIENT == (400000000001,1B0) 9965 ; --- REMAINDER = (-1,1B0) 9966 9967 037650 200 01 0 00 045424 ..0732: MOVE AC1,[[EXP -1,1B0,1B0,1B0,1,1,400000000001,1B0,-1,1B0],,PDEND] 9968 037651 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9969 037652 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9970 ERROR (..0732,14,SCR1,SCR2,,TEST F - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9971 037653 036 14 0 00 045362 9972 037654 255 00 0 00 000000 9973 ^ 9974 9975 037655 200 14 0 00 040521 ..0733: MOVE SCR2,PFLOC ;GET PC 9976 037656 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 9977 ERROR (..0732,13,SCR2,PFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 9978 LL 9979 037657 036 13 0 00 045374 9980 037660 255 00 0 00 000000 9981 ^ 9982 ^ 9983 9984 ; ********************************************************************** 9985 ; ---------- DDIV - TEST F (NOT QUITE OVERFLOW CONDITIONS) ---------- 9986 ; ********************************************************************** 9987 9988 PDIVF (F,-1,1B0,1B0,1B0,-2,-1,377777777777,0,-1,1B0)^ 9989 9990 ; --- DIVIDEND == (-1,1B0,1B0,1B0) 9991 ; --- DIVISOR === (-2,-1) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 30-2 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST F SEQ 0225 9992 ; --- QUOTIENT == (377777777777,0) 9993 ; --- REMAINDER = (-1,1B0) 9994 9995 037661 200 01 0 00 045437 ..0734: MOVE AC1,[[EXP -1,1B0,1B0,1B0,-2,-1,377777777777,0,-1,1B0],,PDEND] 9996 037662 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 9997 037663 260 17 0 00 040513 GO PSUBR ;GO DO TEST 9998 ERROR (..0734,14,SCR1,SCR2,,TEST F - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 9999 037664 036 14 0 00 045362 10000 037665 255 00 0 00 000000 10001 ^ 10002 10003 037666 200 14 0 00 040521 ..0735: MOVE SCR2,PFLOC ;GET PC 10004 037667 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 10005 ERROR (..0734,13,SCR2,PFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 10006 LL 10007 037670 036 13 0 00 045374 10008 037671 255 00 0 00 000000 10009 ^ 10010 ^ 10011 10012 ; ********************************************************************** 10013 ; ---------- DDIV - TEST F (NOT QUITE OVERFLOW CONDITIONS) ---------- 10014 ; ********************************************************************** 10015 10016 PDIVF (F,0,377777777777,377777777777,377777777777,1,0,377777777777,377777777777,0 10017 ,377777777777)^ 10018 10019 ; --- DIVIDEND == (0,377777777777,377777777777,377777777777) 10020 ; --- DIVISOR === (1,0) 10021 ; --- QUOTIENT == (377777777777,377777777777) 10022 ; --- REMAINDER = (0,377777777777) 10023 10024 ..0736: MOVE AC1,[[EXP 0,377777777777,377777777777,377777777777,1,0,377777777777,3777777 10025 037672 200 01 0 00 045452 77777,0,377777777777],,PDEND] 10026 037673 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 10027 037674 260 17 0 00 040513 GO PSUBR ;GO DO TEST 10028 ERROR (..0736,14,SCR1,SCR2,,TEST F - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 10029 037675 036 14 0 00 045362 10030 037676 255 00 0 00 000000 10031 ^ 10032 10033 037677 200 14 0 00 040521 ..0737: MOVE SCR2,PFLOC ;GET PC 10034 037700 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 10035 ERROR (..0736,13,SCR2,PFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 10036 LL 10037 037701 036 13 0 00 045374 10038 037702 255 00 0 00 000000 10039 ^ 10040 ^ 10041 10042 ; ********************************************************************** 10043 ; ---------- DDIV - TEST F (NOT QUITE OVERFLOW CONDITIONS) ---------- 10044 ; ********************************************************************** 10045 10046 PDIVF (F,0,377777777777,377777777777,377777777777,-1,1B0,1B0,400000000001,0,37777 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 30-3 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST F SEQ 0226 10047 7777777)^ 10048 10049 ; --- DIVIDEND == (0,377777777777,377777777777,377777777777) 10050 ; --- DIVISOR === (-1,1B0) 10051 ; --- QUOTIENT == (1B0,400000000001) 10052 ; --- REMAINDER = (0,377777777777) 10053 10054 ..0740: MOVE AC1,[[EXP 0,377777777777,377777777777,377777777777,-1,1B0,1B0,400000000001, 10055 037703 200 01 0 00 045465 0,377777777777],,PDEND] 10056 037704 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 10057 037705 260 17 0 00 040513 GO PSUBR ;GO DO TEST 10058 ERROR (..0740,14,SCR1,SCR2,,TEST F - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 10059 037706 036 14 0 00 045362 10060 037707 255 00 0 00 000000 10061 ^ 10062 10063 037710 200 14 0 00 040521 ..0741: MOVE SCR2,PFLOC ;GET PC 10064 037711 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 10065 ERROR (..0740,13,SCR2,PFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 10066 LL 10067 037712 036 13 0 00 045374 10068 037713 255 00 0 00 000000 10069 ^ 10070 ^ 10071 10072 ; ********************************************************************** 10073 ; ---------- DDIV - TEST F (NOT QUITE OVERFLOW CONDITIONS) ---------- 10074 ; ********************************************************************** 10075 10076 PDIVF (F,-1,1B0,1B0,400000000001,1,0,1B0,400000000001,-1,400000000001)^ 10077 10078 ; --- DIVIDEND == (-1,1B0,1B0,400000000001) 10079 ; --- DIVISOR === (1,0) 10080 ; --- QUOTIENT == (1B0,400000000001) 10081 ; --- REMAINDER = (-1,400000000001) 10082 10083 ..0742: MOVE AC1,[[EXP -1,1B0,1B0,400000000001,1,0,1B0,400000000001,-1,400000000001],,PD 10084 037714 200 01 0 00 045500 END] 10085 037715 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 10086 037716 260 17 0 00 040513 GO PSUBR ;GO DO TEST 10087 ERROR (..0742,14,SCR1,SCR2,,TEST F - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 10088 037717 036 14 0 00 045362 10089 037720 255 00 0 00 000000 10090 ^ 10091 10092 037721 200 14 0 00 040521 ..0743: MOVE SCR2,PFLOC ;GET PC 10093 037722 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 10094 ERROR (..0742,13,SCR2,PFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 10095 LL 10096 037723 036 13 0 00 045374 10097 037724 255 00 0 00 000000 10098 ^ 10099 ^ 10100 10101 ; ********************************************************************** DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 30-4 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST F SEQ 0227 10102 ; ---------- DDIV - TEST F (NOT QUITE OVERFLOW CONDITIONS) ---------- 10103 ; ********************************************************************** 10104 10105 PDIVF (F,-1,1B0,1B0,400000000001,-1,1B0,377777777777,377777777777,-1,400000000001 10106 )^ 10107 10108 ; --- DIVIDEND == (-1,1B0,1B0,400000000001) 10109 ; --- DIVISOR === (-1,1B0) 10110 ; --- QUOTIENT == (377777777777,377777777777) 10111 ; --- REMAINDER = (-1,400000000001) 10112 10113 ..0744: MOVE AC1,[[EXP -1,1B0,1B0,400000000001,-1,1B0,377777777777,377777777777,-1,40000 10114 037725 200 01 0 00 045513 0000001],,PDEND] 10115 037726 251 01 0 00 040555 BLT AC1,PRES+3 ;SET UP OPERANDS 10116 037727 260 17 0 00 040513 GO PSUBR ;GO DO TEST 10117 ERROR (..0744,14,SCR1,SCR2,,TEST F - QUOTIENT/REMAINDER INCORRECT,DPRINT)^SALL 10118 037730 036 14 0 00 045362 10119 037731 255 00 0 00 000000 10120 ^ 10121 10122 037732 200 14 0 00 040521 ..0745: MOVE SCR2,PFLOC ;GET PC 10123 037733 623 14 0 00 400040 TLZE SCR2,AROV+DCK ;CALC OK PC (NO - OV/DIV) & TEST 10124 ERROR (..0744,13,SCR2,PFLOC,,TEST F - PC FLAGS INCORRECT - BITS 0 & 12,DPRINT)^SA 10125 LL 10126 037734 036 13 0 00 045374 10127 037735 255 00 0 00 000000 10128 ^ 10129 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 31 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0228 10130 SUBTTL DDIV - TEST G 10131 10132 ; ********************************************************************** 10133 ;*DDIV - TEST G 10134 ;* 10135 ;* 1 1,0 1,0,0 1,0,0,0 -1 10136 ;* - --- ----- ------- - 10137 ;* 0 0 0 0 0 10138 ;* 10139 ;* 1,0,0 1,0,0 1,0,0,0 1,0,0,0 10140 ;* ----- ----- ------- ------- 10141 ;* 1 -1 1 -1 10142 ;* 10143 ;* -1,0,0 -1,0,0 -1,0,0,0 -1,0,0,0 10144 ;* ------ ------ -------- -------- 10145 ;* 1 -1 1 -1 10146 ;* 10147 ;* 1,0,0,0 1,0,0,0 -1,0,0,0 -1,0,0,0 10148 ;* ------- ------- -------- -------- 10149 ;* 1,0 -1,0 1,0 -1,0 10150 ;* 10151 ;* 0,-1,-1,-1 0,-1,-1,-1 -1,0,0,1 -1,0,0,1 10152 ;* ---------- ---------- -------- -------- 10153 ;* 0,-1 -1,1 0,-1 -1,1 10154 ;* 10155 ;* 1,0,-1,-1 1,0,-1,-1 -2,-1,0,1 -2,-1,0,1 10156 ;* --------- --------- --------- --------- 10157 ;* 0,-1 -1,1 0,-1 -1,1 10158 ;* 10159 ;* -2^140 2^140-1 2^140-1 -2^70+1,-2^70 10160 ;* ------ ------- ------- ------------- 10161 ;* -2^70 2^70-1 -2^70+1 2^70-1 10162 ;* 10163 ;* THESE TESTS ATTEMPT TO PERFORM VARIOUS DIVISIONS THAT 10164 ;* SHOULD RESULT IN OVERFLOW. THE SETTING OF AROV AND NO 10165 ;* DIVIDE FLAGS IS VERIFIED AND THE DIVIDEND IS CHECKED TO 10166 ;* SEE THAT IT DID NOT CHANGE. 10167 ;* 10168 ;* ALSO TRY A FEW WITH INCONSISTENT SIGNS IN THE LEAST 10169 ;* SIGNIFICANT WORDS OF THE DIVIDEND AND DIVISOR JUST TO MAKE 10170 ;* SURE THAT THE DIVIDEND DOES NOT CHANGE ON ANY CONDITION. 10171 ; ********************************************************************** DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0229 10172 10173 ; ********************************************************************** 10174 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10175 ; ********************************************************************** 10176 10177 ODIV (0,0,0,1,0,0)^ 10178 10179 ; --- DIVIDEND == (0,0,0,1) 10180 ; --- DIVISOR === (0,0) 10181 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10182 10183 037736 200 01 0 00 045522 ..0746: MOVE AC1,[[EXP 0,0,0,1,0,0],,ODEND] 10184 037737 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10185 037740 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10186 ERROR (..0746,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10187 037741 036 14 0 00 045532 10188 037742 255 00 0 00 000000 10189 ^ 10190 10191 037743 200 14 0 00 040567 ..0747: MOVE SCR2,OFLOC ;GET PC 10192 037744 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10193 037745 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10194 ERROR (..0746,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10195 10196 037746 036 13 0 00 045545 10197 037747 255 00 0 00 000000 10198 ^ 10199 ^ 10200 10201 ; ********************************************************************** 10202 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10203 ; ********************************************************************** 10204 10205 ODIV (0,0,1,0,0,0)^ 10206 10207 ; --- DIVIDEND == (0,0,1,0) 10208 ; --- DIVISOR === (0,0) 10209 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10210 10211 037750 200 01 0 00 045556 ..0750: MOVE AC1,[[EXP 0,0,1,0,0,0],,ODEND] 10212 037751 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10213 037752 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10214 ERROR (..0750,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10215 037753 036 14 0 00 045532 10216 037754 255 00 0 00 000000 10217 ^ 10218 10219 037755 200 14 0 00 040567 ..0751: MOVE SCR2,OFLOC ;GET PC 10220 037756 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10221 037757 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10222 ERROR (..0750,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10223 10224 037760 036 13 0 00 045545 10225 037761 255 00 0 00 000000 10226 ^ DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-1 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0230 10227 ^ 10228 10229 ; ********************************************************************** 10230 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10231 ; ********************************************************************** 10232 10233 ODIV (0,1,0,0,0,0)^ 10234 10235 ; --- DIVIDEND == (0,1,0,0) 10236 ; --- DIVISOR === (0,0) 10237 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10238 10239 037762 200 01 0 00 045565 ..0752: MOVE AC1,[[EXP 0,1,0,0,0,0],,ODEND] 10240 037763 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10241 037764 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10242 ERROR (..0752,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10243 037765 036 14 0 00 045532 10244 037766 255 00 0 00 000000 10245 ^ 10246 10247 037767 200 14 0 00 040567 ..0753: MOVE SCR2,OFLOC ;GET PC 10248 037770 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10249 037771 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10250 ERROR (..0752,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10251 10252 037772 036 13 0 00 045545 10253 037773 255 00 0 00 000000 10254 ^ 10255 ^ 10256 10257 ; ********************************************************************** 10258 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10259 ; ********************************************************************** 10260 10261 ODIV (1,0,0,0,0,0)^ 10262 10263 ; --- DIVIDEND == (1,0,0,0) 10264 ; --- DIVISOR === (0,0) 10265 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10266 10267 037774 200 01 0 00 045574 ..0754: MOVE AC1,[[EXP 1,0,0,0,0,0],,ODEND] 10268 037775 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10269 037776 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10270 ERROR (..0754,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10271 037777 036 14 0 00 045532 10272 040000 255 00 0 00 000000 10273 ^ 10274 10275 040001 200 14 0 00 040567 ..0755: MOVE SCR2,OFLOC ;GET PC 10276 040002 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10277 040003 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10278 ERROR (..0754,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10279 10280 040004 036 13 0 00 045545 10281 040005 255 00 0 00 000000 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-2 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0231 10282 ^ 10283 ^ 10284 10285 ; ********************************************************************** 10286 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10287 ; ********************************************************************** 10288 10289 ODIV (-1,-1,-1,-1,0,0)^ 10290 10291 ; --- DIVIDEND == (-1,-1,-1,-1) 10292 ; --- DIVISOR === (0,0) 10293 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10294 10295 040006 200 01 0 00 045603 ..0756: MOVE AC1,[[EXP -1,-1,-1,-1,0,0],,ODEND] 10296 040007 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10297 040010 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10298 ERROR (..0756,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10299 040011 036 14 0 00 045532 10300 040012 255 00 0 00 000000 10301 ^ 10302 10303 040013 200 14 0 00 040567 ..0757: MOVE SCR2,OFLOC ;GET PC 10304 040014 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10305 040015 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10306 ERROR (..0756,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10307 10308 040016 036 13 0 00 045545 10309 040017 255 00 0 00 000000 10310 ^ 10311 ^ 10312 10313 ; ********************************************************************** 10314 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10315 ; ********************************************************************** 10316 10317 ODIV (0,1,0,0,0,1)^ 10318 10319 ; --- DIVIDEND == (0,1,0,0) 10320 ; --- DIVISOR === (0,1) 10321 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10322 10323 040020 200 01 0 00 045612 ..0760: MOVE AC1,[[EXP 0,1,0,0,0,1],,ODEND] 10324 040021 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10325 040022 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10326 ERROR (..0760,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10327 040023 036 14 0 00 045532 10328 040024 255 00 0 00 000000 10329 ^ 10330 10331 040025 200 14 0 00 040567 ..0761: MOVE SCR2,OFLOC ;GET PC 10332 040026 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10333 040027 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10334 ERROR (..0760,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10335 10336 040030 036 13 0 00 045545 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-3 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0232 10337 040031 255 00 0 00 000000 10338 ^ 10339 ^ 10340 10341 ; ********************************************************************** 10342 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10343 ; ********************************************************************** 10344 10345 ODIV (0,1,0,0,-1,-1)^ 10346 10347 ; --- DIVIDEND == (0,1,0,0) 10348 ; --- DIVISOR === (-1,-1) 10349 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10350 10351 040032 200 01 0 00 045621 ..0762: MOVE AC1,[[EXP 0,1,0,0,-1,-1],,ODEND] 10352 040033 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10353 040034 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10354 ERROR (..0762,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10355 040035 036 14 0 00 045532 10356 040036 255 00 0 00 000000 10357 ^ 10358 10359 040037 200 14 0 00 040567 ..0763: MOVE SCR2,OFLOC ;GET PC 10360 040040 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10361 040041 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10362 ERROR (..0762,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10363 10364 040042 036 13 0 00 045545 10365 040043 255 00 0 00 000000 10366 ^ 10367 ^ 10368 10369 ; ********************************************************************** 10370 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10371 ; ********************************************************************** 10372 10373 ODIV (1,0,0,0,0,1)^ 10374 10375 ; --- DIVIDEND == (1,0,0,0) 10376 ; --- DIVISOR === (0,1) 10377 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10378 10379 040044 200 01 0 00 045630 ..0764: MOVE AC1,[[EXP 1,0,0,0,0,1],,ODEND] 10380 040045 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10381 040046 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10382 ERROR (..0764,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10383 040047 036 14 0 00 045532 10384 040050 255 00 0 00 000000 10385 ^ 10386 10387 040051 200 14 0 00 040567 ..0765: MOVE SCR2,OFLOC ;GET PC 10388 040052 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10389 040053 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10390 ERROR (..0764,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10391 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-4 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0233 10392 040054 036 13 0 00 045545 10393 040055 255 00 0 00 000000 10394 ^ 10395 ^ 10396 10397 ; ********************************************************************** 10398 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10399 ; ********************************************************************** 10400 10401 ODIV (1,0,0,0,-1,-1)^ 10402 10403 ; --- DIVIDEND == (1,0,0,0) 10404 ; --- DIVISOR === (-1,-1) 10405 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10406 10407 040056 200 01 0 00 045637 ..0766: MOVE AC1,[[EXP 1,0,0,0,-1,-1],,ODEND] 10408 040057 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10409 040060 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10410 ERROR (..0766,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10411 040061 036 14 0 00 045532 10412 040062 255 00 0 00 000000 10413 ^ 10414 10415 040063 200 14 0 00 040567 ..0767: MOVE SCR2,OFLOC ;GET PC 10416 040064 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10417 040065 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10418 ERROR (..0766,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10419 10420 040066 036 13 0 00 045545 10421 040067 255 00 0 00 000000 10422 ^ 10423 ^ 10424 10425 ; ********************************************************************** 10426 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10427 ; ********************************************************************** 10428 10429 ODIV (-1,-1,1B0,1B0,0,1)^ 10430 10431 ; --- DIVIDEND == (-1,-1,1B0,1B0) 10432 ; --- DIVISOR === (0,1) 10433 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10434 10435 040070 200 01 0 00 045646 ..0770: MOVE AC1,[[EXP -1,-1,1B0,1B0,0,1],,ODEND] 10436 040071 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10437 040072 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10438 ERROR (..0770,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10439 040073 036 14 0 00 045532 10440 040074 255 00 0 00 000000 10441 ^ 10442 10443 040075 200 14 0 00 040567 ..0771: MOVE SCR2,OFLOC ;GET PC 10444 040076 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10445 040077 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10446 ERROR (..0770,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-5 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0234 10447 10448 040100 036 13 0 00 045545 10449 040101 255 00 0 00 000000 10450 ^ 10451 ^ 10452 10453 ; ********************************************************************** 10454 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10455 ; ********************************************************************** 10456 10457 ODIV (-1,-1,1B0,1B0,-1,-1)^ 10458 10459 ; --- DIVIDEND == (-1,-1,1B0,1B0) 10460 ; --- DIVISOR === (-1,-1) 10461 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10462 10463 040102 200 01 0 00 045655 ..0772: MOVE AC1,[[EXP -1,-1,1B0,1B0,-1,-1],,ODEND] 10464 040103 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10465 040104 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10466 ERROR (..0772,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10467 040105 036 14 0 00 045532 10468 040106 255 00 0 00 000000 10469 ^ 10470 10471 040107 200 14 0 00 040567 ..0773: MOVE SCR2,OFLOC ;GET PC 10472 040110 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10473 040111 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10474 ERROR (..0772,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10475 10476 040112 036 13 0 00 045545 10477 040113 255 00 0 00 000000 10478 ^ 10479 ^ 10480 10481 ; ********************************************************************** 10482 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10483 ; ********************************************************************** 10484 10485 ODIV (-1,1B0,1B0,1B0,0,1)^ 10486 10487 ; --- DIVIDEND == (-1,1B0,1B0,1B0) 10488 ; --- DIVISOR === (0,1) 10489 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10490 10491 040114 200 01 0 00 045664 ..0774: MOVE AC1,[[EXP -1,1B0,1B0,1B0,0,1],,ODEND] 10492 040115 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10493 040116 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10494 ERROR (..0774,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10495 040117 036 14 0 00 045532 10496 040120 255 00 0 00 000000 10497 ^ 10498 10499 040121 200 14 0 00 040567 ..0775: MOVE SCR2,OFLOC ;GET PC 10500 040122 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10501 040123 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-6 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0235 10502 ERROR (..0774,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10503 10504 040124 036 13 0 00 045545 10505 040125 255 00 0 00 000000 10506 ^ 10507 ^ 10508 10509 ; ********************************************************************** 10510 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10511 ; ********************************************************************** 10512 10513 ODIV (-1,1B0,1B0,1B0,-1,-1)^ 10514 10515 ; --- DIVIDEND == (-1,1B0,1B0,1B0) 10516 ; --- DIVISOR === (-1,-1) 10517 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10518 10519 040126 200 01 0 00 045673 ..0776: MOVE AC1,[[EXP -1,1B0,1B0,1B0,-1,-1],,ODEND] 10520 040127 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10521 040130 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10522 ERROR (..0776,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10523 040131 036 14 0 00 045532 10524 040132 255 00 0 00 000000 10525 ^ 10526 10527 040133 200 14 0 00 040567 ..0777: MOVE SCR2,OFLOC ;GET PC 10528 040134 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10529 040135 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10530 ERROR (..0776,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10531 10532 040136 036 13 0 00 045545 10533 040137 255 00 0 00 000000 10534 ^ 10535 ^ 10536 10537 ; ********************************************************************** 10538 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10539 ; ********************************************************************** 10540 10541 ODIV (1,0,0,0,1,0)^ 10542 10543 ; --- DIVIDEND == (1,0,0,0) 10544 ; --- DIVISOR === (1,0) 10545 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10546 10547 040140 200 01 0 00 045702 ..1000: MOVE AC1,[[EXP 1,0,0,0,1,0],,ODEND] 10548 040141 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10549 040142 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10550 ERROR (..1000,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10551 040143 036 14 0 00 045532 10552 040144 255 00 0 00 000000 10553 ^ 10554 10555 040145 200 14 0 00 040567 ..1001: MOVE SCR2,OFLOC ;GET PC 10556 040146 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-7 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0236 10557 040147 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10558 ERROR (..1000,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10559 10560 040150 036 13 0 00 045545 10561 040151 255 00 0 00 000000 10562 ^ 10563 ^ 10564 10565 ; ********************************************************************** 10566 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10567 ; ********************************************************************** 10568 10569 ODIV (1,0,0,0,-1,0)^ 10570 10571 ; --- DIVIDEND == (1,0,0,0) 10572 ; --- DIVISOR === (-1,0) 10573 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10574 10575 040152 200 01 0 00 045711 ..1002: MOVE AC1,[[EXP 1,0,0,0,-1,0],,ODEND] 10576 040153 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10577 040154 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10578 ERROR (..1002,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10579 040155 036 14 0 00 045532 10580 040156 255 00 0 00 000000 10581 ^ 10582 10583 040157 200 14 0 00 040567 ..1003: MOVE SCR2,OFLOC ;GET PC 10584 040160 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10585 040161 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10586 ERROR (..1002,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10587 10588 040162 036 13 0 00 045545 10589 040163 255 00 0 00 000000 10590 ^ 10591 ^ 10592 10593 ; ********************************************************************** 10594 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10595 ; ********************************************************************** 10596 10597 ODIV (-1,1B0,1B0,1B0,1,0)^ 10598 10599 ; --- DIVIDEND == (-1,1B0,1B0,1B0) 10600 ; --- DIVISOR === (1,0) 10601 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10602 10603 040164 200 01 0 00 045720 ..1004: MOVE AC1,[[EXP -1,1B0,1B0,1B0,1,0],,ODEND] 10604 040165 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10605 040166 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10606 ERROR (..1004,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10607 040167 036 14 0 00 045532 10608 040170 255 00 0 00 000000 10609 ^ 10610 10611 040171 200 14 0 00 040567 ..1005: MOVE SCR2,OFLOC ;GET PC DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-8 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0237 10612 040172 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10613 040173 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10614 ERROR (..1004,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10615 10616 040174 036 13 0 00 045545 10617 040175 255 00 0 00 000000 10618 ^ 10619 ^ 10620 10621 ; ********************************************************************** 10622 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10623 ; ********************************************************************** 10624 10625 ODIV (-1,1B0,1B0,1B0,-1,1B0)^ 10626 10627 ; --- DIVIDEND == (-1,1B0,1B0,1B0) 10628 ; --- DIVISOR === (-1,1B0) 10629 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10630 10631 040176 200 01 0 00 045727 ..1006: MOVE AC1,[[EXP -1,1B0,1B0,1B0,-1,1B0],,ODEND] 10632 040177 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10633 040200 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10634 ERROR (..1006,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10635 040201 036 14 0 00 045532 10636 040202 255 00 0 00 000000 10637 ^ 10638 10639 040203 200 14 0 00 040567 ..1007: MOVE SCR2,OFLOC ;GET PC 10640 040204 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10641 040205 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10642 ERROR (..1006,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10643 10644 040206 036 13 0 00 045545 10645 040207 255 00 0 00 000000 10646 ^ 10647 ^ 10648 10649 ; ********************************************************************** 10650 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10651 ; ********************************************************************** 10652 10653 ODIV (0,377777777777,377777777777,377777777777,0,377777777777)^ 10654 10655 ; --- DIVIDEND == (0,377777777777,377777777777,377777777777) 10656 ; --- DIVISOR === (0,377777777777) 10657 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10658 10659 040210 200 01 0 00 045736 ..1010: MOVE AC1,[[EXP 0,377777777777,377777777777,377777777777,0,377777777777],,ODEND] 10660 040211 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10661 040212 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10662 ERROR (..1010,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10663 040213 036 14 0 00 045532 10664 040214 255 00 0 00 000000 10665 ^ 10666 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-9 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0238 10667 040215 200 14 0 00 040567 ..1011: MOVE SCR2,OFLOC ;GET PC 10668 040216 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10669 040217 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10670 ERROR (..1010,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10671 10672 040220 036 13 0 00 045545 10673 040221 255 00 0 00 000000 10674 ^ 10675 ^ 10676 10677 ; ********************************************************************** 10678 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10679 ; ********************************************************************** 10680 10681 ODIV (0,377777777777,377777777777,377777777777,-1,400000000001)^ 10682 10683 ; --- DIVIDEND == (0,377777777777,377777777777,377777777777) 10684 ; --- DIVISOR === (-1,400000000001) 10685 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10686 10687 040222 ..1012: MOVE AC1,[[EXP 0,377777777777,377777777777,377777777777,-1,400000000001],,ODEND] 10688 040222 200 01 0 00 045745 10689 040223 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10690 040224 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10691 ERROR (..1012,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10692 040225 036 14 0 00 045532 10693 040226 255 00 0 00 000000 10694 ^ 10695 10696 040227 200 14 0 00 040567 ..1013: MOVE SCR2,OFLOC ;GET PC 10697 040230 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10698 040231 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10699 ERROR (..1012,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10700 10701 040232 036 13 0 00 045545 10702 040233 255 00 0 00 000000 10703 ^ 10704 ^ 10705 10706 ; ********************************************************************** 10707 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10708 ; ********************************************************************** 10709 10710 ODIV (-1,1B0,1B0,400000000001,0,377777777777)^ 10711 10712 ; --- DIVIDEND == (-1,1B0,1B0,400000000001) 10713 ; --- DIVISOR === (0,377777777777) 10714 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10715 10716 040234 200 01 0 00 045746 ..1014: MOVE AC1,[[EXP -1,1B0,1B0,400000000001,0,377777777777],,ODEND] 10717 040235 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10718 040236 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10719 ERROR (..1014,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10720 040237 036 14 0 00 045532 10721 040240 255 00 0 00 000000 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-10 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0239 10722 ^ 10723 10724 040241 200 14 0 00 040567 ..1015: MOVE SCR2,OFLOC ;GET PC 10725 040242 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10726 040243 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10727 ERROR (..1014,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10728 10729 040244 036 13 0 00 045545 10730 040245 255 00 0 00 000000 10731 ^ 10732 ^ 10733 10734 ; ********************************************************************** 10735 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10736 ; ********************************************************************** 10737 10738 ODIV (-1,1B0,1B0,400000000001,-1,400000000001)^ 10739 10740 ; --- DIVIDEND == (-1,1B0,1B0,400000000001) 10741 ; --- DIVISOR === (-1,400000000001) 10742 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10743 10744 040246 200 01 0 00 045755 ..1016: MOVE AC1,[[EXP -1,1B0,1B0,400000000001,-1,400000000001],,ODEND] 10745 040247 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10746 040250 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10747 ERROR (..1016,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10748 040251 036 14 0 00 045532 10749 040252 255 00 0 00 000000 10750 ^ 10751 10752 040253 200 14 0 00 040567 ..1017: MOVE SCR2,OFLOC ;GET PC 10753 040254 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10754 040255 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10755 ERROR (..1016,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10756 10757 040256 036 13 0 00 045545 10758 040257 255 00 0 00 000000 10759 ^ 10760 ^ 10761 10762 ; ********************************************************************** 10763 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10764 ; ********************************************************************** 10765 10766 ODIV (1,0,377777777777,377777777777,0,377777777777)^ 10767 10768 ; --- DIVIDEND == (1,0,377777777777,377777777777) 10769 ; --- DIVISOR === (0,377777777777) 10770 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10771 10772 040260 200 01 0 00 045756 ..1020: MOVE AC1,[[EXP 1,0,377777777777,377777777777,0,377777777777],,ODEND] 10773 040261 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10774 040262 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10775 ERROR (..1020,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10776 040263 036 14 0 00 045532 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-11 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0240 10777 040264 255 00 0 00 000000 10778 ^ 10779 10780 040265 200 14 0 00 040567 ..1021: MOVE SCR2,OFLOC ;GET PC 10781 040266 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10782 040267 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10783 ERROR (..1020,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10784 10785 040270 036 13 0 00 045545 10786 040271 255 00 0 00 000000 10787 ^ 10788 ^ 10789 10790 ; ********************************************************************** 10791 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10792 ; ********************************************************************** 10793 10794 ODIV (1,0,377777777777,377777777777,-1,400000000001)^ 10795 10796 ; --- DIVIDEND == (1,0,377777777777,377777777777) 10797 ; --- DIVISOR === (-1,400000000001) 10798 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10799 10800 040272 200 01 0 00 045765 ..1022: MOVE AC1,[[EXP 1,0,377777777777,377777777777,-1,400000000001],,ODEND] 10801 040273 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10802 040274 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10803 ERROR (..1022,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10804 040275 036 14 0 00 045532 10805 040276 255 00 0 00 000000 10806 ^ 10807 10808 040277 200 14 0 00 040567 ..1023: MOVE SCR2,OFLOC ;GET PC 10809 040300 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10810 040301 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10811 ERROR (..1022,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10812 10813 040302 036 13 0 00 045545 10814 040303 255 00 0 00 000000 10815 ^ 10816 ^ 10817 10818 ; ********************************************************************** 10819 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10820 ; ********************************************************************** 10821 10822 ODIV (-2,-1,1B0,400000000001,0,377777777777)^ 10823 10824 ; --- DIVIDEND == (-2,-1,1B0,400000000001) 10825 ; --- DIVISOR === (0,377777777777) 10826 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10827 10828 040304 200 01 0 00 045774 ..1024: MOVE AC1,[[EXP -2,-1,1B0,400000000001,0,377777777777],,ODEND] 10829 040305 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10830 040306 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10831 ERROR (..1024,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-12 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0241 10832 040307 036 14 0 00 045532 10833 040310 255 00 0 00 000000 10834 ^ 10835 10836 040311 200 14 0 00 040567 ..1025: MOVE SCR2,OFLOC ;GET PC 10837 040312 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10838 040313 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10839 ERROR (..1024,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10840 10841 040314 036 13 0 00 045545 10842 040315 255 00 0 00 000000 10843 ^ 10844 ^ 10845 10846 ; ********************************************************************** 10847 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10848 ; ********************************************************************** 10849 10850 ODIV (-2,-1,1B0,400000000001,-1,400000000001)^ 10851 10852 ; --- DIVIDEND == (-2,-1,1B0,400000000001) 10853 ; --- DIVISOR === (-1,400000000001) 10854 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10855 10856 040316 200 01 0 00 046003 ..1026: MOVE AC1,[[EXP -2,-1,1B0,400000000001,-1,400000000001],,ODEND] 10857 040317 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10858 040320 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10859 ERROR (..1026,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10860 040321 036 14 0 00 045532 10861 040322 255 00 0 00 000000 10862 ^ 10863 10864 040323 200 14 0 00 040567 ..1027: MOVE SCR2,OFLOC ;GET PC 10865 040324 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10866 040325 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10867 ERROR (..1026,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10868 10869 040326 036 13 0 00 045545 10870 040327 255 00 0 00 000000 10871 ^ 10872 ^ 10873 10874 ; ********************************************************************** 10875 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10876 ; ********************************************************************** 10877 10878 ODIV (1B0,1B0,1B0,1B0,1B0,1B0)^ 10879 10880 ; --- DIVIDEND == (1B0,1B0,1B0,1B0) 10881 ; --- DIVISOR === (1B0,1B0) 10882 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10883 10884 040330 200 01 0 00 046012 ..1030: MOVE AC1,[[EXP 1B0,1B0,1B0,1B0,1B0,1B0],,ODEND] 10885 040331 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10886 040332 260 17 0 00 040557 GO OSUBR ;GO DO TEST DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-13 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0242 10887 ERROR (..1030,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10888 040333 036 14 0 00 045532 10889 040334 255 00 0 00 000000 10890 ^ 10891 10892 040335 200 14 0 00 040567 ..1031: MOVE SCR2,OFLOC ;GET PC 10893 040336 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10894 040337 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10895 ERROR (..1030,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10896 10897 040340 036 13 0 00 045545 10898 040341 255 00 0 00 000000 10899 ^ 10900 ^ 10901 10902 ; ********************************************************************** 10903 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10904 ; ********************************************************************** 10905 10906 ODIV (377777777777,377777777777,377777777777,377777777777,377777777777,377777777 10907 777)^ 10908 10909 ; --- DIVIDEND == (377777777777,377777777777,377777777777,377777777777) 10910 ; --- DIVISOR === (377777777777,377777777777) 10911 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10912 10913 ..1032: MOVE AC1,[[EXP 377777777777,377777777777,377777777777,377777777777,377777777777, 10914 040342 200 01 0 00 046021 377777777777],,ODEND] 10915 040343 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10916 040344 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10917 ERROR (..1032,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10918 040345 036 14 0 00 045532 10919 040346 255 00 0 00 000000 10920 ^ 10921 10922 040347 200 14 0 00 040567 ..1033: MOVE SCR2,OFLOC ;GET PC 10923 040350 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10924 040351 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10925 ERROR (..1032,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10926 10927 040352 036 13 0 00 045545 10928 040353 255 00 0 00 000000 10929 ^ 10930 ^ 10931 10932 ; ********************************************************************** 10933 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10934 ; ********************************************************************** 10935 10936 ODIV (377777777777,377777777777,377777777777,377777777777,1B0,400000000001)^ 10937 10938 ; --- DIVIDEND == (377777777777,377777777777,377777777777,377777777777) 10939 ; --- DIVISOR === (1B0,400000000001) 10940 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10941 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-14 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0243 10942 ..1034: MOVE AC1,[[EXP 377777777777,377777777777,377777777777,377777777777,1B0,400000000 10943 040354 200 01 0 00 046030 001],,ODEND] 10944 040355 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10945 040356 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10946 ERROR (..1034,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10947 040357 036 14 0 00 045532 10948 040360 255 00 0 00 000000 10949 ^ 10950 10951 040361 200 14 0 00 040567 ..1035: MOVE SCR2,OFLOC ;GET PC 10952 040362 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10953 040363 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10954 ERROR (..1034,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10955 10956 040364 036 13 0 00 045545 10957 040365 255 00 0 00 000000 10958 ^ 10959 ^ 10960 10961 ; ********************************************************************** 10962 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING ---------- 10963 ; ********************************************************************** 10964 10965 ODIV (1B0,400000000001,1B0,1B0,377777777777,377777777777)^ 10966 10967 ; --- DIVIDEND == (1B0,400000000001,1B0,1B0) 10968 ; --- DIVISOR === (377777777777,377777777777) 10969 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10970 10971 040366 200 01 0 00 046037 ..1036: MOVE AC1,[[EXP 1B0,400000000001,1B0,1B0,377777777777,377777777777],,ODEND] 10972 040367 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 10973 040370 260 17 0 00 040557 GO OSUBR ;GO DO TEST 10974 ERROR (..1036,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 10975 040371 036 14 0 00 045532 10976 040372 255 00 0 00 000000 10977 ^ 10978 10979 040373 200 14 0 00 040567 ..1037: MOVE SCR2,OFLOC ;GET PC 10980 040374 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 10981 040375 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 10982 ERROR (..1036,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 10983 10984 040376 036 13 0 00 045545 10985 040377 255 00 0 00 000000 10986 ^ 10987 ^ 10988 10989 ; ********************************************************************** 10990 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING WITH INCONSISTENT SIGNS ------- 10991 --- 10992 ; ********************************************************************** 10993 10994 ODIV (1,1B0,-1,-1,0,377777777777)^ 10995 10996 ; --- DIVIDEND == (1,1B0,-1,-1) DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-15 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0244 10997 ; --- DIVISOR === (0,377777777777) 10998 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 10999 11000 040400 200 01 0 00 046046 ..1040: MOVE AC1,[[EXP 1,1B0,-1,-1,0,377777777777],,ODEND] 11001 040401 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 11002 040402 260 17 0 00 040557 GO OSUBR ;GO DO TEST 11003 ERROR (..1040,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 11004 040403 036 14 0 00 045532 11005 040404 255 00 0 00 000000 11006 ^ 11007 11008 040405 200 14 0 00 040567 ..1041: MOVE SCR2,OFLOC ;GET PC 11009 040406 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 11010 040407 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 11011 ERROR (..1040,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 11012 11013 040410 036 13 0 00 045545 11014 040411 255 00 0 00 000000 11015 ^ 11016 ^ 11017 11018 ; ********************************************************************** 11019 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING WITH INCONSISTENT SIGNS ------- 11020 --- 11021 ; ********************************************************************** 11022 11023 ODIV (1,0,377777777777,377777777777,-1,1)^ 11024 11025 ; --- DIVIDEND == (1,0,377777777777,377777777777) 11026 ; --- DIVISOR === (-1,1) 11027 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 11028 11029 040412 200 01 0 00 046055 ..1042: MOVE AC1,[[EXP 1,0,377777777777,377777777777,-1,1],,ODEND] 11030 040413 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 11031 040414 260 17 0 00 040557 GO OSUBR ;GO DO TEST 11032 ERROR (..1042,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 11033 040415 036 14 0 00 045532 11034 040416 255 00 0 00 000000 11035 ^ 11036 11037 040417 200 14 0 00 040567 ..1043: MOVE SCR2,OFLOC ;GET PC 11038 040420 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 11039 040421 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 11040 ERROR (..1042,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 11041 11042 040422 036 13 0 00 045545 11043 040423 255 00 0 00 000000 11044 ^ 11045 ^ 11046 11047 ; ********************************************************************** 11048 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING WITH INCONSISTENT SIGNS ------- 11049 --- 11050 ; ********************************************************************** 11051 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 32-16 DSKCFM MAC 26-Sep-79 15:49 DDIV - TEST G SEQ 0245 11052 ODIV (-2,377777777777,0,1,0,-1)^ 11053 11054 ; --- DIVIDEND == (-2,377777777777,0,1) 11055 ; --- DIVISOR === (0,-1) 11056 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 11057 11058 040424 200 01 0 00 046064 ..1044: MOVE AC1,[[EXP -2,377777777777,0,1,0,-1],,ODEND] 11059 040425 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 11060 040426 260 17 0 00 040557 GO OSUBR ;GO DO TEST 11061 ERROR (..1044,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 11062 040427 036 14 0 00 045532 11063 040430 255 00 0 00 000000 11064 ^ 11065 11066 040431 200 14 0 00 040567 ..1045: MOVE SCR2,OFLOC ;GET PC 11067 040432 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 11068 040433 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 11069 ERROR (..1044,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 11070 11071 040434 036 13 0 00 045545 11072 040435 255 00 0 00 000000 11073 ^ 11074 ^ 11075 11076 ; ********************************************************************** 11077 ; ---------- DDIV - TEST G - OVERFLOW / NO DIVIDE TESTING WITH INCONSISTENT SIGNS ------- 11078 --- 11079 ; ********************************************************************** 11080 11081 ODIV (-2,-1,0,1,-1,400000000001)^ 11082 11083 ; --- DIVIDEND == (-2,-1,0,1) 11084 ; --- DIVISOR === (-1,400000000001) 11085 ; --- QUOTIENT/REMAINDER - NOT CALCULATED (DIVIDEND UNCHANGED) 11086 11087 040436 200 01 0 00 046073 ..1046: MOVE AC1,[[EXP -2,-1,0,1,-1,400000000001],,ODEND] 11088 040437 251 01 0 00 040635 BLT AC1,ORES-1 ;SET UP OPERANDS 11089 040440 260 17 0 00 040557 GO OSUBR ;GO DO TEST 11090 ERROR (..1046,14,SCR1,SCR2,,TEST G - DIVIDEND CHANGED ON OV/NODIV,DPRINT)^SALL 11091 040441 036 14 0 00 045532 11092 040442 255 00 0 00 000000 11093 ^ 11094 11095 040443 200 14 0 00 040567 ..1047: MOVE SCR2,OFLOC ;GET PC 11096 040444 434 14 0 00 045535 IOR SCR2,[AROV+DCK,,0] ;CALC CORRECT PC (OV/NO DIV) 11097 040445 312 14 0 00 040567 CAME SCR2,OFLOC ;PC CORRECT? 11098 ERROR (..1046,13,SCR2,OFLOC,,TEST G - PC FLAGS INCORRECT - BITS 0&12,DPRINT)^SALL 11099 11100 040446 036 13 0 00 045545 11101 040447 255 00 0 00 000000 11102 ^ 11103 ^ 11104 11105 040450 254 00 0 00 030057 PHALT: JRST BEGEND DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 33 DSKCFM MAC 26-Sep-79 15:49 TESTING SUBROUTINES SEQ 0246 11106 SUBTTL TESTING SUBROUTINES 11107 11108 ; ********************************************************************** 11109 ;*MSUBR - SUBROUTINE TO DO MULTIPLICATION CALCULATIONS 11110 ;* 11111 ;* ARGUMENTS: MCAND - CONTAINS MULTIPLICAND 11112 ;* MPLIER - CONTAINS MULTIPLIER 11113 ;* MRES - CONTAINS THE EXPECTED RESULT 11114 ; ********************************************************************** 11115 11116 040451 200 15 0 00 046074 MSUBR: MOVE SCR3,[MCAND,,MPLIER] ;ADDRS OF OPERANDS FOR ADDL PRINT ROUTINE 11117 040452 120 01 0 00 040502 DMOVE AC1,MCAND ;INIT AC1 WITH MULTIPLICAND 11118 040453 120 03 0 00 043403 DMOVE AC1+2,[EXP 525252525252,252525252525] ;PUT GARBAGE IN 11119 ;RIGHT HALF OF RESULT 11120 040454 255 17 0 00 040455 JFCL 17,.+1 ;CLEAR PC FLAGS 11121 ;---------------------- 11122 040455 116 01 0 00 040504 DMUL AC1,MPLIER ;----- MULTIPLY ----- 11123 ;---------------------- 11124 040456 264 00 0 00 040457 JSR .+1 ;SAVE PC FLAGS 11125 040457 000000 000000 MFLOC: 0 ;PC FLAGS STORED HERE 11126 11127 040460 400 13 0 00 000000 SETZ SCR1, ;KEEP TRACK OF INCORRECT WORD 11128 040461 312 01 0 00 040506 CAME AC1,MRES ;1ST WORD OF RESULT OK? 11129 040462 254 00 0 00 040474 JRST MERROR ;FOUND AN ERROR 11130 11131 040463 201 13 0 00 000001 MOVEI SCR1,1 ;POINT TO 2ND WORD AS INCORRECT 11132 040464 312 02 0 00 040507 CAME AC1+1,MRES+1 ;2ND WORD OF RESULT OK? 11133 040465 254 00 0 00 040474 JRST MERROR ;FOUND AN ERROR 11134 11135 040466 201 13 0 00 000002 MOVEI SCR1,2 ;POINT TO 3RD WORD AS INCORRECT 11136 040467 312 03 0 00 040510 CAME AC1+2,MRES+2 ;3RD WORD OF RESULT OK? 11137 040470 254 00 0 00 040474 JRST MERROR ;FOUND AN ERROR 11138 11139 040471 201 13 0 00 000003 MOVEI SCR1,3 ;POINT TO 4TH WORD AS INCORRECT 11140 040472 316 04 0 00 040511 CAMN AC1+3,MRES+3 ;4TH WORD OF RESULT OK? 11141 040473 254 00 0 00 040477 JRST MTEST ;GO TEST IF PC FLAGS OK 11142 11143 040474 200 14 0 13 000001 MERROR: MOVE SCR2,AC1(SCR1) ;GET ACTUAL RESULT 11144 040475 200 13 0 13 040506 MOVE SCR1,MRES(SCR1) ;GET CORRECT RESULT 11145 040476 263 17 0 00 000000 RTN ;TAKE ERROR RETURN 11146 11147 040477 262 17 0 00 040512 MTEST: GET MRET ;GET RETURN ADDRESS IN MRET 11148 040500 350 00 0 00 040512 AOS MRET ;SET UP +1 NO ERROR RETURN 11149 040501 254 00 1 00 040512 JRST @MRET ;RETURN 11150 11151 040502 MCAND: BLOCK 2 ;MULTIPLICAND 11152 040504 MPLIER: BLOCK 2 ;MULTIPLIER 11153 040506 MRES: BLOCK 4 ;EXPECTED RESULT 11154 040512 MRET: BLOCK 1 ;RETURN + 1 ADDRESS DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 34 DSKCFM MAC 26-Sep-79 15:49 TESTING SUBROUTINES SEQ 0247 11155 11156 ; ********************************************************************** 11157 ;*PSUBR - SUBROUTINE TO DO DIVISION CALCULATIONS 11158 ;* 11159 ;* ARGUMENTS: PDEND - CONTAINS DIVIDEND 11160 ;* PISOR - CONTAINS DIVISOR 11161 ;* PRES - CONTAINS THE EXPECTED RESULT 11162 ; ********************************************************************** 11163 11164 040513 200 15 0 00 046075 PSUBR: MOVE SCR3,[PDEND,,PISOR] ;ADDRS OF OPERANDS FOR ADDL PRINT ROUTINE 11165 040514 120 01 0 00 040544 DMOVE AC1,PDEND ;INIT DIVIDEND (4 WORDS) 11166 040515 120 03 0 00 040546 DMOVE AC1+2,PDEND+2 11167 11168 040516 254 02 1 00 046076 JRSTF @[.+1] ;CLEAR PC FLAGS 11169 ;---------------------- 11170 040517 117 01 0 00 040550 DDIV AC1,PISOR ;----- DIVIDE ------- 11171 ;---------------------- 11172 040520 264 00 0 00 040521 JSR .+1 ;SAVE PC FLAGS 11173 040521 000000 000000 PFLOC: 0 ;PC FLAGS STORED HERE 11174 11175 040522 400 13 0 00 000000 SETZ SCR1, ;KEEP TRACK OF INCORRECT WORD 11176 040523 312 01 0 00 040552 CAME AC1,PRES ;1ST WORD OF QUOTIENT OK? 11177 040524 254 00 0 00 040536 JRST PERROR ;FOUND AN ERROR 11178 11179 040525 201 13 0 00 000001 MOVEI SCR1,1 ;POINT TO 2ND WORD AS INCORRECT 11180 040526 312 02 0 00 040553 CAME AC1+1,PRES+1 ;2ND WORD OF QUOTIENT OK? 11181 040527 254 00 0 00 040536 JRST PERROR ;FOUND AN ERROR 11182 11183 040530 201 13 0 00 000002 MOVEI SCR1,2 ;POINT TO 3RD WORD AS INCORRECT 11184 040531 312 03 0 00 040554 CAME AC1+2,PRES+2 ;1ST WORD OF REMAINDER OK? 11185 040532 254 00 0 00 040536 JRST PERROR ;FOUND AN ERROR 11186 11187 040533 201 13 0 00 000003 MOVEI SCR1,3 ;POINT TO 4TH WORD AS INCORRECT 11188 040534 316 04 0 00 040555 CAMN AC1+3,PRES+3 ;2ND WORD OF REMAINDER OK? 11189 040535 254 00 0 00 040541 JRST PTEST ;GO TEST IF PC FLAGS OK 11190 11191 040536 200 14 0 13 000001 PERROR: MOVE SCR2,AC1(SCR1) ;GET ACTUAL RESULT 11192 040537 200 13 0 13 040552 MOVE SCR1,PRES(SCR1) ;GET CORRECT RESULT 11193 040540 263 17 0 00 000000 RTN ;TAKE ERROR RETURN 11194 11195 040541 262 17 0 00 040512 PTEST: GET MRET ;GET RETURN ADDRESS IN MRET 11196 040542 350 00 0 00 040512 AOS MRET ;SET UP +1 NO ERROR RETURN 11197 040543 254 00 1 00 040512 JRST @MRET ;RETURN 11198 11199 040544 PDEND: BLOCK 4 ;DIVIDEND 11200 040550 PISOR: BLOCK 2 ;DIVISOR 11201 040552 PRES: BLOCK 4 ;EXPECTED RESULT 11202 040556 PRET: BLOCK 1 ;RETURN + 1 ADDRESS DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 35 DSKCFM MAC 26-Sep-79 15:49 TESTING SUBROUTINES SEQ 0248 11203 11204 ; ********************************************************************** 11205 ;*OSUBR - SUBROUTINE TO DO DIVISION CALCULATIONS 11206 ;* 11207 ;* ARGUMENTS: ODEND - CONTAINS DIVIDEND 11208 ;* OISOR - CONTAINS DIVISOR 11209 ;* 11210 ;* NOTE: WHEN ENCOUNTERING A OVERFLOW/NO DIVIDE SITUATION THE PROCESSOR 11211 ;* ENSURES THAT THE OPERANDS DO NOT CHANGE. THE KL10 ENSURES 11212 ;* THAT NEITHER THE MAGNITUDE PORTION NOR THE SIGN BITS CHANGE. 11213 ;* THE KS10 ENSURES THAT THE MAGNITUDE PORTION OF EITHER WORD 11214 ;* DOES NOT CHANGE - HOWEVER, IT ONLY PROTECTS THE SIGN BIT OF 11215 ;* THE MOST SIGNIFICANT WORD. THE SIGN BIT OF THE OTHER WORD 11216 ;* IS INDETERMINATE. THIS TEST CHECKS TO FIND OUT WHAT TYPE OF 11217 ;* PROCESSOR WE HAVE AND WILL MODIFY THE TEST FOR A KS10. 11218 ;* 11219 ;* THE ABOVE WAS NOTICED WHEN RUNNING THE DIAGNOSTIC ON THE KS10 11220 ;* AFTER DEBUGGING ON A KL10. ACCORDING TO DON LEWINE, THIS WAS 11221 ;* DONE TO SAVE SPACE IN THE KS10 MICROCODE. 11222 ; ********************************************************************** 11223 11224 040557 200 15 0 00 046077 OSUBR: MOVE SCR3,[ODEND,,OISOR] ;ADDRS OF OPERANDS FOR ADDL PRINT ROUTINE 11225 040560 120 01 0 00 040630 DMOVE AC1,ODEND ;INIT DIVIDEND (4 WORDS) 11226 040561 120 03 0 00 040632 DMOVE AC1+2,ODEND+2 11227 040562 124 01 0 00 040636 DMOVEM AC1,ORES ;RESULT SHOULD BE SAME AS 11228 040563 124 03 0 00 040640 DMOVEM AC1+2,ORES+2 ; DIVIDEND 11229 11230 040564 254 02 1 00 046100 JRSTF @[.+1] ;CLEAR PC FLAGS 11231 ;---------------------- 11232 040565 117 01 0 00 040634 DDIV AC1,OISOR ;----- DIVIDE ------- 11233 ;---------------------- 11234 040566 264 00 0 00 040567 JSR .+1 ;SAVE PC FLAGS 11235 040567 000000 000000 OFLOC: 0 ;PC FLAGS STORED HERE 11236 11237 040570 336 00 0 00 030524 SKIPN SM10 ;KS10 PROCESSOR? 11238 040571 254 00 0 00 040600 JRST OCON ;NO - KL10 11239 040572 135 13 0 00 040622 LDB SCR1,OBYTEF ;COPY THE LOW ORDER SIGNS OF THE RESULT 11240 040573 137 13 0 00 040625 DPB SCR1,OBYTET ; INTO THE EXPECTED RESULT SINCE THEY 11241 040574 135 13 0 00 040623 LDB SCR1,OBYTEF+1 ; ARE INDETERMINATE AND WE DONT WANT 11242 040575 137 13 0 00 040626 DPB SCR1,OBYTET+1 ; TO TEST THE SIGN BIT. 11243 040576 135 13 0 00 040624 LDB SCR1,OBYTEF+2 11244 040577 137 13 0 00 040627 DPB SCR1,OBYTET+2 11245 11246 040600 400 13 0 00 000000 OCON: SETZ SCR1, ;KEEP TRACK OF INCORRECT WORD 11247 040601 312 01 0 00 040636 CAME AC1,ORES ;1ST WORD OF QUOTIENT OK? 11248 040602 254 00 0 00 040614 JRST OERROR ;FOUND AN ERROR 11249 11250 040603 201 13 0 00 000001 MOVEI SCR1,1 ;POINT TO 2ND WORD AS INCORRECT 11251 040604 312 02 0 00 040637 CAME AC1+1,ORES+1 ;2ND WORD OF QUOTIENT OK? 11252 040605 254 00 0 00 040614 JRST OERROR ;FOUND AN ERROR DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 36 DSKCFM MAC 26-Sep-79 15:49 TESTING SUBROUTINES SEQ 0249 11253 11254 040606 201 13 0 00 000002 MOVEI SCR1,2 ;POINT TO 3RD WORD AS INCORRECT 11255 040607 312 03 0 00 040640 CAME AC1+2,ORES+2 ;1ST WORD OF REMAINDER OK? 11256 040610 254 00 0 00 040614 JRST OERROR ;FOUND AN ERROR 11257 11258 040611 201 13 0 00 000003 MOVEI SCR1,3 ;POINT TO 4TH WORD AS INCORRECT 11259 040612 316 04 0 00 040641 CAMN AC1+3,ORES+3 ;2ND WORD OF REMAINDER OK? 11260 040613 254 00 0 00 040617 JRST OTEST ;GO TEST IF PC FLAGS OK 11261 11262 040614 200 14 0 13 000001 OERROR: MOVE SCR2,AC1(SCR1) ;GET ACTUAL RESULT 11263 040615 200 13 0 13 040636 MOVE SCR1,ORES(SCR1) ;GET CORRECT RESULT 11264 040616 263 17 0 00 000000 RTN ;TAKE ERROR RETURN 11265 11266 040617 262 17 0 00 040512 OTEST: GET MRET ;GET RETURN ADDRESS IN MRET 11267 040620 350 00 0 00 040512 AOS MRET ;SET UP +1 NO ERROR RETURN 11268 040621 254 00 1 00 040512 JRST @MRET ;RETURN 11269 11270 040622 43 01 0 00 000002 OBYTEF: POINT 1,AC1+1,0 ;BYTE POINTERS FOR GETTING SIGN 11271 040623 43 01 0 00 000003 POINT 1,AC1+2,0 ; FROM AC1+1,+2,+3 (ACTUAL RESULT) 11272 040624 43 01 0 00 000004 POINT 1,AC1+3,0 11273 040625 43 01 0 00 040637 OBYTET: POINT 1,ORES+1,0 ;BYTE POINTERS FOR PUTTING SIGN 11274 040626 43 01 0 00 040640 POINT 1,ORES+2,0 ; INTO ORES+1,+2,+3 (EXPECTED RESULT) 11275 040627 43 01 0 00 040641 POINT 1,ORES+3,0 11276 11277 040630 ODEND: BLOCK 4 ;DIVIDEND 11278 040634 OISOR: BLOCK 2 ;DIVISOR 11279 040636 ORES: BLOCK 4 ;EXPECTED RESULT 11280 040642 ORET: BLOCK 1 ;RETURN + 1 ADDRESS DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 37 DSKCFM MAC 26-Sep-79 15:49 ADDL ERROR PRINT ROUTINES SEQ 0250 11281 SUBTTL ADDL ERROR PRINT ROUTINES 11282 SALL 11283 ; ********************************************************************** 11284 ;*APRINT - ADDITION ERROR PRINTER 11285 ; ********************************************************************** 11286 11287 040643 037 02 0 00 046101 APRINT: PMSG (AUGEND: ) 11288 11289 040644 554 13 0 00 000015 HLRZ SCR1,SCR3 ;GET ADDR OF AUGEND 11290 040645 200 00 1 00 000013 MOVE 0,@SCR1 ;GET AUGEND (LEFT WORD) 11291 040646 037 14 0 00 000000 PNTOCT 11292 11293 040647 340 13 0 00 000000 AOJ SCR1, ;POINT TO RIGHT WORD 11294 040650 200 00 1 00 000013 MOVE 0,@SCR1 ;GET AUGEND (RIGHT WORD) 11295 040651 037 14 0 00 000000 PNTOCT 11296 11297 040652 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11298 040653 037 02 0 00 046103 PMSG (ADDEND: ) 11299 11300 040654 550 13 0 00 000015 HRRZ SCR1,SCR3 ;GET ADDR OF ADDEND 11301 040655 200 00 1 00 000013 MOVE 0,@SCR1 ;GET ADDEND (LEFT WORD) 11302 040656 037 14 0 00 000000 PNTOCT 11303 11304 040657 340 13 0 00 000000 AOJ SCR1, ;POINT TO RIGHT WORD 11305 040660 200 00 1 00 000013 MOVE 0,@SCR1 ;GET ADDEND (RIGHT WORD) 11306 040661 037 14 0 00 000000 PNTOCT 11307 11308 040662 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11309 040663 037 02 0 00 046105 PMSG (RESULT: ) 11310 11311 040664 200 00 0 00 000001 MOVE 0,AC1 ;GET LEFT WORD OF RESULT 11312 040665 037 14 0 00 000000 PNTOCT 11313 11314 040666 200 00 0 00 000002 MOVE 0,AC1+1 ;GET RIGHT WORD OF RESULT 11315 040667 037 14 0 00 000000 PNTOCT 11316 11317 040670 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11318 040671 263 17 0 00 000000 RTN DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 38 DSKCFM MAC 26-Sep-79 15:49 ADDL ERROR PRINT ROUTINES SEQ 0251 11319 11320 ; ********************************************************************** 11321 ;*SPRINT - SUBTRACTION ERROR PRINTER 11322 ; ********************************************************************** 11323 11324 040672 037 02 0 00 046107 SPRINT: PMSG (MINUEND: ) 11325 11326 040673 554 13 0 00 000015 HLRZ SCR1,SCR3 ;GET ADDR OF MINUEND 11327 040674 200 00 1 00 000013 MOVE 0,@SCR1 ;GET MINUEND (LEFT WORD) 11328 040675 037 14 0 00 000000 PNTOCT 11329 11330 040676 340 13 0 00 000000 AOJ SCR1, ;POINT TO RIGHT WORD 11331 040677 200 00 1 00 000013 MOVE 0,@SCR1 ;GET MINUEND (RIGHT WORD) 11332 040700 037 14 0 00 000000 PNTOCT 11333 11334 040701 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11335 040702 037 02 0 00 046112 PMSG (SUBTRAHEND: ) 11336 11337 040703 550 13 0 00 000015 HRRZ SCR1,SCR3 ;GET ADDR OF SUBTRAHEND 11338 040704 200 00 1 00 000013 MOVE 0,@SCR1 ;GET SUBTRAHEND (LEFT WORD) 11339 040705 037 14 0 00 000000 PNTOCT 11340 11341 040706 340 13 0 00 000000 AOJ SCR1, ;POINT TO RIGHT WORD 11342 040707 200 00 1 00 000013 MOVE 0,@SCR1 ;GET SUBTRAHEND (RIGHT WORD) 11343 040710 037 14 0 00 000000 PNTOCT 11344 11345 040711 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11346 040712 037 02 0 00 046115 PMSG (RESULT: ) 11347 11348 040713 200 00 0 00 000001 MOVE 0,AC1 ;GET LEFT WORD OF RESULT 11349 040714 037 14 0 00 000000 PNTOCT 11350 11351 040715 200 00 0 00 000002 MOVE 0,AC1+1 ;GET RIGHT WORD OF RESULT 11352 040716 037 14 0 00 000000 PNTOCT 11353 11354 040717 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11355 040720 263 17 0 00 000000 RTN DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 39 DSKCFM MAC 26-Sep-79 15:49 ADDL ERROR PRINT ROUTINES SEQ 0252 11356 11357 ; ********************************************************************** 11358 ;*MPRINT - MULTIPLICATION ERROR PRINTER 11359 ; ********************************************************************** 11360 11361 040721 037 02 0 00 046120 MPRINT: PMSG (MULTIPLICAND: ) 11362 11363 040722 554 13 0 00 000015 HLRZ SCR1,SCR3 ;GET ADDR OF MULTIPLICAND 11364 040723 200 00 1 00 000013 MOVE 0,@SCR1 ;GET MULTIPLICAND (LEFT WORD) 11365 040724 037 14 0 00 000000 PNTOCT 11366 11367 040725 340 13 0 00 000000 AOJ SCR1, ;POINT TO RIGHT WORD 11368 040726 200 00 1 00 000013 MOVE 0,@SCR1 ;GET MULTIPLICAND (RIGHT WORD) 11369 040727 037 14 0 00 000000 PNTOCT 11370 11371 040730 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11372 040731 037 02 0 00 046123 PMSG (MULTIPLIER: ) 11373 11374 040732 550 13 0 00 000015 HRRZ SCR1,SCR3 ;GET ADDRESS OF MULTIPLIER 11375 040733 200 00 1 00 000013 MOVE 0,@SCR1 ;GET LEFT WORD OF MULTIPLIER 11376 040734 037 14 0 00 000000 PNTOCT 11377 11378 040735 340 13 0 00 000000 AOJ SCR1, ;POINT TO RIGHT WORD 11379 040736 200 00 1 00 000013 MOVE 0,@SCR1 ;GET RIGHT WORD OF MULTIPLIER 11380 040737 037 14 0 00 000000 PNTOCT 11381 11382 040740 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11383 040741 037 02 0 00 046126 PMSG (RESULT: ) 11384 11385 040742 200 00 0 00 000001 MOVE 0,AC1 ;GET RESULT WORD 1 11386 040743 037 14 0 00 000000 PNTOCT 11387 11388 040744 200 00 0 00 000002 MOVE 0,AC1+1 ;GET RESULT WORD 2 11389 040745 037 14 0 00 000000 PNTOCT 11390 11391 040746 200 00 0 00 000003 MOVE 0,AC1+2 ;GET RESULT WORD 3 11392 040747 037 14 0 00 000000 PNTOCT 11393 11394 040750 200 00 0 00 000004 MOVE 0,AC1+3 ;GET RESULT WORD 4 11395 040751 037 14 0 00 000000 PNTOCT 11396 11397 040752 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11398 040753 263 17 0 00 000000 RTN DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 40 DSKCFM MAC 26-Sep-79 15:49 ADDL ERROR PRINT ROUTINES SEQ 0253 11399 11400 ; ********************************************************************** 11401 ;*DPRINT - DIVIDE ERROR PRINTER 11402 ; ********************************************************************** 11403 11404 040754 037 02 0 00 046131 DPRINT: PMSG (DIVIDEND: ) 11405 11406 040755 554 13 0 00 000015 HLRZ SCR1,SCR3 ;GET ADDR OF DIVIDEND 11407 040756 200 00 1 00 000013 MOVE 0,@SCR1 ;GET DIVIDEND (WORD 1) 11408 040757 037 14 0 00 000000 PNTOCT 11409 11410 040760 340 13 0 00 000000 AOJ SCR1, ;POINT TO 2ND WORD 11411 040761 200 00 1 00 000013 MOVE 0,@SCR1 ;GET DIVIDEND (WORD 2) 11412 040762 037 14 0 00 000000 PNTOCT 11413 11414 040763 340 13 0 00 000000 AOJ SCR1, ;POINT TO 3RD WORD 11415 040764 200 00 1 00 000013 MOVE 0,@SCR1 ;GET DIVIDEND (WORD 3) 11416 040765 037 14 0 00 000000 PNTOCT 11417 11418 040766 340 13 0 00 000000 AOJ SCR1, ;POINT TO 4TH WORD 11419 040767 200 00 1 00 000013 MOVE 0,@SCR1 ;GET DIVIDEND (WORD 4) 11420 040770 037 14 0 00 000000 PNTOCT 11421 11422 040771 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11423 040772 037 02 0 00 046133 PMSG (DIVISOR: ) 11424 11425 040773 550 13 0 00 000015 HRRZ SCR1,SCR3 ;GET ADDRESS OF DIVISOR 11426 040774 200 00 1 00 000013 MOVE 0,@SCR1 ;GET LEFT WORD OF DIVISOR 11427 040775 037 14 0 00 000000 PNTOCT 11428 11429 040776 340 13 0 00 000000 AOJ SCR1, ;POINT TO RIGHT WORD 11430 040777 200 00 1 00 000013 MOVE 0,@SCR1 ;GET RIGHT WORD OF DIVISOR 11431 041000 037 14 0 00 000000 PNTOCT 11432 11433 041001 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11434 041002 037 02 0 00 046135 PMSG (QUOTIENT: ) 11435 11436 041003 200 00 0 00 000001 MOVE 0,AC1 ;GET LEFT WORD OF QUOTIENT 11437 041004 037 14 0 00 000000 PNTOCT 11438 11439 041005 200 00 0 00 000002 MOVE 0,AC1+1 ;GET RIGHT WORD OF QUOTIENT 11440 041006 037 14 0 00 000000 PNTOCT 11441 11442 041007 037 02 0 00 046137 PMSG ( REMAINDER: ) 11443 11444 041010 200 00 0 00 000003 MOVE 0,AC1+2 ;GET LEFT WORD OF REMAINDER 11445 041011 037 14 0 00 000000 PNTOCT 11446 11447 041012 200 00 0 00 000004 MOVE 0,AC1+3 ;GET RIGHT WORD OF REMAINDER 11448 041013 037 14 0 00 000000 PNTOCT 11449 11450 041014 037 00 0 00 030242 PCRL ;PRINT OUT A CRLF 11451 041015 263 17 0 00 000000 RTN DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 41 DSKCFM MAC 26-Sep-79 15:49 ADDL ERROR PRINT ROUTINES SEQ 0254 11452 11453 SUBTTL *STOR* RESERVED STORAGE, SEPTEMBER 1979 11454 11455 ;PROGRAM LITERALS 11456 11457 XLIST 11458 IFNDEF $LPAPER, 11459 041016 LIT 11460 041016 44 41 44 44 00 64 11461 041017 45 63 64 77 00 00 11462 041020 000000 000000 11463 041021 123456 765432 11464 041022 000000 000000 11465 041023 000000 000000 11466 041024 041020 041022 11467 041025 77 00 00 00 00 00 11468 041026 64 45 63 64 00 41 11469 041027 21 00 15 00 62 45 11470 041030 63 65 54 64 00 51 11471 041031 63 00 51 56 43 57 11472 041032 62 62 45 43 64 77 11473 041033 041016 041025 11474 041034 000013 000014 11475 041035 041026 040643 11476 041036 041021 041022 11477 041037 64 45 63 64 00 41 11478 041040 22 00 15 00 62 45 11479 041041 63 65 54 64 00 51 11480 041042 63 00 51 56 43 57 11481 041043 62 62 45 43 64 77 11482 041044 041016 041025 11483 041045 000013 000014 11484 041046 041037 040643 11485 041047 123456 765432 11486 041050 123456 765432 11487 041051 041047 041022 11488 041052 64 45 63 64 00 41 11489 041053 23 00 15 00 62 45 11490 041054 63 65 54 64 00 51 11491 041055 63 00 51 56 43 57 11492 041056 62 62 45 43 64 77 11493 041057 041016 041025 11494 041060 000013 000014 11495 041061 041052 040643 11496 041062 041022 041020 11497 041063 64 45 63 64 00 41 11498 041064 24 00 15 00 62 45 11499 041065 63 65 54 64 00 51 11500 041066 63 00 51 56 43 57 11501 041067 62 62 45 43 64 77 11502 041070 041016 041025 11503 041071 000013 000014 11504 041072 041063 040643 11505 041073 041022 041021 11506 041074 64 45 63 64 00 41 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0255 11507 041075 25 00 15 00 62 45 11508 041076 63 65 54 64 00 51 11509 041077 63 00 51 56 43 57 11510 041100 62 62 45 43 64 77 11511 041101 041016 041025 11512 041102 000013 000014 11513 041103 041074 040643 11514 041104 041022 041047 11515 041105 64 45 63 64 00 41 11516 041106 26 00 15 00 62 45 11517 041107 63 65 54 64 00 51 11518 041110 63 00 51 56 43 57 11519 041111 62 62 45 43 64 77 11520 041112 041016 041025 11521 041113 000013 000014 11522 041114 041105 040643 11523 041115 041022 041022 11524 041116 64 45 63 64 00 41 11525 041117 27 00 15 00 62 45 11526 041120 63 65 54 64 00 51 11527 041121 63 00 51 56 43 57 11528 041122 62 62 45 43 64 77 11529 041123 041016 041025 11530 041124 000013 000014 11531 041125 041116 040643 11532 041126 000000 000000 11533 041127 000000 000001 11534 041130 041126 041022 11535 041131 64 45 63 64 00 42 11536 041132 21 00 15 00 62 45 11537 041133 63 65 54 64 00 51 11538 041134 63 00 51 56 43 57 11539 041135 62 62 45 43 64 77 11540 041136 041016 041025 11541 041137 000013 000014 11542 041140 041131 040643 11543 041141 041022 041126 11544 041142 64 45 63 64 00 42 11545 041143 22 00 15 00 62 45 11546 041144 63 65 54 64 00 51 11547 041145 63 00 51 56 43 57 11548 041146 62 62 45 43 64 77 11549 041147 041016 041025 11550 041150 000013 000014 11551 041151 041142 040643 11552 041152 000000 000000 11553 041153 200000 000000 11554 041154 041152 041022 11555 041155 041022 041152 11556 041156 000000 000001 11557 041157 000000 000000 11558 041160 041156 041022 11559 041161 041022 041156 11560 041162 200000 000000 11561 041163 000000 000000 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-1 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0256 11562 041164 041162 041022 11563 041165 041022 041162 11564 041166 777777 777777 11565 041167 777777 777776 11566 041170 041166 041022 11567 041171 041022 041166 11568 041172 777777 777777 11569 041173 577777 777777 11570 041174 041172 041022 11571 041175 041022 041172 11572 041176 777777 777776 11573 041177 777777 777777 11574 041200 041176 041022 11575 041201 041022 041176 11576 041202 577777 777777 11577 041203 777777 777777 11578 041204 041202 041022 11579 041205 041022 041202 11580 041206 031327 031327 11581 041207 64 45 63 64 00 43 11582 041210 00 15 00 62 45 63 11583 041211 65 54 64 00 51 56 11584 041212 43 57 62 62 45 43 11585 041213 64 77 00 00 00 00 11586 041214 041016 041025 11587 041215 000014 000013 11588 041216 041207 040643 11589 041217 000000 000000 11590 041220 777777 777777 11591 041221 041217 041126 11592 041222 64 45 63 64 00 44 11593 041223 21 00 15 00 62 45 11594 041224 63 65 54 64 00 51 11595 041225 63 00 51 56 43 57 11596 041226 62 62 45 43 64 77 11597 041227 041016 041025 11598 041230 000013 000014 11599 041231 041222 040643 11600 041232 041126 041217 11601 041233 64 45 63 64 00 44 11602 041234 22 00 15 00 62 45 11603 041235 63 65 54 64 00 51 11604 041236 63 00 51 56 43 57 11605 041237 62 62 45 43 64 77 11606 041240 041016 041025 11607 041241 000013 000014 11608 041242 041233 040643 11609 041243 64 45 63 64 00 45 11610 041244 00 15 00 62 45 63 11611 041245 65 54 64 00 51 63 11612 041246 00 51 56 43 57 62 11613 041247 62 45 43 64 77 00 11614 041250 041016 041025 11615 041251 000013 000014 11616 041252 041243 040643 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-2 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0257 11617 041253 64 45 63 64 00 45 11618 041254 00 15 00 60 43 00 11619 041255 46 54 41 47 63 00 11620 041256 51 56 43 57 62 62 11621 041257 45 43 64 00 10 54 11622 041260 45 46 64 00 24 00 11623 041261 42 51 64 63 11 77 11624 041262 041016 041025 11625 041263 000014 031375 11626 041264 041253 040643 11627 041265 041016 041025 11628 041266 000014 031424 11629 041267 041253 040643 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11665 041333 041315 040643 11666 041334 033067 033071 11667 041335 041016 041025 11668 041336 000014 031713 11669 041337 041315 040643 11670 041340 033073 033075 11671 041341 777777 777777 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-3 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0258 11672 041342 777777 777777 11673 041343 041016 041025 11674 041344 000014 031741 11675 041345 041315 040643 11676 041346 033077 033101 11677 041347 041016 041025 11678 041350 000014 031767 11679 041351 041315 040643 11680 041352 033103 033105 11681 041353 041016 041025 11682 041354 000014 032015 11683 041355 041315 040643 11684 041356 033107 033111 11685 041357 777777 777776 11686 041360 777777 777776 11687 041361 64 45 63 64 00 46 11688 041362 22 00 15 00 62 45 11689 041363 63 65 54 64 00 51 11690 041364 63 00 51 56 43 57 11691 041365 62 62 45 43 64 77 11692 041366 041016 041025 11693 041367 000013 000014 11694 041370 041361 040643 11695 041371 300000 000000 11696 041372 64 45 63 64 00 46 11697 041373 22 00 15 00 60 43 11698 041374 00 46 54 41 47 63 11699 041375 00 51 56 43 57 62 11700 041376 62 45 43 64 00 10 11701 041377 54 45 46 64 00 24 11702 041400 00 42 51 64 63 11 11703 041401 77 00 00 00 00 00 11704 041402 041016 041025 11705 041403 000014 032043 11706 041404 041372 040643 11707 041405 033113 033115 11708 041406 041016 041025 11709 041407 000014 032071 11710 041410 041372 040643 11711 041411 033117 033121 11712 041412 041016 041025 11713 041413 000014 032117 11714 041414 041372 040643 11715 041415 033123 033125 11716 041416 041016 041025 11717 041417 000014 032145 11718 041420 041372 040643 11719 041421 033127 033131 11720 041422 041016 041025 11721 041423 000014 032173 11722 041424 041372 040643 11723 041425 033133 033135 11724 041426 041016 041025 11725 041427 000014 032221 11726 041430 041372 040643 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-4 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0259 11727 041431 033137 033141 11728 041432 000000 000001 11729 041433 000000 000001 11730 041434 64 45 63 64 00 46 11731 041435 23 00 15 00 62 45 11732 041436 63 65 54 64 00 51 11733 041437 63 00 51 56 43 57 11734 041440 62 62 45 43 64 77 11735 041441 041016 041025 11736 041442 000013 000014 11737 041443 041434 040643 11738 041444 64 45 63 64 00 46 11739 041445 23 00 15 00 60 43 11740 041446 00 46 54 41 47 63 11741 041447 00 51 56 43 57 62 11742 041450 62 45 43 64 00 10 11743 041451 54 45 46 64 00 24 11744 041452 00 42 51 64 63 11 11745 041453 77 00 00 00 00 00 11746 041454 041016 041025 11747 041455 000014 032247 11748 041456 041444 040643 11749 041457 033143 033145 11750 041460 041016 041025 11751 041461 000014 032275 11752 041462 041444 040643 11753 041463 033147 033151 11754 041464 041016 041025 11755 041465 000014 032323 11756 041466 041444 040643 11757 041467 033153 033155 11758 041470 041016 041025 11759 041471 000014 032351 11760 041472 041444 040643 11761 041473 033157 033161 11762 041474 041016 041025 11763 041475 000014 032377 11764 041476 041444 040643 11765 041477 033163 033165 11766 041500 041016 041025 11767 041501 000014 032425 11768 041502 041444 040643 11769 041503 033167 033171 11770 041504 64 45 63 64 00 46 11771 041505 24 00 15 00 62 45 11772 041506 63 65 54 64 00 51 11773 041507 63 00 51 56 43 57 11774 041510 62 62 45 43 64 77 11775 041511 041016 041025 11776 041512 000013 000014 11777 041513 041504 040643 11778 041514 64 45 63 64 00 46 11779 041515 24 00 15 00 60 43 11780 041516 00 46 54 41 47 63 11781 041517 00 51 56 43 57 62 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-5 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0260 11782 041520 62 45 43 64 00 10 11783 041521 54 45 46 64 00 24 11784 041522 00 42 51 64 63 11 11785 041523 77 00 00 00 00 00 11786 041524 041016 041025 11787 041525 000014 032453 11788 041526 041514 040643 11789 041527 033173 033175 11790 041530 041016 041025 11791 041531 000014 032501 11792 041532 041514 040643 11793 041533 033177 033201 11794 041534 041016 041025 11795 041535 000014 032527 11796 041536 041514 040643 11797 041537 033203 033205 11798 041540 041016 041025 11799 041541 000014 032555 11800 041542 041514 040643 11801 041543 033207 033211 11802 041544 041016 041025 11803 041545 000014 032603 11804 041546 041514 040643 11805 041547 033213 033215 11806 041550 041016 041025 11807 041551 000014 032631 11808 041552 041514 040643 11809 041553 033217 033221 11810 041554 64 45 63 64 00 46 11811 041555 25 00 15 00 62 45 11812 041556 63 65 54 64 00 51 11813 041557 63 00 51 56 43 57 11814 041560 62 62 45 43 64 77 11815 041561 041016 041025 11816 041562 000013 000014 11817 041563 041554 040643 11818 041564 64 45 63 64 00 46 11819 041565 25 00 15 00 60 43 11820 041566 00 46 54 41 47 63 11821 041567 00 51 56 43 57 62 11822 041570 62 45 43 64 00 10 11823 041571 54 45 46 64 00 24 11824 041572 00 42 51 64 63 11 11825 041573 77 00 00 00 00 00 11826 041574 041016 041025 11827 041575 000014 032657 11828 041576 041564 040643 11829 041577 033223 033225 11830 041600 041016 041025 11831 041601 000014 032705 11832 041602 041564 040643 11833 041603 033227 033231 11834 041604 041016 041025 11835 041605 000014 032733 11836 041606 041564 040643 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-6 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0261 11837 041607 033233 033235 11838 041610 041016 041025 11839 041611 000014 032761 11840 041612 041564 040643 11841 041613 033237 033241 11842 041614 041016 041025 11843 041615 000014 033007 11844 041616 041564 040643 11845 041617 033243 033245 11846 041620 041016 041025 11847 041621 000014 033035 11848 041622 041564 040643 11849 041623 033530 033532 11850 041624 64 45 63 64 00 47 11851 041625 00 15 00 62 45 63 11852 041626 65 54 64 00 51 63 11853 041627 00 51 56 43 57 62 11854 041630 62 45 43 64 77 00 11855 041631 041016 041025 11856 041632 000013 000014 11857 041633 041624 040643 11858 041634 500000 000000 11859 041635 64 45 63 64 00 47 11860 041636 00 15 00 60 43 00 11861 041637 46 54 41 47 63 00 11862 041640 51 56 43 57 62 62 11863 041641 45 43 64 00 10 54 11864 041642 45 46 64 00 24 00 11865 041643 42 51 64 63 11 77 11866 041644 041016 041025 11867 041645 000014 033254 11868 041646 041635 040643 11869 041647 033536 033540 11870 041650 041016 041025 11871 041651 000014 033302 11872 041652 041635 040643 11873 041653 033544 033546 11874 041654 041016 041025 11875 041655 000014 033330 11876 041656 041635 040643 11877 041657 033552 033554 11878 041660 041016 041025 11879 041661 000014 033356 11880 041662 041635 040643 11881 041663 033560 033562 11882 041664 600000 000000 11883 041665 041016 041025 11884 041666 000014 033404 11885 041667 041635 040643 11886 041670 033566 033570 11887 041671 041016 041025 11888 041672 000014 033432 11889 041673 041635 040643 11890 041674 033574 033576 11891 041675 041016 041025 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-7 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0262 11892 041676 000014 033460 11893 041677 041635 040643 11894 041700 033602 033604 11895 041701 041016 041025 11896 041702 000014 033506 11897 041703 041635 040643 11898 041704 44 63 65 42 00 64 11899 041705 45 63 64 77 00 00 11900 041706 041704 041025 11901 041707 000013 000014 11902 041710 041026 040672 11903 041711 041704 041025 11904 041712 000013 000014 11905 041713 041037 040672 11906 041714 041704 041025 11907 041715 000013 000014 11908 041716 041052 040672 11909 041717 654321 012346 11910 041720 777777 777777 11911 041721 654321 012346 11912 041722 041704 041025 11913 041723 000013 000014 11914 041724 041063 040672 11915 041725 400000 000000 11916 041726 654321 012346 11917 041727 400000 000000 11918 041730 041704 041025 11919 041731 000013 000014 11920 041732 041074 040672 11921 041733 654321 012345 11922 041734 654321 012346 11923 041735 041704 041025 11924 041736 000013 000014 11925 041737 041105 040672 11926 041740 777766 034012 11927 041741 64 45 63 64 00 42 11928 041742 00 15 00 62 45 63 11929 041743 65 54 64 00 51 56 11930 041744 43 57 62 62 45 43 11931 041745 64 77 00 00 00 00 11932 041746 041704 041025 11933 041747 000012 000013 11934 041750 041741 040672 11935 041751 64 45 63 64 00 42 11936 041752 00 15 00 60 43 00 11937 041753 46 54 41 47 63 00 11938 041754 51 56 43 57 62 62 11939 041755 45 43 64 00 10 54 11940 041756 45 46 64 00 24 00 11941 041757 42 51 64 63 11 77 11942 041760 041704 041025 11943 041761 000014 033752 11944 041762 041751 040672 11945 041763 034647 034651 11946 041764 64 45 63 64 00 43 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-8 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0263 11947 041765 21 00 15 00 62 45 11948 041766 63 65 54 64 00 51 11949 041767 63 00 51 56 43 57 11950 041770 62 62 45 43 64 77 11951 041771 041704 041025 11952 041772 000013 000014 11953 041773 041764 040672 11954 041774 034655 034657 11955 041775 034663 034665 11956 041776 034671 034673 11957 041777 034677 034701 11958 042000 034705 034707 11959 042001 034713 034715 11960 042002 64 45 63 64 00 43 11961 042003 22 00 15 00 62 45 11962 042004 63 65 54 64 00 51 11963 042005 63 00 51 56 43 57 11964 042006 62 62 45 43 64 77 11965 042007 041704 041025 11966 042010 000013 000014 11967 042011 042002 040672 11968 042012 034721 034723 11969 042013 034727 034731 11970 042014 034735 034737 11971 042015 034743 034745 11972 042016 034751 034753 11973 042017 034757 034761 11974 042020 64 45 63 64 00 43 11975 042021 23 00 15 00 62 45 11976 042022 63 65 54 64 00 51 11977 042023 63 00 51 56 43 57 11978 042024 62 62 45 43 64 77 11979 042025 041704 041025 11980 042026 000013 000014 11981 042027 042020 040672 11982 042030 034765 034767 11983 042031 034773 034775 11984 042032 035001 035003 11985 042033 035007 035011 11986 042034 035015 035017 11987 042035 035023 035025 11988 042036 777777 777775 11989 042037 777777 777777 11990 042040 777777 777775 11991 042041 64 45 63 64 00 43 11992 042042 24 00 15 00 62 45 11993 042043 63 65 54 64 00 51 11994 042044 63 00 51 56 43 57 11995 042045 62 62 45 43 64 77 11996 042046 041704 041025 11997 042047 000013 000014 11998 042050 042041 040672 11999 042051 035027 035031 12000 042052 035033 035035 12001 042053 035037 035041 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-9 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0264 12002 042054 035043 035045 12003 042055 035047 035051 12004 042056 035053 035055 12005 042057 000000 000003 12006 042060 000000 000000 12007 042061 000000 000003 12008 042062 64 45 63 64 00 43 12009 042063 25 00 15 00 62 45 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035137 12045 042127 042112 040672 12046 042130 035404 035406 12047 042131 041704 041025 12048 042132 000014 035166 12049 042133 042112 040672 12050 042134 035410 035412 12051 042135 041704 041025 12052 042136 000014 035215 12053 042137 042112 040672 12054 042140 035414 035416 12055 042141 377777 777777 12056 042142 377777 777777 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-10 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0265 12057 042143 041704 041025 12058 042144 000014 035244 12059 042145 042112 040672 12060 042146 035420 035422 12061 042147 041704 041025 12062 042150 000014 035273 12063 042151 042112 040672 12064 042152 035424 035426 12065 042153 041704 041025 12066 042154 000014 035322 12067 042155 042112 040672 12068 042156 035430 035432 12069 042157 041704 041025 12070 042160 000014 035351 12071 042161 042112 040672 12072 042162 44 55 65 54 00 64 12073 042163 45 63 64 77 00 00 12074 042164 000000 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045363 000013 000014 13738 045364 045353 040754 13739 045365 64 45 63 64 00 46 13740 045366 00 15 00 60 43 00 13741 045367 46 54 41 47 63 00 13742 045370 51 56 43 57 62 62 13743 045371 45 43 64 00 15 00 13744 045372 42 51 64 63 00 20 13745 045373 00 06 00 21 22 77 13746 045374 044073 041025 13747 045375 000014 040521 13748 045376 045365 040754 13749 045377 000000 000001 13750 045400 000000 000000 13751 045401 000000 000000 13752 045402 000000 000000 13753 045403 777777 777776 13754 045404 777777 777777 13755 045405 400000 000001 13756 045406 400000 000000 13757 045407 000000 000001 13758 045410 000000 000000 13759 045411 045377 040544 13760 045412 777777 777777 13761 045413 400000 000000 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-41 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0296 13762 045414 400000 000000 13763 045415 400000 000000 13764 045416 000000 000001 13765 045417 000000 000001 13766 045420 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045663 000000 000001 13930 045664 045656 040630 13931 045665 777777 777777 13932 045666 400000 000000 13933 045667 400000 000000 13934 045670 400000 000000 13935 045671 777777 777777 13936 045672 777777 777777 13937 045673 045665 040630 13938 045674 000000 000001 13939 045675 000000 000000 13940 045676 000000 000000 13941 045677 000000 000000 13942 045700 000000 000001 13943 045701 000000 000000 13944 045702 045674 040630 13945 045703 000000 000001 13946 045704 000000 000000 13947 045705 000000 000000 13948 045706 000000 000000 13949 045707 777777 777777 13950 045710 000000 000000 13951 045711 045703 040630 13952 045712 777777 777777 13953 045713 400000 000000 13954 045714 400000 000000 13955 045715 400000 000000 13956 045716 000000 000001 13957 045717 000000 000000 13958 045720 045712 040630 13959 045721 777777 777777 13960 045722 400000 000000 13961 045723 400000 000000 13962 045724 400000 000000 13963 045725 777777 777777 13964 045726 400000 000000 13965 045727 045721 040630 13966 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777777 777776 13997 045767 777777 777777 13998 045770 400000 000000 13999 045771 400000 000001 14000 045772 000000 000000 14001 045773 377777 777777 14002 045774 045766 040630 14003 045775 777777 777776 14004 045776 777777 777777 14005 045777 400000 000000 14006 046000 400000 000001 14007 046001 777777 777777 14008 046002 400000 000001 14009 046003 045775 040630 14010 046004 400000 000000 14011 046005 400000 000000 14012 046006 400000 000000 14013 046007 400000 000000 14014 046010 400000 000000 14015 046011 400000 000000 14016 046012 046004 040630 14017 046013 377777 777777 14018 046014 377777 777777 14019 046015 377777 777777 14020 046016 377777 777777 14021 046017 377777 777777 14022 046020 377777 777777 14023 046021 046013 040630 14024 046022 377777 777777 14025 046023 377777 777777 14026 046024 377777 777777 14027 046025 377777 777777 14028 046026 400000 000000 14029 046027 400000 000001 14030 046030 046022 040630 14031 046031 400000 000000 14032 046032 400000 000001 14033 046033 400000 000000 14034 046034 400000 000000 14035 046035 377777 777777 14036 046036 377777 777777 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-46 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0301 14037 046037 046031 040630 14038 046040 000000 000001 14039 046041 400000 000000 14040 046042 777777 777777 14041 046043 777777 777777 14042 046044 000000 000000 14043 046045 377777 777777 14044 046046 046040 040630 14045 046047 000000 000001 14046 046050 000000 000000 14047 046051 377777 777777 14048 046052 377777 777777 14049 046053 777777 777777 14050 046054 000000 000001 14051 046055 046047 040630 14052 046056 777777 777776 14053 046057 377777 777777 14054 046060 000000 000000 14055 046061 000000 000001 14056 046062 000000 000000 14057 046063 777777 777777 14058 046064 046056 040630 14059 046065 777777 777776 14060 046066 777777 777777 14061 046067 000000 000000 14062 046070 000000 000001 14063 046071 777777 777777 14064 046072 400000 000001 14065 046073 046065 040630 14066 046074 040502 040504 14067 046075 040544 040550 14068 046076 000000 040517 14069 046077 040630 040634 14070 046100 000000 040565 14071 046101 41 65 47 45 56 44 14072 046102 32 00 00 77 00 00 14073 046103 41 44 44 45 56 44 14074 046104 32 00 00 77 00 00 14075 046105 62 45 63 65 54 64 14076 046106 32 00 00 77 00 00 14077 046107 55 51 56 65 45 56 14078 046110 44 32 00 00 00 00 14079 046111 00 77 00 00 00 00 14080 046112 63 65 42 64 62 41 14081 046113 50 45 56 44 32 00 14082 046114 00 77 00 00 00 00 14083 046115 62 45 63 65 54 64 14084 046116 32 00 00 00 00 00 14085 046117 00 77 00 00 00 00 14086 046120 55 65 54 64 51 60 14087 046121 54 51 43 41 56 44 14088 046122 32 00 00 77 00 00 14089 046123 55 65 54 64 51 60 14090 046124 54 51 45 62 32 00 14091 046125 00 00 00 77 00 00 DSKCF DECSYSTEM 2020 ADVANCED INSTRUCTION DIAGNOSTIC #6, VER 0,3 MACRO %53(1020) 15:50 26-Sep-79 Page 1-47 STOR KSM 18-Sep-79 17:06 *STOR* RESERVED STORAGE, SEPTEMBER 1979 SEQ 0302 14092 046126 62 45 63 65 54 64 14093 046127 32 00 00 00 00 00 14094 046130 00 00 00 77 00 00 14095 046131 44 51 66 51 44 45 14096 046132 56 44 32 00 00 77 14097 046133 44 51 66 51 63 57 14098 046134 62 32 00 00 00 77 14099 046135 61 65 57 64 51 45 14100 046136 56 64 32 00 00 77 14101 046137 00 00 62 45 55 41 14102 046140 51 56 44 45 62 32 14103 046141 00 00 77 00 00 00 14104 LIST 14105 051403 000000 000000 ENDSLD: 0 14106 14107 IFDEF DEBUG,< 14108 051404 PATCH: BLOCK DEBUG ;PATCHING AREA 14109 > 14110 14111 ;PROGRAM VARIABLES 14112 051434 VAR 14113 14114 IFDEF PGMEND,< 14115 051434 000000 000000 END: 0 14116 030000 END BEGIN > NO ERRORS DETECTED PROGRAM BREAK IS 000000 ABSOLUTE BREAK IS 051435 CPU TIME USED 01:14.863 78P CORE USED ABORT 290# AC1 35# 943 944 948 951 955 968 969 973 976 980 993 994 998 SEQ 0303 1001 1005 1018 1019 1023 1026 1030 1043 1044 1048 1051 1055 1068 1069 1073 1076 1080 1093 1094 1098 1101 1105 1172 1173 1177 1180 1184 1193 1195 1199 1202 1206 1229 1230 1234 1237 1241 1250 1252 1256 1259 1263 1286 1287 1291 1294 1298 1307 1309 1313 1316 1320 1343 1344 1348 1351 1355 1364 1366 1370 1373 1377 1400 1401 1405 1408 1412 1421 1423 1427 1430 1434 1457 1458 1462 1465 1469 1478 1480 1484 1487 1491 1514 1515 1519 1522 1526 1535 1537 1541 1544 1548 1571 1572 1576 1579 1583 1592 1594 1598 1601 1605 1635 1640 1642 1643 1644 1646 1649 1652 1656 1670 1686 1687 1691 1694 1698 1711 1712 1716 1719 1723 1770 1774 1783 1786 1790 1815 1819 1828 1831 1835 1860 1864 1873 1876 1880 1905 1909 1918 1921 1925 1950 1954 1963 1966 1970 1995 1999 2008 2011 2015 2114 2116 2127 2130 2134 2162 2164 2175 2178 2182 2210 2212 2223 2226 2230 2258 2260 2271 2274 2278 2306 2308 2319 2322 2326 2354 2356 2367 2370 2374 2421 2423 2432 2435 2439 2466 2468 2477 2480 2484 2511 2513 2522 2525 2529 2556 2558 2567 2570 2574 2601 2603 2612 2615 2619 2646 2648 2657 2660 2664 2711 2713 2722 2725 2729 2756 2758 2767 2770 2774 2801 2803 2812 2815 2819 2846 2848 2857 2860 2864 2891 2893 2902 2905 2909 2936 2938 2947 2950 2954 3001 3003 3012 3015 3019 3046 3048 3057 3060 3064 3091 3093 3102 3105 3109 3136 3138 3147 3150 3154 3181 3183 3192 3195 3199 3226 3228 3237 3240 3244 3291 3293 3302 3305 3309 3336 3338 3347 3350 3354 3381 3383 3392 3395 3399 3426 3428 3437 3440 3444 3471 3473 3482 3485 3489 3516 3518 3527 3530 3534 3735 3737 3746 3749 3753 3780 3782 3791 3794 3798 3825 3827 3836 3839 3843 3870 3872 3881 3884 3888 3915 3917 3926 3929 3933 3960 3962 3971 3974 3978 4005 4007 4016 4019 4023 4050 4052 4061 4064 4068 4163 4164 4168 4171 4175 4188 4189 4193 4196 4200 4213 4214 4218 4221 4225 4238 4239 4243 4246 4250 4263 4264 4268 4271 4275 4288 4289 4293 4296 4300 4344 4371 4375 4380 4387 4390 4394 4499 4500 4504 4507 4511 4526 4527 4531 4534 4538 4553 4554 4558 4561 4565 4580 4581 4585 4588 4592 4607 4608 4612 4615 4619 4634 4635 4639 4642 4646 4678 4679 4683 4686 4690 4705 4706 4710 4713 4717 4732 4733 4737 4740 4744 4759 4760 4764 4767 4771 4786 4787 4791 4794 4798 4813 4814 4818 4821 4825 4857 4858 4862 4865 4869 4884 4885 4889 4892 4896 4911 4912 4916 4919 4923 4938 4939 4943 4946 4950 4965 4966 4970 4973 4977 4992 4993 4997 5000 5004 5036 5037 5041 5044 5048 5063 5064 5068 5071 5075 5090 5091 5095 5098 5102 5117 5118 5122 5125 5129 5144 5145 5149 5152 5156 5171 5172 5176 5179 5183 5215 5216 5220 5223 5227 5242 5243 5247 5250 5254 5269 5270 5274 5277 5281 5296 5297 5301 5304 5308 5323 5324 5328 5331 5335 5350 5351 5355 5358 5362 5592 5594 5603 5606 5610 5640 5642 5651 5654 5658 5688 5690 5699 5702 5706 5736 5738 5747 5750 5754 5784 5786 5795 5798 5802 5832 5834 5843 5846 5850 5880 5882 5891 5894 5898 5928 5930 5939 5942 5946 6033 6034 6052 6053 6071 6072 6090 6091 6109 6110 6128 6129 6147 6148 6166 6167 6185 6186 6204 6205 6223 6224 6242 6243 6261 6262 6292 6293 6311 6312 6330 6331 6349 6350 6368 6369 6387 6388 6406 6407 6425 6426 6444 6445 6463 6464 6482 6483 6501 6502 6539 6540 6566 6567 6593 6595 6621 6623 6649 6650 6676 6677 6703 6705 6731 6732 6758 6759 6785 6787 6813 6814 6840 6841 6867 6869 6895 6897 6923 6924 6950 6951 6977 6979 7005 7006 7032 7033 7059 7061 7106 7107 7133 7134 7160 7162 7188 7190 7216 7217 7243 7244 7271 7273 7299 7300 7326 7327 7354 7356 7382 7383 7409 7410 7436 7438 7464 7466 7492 7493 7519 7520 7547 7549 7575 7576 7602 7603 7630 7632 7664 7665 7669 7675 7678 7681 7684 7686 7695 7722 7723 7749 7750 7776 7777 7803 7804 7840 7841 7867 7868 7894 7895 7921 7922 7948 7949 7975 7976 8002 8003 8029 8030 8056 8057 8083 8084 8110 8111 8137 8138 8164 8165 SEQ 0304 8191 8192 8218 8219 8245 8246 8272 8273 8299 8301 8327 8329 8355 8356 8382 8383 8409 8410 8436 8437 8463 8464 8503 8504 8523 8524 8553 8554 8573 8574 8607 8608 8627 8628 8647 8648 8667 8668 8687 8688 8707 8708 8727 8728 8747 8748 8767 8768 8787 8788 8807 8808 8827 8828 8847 8848 8867 8868 8887 8888 8907 8908 8927 8928 8947 8948 8967 8968 8987 8988 9007 9008 9027 9028 9047 9048 9067 9068 9102 9104 9132 9134 9161 9163 9191 9193 9221 9223 9251 9253 9282 9284 9312 9314 9342 9344 9372 9374 9402 9404 9444 9446 9473 9474 9501 9503 9530 9531 9558 9559 9586 9587 9614 9615 9642 9643 9670 9671 9698 9699 9726 9727 9754 9755 9782 9783 9810 9811 9838 9839 9866 9867 9911 9912 9939 9940 9967 9968 9995 9996 10024 10026 10054 10056 10083 10085 10113 10115 10183 10184 10211 10212 10239 10240 10267 10268 10295 10296 10323 10324 10351 10352 10379 10380 10407 10408 10435 10436 10463 10464 10491 10492 10519 10520 10547 10548 10575 10576 10603 10604 10631 10632 10659 10660 10687 10689 10716 10717 10744 10745 10772 10773 10800 10801 10828 10829 10856 10857 10884 10885 10913 10915 10942 10944 10971 10972 11000 11001 11029 11030 11058 11059 11087 11088 11117 11118 11122 11128 11132 11136 11140 11143 11165 11166 11170 11176 11180 11184 11188 11191 11225 11226 11227 11228 11232 11247 11251 11255 11259 11262 11270 11271 11272 11311 11314 11348 11351 11385 11388 11391 11394 11436 11439 11444 11447 ACONE 1748 2037# ACONF1 2087 3557# ACONF2 2399 3581# ACONF3 2689 3606# ACONF4 2979 3630# ACONF5 3269 3655# ACONG 3709 3733 3778 3823 3868 3913 3958 4003 4048 4094# ADADDI 1665 1669 1670# ADATA 1640 1641 1644 1667# AENDB 1617# AENDD 2035 2061# AENDF 3555 3679# AENDG 4088 4142# AERR 1650 1655# AERRC 1653 1657# ALEFT 1166# 1171 1172 1177 1185 1194 1195 1199 1207 1223# 1228 1229 1234 1242 1251 1252 1256 1264 1280# 1285 1286 1291 1299 1308 1309 1313 1321 1337# 1342 1343 1348 1356 1365 1366 1370 1378 1394# 1396 1396# 1399 1400 1405 1413 1422 1423 1427 1435 1451# 1453 1453# 1456 1457 1462 1470 1479 1480 1484 1492 1508# 1510 1510# 1513 1514 1519 1527 1536 1537 1541 1549 1565# 1567 1567# 1570 1571 1576 1584 1593 1594 1598 1606 ALOOP 1637# 1664 ALTMGO 640# APRINT 958 983 1008 1033 1058 1083 1108 1187 1209 1244 1266 1301 1323 1358 1380 1415 1437 1472 1494 1529 1551 1586 1608 1658 1701 1726 1793 1804 1838 1849 1883 1894 1928 1939 1973 1984 2018 2029 2137 2149 2185 2197 2233 2245 2281 2293 2329 2341 2377 2389 2442 2454 2487 2499 2532 2544 2577 2589 2622 2634 2667 2679 2732 2744 2777 2789 2822 2834 2867 2879 2912 2924 2957 2969 3022 3034 3067 3079 3112 3124 3157 3169 3202 3214 3247 3259 3312 3324 3357 3369 3402 3414 3447 3459 3492 3504 3537 3549 3756 3767 3801 3812 3846 3857 3891 3902 3936 3947 3981 3992 4026 4037 4071 4082 11287# ARIGHT 1167# 1171 1172 1180 1185 1194 1195 1202 1207 1224# 1228 1229 1237 1242 1251 1252 1259 1264 1281# 1285 1286 1294 1299 1308 1309 1316 1321 1338# SEQ 0305 1342 1343 1351 1356 1365 1366 1373 1378 1395# 1397 1397# 1399 1400 1408 1413 1422 1423 1430 1435 1452# 1454 1454# 1456 1457 1465 1470 1479 1480 1487 1492 1509# 1511 1511# 1513 1514 1522 1527 1536 1537 1544 1549 1566# 1568 1568# 1570 1571 1579 1584 1593 1594 1601 1606 AROV 554# 6548 6575 6603 6631 6658 6685 6713 6740 6767 6795 6822 6849 6877 6905 6932 6959 6987 7014 7041 7069 7115 7142 7170 7198 7225 7252 7281 7308 7335 7364 7391 7418 7446 7474 7501 7528 7557 7584 7611 7640 7731 7758 7785 7812 7849 7876 7903 7930 7957 7984 8011 8038 8065 8092 8119 8146 8173 8200 8227 8254 8281 8309 8337 8364 8391 8418 8445 8472 9112 9142 9171 9201 9231 9261 9292 9322 9352 9382 9412 9454 9482 9511 9539 9567 9595 9623 9651 9679 9707 9735 9763 9791 9819 9847 9875 9920 9948 9976 10004 10034 10064 10093 10123 10192 10220 10248 10276 10304 10332 10360 10388 10416 10444 10472 10500 10528 10556 10584 10612 10640 10668 10697 10725 10753 10781 10809 10837 10865 10893 10923 10952 10980 11009 11038 11067 11096 AROVTP 554# AROVU 554# ASHIFT 1637 1638 1669# AST 755# ATEST1 942# 959 ATEST2 967# 984 ATEST3 992# 1009 ATEST4 1017# 1034 ATEST5 1042# 1059 ATEST6 1067# 1084 ATEST7 1092# 1109 ATSIN 756# ATSTD1 1685# 1702 ATSTD2 1710# 1727 BDONE 4356 4454# BDONEI 4406 4409 4413 4420# BEGEND 636# 11105 BEGIN 55 56 57 58 59 505 506 567# 14116 BEGIN1 583# 637 BELL 759# BERROR 4388 4393# BFLAG 4391 4400# BFSET 4408# 4415 4418 BIS 554# BSAME 4404 4411# BTESTB 4371# 4397 4429 CCA 554# CHAIN 310# CHNOFF 554# CHNON 554# CLKU 554# CLOCKF 622# CNT 38# 1634 1637 1662 1663 CNTLC 639# CNTRP 554# CNUM 1748# 1769 1769# 1770 1772 1783 1786 1791 1814 1814# 1815 1817 1828 1831 1836 1859 1859# 1860 1862 1873 1876 1881 1904 1904# 1905 1907 1918 1921 1926 1949 1949# 1950 1952 1963 1966 1971 1994 1994# 1995 1997 2008 2011 2016 2087# 2112 2112# 2113 2114 2116 2160 2160# 2161 2162 2164 2208 2208# SEQ 0306 2209 2210 2212 2256 2256# 2257 2258 2260 2304 2304# 2305 2306 2308 2352 2352# 2353 2354 2356 2399# 2419 2419# 2420 2421 2423 2464 2464# 2465 2466 2468 2509 2509# 2510 2511 2513 2554 2554# 2555 2556 2558 2599 2599# 2600 2601 2603 2644 2644# 2645 2646 2648 2689# 2709 2709# 2710 2711 2713 2754 2754# 2755 2756 2758 2799 2799# 2800 2801 2803 2844 2844# 2845 2846 2848 2889 2889# 2890 2891 2893 2934 2934# 2935 2936 2938 2979# 2999 2999# 3000 3001 3003 3044 3044# 3045 3046 3048 3089 3089# 3090 3091 3093 3134 3134# 3135 3136 3138 3179 3179# 3180 3181 3183 3224 3224# 3225 3226 3228 3269# 3289 3289# 3290 3291 3293 3334 3334# 3335 3336 3338 3379 3379# 3380 3381 3383 3424 3424# 3425 3426 3428 3469 3469# 3470 3471 3473 3514 3514# 3515 3516 3518 3709# 3731 3731# 3733 3734 3735 3737 3746 3749 3754 3776 3776# 3778 3779 3780 3782 3791 3794 3799 3821 3821# 3823 3824 3825 3827 3836 3839 3844 3866 3866# 3868 3869 3870 3872 3881 3884 3889 3911 3911# 3913 3914 3915 3917 3926 3929 3934 3956 3956# 3958 3959 3960 3962 3971 3974 3979 4001 4001# 4003 4004 4005 4007 4016 4019 4024 4046 4046# 4048 4049 4050 4052 4061 4064 4069 4480# 4497 4497# 4498 4499 4500 4504 4507 4512 4524 4524# 4525 4526 4527 4531 4534 4539 4551 4551# 4552 4553 4554 4558 4561 4566 4578 4578# 4579 4580 4581 4585 4588 4593 4605 4605# 4606 4607 4608 4612 4615 4620 4632 4632# 4633 4634 4635 4639 4642 4647 4659# 4676 4676# 4677 4678 4679 4683 4686 4691 4703 4703# 4704 4705 4706 4710 4713 4718 4730 4730# 4731 4732 4733 4737 4740 4745 4757 4757# 4758 4759 4760 4764 4767 4772 4784 4784# 4785 4786 4787 4791 4794 4799 4811 4811# 4812 4813 4814 4818 4821 4826 4838# 4855 4855# 4856 4857 4858 4862 4865 4870 4882 4882# 4883 4884 4885 4889 4892 4897 4909 4909# 4910 4911 4912 4916 4919 4924 4936 4936# 4937 4938 4939 4943 4946 4951 4963 4963# 4964 4965 4966 4970 4973 4978 4990 4990# 4991 4992 4993 4997 5000 5005 5017# 5034 5034# 5035 5036 5037 5061 5061# 5062 5063 5064 5088 5088# 5089 5090 5091 5115 5115# 5116 5117 5118 5142 5142# 5143 5144 5145 5169 5169# 5170 5171 5172 5196# 5213 5213# 5214 5215 5216 5240 5240# 5241 5242 5243 5267 5267# 5268 5269 5270 5294 5294# 5295 5296 5297 5321 5321# 5322 5323 5324 5348 5348# 5349 5350 5351 5559# 5587 5587# 5591 5592 5594 5617 5635 5635# 5639 5640 5642 5665 5683 5683# 5687 5688 5690 5713 5731 5731# 5735 5736 5738 5761 5779 5779# 5783 5784 5786 5809 5827 5827# 5831 5832 5834 5857 5875 5875# 5879 5880 5882 5905 5923 5923# 5927 5928 5930 5953 COMMA 748# CONSW 623# CPOPJ 643# CPOPJ1 641# CRLF 440 441 743# CRLF2 444 445 745# CRY0 554# CRY1 554# CSHFLG 802# CSHMEM 803# CTRP 554# CYCL60 796# DCK 554# 9112 9142 9171 9201 9231 9261 9292 9322 9352 9382 9412 9454 9482 9511 9539 9567 9595 9623 9651 9679 9707 9735 9763 9791 9819 9847 9875 9920 9948 9976 10004 10034 10064 10093 10123 10192 10220 10248 10276 10304 10332 10360 10388 10416 10444 10472 10500 10528 10556 10584 10612 10640 10668 10697 10725 10753 10781 10809 10837 10865 10893 10923 10952 10980 11009 11038 11067 11096 DDTLNK 324# 581 DDTSRT 581# SEQ 0307 DEBUG 71# 14107 14108 DECVER 4# 10 16 602 DF22F 707# DIAGMN 570# DING 296# DOLLAR 762# DPRINT 8507 8527 8557 8577 8611 8631 8651 8671 8691 8711 8731 8751 8771 8791 8811 8831 8851 8871 8891 8911 8931 8951 8971 8991 9011 9031 9051 9071 9107 9115 9137 9145 9166 9174 9196 9204 9226 9234 9256 9264 9287 9295 9317 9325 9347 9355 9377 9385 9407 9415 9449 9457 9477 9485 9506 9514 9534 9542 9562 9570 9590 9598 9618 9626 9646 9654 9674 9682 9702 9710 9730 9738 9758 9766 9786 9794 9814 9822 9842 9850 9870 9878 9915 9923 9943 9951 9971 9979 9999 10007 10029 10037 10059 10067 10088 10096 10118 10126 10187 10196 10215 10224 10243 10252 10271 10280 10299 10308 10327 10336 10355 10364 10383 10392 10411 10420 10439 10448 10467 10476 10495 10504 10523 10532 10551 10560 10579 10588 10607 10616 10635 10644 10663 10672 10692 10701 10720 10729 10748 10757 10776 10785 10804 10813 10832 10841 10860 10869 10888 10897 10918 10927 10947 10956 10975 10984 11004 11013 11033 11042 11062 11071 11091 11100 11404# DSKUPD 607 EBIT0 554# EBIT1 554# EBIT10 554# EBIT11 554# EBIT12 554# EBIT13 554# EBIT14 554# EBIT15 554# EBIT2 554# EBIT3 554# EBIT4 554# EBIT5 554# EBIT6 554# EBIT7 554# EBIT8 554# EBIT9 554# END 14115# ENDFIX 882# ENDSLD 14105# ERMORE 656# EROLD 516 ERRPC 627# ERRTLS 628# ERSTOP 299# EXCASB 69# 605 EXIOT 554# FIVE 9088# 9221 9251 9342 9372 9402 FLAGL 1777# 1799 1804 1822# 1844 1849 1867# 1889 1894 1912# 1934 1939 1957# 1979 1984 2002# 2024 2029 2119# 2143 2149 2167# 2191 2197 2215# 2239 2245 2263# 2287 2293 2311# 2335 2341 2359# 2383 2389 2426# 2448 2454 2471# 2493 2499 2516# 2538 2544 2561# 2583 2589 2606# 2628 2634 2651# 2673 2679 2716# 2738 2744 2761# 2783 2789 2806# 2828 2834 2851# 2873 2879 2896# 2918 2924 2941# 2963 2969 3006# 3028 3034 3051# 3073 3079 3096# 3118 3124 3141# 3163 3169 3186# 3208 3214 3231# 3253 3259 3296# 3318 3324 3341# 3363 3369 3386# 3408 SEQ 0308 3414 3431# 3453 3459 3476# 3498 3504 3521# 3543 3549 3740# 3762 3767 3785# 3807 3812 3830# 3852 3857 3875# 3897 3902 3920# 3942 3947 3965# 3987 3992 4010# 4032 4037 4055# 4077 4082 4384# 4400 4422 4428 5597# 5620 5625 5645# 5668 5673 5693# 5716 5721 5741# 5764 5769 5789# 5812 5817 5837# 5860 5865 5885# 5908 5913 5933# 5956 5961 7672# 7695 FLAGS 3711# 3763 3808 3853 3898 3913# 3943 3988 4033 4078 5563# 5621 5669 5717 5765 5781# 5813 5829# 5861 5877# 5909 5925# 5957 FOUR 9087# 9102 9132 9191 9312 9342 9372 FOV 554# FOVU 554# FRDLNK 322# FSELNK 321# FXU 554# HYPEN 753# ILOOP 4360# 4432 IMINU 4357 4371 4402 4405 4411 4452# INHCSH 307# INHPAG 304# IOCLR 554# ISUBTR 4363 4372 4380 4401 4412 4414 4416 4417 4453# ITERAT 60# 600 ITRCH1 660# ITRCNT 600# JOB41 554# JOBAPR 554# JOBCNI 554# JOBDDT 554# JOBFF 554# JOBOPC 554# JOBREL 554# JOBREN 554# JOBSA 554# JOBSYM 554# JOBTPC 554# JOBUSY 554# JOBUUO 554# JOBVER 554# K 9273# 9282 KAIFLG 617# KLFLG 618# KNTRP 554# KTRP 554# LACLK 554# LACLKE 554# LAPRAL 554# LAPRP1 554# LAPRP2 554# LAPRP3 554# LAPRP4 554# LAPRP5 554# LAPRP6 554# LAPRP7 554# LCHNOF 554# SEQ 0309 LCHNON 554# LCNTXT 554# LCNXER 554# LCPAER 554# LCPSFT 554# LCPWRF 554# LDATAF 554# LDLNK 323# 570 572 LDNXER 554# LDPAER 554# LDPSFT 554# LDPWRF 554# LEBXMH 554# LEBXML 554# LENXER 554# LEPAER 554# LEPSFT 554# LEPWRF 554# LEUPFW 554# LEXCMP 554# LFLGCL 554# LFLGDS 554# LFLGEN 554# LFLGST 554# LFP 757# LINSTF 554# LINT 554# LIOCLR 554# LLACBL 554# LLDUSB 554# LMBXMH 554# LMBXML 554# LNXMEN 554# LNXMER 554# LOC 1165# 1188 1192# 1210 1222# 1245 1249# 1267 1279# 1302 1306# 1324 1336# 1359 1363# 1381 1393# 1416 1420# 1438 1450# 1473 1477# 1495 1507# 1530 1534# 1552 1564# 1587 1591# 1609 1659 1768# 1794 1805 1813# 1839 1850 1858# 1884 1895 1903# 1929 1940 1948# 1974 1985 1993# 2019 2030 2110# 2138 2150 2158# 2186 2198 2206# 2234 2246 2254# 2282 2294 2302# 2330 2342 2350# 2378 2390 2418# 2443 2455 2463# 2488 2500 2508# 2533 2545 2553# 2578 2590 2598# 2623 2635 2643# 2668 2680 2708# 2733 2745 2753# 2778 2790 2798# 2823 2835 2843# 2868 2880 2888# 2913 2925 2933# 2958 2970 2998# 3023 3035 3043# 3068 3080 3088# 3113 3125 3133# 3158 3170 3178# 3203 3215 3223# 3248 3260 3288# 3313 3325 3333# 3358 3370 3378# 3403 3415 3423# 3448 3460 3468# 3493 3505 3513# 3538 3550 3732# 3757 3768 3777# 3802 3813 3822# 3847 3858 3867# 3892 3903 3912# 3937 3948 3957# 3982 3993 4002# 4027 4038 4047# 4072 4083 4496# 4515 4523# 4542 4550# 4569 4577# 4596 4604# 4623 4631# 4650 4675# 4694 4702# 4721 4729# 4748 4756# 4775 4783# 4802 4810# 4829 4854# 4873 4881# 4900 4908# 4927 4935# 4954 4962# 4981 4989# 5008 5033# 5052 5060# 5079 5087# 5106 5114# 5133 5141# 5160 5168# 5187 5212# 5231 5239# 5258 5266# 5285 5293# 5312 5320# 5339 5347# 5366 5586# 5614 5626 5634# 5662 5674 5682# 5710 5722 5730# 5758 5770 5778# 5806 5818 5826# 5854 5866 5874# 5902 5914 5922# 5950 5962 7662# 7689 7696 LOOPER 298# SEQ 0310 LPAREN 554# LPARER 554# LPFWPC 554# LPGFTR 554# LPICH1 554# LPICH2 554# LPICH3 554# LPICH4 554# LPICH5 554# LPICH6 554# LPICH7 554# LPICHA 554# LPICLR 554# LPIIP1 554# LPIIP2 554# LPIIP3 554# LPIIP4 554# LPIIP5 554# LPIIP6 554# LPIIP7 554# LPIOFF 554# LPION 554# LPRCH1 554# LPRCH2 554# LPRCH3 554# LPRCH4 554# LPRCH5 554# LPRCH6 554# LPRCH7 554# LPRFMH 554# LPRFML 554# LPSFT 554# LPSFTE 554# LPWRFE 554# LPWRFL 554# LREQSE 554# LRQCLR 554# LSECMO 554# LSMODE 554# LSNXER 554# LSPAER 554# LSPSFT 554# LSPWRF 554# LTBASH 554# LTBASL 554# LTRPAE 554# LTRPEN 554# LUSCMP 554# LUUO 554# LUUO1 687 688 LUUO10 687 692 LUUO11 687 692 LUUO12 687 693 SEQ 0311 LUUO13 687 693 LUUO14 687 694 LUUO15 687 694 LUUO16 687 695 LUUO17 687 695 LUUO2 687 689 LUUO20 687 696 LUUO21 687 696 LUUO22 687 697 LUUO23 687 697 LUUO24 687 698 LUUO25 687 698 LUUO26 687 699 LUUO27 687 699 LUUO3 687 689 LUUO30 687 700 LUUO31 687 700 LUUO32 687 701 LUUO33 687 701 LUUO4 687 690 LUUO5 687 690 LUUO6 687 691 LUUO7 687 691 LUUOI 554# LWRITE 554# MAPNEW 708# MARGIN 630# MCAND 6033 6052 6071 6090 6109 6128 6147 6166 6185 6204 6223 6242 6261 6292 6311 6330 6349 6368 6387 6406 6425 6444 6463 6482 6501 6539 6566 6594 6622 6649 6676 6704 6731 6758 6786 6813 6840 6868 6896 6923 6950 6978 7005 7032 7060 7106 7133 7161 7189 7216 7243 7272 7299 7326 7355 7382 7409 7437 7465 7492 7519 7548 7575 7602 7631 7722 7749 7776 7803 7840 7867 7894 7921 7948 7975 8002 8029 8056 8083 8110 8137 8164 8191 8218 8245 8272 8300 8328 8355 8382 8409 8436 8463 11116 11117 11151# MCNVER 3# 10 16 602 MEMLOW 710# MEMMAP 608 MEMSIZ 711# MEMTOT 709# MERROR 11129 11133 11137 11143# MFLOC 6547 6551 6574 6578 6602 6606 6630 6634 6657 6661 6684 6688 6712 6716 6739 6743 6766 6770 6794 6798 6821 6825 6848 6852 6876 6880 6904 6908 6931 6935 6958 6962 6986 6990 7013 7017 7040 7044 7068 7072 7114 7118 7141 7145 7169 7173 7197 7201 7224 7228 7251 7255 7280 7284 7307 7311 7334 7338 7363 7367 7390 7394 7417 7421 7445 7449 7473 7477 7500 7504 7527 7531 7556 7560 7583 7587 7610 7614 7639 7643 7730 7734 7757 7761 7784 7788 7811 7815 7848 7852 7875 7879 7902 7906 7929 7933 7956 7960 7983 7987 8010 8014 8037 8041 8064 8068 8091 8095 8118 8122 8145 8149 8172 8176 8199 8203 8226 8230 8253 8257 8280 8284 8308 8312 8336 8340 8363 8367 8390 8394 8417 8421 8444 8448 8471 8475 11125# MINU 4344# 4345 4353 4355 4356 4357 4364 MINUS 752# MODDVC 306# SEQ 0312 MODDVL 505 505# 603 MODDVU 506 506# 604 MODLNK 325# 567 MONCTL 620# MONFLG 619# MONTEN 621# MONTYP 834# MOVERR 7676 7679 7682 7686# MOVOK 7685 7691# MOVRR 7691 7694# MPLIER 11116 11122 11152# MPRINT 6037 6056 6075 6094 6113 6132 6151 6170 6189 6208 6227 6246 6265 6296 6315 6334 6353 6372 6391 6410 6429 6448 6467 6486 6505 6543 6551 6570 6578 6598 6606 6626 6634 6653 6661 6680 6688 6708 6716 6735 6743 6762 6770 6790 6798 6817 6825 6844 6852 6872 6880 6900 6908 6927 6935 6954 6962 6982 6990 7009 7017 7036 7044 7064 7072 7110 7118 7137 7145 7165 7173 7193 7201 7220 7228 7247 7255 7276 7284 7303 7311 7330 7338 7359 7367 7386 7394 7413 7421 7441 7449 7469 7477 7496 7504 7523 7531 7552 7560 7579 7587 7606 7614 7635 7643 7688 7695 7726 7734 7753 7761 7780 7788 7807 7815 7844 7852 7871 7879 7898 7906 7925 7933 7952 7960 7979 7987 8006 8014 8033 8041 8060 8068 8087 8095 8114 8122 8141 8149 8168 8176 8195 8203 8222 8230 8249 8257 8276 8284 8304 8312 8332 8340 8359 8367 8386 8394 8413 8421 8440 8448 8467 8475 11361# MPVU 554# MRES 6034 6053 6072 6091 6110 6129 6148 6167 6186 6205 6224 6243 6262 6293 6312 6331 6350 6369 6388 6407 6426 6445 6464 6483 6502 6540 6567 6595 6623 6650 6677 6705 6732 6759 6787 6814 6841 6869 6897 6924 6951 6979 7006 7033 7061 7107 7134 7162 7190 7217 7244 7273 7300 7327 7356 7383 7410 7438 7466 7493 7520 7549 7576 7603 7632 7723 7750 7777 7804 7841 7868 7895 7922 7949 7976 8003 8030 8057 8084 8111 8138 8165 8192 8219 8246 8273 8301 8329 8356 8383 8410 8437 8464 11128 11132 11136 11140 11144 11153# MRET 11147 11148 11149 11154# 11195 11196 11197 11266 11267 11268 MSUBR 6035 6054 6073 6092 6111 6130 6149 6168 6187 6206 6225 6244 6263 6294 6313 6332 6351 6370 6389 6408 6427 6446 6465 6484 6503 6541 6568 6596 6624 6651 6678 6706 6733 6760 6788 6815 6842 6870 6898 6925 6952 6980 7007 7034 7062 7108 7135 7163 7191 7218 7245 7274 7301 7328 7357 7384 7411 7439 7467 7494 7521 7550 7577 7604 7633 7724 7751 7778 7805 7842 7869 7896 7923 7950 7977 8004 8031 8058 8085 8112 8139 8166 8193 8220 8247 8274 8302 8330 8357 8384 8411 8438 8465 11116# MTEST 11141 11147# MUUO 554# MUUOPC 554# NOPNT 294# NUM 907# 942 943 951 956 967 968 973 981 992 993 998 1001 1006 1017 1019 1026 1031 1042 1044 1048 1056 1067 1069 1073 1076 1081 4162 4163 4171 4176 4187 4188 4193 4201 4212 4213 4218 4221 4226 4237 4239 4246 4251 4262 4264 4268 4276 4287 4289 4293 4296 4301 6033 6052 6071 6090 6109 6128 6147 6166 6185 6204 6223 6242 6292 6311 6330 6349 6368 6387 6406 6425 6444 6463 6482 6501 8503 8523 8553 8573 NXMU 554# OBYTEF 11239 11241 11243 11270# OBYTET 11240 11242 11244 11273# SEQ 0313 OCON 11238 11246# ODEND 10183 10211 10239 10267 10295 10323 10351 10379 10407 10435 10463 10491 10519 10547 10575 10603 10631 10659 10687 10716 10744 10772 10800 10828 10856 10884 10914 10943 10971 11000 11029 11058 11087 11224 11225 11226 11277# OERROR 11248 11252 11256 11262# OFLOC 10191 10193 10196 10219 10221 10224 10247 10249 10252 10275 10277 10280 10303 10305 10308 10331 10333 10336 10359 10361 10364 10387 10389 10392 10415 10417 10420 10443 10445 10448 10471 10473 10476 10499 10501 10504 10527 10529 10532 10555 10557 10560 10583 10585 10588 10611 10613 10616 10639 10641 10644 10667 10669 10672 10696 10698 10701 10724 10726 10729 10752 10754 10757 10780 10782 10785 10808 10810 10813 10836 10838 10841 10864 10866 10869 10892 10894 10897 10922 10924 10927 10951 10953 10956 10979 10981 10984 11008 11010 11013 11037 11039 11042 11066 11068 11071 11095 11097 11100 11235# OISOR 11224 11232 11278# OLOOP 4355# 4361 ONE 9084# 9161 9221 OPRSEL 308# OPTIME 722# ORES 10184 10212 10240 10268 10296 10324 10352 10380 10408 10436 10464 10492 10520 10548 10576 10604 10632 10660 10689 10717 10745 10773 10801 10829 10857 10885 10915 10944 10972 11001 11030 11059 11088 11227 11228 11247 11251 11255 11259 11263 11273 11274 11275 11279# ORET 11280# OSUBR 10185 10213 10241 10269 10297 10325 10353 10381 10409 10437 10465 10493 10521 10549 10577 10605 10633 10661 10690 10718 10746 10774 10802 10830 10858 10886 10916 10945 10973 11002 11031 11060 11089 11224# OTEST 11260 11266# P 351 352 353 354 554# 642 PAG 554# PALERS 300# PAREA1 61# 598 PAREA2 62# 599 PAREA3 63# 596 PAREA4 64# 597 PAREA5 65# 609 PAREA6 66# 610 PAREA7 609# PAREA8 610# PARU 554# PASCNT 624# PATCH 14108# PDEND 8503 8523 8553 8573 8607 8627 8647 8667 8687 8707 8727 8747 8767 8787 8807 8827 8847 8867 8887 8907 8927 8947 8967 8987 9007 9027 9047 9067 9103 9133 9162 9192 9222 9252 9283 9313 9343 9373 9403 9445 9473 9502 9530 9558 9586 9614 9642 9670 9698 9726 9754 9782 9810 9838 9866 9911 9939 9967 9995 10025 10055 10084 10114 11164 11165 11166 11199# PDISF 719# PDLOVU 554# PDOVTP 554# PERIOD 749# PERROR 11177 11181 11185 11191# PFLOC 9111 9115 9141 9145 9170 9174 9200 9204 9230 9234 9260 9264 9291 9295 9321 9325 9351 9355 9381 9385 9411 9415 9453 9457 9481 9485 9510 9514 SEQ 0314 9538 9542 9566 9570 9594 9598 9622 9626 9650 9654 9678 9682 9706 9710 9734 9738 9762 9766 9790 9794 9818 9822 9846 9850 9874 9878 9919 9923 9947 9951 9975 9979 10003 10007 10033 10037 10063 10067 10092 10096 10122 10126 11173# PFSTRT 576# PGMEND 68# 14114 PGMNAM 601 887# PHALT 54 11105# PICHN1 554# PICHN2 554# PICHN3 554# PICHN4 554# PICHN5 554# PICHN6 554# PICHN7 554# PICHNA 554# PICLR 554# PIOFF 554# PION 554# PISOR 11164 11170 11200# PLIST 788# 788 PLISTE 788 790# PLISTS 789# PLUS 754# PNTENB 718# PNTEXT 597# PNTFLG 717# PNTINH 720# PNTLPT 295# PNTNAM 596# PNTRP 554# PNTSPC 721# PRES 8504 8524 8554 8574 8608 8628 8648 8668 8688 8708 8728 8748 8768 8788 8808 8828 8848 8868 8888 8908 8928 8948 8968 8988 9008 9028 9048 9068 9104 9134 9163 9193 9223 9253 9284 9314 9344 9374 9404 9446 9474 9503 9531 9559 9587 9615 9643 9671 9699 9727 9755 9783 9811 9839 9867 9912 9940 9968 9996 10026 10056 10085 10115 11176 11180 11184 11188 11192 11201# PRET 11202# PSUBR 8505 8525 8555 8575 8609 8629 8649 8669 8689 8709 8729 8749 8769 8789 8809 8829 8849 8869 8889 8909 8929 8949 8969 8989 9009 9029 9049 9069 9105 9135 9164 9194 9224 9254 9285 9315 9345 9375 9405 9447 9475 9504 9532 9560 9588 9616 9644 9672 9700 9728 9756 9784 9812 9840 9868 9913 9941 9969 9997 10027 10057 10086 10116 11164# PTEST 11189 11195# PTRP 554# PVPAGI 815# QUEST 760# RADIX 763# RADLSC 765# RADLSP 764# RANDBS 598# REENTR 578# RELIAB 302# SEQ 0315 REP 1133# 1164 1164# 1166 1167 1214 1221 1221# 1223 1224 1271 1278 1278# 1280 1281 1328 1335 1335# 1337 1338 1385 1386# 1392 1392# 1394 1395 1442 1449 1449# 1451 1452 1499 1506 1506# 1508 1509 1556 1563 1563# 1565 1566 1613 1614# 2088# 2111 2111# 2122 2123 2159 2159# 2170 2171 2207 2207# 2218 2219 2255 2255# 2266 2267 2303 2303# 2314 2315 2351 2351# 2362 2363 5561# 5588 5588# 5589 5636 5636# 5637 5684 5684# 5685 5732 5732# 5733 5780 5780# 5781 5828 5828# 5829 5876 5876# 5877 5924 5924# 5925 REPP 1134# 1168 1225 1282 1339 1385# 1396 1453 1510 1567 1613# REPT 554# REPT1 554# REPTU 676# REQSET 554# RESRT1 653# RESRT2 654# RESULT 5562# 5603 5606 5611 5651 5654 5659 5699 5702 5707 5747 5750 5755 5782# 5795 5798 5803 5830# 5843 5846 5851 5878# 5891 5894 5899 5926# 5939 5942 5947 RETURN 585# RLEFT 2122# 2127 2135 2170# 2175 2183 2218# 2223 2231 2266# 2271 2279 2314# 2319 2327 2362# 2367 2375 RRIGHT 2123# 2130 2135 2171# 2178 2183 2219# 2226 2231 2267# 2274 2279 2315# 2322 2327 2363# 2370 2375 RSTART 291# RTP 758# RUNFLG 625# SADR1 49# 574 SADR10 58# 590 SADR11 59# 591 SADR2 50# 576 SADR3 51# 578 SADR4 52# SADR5 53# 639 SADR6 54# 640 SADR7 55# 587 SADR8 56# 588 SADR9 57# 589 SBINIT 364 584# SCONC1 4480 5373# SCONC2 4659 5410# SCONC3 4838 5447# SCONC4 5017 5484# SCONC5 5196 5508# SCOND 5559 5973# SCOPE 677# SCR0 40# 41 42 43 4346 4346# 4372 4373 4375 4376 4387 4393 4396 4401 4402 4403 4411 4412 4414 SCR1 41# 947 950 955 956 958 972 975 980 981 983 997 1000 1005 1006 1008 1022 1025 1030 1031 1033 1047 1050 1055 1056 1058 1072 1075 1080 1081 1083 1097 1100 1105 1106 1108 1176 1179 1184 1185 1187 1198 1201 1206 1207 1209 1233 1236 1241 1242 1244 1255 1258 1263 1264 1266 1290 1293 1298 1299 1301 1312 1315 1320 1321 1323 1347 1350 1355 1356 1358 1369 1372 1377 1378 1380 1404 1407 1412 1413 1415 1426 1429 1434 1435 1437 1461 1464 1469 1470 1472 1483 1486 1491 1492 1494 1518 1521 SEQ 0316 1526 1527 1529 1540 1543 1548 1549 1551 1575 1578 1583 1584 1586 1597 1600 1605 1606 1608 1648 1651 1655 1656 1658 1690 1693 1698 1699 1701 1715 1718 1723 1724 1726 1782 1785 1790 1791 1793 1799 1801 1802 1827 1830 1835 1836 1838 1844 1846 1847 1872 1875 1880 1881 1883 1889 1891 1892 1917 1920 1925 1926 1928 1934 1936 1937 1962 1965 1970 1971 1973 1979 1981 1982 2007 2010 2015 2016 2018 2024 2026 2027 2126 2129 2134 2135 2137 2143 2145 2146 2174 2177 2182 2183 2185 2191 2193 2194 2222 2225 2230 2231 2233 2239 2241 2242 2270 2273 2278 2279 2281 2287 2289 2290 2318 2321 2326 2327 2329 2335 2337 2338 2366 2369 2374 2375 2377 2383 2385 2386 2431 2434 2439 2440 2442 2448 2450 2451 2476 2479 2484 2485 2487 2493 2495 2496 2521 2524 2529 2530 2532 2538 2540 2541 2566 2569 2574 2575 2577 2583 2585 2586 2611 2614 2619 2620 2622 2628 2630 2631 2656 2659 2664 2665 2667 2673 2675 2676 2721 2724 2729 2730 2732 2738 2740 2741 2766 2769 2774 2775 2777 2783 2785 2786 2811 2814 2819 2820 2822 2828 2830 2831 2856 2859 2864 2865 2867 2873 2875 2876 2901 2904 2909 2910 2912 2918 2920 2921 2946 2949 2954 2955 2957 2963 2965 2966 3011 3014 3019 3020 3022 3028 3030 3031 3056 3059 3064 3065 3067 3073 3075 3076 3101 3104 3109 3110 3112 3118 3120 3121 3146 3149 3154 3155 3157 3163 3165 3166 3191 3194 3199 3200 3202 3208 3210 3211 3236 3239 3244 3245 3247 3253 3255 3256 3301 3304 3309 3310 3312 3318 3320 3321 3346 3349 3354 3355 3357 3363 3365 3366 3391 3394 3399 3400 3402 3408 3410 3411 3436 3439 3444 3445 3447 3453 3455 3456 3481 3484 3489 3490 3492 3498 3500 3501 3526 3529 3534 3535 3537 3543 3545 3546 3745 3748 3753 3754 3756 3762 3764 3765 3790 3793 3798 3799 3801 3807 3809 3810 3835 3838 3843 3844 3846 3852 3854 3855 3880 3883 3888 3889 3891 3897 3899 3900 3925 3928 3933 3934 3936 3942 3944 3945 3970 3973 3978 3979 3981 3987 3989 3990 4015 4018 4023 4024 4026 4032 4034 4035 4060 4063 4068 4069 4071 4077 4079 4080 4167 4170 4175 4176 4178 4192 4195 4200 4201 4203 4217 4220 4225 4226 4228 4242 4245 4250 4251 4253 4267 4270 4275 4276 4278 4292 4295 4300 4301 4303 4374 4390 4394 4396 4417 4422 4424 4425 4503 4506 4511 4512 4514 4530 4533 4538 4539 4541 4557 4560 4565 4566 4568 4584 4587 4592 4593 4595 4611 4614 4619 4620 4622 4638 4641 4646 4647 4649 4682 4685 4690 4691 4693 4709 4712 4717 4718 4720 4736 4739 4744 4745 4747 4763 4766 4771 4772 4774 4790 4793 4798 4799 4801 4817 4820 4825 4826 4828 4861 4864 4869 4870 4872 4888 4891 4896 4897 4899 4915 4918 4923 4924 4926 4942 4945 4950 4951 4953 4969 4972 4977 4978 4980 4996 4999 5004 5005 5007 5040 5043 5048 5049 5051 5067 5070 5075 5076 5078 5094 5097 5102 5103 5105 5121 5124 5129 5130 5132 5148 5151 5156 5157 5159 5175 5178 5183 5184 5186 5219 5222 5227 5228 5230 5246 5249 5254 5255 5257 5273 5276 5281 5282 5284 5300 5303 5308 5309 5311 5327 5330 5335 5336 5338 5354 5357 5362 5363 5365 5602 5605 5610 5611 5613 5620 5622 5623 5650 5653 5658 5659 5661 5668 5670 5671 5698 5701 5706 5707 5709 5716 5718 5719 5746 5749 5754 5755 5757 5764 5766 5767 5794 5797 5802 5803 5805 5812 5814 5815 5842 5845 5850 5851 5853 5860 5862 5863 5890 5893 5898 5899 5901 5908 5910 5911 5938 5941 5946 5947 5949 5956 5958 5959 6037 6056 6075 6094 6113 6132 6151 6170 6189 6208 6227 6246 6265 6296 6315 6334 6353 6372 6391 6410 6429 6448 6467 6486 6505 6543 6570 6598 6626 6653 6680 6708 6735 6762 6790 6817 6844 6872 6900 6927 6954 6982 7009 7036 7064 7110 7137 7165 7193 7220 7247 7276 7303 7330 7359 7386 7413 7441 7469 7496 7523 7552 7579 7606 7635 7667 7677 7680 7683 7686 7688 7726 7753 7780 7807 7844 7871 7898 7925 7952 7979 8006 8033 8060 8087 8114 8141 8168 8195 8222 8249 8276 8304 8332 8359 8386 8413 8440 8467 8507 8527 8557 8577 8611 8631 SEQ 0317 8651 8671 8691 8711 8731 8751 8771 8791 8811 8831 8851 8871 8891 8911 8931 8951 8971 8991 9011 9031 9051 9071 9107 9137 9166 9196 9226 9256 9287 9317 9347 9377 9407 9449 9477 9506 9534 9562 9590 9618 9646 9674 9702 9730 9758 9786 9814 9842 9870 9915 9943 9971 9999 10029 10059 10088 10118 10187 10215 10243 10271 10299 10327 10355 10383 10411 10439 10467 10495 10523 10551 10579 10607 10635 10663 10692 10720 10748 10776 10804 10832 10860 10888 10918 10947 10975 11004 11033 11062 11091 11127 11131 11135 11139 11143 11144 11175 11179 11183 11187 11191 11192 11239 11240 11241 11242 11243 11244 11246 11250 11254 11258 11262 11263 11289 11290 11293 11294 11300 11301 11304 11305 11326 11327 11330 11331 11337 11338 11341 11342 11363 11364 11367 11368 11374 11375 11378 11379 11406 11407 11410 11411 11414 11415 11418 11419 11425 11426 11429 11430 SCR2 42# 955 958 980 983 1005 1008 1030 1033 1055 1058 1080 1083 1105 1108 1184 1187 1206 1209 1241 1244 1263 1266 1298 1301 1320 1323 1355 1358 1377 1380 1412 1415 1434 1437 1469 1472 1491 1494 1526 1529 1548 1551 1583 1586 1605 1608 1655 1658 1698 1701 1723 1726 1790 1793 1800 1801 1804 1835 1838 1845 1846 1849 1880 1883 1890 1891 1894 1925 1928 1935 1936 1939 1970 1973 1980 1981 1984 2015 2018 2025 2026 2029 2134 2137 2144 2145 2149 2182 2185 2192 2193 2197 2230 2233 2240 2241 2245 2278 2281 2288 2289 2293 2326 2329 2336 2337 2341 2374 2377 2384 2385 2389 2439 2442 2449 2450 2454 2484 2487 2494 2495 2499 2529 2532 2539 2540 2544 2574 2577 2584 2585 2589 2619 2622 2629 2630 2634 2664 2667 2674 2675 2679 2729 2732 2739 2740 2744 2774 2777 2784 2785 2789 2819 2822 2829 2830 2834 2864 2867 2874 2875 2879 2909 2912 2919 2920 2924 2954 2957 2964 2965 2969 3019 3022 3029 3030 3034 3064 3067 3074 3075 3079 3109 3112 3119 3120 3124 3154 3157 3164 3165 3169 3199 3202 3209 3210 3214 3244 3247 3254 3255 3259 3309 3312 3319 3320 3324 3354 3357 3364 3365 3369 3399 3402 3409 3410 3414 3444 3447 3454 3455 3459 3489 3492 3499 3500 3504 3534 3537 3544 3545 3549 3753 3756 3763 3764 3767 3798 3801 3808 3809 3812 3843 3846 3853 3854 3857 3888 3891 3898 3899 3902 3933 3936 3943 3944 3947 3978 3981 3988 3989 3992 4023 4026 4033 4034 4037 4068 4071 4078 4079 4082 4175 4178 4200 4203 4225 4228 4250 4253 4275 4278 4300 4303 4378 4389 4393 4394 4400 4408 4423 4424 4428 4511 4514 4538 4541 4565 4568 4592 4595 4619 4622 4646 4649 4690 4693 4717 4720 4744 4747 4771 4774 4798 4801 4825 4828 4869 4872 4896 4899 4923 4926 4950 4953 4977 4980 5004 5007 5048 5051 5075 5078 5102 5105 5129 5132 5156 5159 5183 5186 5227 5230 5254 5257 5281 5284 5308 5311 5335 5338 5362 5365 5610 5613 5621 5622 5625 5658 5661 5669 5670 5673 5706 5709 5717 5718 5721 5754 5757 5765 5766 5769 5802 5805 5813 5814 5817 5850 5853 5861 5862 5865 5898 5901 5909 5910 5913 5946 5949 5957 5958 5961 6037 6056 6075 6094 6113 6132 6151 6170 6189 6208 6227 6246 6265 6296 6315 6334 6353 6372 6391 6410 6429 6448 6467 6486 6505 6543 6547 6548 6551 6570 6574 6575 6578 6598 6602 6603 6606 6626 6630 6631 6634 6653 6657 6658 6661 6680 6684 6685 6688 6708 6712 6713 6716 6735 6739 6740 6743 6762 6766 6767 6770 6790 6794 6795 6798 6817 6821 6822 6825 6844 6848 6849 6852 6872 6876 6877 6880 6900 6904 6905 6908 6927 6931 6932 6935 6954 6958 6959 6962 6982 6986 6987 6990 7009 7013 7014 7017 7036 7040 7041 7044 7064 7068 7069 7072 7110 7114 7115 7118 7137 7141 7142 7145 7165 7169 7170 7173 7193 7197 7198 7201 7220 7224 7225 7228 7247 7251 7252 7255 7276 7280 7281 7284 7303 7307 7308 7311 7330 7334 7335 7338 7359 7363 7364 7367 7386 7390 7391 7394 7413 7417 7418 7421 7441 7445 7446 7449 7469 7473 7474 7477 7496 7500 7501 7504 7523 7527 7528 7531 7552 7556 7557 7560 7579 7583 7584 7587 7606 7610 7611 7614 7635 7639 7640 7643 7726 7730 7731 7734 7753 7757 7758 7761 7780 SEQ 0318 7784 7785 7788 7807 7811 7812 7815 7844 7848 7849 7852 7871 7875 7876 7879 7898 7902 7903 7906 7925 7929 7930 7933 7952 7956 7957 7960 7979 7983 7984 7987 8006 8010 8011 8014 8033 8037 8038 8041 8060 8064 8065 8068 8087 8091 8092 8095 8114 8118 8119 8122 8141 8145 8146 8149 8168 8172 8173 8176 8195 8199 8200 8203 8222 8226 8227 8230 8249 8253 8254 8257 8276 8280 8281 8284 8304 8308 8309 8312 8332 8336 8337 8340 8359 8363 8364 8367 8386 8390 8391 8394 8413 8417 8418 8421 8440 8444 8445 8448 8467 8471 8472 8475 8507 8527 8557 8577 8611 8631 8651 8671 8691 8711 8731 8751 8771 8791 8811 8831 8851 8871 8891 8911 8931 8951 8971 8991 9011 9031 9051 9071 9107 9111 9112 9115 9137 9141 9142 9145 9166 9170 9171 9174 9196 9200 9201 9204 9226 9230 9231 9234 9256 9260 9261 9264 9287 9291 9292 9295 9317 9321 9322 9325 9347 9351 9352 9355 9377 9381 9382 9385 9407 9411 9412 9415 9449 9453 9454 9457 9477 9481 9482 9485 9506 9510 9511 9514 9534 9538 9539 9542 9562 9566 9567 9570 9590 9594 9595 9598 9618 9622 9623 9626 9646 9650 9651 9654 9674 9678 9679 9682 9702 9706 9707 9710 9730 9734 9735 9738 9758 9762 9763 9766 9786 9790 9791 9794 9814 9818 9819 9822 9842 9846 9847 9850 9870 9874 9875 9878 9915 9919 9920 9923 9943 9947 9948 9951 9971 9975 9976 9979 9999 10003 10004 10007 10029 10033 10034 10037 10059 10063 10064 10067 10088 10092 10093 10096 10118 10122 10123 10126 10187 10191 10192 10193 10196 10215 10219 10220 10221 10224 10243 10247 10248 10249 10252 10271 10275 10276 10277 10280 10299 10303 10304 10305 10308 10327 10331 10332 10333 10336 10355 10359 10360 10361 10364 10383 10387 10388 10389 10392 10411 10415 10416 10417 10420 10439 10443 10444 10445 10448 10467 10471 10472 10473 10476 10495 10499 10500 10501 10504 10523 10527 10528 10529 10532 10551 10555 10556 10557 10560 10579 10583 10584 10585 10588 10607 10611 10612 10613 10616 10635 10639 10640 10641 10644 10663 10667 10668 10669 10672 10692 10696 10697 10698 10701 10720 10724 10725 10726 10729 10748 10752 10753 10754 10757 10776 10780 10781 10782 10785 10804 10808 10809 10810 10813 10832 10836 10837 10838 10841 10860 10864 10865 10866 10869 10888 10892 10893 10894 10897 10918 10922 10923 10924 10927 10947 10951 10952 10953 10956 10975 10979 10980 10981 10984 11004 11008 11009 11010 11013 11033 11037 11038 11039 11042 11062 11066 11067 11068 11071 11091 11095 11096 11097 11100 11143 11191 11262 SCR3 43# 942 967 992 1017 1042 1067 1092 1171 1194 1228 1251 1285 1308 1342 1365 1399 1422 1456 1479 1513 1536 1570 1593 1641 1685 1710 1772 1773 1817 1818 1862 1863 1907 1908 1952 1953 1997 1998 2113 2161 2209 2257 2305 2353 2420 2465 2510 2555 2600 2645 2710 2755 2800 2845 2890 2935 3000 3045 3090 3135 3180 3225 3290 3335 3380 3425 3470 3515 3734 3779 3824 3869 3914 3959 4004 4049 4162 4187 4212 4237 4262 4287 4364 4365 4498 4525 4552 4579 4606 4633 4677 4704 4731 4758 4785 4812 4856 4883 4910 4937 4964 4991 5035 5062 5089 5116 5143 5170 5214 5241 5268 5295 5322 5349 5591 5617 5639 5665 5687 5713 5735 5761 5783 5809 5831 5857 5879 5905 5927 5953 7692 7693 11116 11164 11224 11289 11300 11326 11337 11363 11374 11406 11425 SENDC 5371 5532# SENDD 5967 6005# SFSTRT 574# SLASH 761# SM10 865# 11237 SNTRP 554# SPACE 750# SPRINT 4178 4203 4228 4253 4278 4303 4396 4428 4514 4541 4568 4595 4622 4649 4693 4720 4747 4774 4801 4828 4872 4899 4926 4953 4980 5007 5051 5078 5105 5132 5159 5186 5230 5257 5284 5311 5338 5365 5613 5625 5661 5673 SEQ 0319 5709 5721 5757 5769 5805 5817 5853 5865 5901 5913 5949 5961 11324# SRTDDT 52 580# START 51 568 920# START1 587# START2 588# START3 589# START4 590# START5 591# STARTA 49 50 53 583 921# STEST1 4162# 4179 STEST2 4187# 4204 STEST3 4212# 4229 STEST4 4237# 4254 STEST5 4262# 4279 STEST6 4287# 4304 STRP 554# SUBLNK 326# 584 SUBT 4353 4358 4434# SUBTR 4345# 4358 4360 4361 4363 4365 SWPTAB 871# SWTEXR 599# SYSEXR 572# T 924# 958 983 1008 1033 1058 1083 1108 1187 1209 1244 1266 1301 1323 1358 1380 1415 1437 1472 1494 1529 1551 1586 1608 1658 1701 1726 1793 1804 1838 1849 1883 1894 1928 1939 1973 1984 2018 2029 2137 2149 2185 2197 2233 2245 2281 2293 2329 2341 2377 2389 2442 2454 2487 2499 2532 2544 2577 2589 2622 2634 2667 2679 2732 2744 2777 2789 2822 2834 2867 2879 2912 2924 2957 2969 3022 3034 3067 3079 3112 3124 3157 3169 3202 3214 3247 3259 3312 3324 3357 3369 3402 3414 3447 3459 3492 3504 3537 3549 3756 3767 3801 3812 3846 3857 3891 3902 3936 3947 3981 3992 4026 4037 4071 4082 4145# 4178 4203 4228 4253 4278 4303 4396 4428 4514 4541 4568 4595 4622 4649 4693 4720 4747 4774 4801 4828 4872 4899 4926 4953 4980 5007 5051 5078 5105 5132 5159 5186 5230 5257 5284 5311 5338 5365 5613 5625 5661 5673 5709 5721 5757 5769 5805 5817 5853 5865 5901 5913 5949 5961 6008# 6037 6056 6075 6094 6113 6132 6151 6170 6189 6208 6227 6246 6265 6296 6315 6334 6353 6372 6391 6410 6429 6448 6467 6486 6505 6543 6551 6570 6578 6598 6606 6626 6634 6653 6661 6680 6688 6708 6716 6735 6743 6762 6770 6790 6798 6817 6825 6844 6852 6872 6880 6900 6908 6927 6935 6954 6962 6982 6990 7009 7017 7036 7044 7064 7072 7110 7118 7137 7145 7165 7173 7193 7201 7220 7228 7247 7255 7276 7284 7303 7311 7330 7338 7359 7367 7386 7394 7413 7421 7441 7449 7469 7477 7496 7504 7523 7531 7552 7560 7579 7587 7606 7614 7635 7643 7688 7695 7726 7734 7753 7761 7780 7788 7807 7815 7844 7852 7871 7879 7898 7906 7925 7933 7952 7960 7979 7987 8006 8014 8033 8041 8060 8068 8087 8095 8114 8122 8141 8149 8168 8176 8195 8203 8222 8230 8249 8257 8276 8284 8304 8312 8332 8340 8359 8367 8386 8394 8413 8421 8440 8448 8467 8475 8481# 8507 8527 8557 8577 8611 8631 8651 8671 8691 8711 8731 8751 8771 8791 8811 8831 8851 8871 8891 8911 8931 8951 8971 8991 9011 9031 9051 9071 9107 9115 9137 9145 9166 9174 9196 9204 9226 9234 9256 9264 9287 9295 9317 9325 9347 9355 9377 9385 9407 9415 9449 9457 9477 9485 9506 9514 9534 9542 9562 9570 9590 9598 9618 9626 9646 9654 9674 9682 9702 9710 9730 9738 9758 9766 9786 9794 9814 9822 9842 9850 9870 9878 9915 9923 9943 9951 9971 9979 9999 10007 10029 10037 10059 10067 10088 10096 10118 10126 10187 SEQ 0320 10196 10215 10224 10243 10252 10271 10280 10299 10308 10327 10336 10355 10364 10383 10392 10411 10420 10439 10448 10467 10476 10495 10504 10523 10532 10551 10560 10579 10588 10607 10616 10635 10644 10663 10672 10692 10701 10720 10729 10748 10757 10776 10785 10804 10813 10832 10841 10860 10869 10888 10897 10918 10927 10947 10956 10975 10984 11004 11013 11033 11042 11062 11071 11091 11100 TAB 751# TEMP 1643 1649 1652 1655 1668# TESTPC 626# THREE 9086# 9102 9132 9161 9191 9312 TICKS 629# TN0 554# TN1 554# TOTALS 292# TRP3TP 554# TTNBRF 809# TTYFIL 725# TTYSPD 726# TWO 9085# 9161 9191 9251 9402 TXTINH 303# UBAVEC 554# USER 616# USERF 554# USRASB 70# 606 USRCRF 735# USRLFF 734# UUODIS 688# UUOEXT 644# UUORTN 645# UUOSKP 642# $$MUUO 840# $$OUTE 846# $$TAX1 858# $$TAX2 859# $$TOGG 852# $$UUO 829# $ACC0 667# $BEND1 637# $BEND2 638# $CHRIN 728# $CRLF 730# $DEVCH 554# $DSKUP 607# $DVOFF 724# $EMODE 605# $FFF 732# $IBUF 780# $INEXT 782# $INNM 781# $ITRHL 648# $ITRX1 649# $LPAPE 11458 $MMAP 608# $MODVL 603# SEQ 0321 $MODVU 604# $OBUF 771# $ONETM 631# $OUTEX 773# $OUTNM 772# $PAPER 554 $PARER 655# $PNAME 601# $PSHER 659# $PVER 602# $RSRTX 651# $RSRTY 652# $SPAG1 671# $START 568# $SVAPR 669# $SVPAG 670# $SVPI 668# $SVUPC 674# $SVUUO 673# $TABF 731# $TTCHR 727# $TWCNT 723# $TYPNB 729# $UMODE 606# $UORTX 646# $USRHL 650# $UUOER 647# 688 $VTF 733# %ACTFL 680# %ACTUL 681# %COREC 679# %CORFL 678# %DISCR 682# %ERHI1 821# %ERHI2 822# %ERHI3 823# ..0001 949 955# ..0002 952 957# ..0003 974 980# ..0004 977 982# ..0005 999 1005# ..0006 1002 1007# ..0007 1024 1030# ..0010 1027 1032# ..0011 1049 1055# ..0012 1052 1057# ..0013 1074 1080# ..0014 1077 1082# ..0015 1099 1105# ..0016 1102 1107# ..0017 1178 1184# ..0020 1181 1186# ..0021 1200 1206# SEQ 0322 ..0022 1203 1208# ..0023 1235 1241# ..0024 1238 1243# ..0025 1257 1263# ..0026 1260 1265# ..0027 1292 1298# ..0030 1295 1300# ..0031 1314 1320# ..0032 1317 1322# ..0033 1349 1355# ..0034 1352 1357# ..0035 1371 1377# ..0036 1374 1379# ..0037 1406 1412# ..0040 1409 1414# ..0041 1428 1434# ..0042 1431 1436# ..0043 1463 1469# ..0044 1466 1471# ..0045 1485 1491# ..0046 1488 1493# ..0047 1520 1526# ..0050 1523 1528# ..0051 1542 1548# ..0052 1545 1550# ..0053 1577 1583# ..0054 1580 1585# ..0055 1599 1605# ..0056 1602 1607# ..0057 1692 1698# ..0060 1695 1700# ..0061 1717 1723# ..0062 1720 1725# ..0063 1784 1790# ..0064 1787 1792# ..0065 1829 1835# ..0066 1832 1837# ..0067 1874 1880# ..0070 1877 1882# ..0071 1919 1925# ..0072 1922 1927# ..0073 1964 1970# ..0074 1967 1972# ..0075 2009 2015# ..0076 2012 2017# ..0077 2128 2134# ..0100 2131 2136# ..0101 2176 2182# ..0102 2179 2184# ..0103 2224 2230# ..0104 2227 2232# ..0105 2272 2278# ..0106 2275 2280# SEQ 0323 ..0107 2320 2326# ..0110 2323 2328# ..0111 2368 2374# ..0112 2371 2376# ..0113 2433 2439# ..0114 2436 2441# ..0115 2478 2484# ..0116 2481 2486# ..0117 2523 2529# ..0120 2526 2531# ..0121 2568 2574# ..0122 2571 2576# ..0123 2613 2619# ..0124 2616 2621# ..0125 2658 2664# ..0126 2661 2666# ..0127 2723 2729# ..0130 2726 2731# ..0131 2768 2774# ..0132 2771 2776# ..0133 2813 2819# ..0134 2816 2821# ..0135 2858 2864# ..0136 2861 2866# ..0137 2903 2909# ..0140 2906 2911# ..0141 2948 2954# ..0142 2951 2956# ..0143 3013 3019# ..0144 3016 3021# ..0145 3058 3064# ..0146 3061 3066# ..0147 3103 3109# ..0150 3106 3111# ..0151 3148 3154# ..0152 3151 3156# ..0153 3193 3199# ..0154 3196 3201# ..0155 3238 3244# ..0156 3241 3246# ..0157 3303 3309# ..0160 3306 3311# ..0161 3348 3354# ..0162 3351 3356# ..0163 3393 3399# ..0164 3396 3401# ..0165 3438 3444# ..0166 3441 3446# ..0167 3483 3489# ..0170 3486 3491# ..0171 3528 3534# ..0172 3531 3536# ..0173 3747 3753# SEQ 0324 ..0174 3750 3755# ..0175 3792 3798# ..0176 3795 3800# ..0177 3837 3843# ..0200 3840 3845# ..0201 3882 3888# ..0202 3885 3890# ..0203 3927 3933# ..0204 3930 3935# ..0205 3972 3978# ..0206 3975 3980# ..0207 4017 4023# ..0210 4020 4025# ..0211 4062 4068# ..0212 4065 4070# ..0213 4169 4175# ..0214 4172 4177# ..0215 4194 4200# ..0216 4197 4202# ..0217 4219 4225# ..0220 4222 4227# ..0221 4244 4250# ..0222 4247 4252# ..0223 4269 4275# ..0224 4272 4277# ..0225 4294 4300# ..0226 4297 4302# ..0227 4505 4511# ..0230 4508 4513# ..0231 4532 4538# ..0232 4535 4540# ..0233 4559 4565# ..0234 4562 4567# ..0235 4586 4592# ..0236 4589 4594# ..0237 4613 4619# ..0240 4616 4621# ..0241 4640 4646# ..0242 4643 4648# ..0243 4684 4690# ..0244 4687 4692# ..0245 4711 4717# ..0246 4714 4719# ..0247 4738 4744# ..0250 4741 4746# ..0251 4765 4771# ..0252 4768 4773# ..0253 4792 4798# ..0254 4795 4800# ..0255 4819 4825# ..0256 4822 4827# ..0257 4863 4869# ..0260 4866 4871# SEQ 0325 ..0261 4890 4896# ..0262 4893 4898# ..0263 4917 4923# ..0264 4920 4925# ..0265 4944 4950# ..0266 4947 4952# ..0267 4971 4977# ..0270 4974 4979# ..0271 4998 5004# ..0272 5001 5006# ..0273 5042 5048# ..0274 5045 5050# ..0275 5069 5075# ..0276 5072 5077# ..0277 5096 5102# ..0300 5099 5104# ..0301 5123 5129# ..0302 5126 5131# ..0303 5150 5156# ..0304 5153 5158# ..0305 5177 5183# ..0306 5180 5185# ..0307 5221 5227# ..0310 5224 5229# ..0311 5248 5254# ..0312 5251 5256# ..0313 5275 5281# ..0314 5278 5283# ..0315 5302 5308# ..0316 5305 5310# ..0317 5329 5335# ..0320 5332 5337# ..0321 5356 5362# ..0322 5359 5364# ..0323 5604 5610# ..0324 5607 5612# ..0325 5652 5658# ..0326 5655 5660# ..0327 5700 5706# ..0330 5703 5708# ..0331 5748 5754# ..0332 5751 5756# ..0333 5796 5802# ..0334 5799 5804# ..0335 5844 5850# ..0336 5847 5852# ..0337 5892 5898# ..0340 5895 5900# ..0341 5940 5946# ..0342 5943 5948# ..0343 6033# 6038 ..0344 6052# 6057 ..0345 6071# 6076 SEQ 0326 ..0346 6090# 6095 ..0347 6109# 6114 ..0350 6128# 6133 ..0351 6147# 6152 ..0352 6166# 6171 ..0353 6185# 6190 ..0354 6204# 6209 ..0355 6223# 6228 ..0356 6242# 6247 ..0357 6261# 6266 ..0360 6292# 6297 ..0361 6311# 6316 ..0362 6330# 6335 ..0363 6349# 6354 ..0364 6368# 6373 ..0365 6387# 6392 ..0366 6406# 6411 ..0367 6425# 6430 ..0370 6444# 6449 ..0371 6463# 6468 ..0372 6482# 6487 ..0373 6501# 6506 ..0374 6539# 6544 6552 ..0375 6547# ..0376 6566# 6571 6579 ..0377 6574# ..0400 6593# 6599 6607 ..0401 6602# ..0402 6621# 6627 6635 ..0403 6630# ..0404 6649# 6654 6662 ..0405 6657# ..0406 6676# 6681 6689 ..0407 6684# ..0410 6703# 6709 6717 ..0411 6712# ..0412 6731# 6736 6744 ..0413 6739# ..0414 6758# 6763 6771 ..0415 6766# ..0416 6785# 6791 6799 ..0417 6794# ..0420 6813# 6818 6826 ..0421 6821# ..0422 6840# 6845 6853 ..0423 6848# ..0424 6867# 6873 6881 ..0425 6876# ..0426 6895# 6901 6909 ..0427 6904# ..0430 6923# 6928 6936 ..0431 6931# ..0432 6950# 6955 6963 SEQ 0327 ..0433 6958# ..0434 6977# 6983 6991 ..0435 6986# ..0436 7005# 7010 7018 ..0437 7013# ..0440 7032# 7037 7045 ..0441 7040# ..0442 7059# 7065 7073 ..0443 7068# ..0444 7106# 7111 7119 ..0445 7114# ..0446 7133# 7138 7146 ..0447 7141# ..0450 7160# 7166 7174 ..0451 7169# ..0452 7188# 7194 7202 ..0453 7197# ..0454 7216# 7221 7229 ..0455 7224# ..0456 7243# 7248 7256 ..0457 7251# ..0460 7271# 7277 7285 ..0461 7280# ..0462 7299# 7304 7312 ..0463 7307# ..0464 7326# 7331 7339 ..0465 7334# ..0466 7354# 7360 7368 ..0467 7363# ..0470 7382# 7387 7395 ..0471 7390# ..0472 7409# 7414 7422 ..0473 7417# ..0474 7436# 7442 7450 ..0475 7445# ..0476 7464# 7470 7478 ..0477 7473# ..0500 7492# 7497 7505 ..0501 7500# ..0502 7519# 7524 7532 ..0503 7527# ..0504 7547# 7553 7561 ..0505 7556# ..0506 7575# 7580 7588 ..0507 7583# ..0510 7602# 7607 7615 ..0511 7610# ..0512 7630# 7636 7644 ..0513 7639# ..0514 7722# 7727 7735 ..0515 7730# ..0516 7749# 7754 7762 ..0517 7757# SEQ 0328 ..0520 7776# 7781 7789 ..0521 7784# ..0522 7803# 7808 7816 ..0523 7811# ..0524 7840# 7845 7853 ..0525 7848# ..0526 7867# 7872 7880 ..0527 7875# ..0530 7894# 7899 7907 ..0531 7902# ..0532 7921# 7926 7934 ..0533 7929# ..0534 7948# 7953 7961 ..0535 7956# ..0536 7975# 7980 7988 ..0537 7983# ..0540 8002# 8007 8015 ..0541 8010# ..0542 8029# 8034 8042 ..0543 8037# ..0544 8056# 8061 8069 ..0545 8064# ..0546 8083# 8088 8096 ..0547 8091# ..0550 8110# 8115 8123 ..0551 8118# ..0552 8137# 8142 8150 ..0553 8145# ..0554 8164# 8169 8177 ..0555 8172# ..0556 8191# 8196 8204 ..0557 8199# ..0560 8218# 8223 8231 ..0561 8226# ..0562 8245# 8250 8258 ..0563 8253# ..0564 8272# 8277 8285 ..0565 8280# ..0566 8299# 8305 8313 ..0567 8308# ..0570 8327# 8333 8341 ..0571 8336# ..0572 8355# 8360 8368 ..0573 8363# ..0574 8382# 8387 8395 ..0575 8390# ..0576 8409# 8414 8422 ..0577 8417# ..0600 8436# 8441 8449 ..0601 8444# ..0602 8463# 8468 8476 ..0603 8471# ..0604 8503# 8508 SEQ 0329 ..0605 8523# 8528 ..0606 8553# 8558 ..0607 8573# 8578 ..0610 8607# 8612 ..0611 8627# 8632 ..0612 8647# 8652 ..0613 8667# 8672 ..0614 8687# 8692 ..0615 8707# 8712 ..0616 8727# 8732 ..0617 8747# 8752 ..0620 8767# 8772 ..0621 8787# 8792 ..0622 8807# 8812 ..0623 8827# 8832 ..0624 8847# 8852 ..0625 8867# 8872 ..0626 8887# 8892 ..0627 8907# 8912 ..0630 8927# 8932 ..0631 8947# 8952 ..0632 8967# 8972 ..0633 8987# 8992 ..0634 9007# 9012 ..0635 9027# 9032 ..0636 9047# 9052 ..0637 9067# 9072 ..0640 9102# 9108 9116 ..0641 9111# ..0642 9132# 9138 9146 ..0643 9141# ..0644 9161# 9167 9175 ..0645 9170# ..0646 9191# 9197 9205 ..0647 9200# ..0650 9221# 9227 9235 ..0651 9230# ..0652 9251# 9257 9265 ..0653 9260# ..0654 9282# 9288 9296 ..0655 9291# ..0656 9312# 9318 9326 ..0657 9321# ..0660 9342# 9348 9356 ..0661 9351# ..0662 9372# 9378 9386 ..0663 9381# ..0664 9402# 9408 9416 ..0665 9411# ..0666 9444# 9450 9458 ..0667 9453# ..0670 9473# 9478 9486 ..0671 9481# SEQ 0330 ..0672 9501# 9507 9515 ..0673 9510# ..0674 9530# 9535 9543 ..0675 9538# ..0676 9558# 9563 9571 ..0677 9566# ..0700 9586# 9591 9599 ..0701 9594# ..0702 9614# 9619 9627 ..0703 9622# ..0704 9642# 9647 9655 ..0705 9650# ..0706 9670# 9675 9683 ..0707 9678# ..0710 9698# 9703 9711 ..0711 9706# ..0712 9726# 9731 9739 ..0713 9734# ..0714 9754# 9759 9767 ..0715 9762# ..0716 9782# 9787 9795 ..0717 9790# ..0720 9810# 9815 9823 ..0721 9818# ..0722 9838# 9843 9851 ..0723 9846# ..0724 9866# 9871 9879 ..0725 9874# ..0726 9911# 9916 9924 ..0727 9919# ..0730 9939# 9944 9952 ..0731 9947# ..0732 9967# 9972 9980 ..0733 9975# ..0734 9995# 10000 10008 ..0735 10003# ..0736 10024# 10030 10038 ..0737 10033# ..0740 10054# 10060 10068 ..0741 10063# ..0742 10083# 10089 10097 ..0743 10092# ..0744 10113# 10119 10127 ..0745 10122# ..0746 10183# 10188 10197 ..0747 10191# ..0750 10211# 10216 10225 ..0751 10219# ..0752 10239# 10244 10253 ..0753 10247# ..0754 10267# 10272 10281 ..0755 10275# ..0756 10295# 10300 10309 SEQ 0331 ..0757 10303# ..0760 10323# 10328 10337 ..0761 10331# ..0762 10351# 10356 10365 ..0763 10359# ..0764 10379# 10384 10393 ..0765 10387# ..0766 10407# 10412 10421 ..0767 10415# ..0770 10435# 10440 10449 ..0771 10443# ..0772 10463# 10468 10477 ..0773 10471# ..0774 10491# 10496 10505 ..0775 10499# ..0776 10519# 10524 10533 ..0777 10527# ..1000 10547# 10552 10561 ..1001 10555# ..1002 10575# 10580 10589 ..1003 10583# ..1004 10603# 10608 10617 ..1005 10611# ..1006 10631# 10636 10645 ..1007 10639# ..1010 10659# 10664 10673 ..1011 10667# ..1012 10687# 10693 10702 ..1013 10696# ..1014 10716# 10721 10730 ..1015 10724# ..1016 10744# 10749 10758 ..1017 10752# ..1020 10772# 10777 10786 ..1021 10780# ..1022 10800# 10805 10814 ..1023 10808# ..1024 10828# 10833 10842 ..1025 10836# ..1026 10856# 10861 10870 ..1027 10864# ..1030 10884# 10889 10898 ..1031 10892# ..1032 10913# 10919 10928 ..1033 10922# ..1034 10942# 10948 10957 ..1035 10951# ..1036 10971# 10976 10985 ..1037 10979# ..1040 11000# 11005 11014 ..1041 11008# ..1042 11029# 11034 11043 ..1043 11037# SEQ 0332 ..1044 11058# 11063 11072 ..1045 11066# ..1046 11087# 11092 11101 ..1047 11095# .JB41 554# .JBAPR 554# .JBCNI 554# .JBDDT 554# .JBFF 554# .JBOPC 554# .JBREL 554# .JBREN 554# .JBSA 554# .JBSYM 554# .JBTPC 554# .JBUSY 554# .JBUUO 554# .JBVER 554# APRID 554# BCIO 554# SEQ 0333 BCIOB 554# BSIO 554# BSIOB 554# CFLUSH 476# CHECKA 204# 945 970 995 1020 1045 1070 1095 1174 1196 1231 1253 1288 1310 1345 1367 1402 1424 1459 1481 1516 1538 1573 1595 1688 1713 2124 2172 2220 2268 2316 2364 2429 2474 2519 2564 2609 2654 2719 2764 2809 2854 2899 2944 3009 3054 3099 3144 3189 3234 3299 3344 3389 3434 3479 3524 CHECKB 245# 1780 1825 1870 1915 1960 2005 3743 3788 3833 3878 3923 3968 4013 4058 CHECKS 224# 4165 4190 4215 4240 4265 4290 5038 5065 5092 5119 5146 5173 5217 5244 5271 5298 5325 5352 5600 5648 5696 5744 5792 5840 5888 5936 CHECKT 265# 4501 4528 4555 4582 4609 4636 4680 4707 4734 4761 4788 4815 4859 4886 4913 4940 4967 4994 CINVAL 475# CLOKOP 470# CLRPT 554# CWRTBI 477# DROPDV 437# ENDUUO 483# 636 EOPUUO 484# 638 ERLOOP 524# 959 984 1009 1034 1059 1084 1109 1188 1210 1245 1267 1302 1324 1359 1381 1416 1438 1473 1495 1530 1552 1587 1609 1659 1702 1727 1794 1805 1839 1850 1884 1895 1929 1940 1974 1985 2019 2030 2138 2150 2186 2198 2234 2246 2282 2294 2330 2342 2378 2390 2443 2455 2488 2500 2533 2545 2578 2590 2623 2635 2668 2680 2733 2745 2778 2790 2823 2835 2868 2880 2913 2925 2958 2970 3023 3035 3068 3080 3113 3125 3158 3170 3203 3215 3248 3260 3313 3325 3358 3370 3403 3415 3448 3460 3493 3505 3538 3550 3757 3768 3802 3813 3847 3858 3892 3903 3937 3948 3982 3993 4027 4038 4072 4083 4179 4204 4229 4254 4279 4304 4397 4429 4515 4542 4569 4596 4623 4650 4694 4721 4748 4775 4802 4829 4873 4900 4927 4954 4981 5008 5052 5079 5106 5133 5160 5187 5231 5258 5285 5312 5339 5366 5614 5626 5662 5674 5710 5722 5758 5770 5806 5818 5854 5866 5902 5914 5950 5962 6038 6057 6076 6095 6114 6133 6152 6171 6190 6209 6228 6247 6266 6297 6316 6335 6354 6373 6392 6411 6430 6449 6468 6487 6506 6544 6552 6571 6579 6599 6607 6627 6635 6654 6662 6681 6689 6709 6717 6736 6744 6763 6771 6791 6799 6818 6826 6845 6853 6873 6881 6901 6909 6928 6936 6955 6963 6983 6991 7010 7018 7037 7045 7065 7073 7111 7119 7138 7146 7166 7174 7194 7202 7221 7229 7248 7256 7277 7285 7304 7312 7331 7339 7360 7368 7387 7395 7414 7422 7442 7450 7470 7478 7497 7505 7524 7532 7553 7561 7580 7588 7607 7615 7636 7644 7689 7696 7727 7735 7754 7762 7781 7789 7808 7816 7845 7853 7872 7880 7899 7907 7926 7934 7953 7961 7980 7988 8007 8015 8034 8042 8061 8069 8088 8096 8115 8123 8142 8150 8169 8177 8196 8204 8223 8231 8250 8258 8277 8285 8305 8313 8333 8341 8360 8368 8387 8395 8414 8422 8441 8449 8468 8476 8508 8528 8558 8578 8612 8632 8652 8672 8692 8712 8732 8752 8772 8792 8812 8832 8852 8872 8892 8912 8932 8952 8972 8992 9012 9032 9052 9072 9108 9116 9138 9146 9167 9175 9197 9205 9227 9235 9257 9265 9288 9296 9318 9326 9348 9356 9378 9386 9408 9416 9450 9458 9478 9486 9507 9515 9535 9543 9563 9571 9591 9599 9619 9627 9647 9655 9675 9683 9703 9711 9731 9739 9759 9767 9787 9795 9815 9823 9843 9851 9871 9879 9916 9924 9944 9952 9972 9980 10000 10008 10030 10038 10060 10068 10089 10097 10119 10127 10188 10197 10216 10225 10244 10253 10272 10281 10300 10309 10328 10337 10356 10365 10384 10393 10412 10421 SEQ 0334 10440 10449 10468 10477 10496 10505 10524 10533 10552 10561 10580 10589 10608 10617 10636 10645 10664 10673 10693 10702 10721 10730 10749 10758 10777 10786 10805 10814 10833 10842 10861 10870 10889 10898 10919 10928 10948 10957 10976 10985 11005 11014 11034 11043 11063 11072 11092 11101 ERLP1 525# ERLP2 526# ERRHLT 371# ERROR 533# 912# 957 982 1007 1032 1057 1082 1107 1186 1208 1243 1265 1300 1322 1357 1379 1414 1436 1471 1493 1528 1550 1585 1607 1657 1700 1725 1792 1803 1837 1848 1882 1893 1927 1938 1972 1983 2017 2028 2136 2147 2184 2195 2232 2243 2280 2291 2328 2339 2376 2387 2441 2452 2486 2497 2531 2542 2576 2587 2621 2632 2666 2677 2731 2742 2776 2787 2821 2832 2866 2877 2911 2922 2956 2967 3021 3032 3066 3077 3111 3122 3156 3167 3201 3212 3246 3257 3311 3322 3356 3367 3401 3412 3446 3457 3491 3502 3536 3547 3755 3766 3800 3811 3845 3856 3890 3901 3935 3946 3980 3991 4025 4036 4070 4081 4177 4202 4227 4252 4277 4302 4395 4426 4513 4540 4567 4594 4621 4648 4692 4719 4746 4773 4800 4827 4871 4898 4925 4952 4979 5006 5050 5077 5104 5131 5158 5185 5229 5256 5283 5310 5337 5364 5612 5624 5660 5672 5708 5720 5756 5768 5804 5816 5852 5864 5900 5912 5948 5960 6036 6055 6074 6093 6112 6131 6150 6169 6188 6207 6226 6245 6264 6295 6314 6333 6352 6371 6390 6409 6428 6447 6466 6485 6504 6542 6549 6569 6576 6597 6604 6625 6632 6652 6659 6679 6686 6707 6714 6734 6741 6761 6768 6789 6796 6816 6823 6843 6850 6871 6878 6899 6906 6926 6933 6953 6960 6981 6988 7008 7015 7035 7042 7063 7070 7109 7116 7136 7143 7164 7171 7192 7199 7219 7226 7246 7253 7275 7282 7302 7309 7329 7336 7358 7365 7385 7392 7412 7419 7440 7447 7468 7475 7495 7502 7522 7529 7551 7558 7578 7585 7605 7612 7634 7641 7687 7694 7725 7732 7752 7759 7779 7786 7806 7813 7843 7850 7870 7877 7897 7904 7924 7931 7951 7958 7978 7985 8005 8012 8032 8039 8059 8066 8086 8093 8113 8120 8140 8147 8167 8174 8194 8201 8221 8228 8248 8255 8275 8282 8303 8310 8331 8338 8358 8365 8385 8392 8412 8419 8439 8446 8466 8473 8506 8526 8556 8576 8610 8630 8650 8670 8690 8710 8730 8750 8770 8790 8810 8830 8850 8870 8890 8910 8930 8950 8970 8990 9010 9030 9050 9070 9106 9113 9136 9143 9165 9172 9195 9202 9225 9232 9255 9262 9286 9293 9316 9323 9346 9353 9376 9383 9406 9413 9448 9455 9476 9483 9505 9512 9533 9540 9561 9568 9589 9596 9617 9624 9645 9652 9673 9680 9701 9708 9729 9736 9757 9764 9785 9792 9813 9820 9841 9848 9869 9876 9914 9921 9942 9949 9970 9977 9998 10005 10028 10035 10058 10065 10087 10094 10117 10124 10186 10194 10214 10222 10242 10250 10270 10278 10298 10306 10326 10334 10354 10362 10382 10390 10410 10418 10438 10446 10466 10474 10494 10502 10522 10530 10550 10558 10578 10586 10606 10614 10634 10642 10662 10670 10691 10699 10719 10727 10747 10755 10775 10783 10803 10811 10831 10839 10859 10867 10887 10895 10917 10925 10946 10954 10974 10982 11003 11011 11032 11040 11061 11069 11090 11098 ERROR1 544# ERUUO 523# 958 983 1008 1033 1058 1083 1108 1187 1209 1244 1266 1301 1323 1358 1380 1415 1437 1472 1494 1529 1551 1586 1608 1658 1701 1726 1793 1804 1838 1849 1883 1894 1928 1939 1973 1984 2018 2029 2137 2149 2185 2197 2233 2245 2281 2293 2329 2341 2377 2389 2442 2454 2487 2499 2532 2544 2577 2589 2622 2634 2667 2679 2732 2744 2777 2789 2822 2834 2867 2879 2912 2924 2957 2969 3022 3034 3067 3079 3112 3124 3157 3169 3202 3214 3247 3259 3312 3324 3357 3369 3402 3414 3447 3459 3492 3504 3537 3549 3756 3767 3801 3812 3846 3857 3891 3902 3936 3947 3981 3992 4026 4037 4071 4082 4178 4203 4228 4253 4278 4303 4396 4428 4514 4541 4568 SEQ 0335 4595 4622 4649 4693 4720 4747 4774 4801 4828 4872 4899 4926 4953 4980 5007 5051 5078 5105 5132 5159 5186 5230 5257 5284 5311 5338 5365 5613 5625 5661 5673 5709 5721 5757 5769 5805 5817 5853 5865 5901 5913 5949 5961 6037 6056 6075 6094 6113 6132 6151 6170 6189 6208 6227 6246 6265 6296 6315 6334 6353 6372 6391 6410 6429 6448 6467 6486 6505 6543 6551 6570 6578 6598 6606 6626 6634 6653 6661 6680 6688 6708 6716 6735 6743 6762 6770 6790 6798 6817 6825 6844 6852 6872 6880 6900 6908 6927 6935 6954 6962 6982 6990 7009 7017 7036 7044 7064 7072 7110 7118 7137 7145 7165 7173 7193 7201 7220 7228 7247 7255 7276 7284 7303 7311 7330 7338 7359 7367 7386 7394 7413 7421 7441 7449 7469 7477 7496 7504 7523 7531 7552 7560 7579 7587 7606 7614 7635 7643 7688 7695 7726 7734 7753 7761 7780 7788 7807 7815 7844 7852 7871 7879 7898 7906 7925 7933 7952 7960 7979 7987 8006 8014 8033 8041 8060 8068 8087 8095 8114 8122 8141 8149 8168 8176 8195 8203 8222 8230 8249 8257 8276 8284 8304 8312 8332 8340 8359 8367 8386 8394 8413 8421 8440 8448 8467 8475 8507 8527 8557 8577 8611 8631 8651 8671 8691 8711 8731 8751 8771 8791 8811 8831 8851 8871 8891 8911 8931 8951 8971 8991 9011 9031 9051 9071 9107 9115 9137 9145 9166 9174 9196 9204 9226 9234 9256 9264 9287 9295 9317 9325 9347 9355 9377 9385 9407 9415 9449 9457 9477 9485 9506 9514 9534 9542 9562 9570 9590 9598 9618 9626 9646 9654 9674 9682 9702 9710 9730 9738 9758 9766 9786 9794 9814 9822 9842 9850 9870 9878 9915 9923 9943 9951 9971 9979 9999 10007 10029 10037 10059 10067 10088 10096 10118 10126 10187 10196 10215 10224 10243 10252 10271 10280 10299 10308 10327 10336 10355 10364 10383 10392 10411 10420 10439 10448 10467 10476 10495 10504 10523 10532 10551 10560 10579 10588 10607 10616 10635 10644 10663 10672 10692 10701 10720 10729 10748 10757 10776 10785 10804 10813 10832 10841 10860 10869 10888 10897 10918 10927 10947 10956 10975 10984 11004 11013 11033 11042 11062 11071 11091 11100 FATAL 370# FRD36 512# FRD8 513# FREAD 511# FSELEC 510# GET 354# 11147 11195 11266 GO 351# 6035 6054 6073 6092 6111 6130 6149 6168 6187 6206 6225 6244 6263 6294 6313 6332 6351 6370 6389 6408 6427 6446 6465 6484 6503 6541 6568 6596 6624 6651 6678 6706 6733 6760 6788 6815 6842 6870 6898 6925 6952 6980 7007 7034 7062 7108 7135 7163 7191 7218 7245 7274 7301 7328 7357 7384 7411 7439 7467 7494 7521 7550 7577 7604 7633 7724 7751 7778 7805 7842 7869 7896 7923 7950 7977 8004 8031 8058 8085 8112 8139 8166 8193 8220 8247 8274 8302 8330 8357 8384 8411 8438 8465 8505 8525 8555 8575 8609 8629 8649 8669 8689 8709 8729 8749 8769 8789 8809 8829 8849 8869 8889 8909 8929 8949 8969 8989 9009 9029 9049 9069 9105 9135 9164 9194 9224 9254 9285 9315 9345 9375 9405 9447 9475 9504 9532 9560 9588 9616 9644 9672 9700 9728 9756 9784 9812 9840 9868 9913 9941 9969 9997 10027 10057 10086 10116 10185 10213 10241 10269 10297 10325 10353 10381 10409 10437 10465 10493 10521 10549 10577 10605 10633 10661 10690 10718 10746 10774 10802 10830 10858 10886 10916 10945 10973 11002 11031 11060 11089 HALT 55 56 57 58 59 356# 657 JEN 358# JRSTF 357# 11168 11230 MAPADR 493# MAPCNK 494# MAPMEM 490# SEQ 0336 MAPPNT 496# MAPSET 495# MEMSEG 492# MEMZRO 491# MODPCP 503# MODPCU 502# MTROP 471# MULT 101# 6027 6046 6065 6084 6103 6122 6141 6160 6179 6198 6217 6236 6255 6286 6305 6324 6343 6362 6381 6400 6419 6438 6457 6476 6495 MULTF 118# 6533 6560 6587 6615 6643 6670 6697 6725 6752 6779 6807 6834 6861 6889 6917 6944 6971 6999 7026 7053 7100 7127 7154 7182 7210 7237 7264 7293 7320 7347 7376 7403 7430 7458 7486 7513 7540 7569 7596 7623 7716 7743 7770 7797 7834 7861 7888 7915 7942 7969 7996 8023 8050 8077 8104 8131 8158 8185 8212 8239 8266 8293 8321 8349 8376 8403 8430 8457 NAME 7# 10 ODIV 180# 10177 10205 10233 10261 10289 10317 10345 10373 10401 10429 10457 10485 10513 10541 10569 10597 10625 10653 10681 10710 10738 10766 10794 10822 10850 10878 10906 10936 10965 10994 11023 11052 11081 PBELL 446# PCRL 440# 11297 11308 11317 11334 11345 11354 11371 11382 11397 11422 11433 11450 PCRL2 444# PCRL2F 445# PCRLF 441# PCSAVE 78# 1775 1820 1865 1910 1955 2000 2117 2165 2213 2261 2309 2357 2424 2469 2514 2559 2604 2649 2714 2759 2804 2849 2894 2939 3004 3049 3094 3139 3184 3229 3294 3339 3384 3429 3474 3519 3738 3783 3828 3873 3918 3963 4008 4053 4382 5595 5643 5691 5739 5787 5835 5883 5931 7670 PDIV 139# 8496 8516 8546 8566 8600 8620 8640 8660 8680 8700 8720 8740 8760 8780 8800 8820 8840 8860 8880 8900 8920 8940 8960 8980 9000 9020 9040 9060 PDIVF 157# 9094 9124 9154 9183 9213 9243 9274 9304 9334 9364 9394 9437 9466 9494 9523 9551 9579 9607 9635 9663 9691 9719 9747 9775 9803 9831 9859 9904 9932 9960 9988 10016 10046 10076 10105 PFORCE 448# PGMINT 364# 920 PJRST 355# PMSG 450# 11287 11298 11309 11324 11335 11346 11361 11372 11383 11404 11423 11434 11442 PMSGF 453# PNT1 406# PNT11 420# PNT11F 421# PNT1F 407# PNT2 408# PNT2F 409# PNT3 410# PNT3F 411# PNT4 412# PNT4F 413# PNT5 414# PNT5F 415# PNT6 416# PNT6F 417# PNT7 418# SEQ 0337 PNT7F 419# PNTA 392# PNTADF 423# PNTADR 422# PNTAF 393# PNTAL 394# PNTALF 395# PNTCHF 405# PNTCHR 404# PNTCI 402# PNTCIF 403# PNTCW 438# PNTCWF 439# PNTDCF 431# PNTDEC 430# PNTDS 432# PNTDSF 433# PNTHW 426# PNTHWF 427# PNTMSF 399# PNTMSG 398# PNTNM 434# PNTOCF 429# PNTOCS 428# PNTOCT 424# 11291 11295 11302 11306 11312 11315 11328 11332 11339 11343 11349 11352 11365 11369 11376 11380 11386 11389 11392 11395 11408 11412 11416 11420 11427 11431 11437 11440 11445 11448 PNTOTF 425# PNTSIX 435# PNTSXF 436# PSIXL 396# PSIXLF 397# PSIXM 400# 11287 11298 11309 11324 11335 11346 11361 11372 11383 11404 11423 11434 11442 PSIXMF 401# PSP 442# PSPF 443# PUT 353# RDAPR 554# RDCSB 554# RDCSTM 554# RDEBR 554# RDHSB 554# RDINT 554# RDIO 554# RDIOB 554# RDPI 554# RDPUR 554# RDSPB 554# RDTIM 554# RDUBR 554# REPTUO 527# RTN 352# 644 11145 11193 11264 11318 11355 11398 11451 S 282# SEQ 0338 SIXBTZ 459# 924 4145 6008 8481 SWITCH 465# TFLAG 88# 1797 1842 1887 1932 1977 2022 2141 2189 2237 2285 2333 2381 2446 2491 2536 2581 2626 2671 2736 2781 2826 2871 2916 2961 3026 3071 3116 3161 3206 3251 3316 3361 3406 3451 3496 3541 3760 3805 3850 3895 3940 3985 4030 4075 4420 5618 5666 5714 5762 5810 5858 5906 5954 TIOE 554# TIOEB 554# TION 554# TIONB 554# TTALTM 386# TTICHR 379# TTICLR 389# TTICNV 384# TTIDEC 383# TTINO 381# TTIOCT 382# TTIYES 380# TTLOOK 385# TTSIXB 387# TTYINP 388# WRAPR 554# WRCSB 554# WRCSTM 554# WREBR 554# WRHSB 554# WRINT 554# WRIO 554# WRIOB 554# WRPI 554# WRPUR 554# WRSPB 554# WRTIM 554# WRUBR 554# Dist/rtl/testbench/sav2verilog.exe0000700000175100010010000004725512065220700015700 0ustar RobNoneMZ@ !L!This program cannot be run in DOS mode. $PEL !P"   @ P.text  `P`.data @`/40@0.bss(@`.idataP@0/146`B/30JpB/42hB/56 BU$@D$D$$/D$D$$#D$D$$D$D$$ ÐU$@ @& tgD$O @$ tPD$@@$0@С!@t3$e @ t3D$r @$ t$!@Ð @t륐t& @uÐt&U$@ @ t'D$ @$w t$0@Ðt& @uÐL$qUVSQME8$D$ @D$ @D$ $ @UB0UB@t$ \$D$ @$UB$Y[^]aUWVSE%EE%E=Xt$D$ i!@D$ @D$G$ @]@\$D$x!@$E$<[^_]U(ED$ D$D$E$E}tED$$!@$E E E ‹E E? E E ‹E PU(EE}E A@=XuE$A@uԁ}~$D$ !@D$!@D$^$ @E A@XÐ%QD%QDUED$$PDU]ÐU]ÐU]ÐU]Ð%PD%PD%PD%PD%PD%PD%PD%PD%PDUVS] u$ۉPDCCC CEǃǃC,@C0 @C @@s(CH`@CLp@CP@CT@C$$@@C@@CH@C P@CDX@Qx(@@ @$ @( @, @0 @54 @ 8 @b< @G @$ @B( @B, @B 0 @B4 @B8 @B< @B$RC4 @C8!@C<@@C@(ADǃ0@C|ǃ0@ǃ@ue[^]&@PD@@ ǀǀ@,@@0 @@ @@q(AH`@ALp@EAP@AT@A$$@@A@@AH@A P@ADX@= 2sav2verilog.c // // Do not edit this file. It was created by %s %s // rdsavrsavfp != NULLa = %06o d1.rh>=AMEM && d1.rh<=AMEM+NMEM-1 SSRAM[%05d] = 36'o%06o%06o; // %06o d1.lh == JRST // // Starting Address is %06o // ---------> size was %d xhalta < AMEM+NMEMPPRPPRQPR QQ(Q8QDQTQ`QpQ|QQQQQQQQQQQR$R $ > '  I: ; II!I/ 4: ;I?  z /gnu/gcc/releases/respins/4.3.4-4/gcc4-4.3.4-4/src/gcc-4.3.4/libgcc/../gcclibgcc2.cgbl-ctors.hD T .text.data.bss.filegcygming-crtbegin.cg_obj{ 0 .text.data .bss .rdata@^.jcr.filegsav2verilog.c_main _rdsav" _rdfwsav _xhalt .text,.data .bss .rdata).text.idata$7.idata$5.idata$4.idata$6@feat.00.text.idata$7.idata$5.idata$4.idata$6$@feat.000 .text0".data .bss ` .text`.data .bss p .textp.data .bss ) .text.data .bss : .text.data .bss .text.text.text.text.text.text.text.text.textK .text=.data  .bss .text.idata$7x.idata$5.idata$4d.idata$6`b mPx@0  `  .text).data@.bss(H.text 0  .text0 .data@.bssp.text@ .textH .textP .textX `  _u.8577p.text` 3.data@.bssp.text   .text  .data@.bss .text .text .data@.bss .idata$7.idata$5 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printf " //\n"; printf " // " filename "\n"; printf " // Do not edit this file.\n" printf " // It was created by an awk script.\n" printf " //\n"; printf " \n"; } # # Pointers # # These looks like: # #" xxx xxxxxx xx xx x xx xxxxxx /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7][0-7] [0-7][0-7] [0-7] [0-7][0-7] [0-7][0-7][0-7][0-7][0-7][0-7].*/ { data1 = lshift(strtonum("0" substr($3, 1, 2)), 30); data2 = lshift(strtonum("0" substr($3, 4, 2)), 24); data3 = lshift(strtonum("0" substr($3, 7, 1)), 22); data4 = lshift(strtonum("0" substr($3, 9, 2)), 18); data5 = lshift(strtonum("0" substr($3, 12, 6)), 0); data = sprintf("%012o", data1 + data2 + data3 + data4 + data5); i = strtonum("0" $2) map[i] = data; } # # IO Instructions # # These looks like: # #" xxx xxxxxx 7 xxx xx x xx xxxxxx /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7] [0-7][0-7][0-7] [0-7][0-7] [0-7] [0-7][0-7] [0-7][0-7][0-7][0-7][0-7][0-7].*/ { data1 = lshift(strtonum("0" substr($3, 1, 1)), 33); data2 = lshift(strtonum("0" substr($3, 3, 3)), 24); data3 = lshift(strtonum("0" substr($3, 7, 2)), 21); data4 = lshift(strtonum("0" substr($3, 10, 1)), 22); data5 = lshift(strtonum("0" substr($3, 12, 2)), 18); data6 = lshift(strtonum("0" substr($3, 15, 6)), 0); data = sprintf("%012o", data1 + data2 + data3 + data4 + data5 + data6); i = strtonum("0" $2) map[i] = data; } # # IO Instructions # # These looks like: # #" xxx xxxxxx 7 xxx x x xx xxxxxx /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7] [0-7][0-7][0-7] [0-7] [0-7] [0-7][0-7] [0-7][0-7][0-7][0-7][0-7][0-7].*/ { data1 = lshift(strtonum("0" substr($3, 1, 1)), 33); data2 = lshift(strtonum("0" substr($3, 3, 3)), 24); data3 = lshift(strtonum("0" substr($3, 7, 1)), 23); data4 = lshift(strtonum("0" substr($3, 9, 1)), 22); data5 = lshift(strtonum("0" substr($3, 11, 2)), 18); data6 = lshift(strtonum("0" substr($3, 14, 6)), 0); data = sprintf("%012o", data1 + data2 + data3 + data4 + data5 + data6); i = strtonum("0" $2) map[i] = data; } # # CONO Instructions # # These looks like: # #" xxx xxxxxx xxx xx xx xx xxxxxx /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7][0-7][0-7] [0-7][0-7] [0-7][0-7] [0-7][0-7] [0-7][0-7][0-7][0-7][0-7][0-7].*/ { data1 = lshift(strtonum("0" substr($3, 1, 3)), 27); data2 = lshift(strtonum("0" substr($3, 5, 2)), 21) data3 = lshift(strtonum("0" substr($3, 8, 2)), 20); data4 = lshift(strtonum("0" substr($3, 11, 2)), 18); data5 = lshift(strtonum("0" substr($3, 14, 6)), 0); data = sprintf("%012o", data1 + data2 + data3 + data4 + data5); i = strtonum("0" $2) map[i] = data; } # # Sixbit # 6x 6-bit characters span the 36-bit word # # These looks like: # #" xxx aaaaaa dd dd dd dd dd dd " # /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7][0-7] [0-7][0-7] [0-7][0-7] [0-7][0-7] [0-7][0-7] [0-7][0-7].*/ { data1 = substr($3, 1, 2); data2 = substr($3, 4, 2); data3 = substr($3, 7, 2); data4 = substr($3, 10, 2); data5 = substr($3, 13, 2); data6 = substr($3, 16, 2); #print $2, (data1 data2 data3 data4 data5 data6) i = strtonum("0" $2) map[i] = (data1 data2 data3 data4 data5 data6) } # # ASCII # 5x 7-bit characters are left justified in the 36-bit word. # # These looks like: # #" xxx aaaaaa ddd ddd ddd ddd ddd " # /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7][0-7][0-7] [0-7][0-7][0-7] [0-7][0-7][0-7] [0-7][0-7][0-7] [0-7][0-7][0-7].*/ { data1 = lshift(and(strtonum("0" substr($3, 1, 3)), 0177), 29) data2 = lshift(and(strtonum("0" substr($3, 5, 3)), 0177), 22) data3 = lshift(and(strtonum("0" substr($3, 9, 3)), 0177), 15) data4 = lshift(and(strtonum("0" substr($3, 13, 3)), 0177), 8) data5 = lshift(and(strtonum("0" substr($3, 17, 3)), 0177), 1) data = sprintf("%012o", data1 + data2 + data3 + data4 + data5); #print $2 " " data i = strtonum("0" $2) map[i] = data } # # BYTE # 1x 8-bit byte is left justified in the 36-bit word. # # These looks like: # #" xxx aaaaaa ddd 0000000000 " # /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7][0-7][0-7] 0000000000.*/ { data1 = lshift(and(strtonum("0" substr($3, 1, 3)), 0377), 29); data = sprintf("%012o", data1) i = strtonum("0" $2) map[i] = data } # # Bytes #" 2791 023352 0 117 124 0 123 120 " # # See DSQDC # /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7] [0-7][0-7][0-7] [0-7][0-7][0-7] [0-7] [0-7][0-7][0-7] [0-7][0-7][0-7].*/ { data1 = lshift(strtonum("0" substr($3, 1, 1)), 34); data2 = lshift(strtonum("0" substr($3, 3, 3)), 26); data3 = lshift(strtonum("0" substr($3, 7, 3)), 18); data4 = lshift(strtonum("0" substr($3, 11, 1)), 16); data5 = lshift(strtonum("0" substr($3, 13, 3)), 8); data6 = lshift(strtonum("0" substr($3, 17, 3)), 0); data = sprintf("%012o", data1 + data2 + data3 + data4 + data5 + data6); i = strtonum("0" $2) map[i] = data } # # OPCODES # # These looks like: # #" xxx aaaaaa ddd dd d dd dddddd " # /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7][0-7][0-7] [0-7][0-7] [0-7] [0-7][0-7] [0-7][0-7][0-7][0-7][0-7][0-7].*/ { data1 = lshift(strtonum("0" substr($3, 1, 3)), 27); data2 = lshift(strtonum("0" substr($3, 5, 2)), 23); data3 = lshift(strtonum("0" substr($3, 8, 1)), 22); data4 = lshift(strtonum("0" substr($3, 10, 2)), 18); data5 = lshift(strtonum("0" substr($3, 13, 6)), 0); data = sprintf("%012o", data1 + data2 + data3 + data4 + data5); i = strtonum("0" $2) map[i] = data } # # Definitions # # These looks like: # #" xxx aaaaaa dddddd dddddd " # /^.*\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7][0-7][0-7][0-7][0-7][0-7]\t[0-7][0-7][0-7][0-7][0-7][0-7].*/ { #print $2, ($3 $4) i = strtonum("0" $2) map[i] = ($3 $4) } # # Write Sorted output to file # END { for (i = 0; i < 077777; i++) { if (map[i] != "") { printf " SSRAM[%05d] = 36'o%s; // %06o\n", i, map[i], i } else { #printf " SSRAM[%05d] = 36'o%s; // %06o (unused)\n", i, "000000000000", i } } } Dist/rtl/testbench/ssram.dat0000700000175100010010000131052012151540236014543 0ustar RobNone // // MAINDEC-10-DSKCF-RD00.SEQ // Do not edit this file. // It was created by an awk script. // SSRAM[00095] = 36'o000000000003; // 000137 SSRAM[12288] = 36'o254020027776; // 030000 SSRAM[12289] = 36'o254000030623; // 030001 SSRAM[12290] = 36'o254020027774; // 030002 SSRAM[12291] = 36'o254020027774; // 030003 SSRAM[12292] = 36'o254000030624; // 030004 SSRAM[12293] = 36'o254000030624; // 030005 SSRAM[12294] = 36'o254000030623; // 030006 SSRAM[12295] = 36'o254020027775; // 030007 SSRAM[12296] = 36'o254000030624; // 030010 SSRAM[12297] = 36'o254020027777; // 030011 SSRAM[12298] = 36'o000000000000; // 030012 SSRAM[12299] = 36'o254200030000; // 030013 SSRAM[12300] = 36'o254200030000; // 030014 SSRAM[12301] = 36'o254200030000; // 030015 SSRAM[12302] = 36'o254200030000; // 030016 SSRAM[12303] = 36'o254200030000; // 030017 SSRAM[12304] = 36'o446353434600; // 030020 SSRAM[12305] = 36'o546364000000; // 030021 SSRAM[12306] = 36'o000000000000; // 030022 SSRAM[12307] = 36'o000000000000; // 030023 SSRAM[12308] = 36'o000000000010; // 030024 SSRAM[12309] = 36'o000000030600; // 030025 SSRAM[12310] = 36'o000000000003; // 030026 SSRAM[12311] = 36'o000000030000; // 030027 SSRAM[12312] = 36'o000000030000; // 030030 SSRAM[12313] = 36'o777777777777; // 030031 SSRAM[12314] = 36'o777777777777; // 030032 SSRAM[12315] = 36'o000000000000; // 030033 SSRAM[12316] = 36'o000000000000; // 030034 SSRAM[12317] = 36'o000000000000; // 030035 SSRAM[12318] = 36'o000000000000; // 030036 SSRAM[12319] = 36'o000000000000; // 030037 SSRAM[12320] = 36'o000000000000; // 030040 SSRAM[12321] = 36'o777777777777; // 030041 SSRAM[12322] = 36'o777777777777; // 030042 SSRAM[12323] = 36'o000000000000; // 030043 SSRAM[12324] = 36'o000000000000; // 030044 SSRAM[12325] = 36'o000000000000; // 030045 SSRAM[12326] = 36'o000000000000; // 030046 SSRAM[12327] = 36'o000000000000; // 030047 SSRAM[12328] = 36'o000000000000; // 030050 SSRAM[12329] = 36'o000000000000; // 030051 SSRAM[12330] = 36'o000000000000; // 030052 SSRAM[12331] = 36'o000000000000; // 030053 SSRAM[12332] = 36'o000000000000; // 030054 SSRAM[12333] = 36'o000000000000; // 030055 SSRAM[12334] = 36'o000000000000; // 030056 SSRAM[12335] = 36'o037500000004; // 030057 SSRAM[12336] = 36'o254000030010; // 030060 SSRAM[12337] = 36'o037700000004; // 030061 SSRAM[12338] = 36'o000000030624; // 030062 SSRAM[12339] = 36'o000000040450; // 030063 SSRAM[12340] = 36'o350017000000; // 030064 SSRAM[12341] = 36'o263740000000; // 030065 SSRAM[12342] = 36'o255000000000; // 030066 SSRAM[12343] = 36'o255000000000; // 030067 SSRAM[12344] = 36'o255000000000; // 030070 SSRAM[12345] = 36'o255000000000; // 030071 SSRAM[12346] = 36'o255000000000; // 030072 SSRAM[12347] = 36'o255000000000; // 030073 SSRAM[12348] = 36'o255000000000; // 030074 SSRAM[12349] = 36'o255000000000; // 030075 SSRAM[12350] = 36'o255000000000; // 030076 SSRAM[12351] = 36'o255000000000; // 030077 SSRAM[12352] = 36'o255000000000; // 030100 SSRAM[12353] = 36'o255000000000; // 030101 SSRAM[12354] = 36'o254200030102; // 030102 SSRAM[12355] = 36'o000000000000; // 030103 SSRAM[12356] = 36'o000000000000; // 030104 SSRAM[12357] = 36'o000000000000; // 030105 SSRAM[12358] = 36'o000000000000; // 030106 SSRAM[12359] = 36'o000000000000; // 030107 SSRAM[12360] = 36'o000000000000; // 030110 SSRAM[12361] = 36'o000000000000; // 030111 SSRAM[12362] = 36'o000000000000; // 030112 SSRAM[12363] = 36'o000000000000; // 030113 SSRAM[12364] = 36'o000000000000; // 030114 SSRAM[12365] = 36'o000000000000; // 030115 SSRAM[12366] = 36'o000000000000; // 030116 SSRAM[12367] = 36'o000000000000; // 030117 SSRAM[12368] = 36'o000000000000; // 030120 SSRAM[12369] = 36'o000000000000; // 030121 SSRAM[12370] = 36'o000000000000; // 030122 SSRAM[12371] = 36'o000000000000; // 030123 SSRAM[12372] = 36'o030070030070; // 030124 SSRAM[12373] = 36'o030070030070; // 030125 SSRAM[12374] = 36'o030070030070; // 030126 SSRAM[12375] = 36'o030070030070; // 030127 SSRAM[12376] = 36'o030070030070; // 030130 SSRAM[12377] = 36'o030070030070; // 030131 SSRAM[12378] = 36'o030070030070; // 030132 SSRAM[12379] = 36'o030070030070; // 030133 SSRAM[12380] = 36'o030070030070; // 030134 SSRAM[12381] = 36'o030070030070; // 030135 SSRAM[12382] = 36'o030070030070; // 030136 SSRAM[12383] = 36'o030070030070; // 030137 SSRAM[12384] = 36'o030070030070; // 030140 SSRAM[12385] = 36'o030070030070; // 030141 SSRAM[12386] = 36'o000000000000; // 030142 SSRAM[12387] = 36'o000000000000; // 030143 SSRAM[12388] = 36'o000000000000; // 030144 SSRAM[12389] = 36'o000000000000; // 030145 SSRAM[12431] = 36'o000000000000; // 030217 SSRAM[12432] = 36'o000000000000; // 030220 SSRAM[12433] = 36'o000000000000; // 030221 SSRAM[12434] = 36'o000000000000; // 030222 SSRAM[12435] = 36'o000000000000; // 030223 SSRAM[12436] = 36'o000000000000; // 030224 SSRAM[12437] = 36'o000000000000; // 030225 SSRAM[12438] = 36'o000000000000; // 030226 SSRAM[12439] = 36'o000000000000; // 030227 SSRAM[12440] = 36'o000000000000; // 030230 SSRAM[12441] = 36'o000000000000; // 030231 SSRAM[12442] = 36'o000000000000; // 030232 SSRAM[12443] = 36'o000000000000; // 030233 SSRAM[12444] = 36'o000000000000; // 030234 SSRAM[12445] = 36'o000000000000; // 030235 SSRAM[12446] = 36'o000000000000; // 030236 SSRAM[12447] = 36'o000000000000; // 030237 SSRAM[12448] = 36'o000000000000; // 030240 SSRAM[12449] = 36'o000000000000; // 030241 SSRAM[12450] = 36'o064240000000; // 030242 SSRAM[12451] = 36'o064241505000; // 030243 SSRAM[12452] = 36'o260000000000; // 030244 SSRAM[12453] = 36'o270000000000; // 030245 SSRAM[12454] = 36'o200000000000; // 030246 SSRAM[12455] = 36'o044000000000; // 030247 SSRAM[12456] = 36'o264000000000; // 030250 SSRAM[12457] = 36'o254000000000; // 030251 SSRAM[12458] = 36'o250000000000; // 030252 SSRAM[12459] = 36'o400000000000; // 030253 SSRAM[12460] = 36'o240000000000; // 030254 SSRAM[12461] = 36'o244000000000; // 030255 SSRAM[12462] = 36'o034000000000; // 030256 SSRAM[12463] = 36'o374000000000; // 030257 SSRAM[12464] = 36'o274000000000; // 030260 SSRAM[12465] = 36'o220000000000; // 030261 SSRAM[12466] = 36'o000000000012; // 030262 SSRAM[12467] = 36'o000000000040; // 030263 SSRAM[12468] = 36'o000000000012; // 030264 SSRAM[12472] = 36'o606251566400; // 030270 SSRAM[12473] = 36'o605664000000; // 030271 SSRAM[12479] = 36'o606251566400; // 030277 SSRAM[12480] = 36'o605664000000; // 030300 SSRAM[12483] = 36'o777577030303; // 030303 SSRAM[12612] = 36'o000000000000; // 030504 SSRAM[12613] = 36'o000000000000; // 030505 SSRAM[12614] = 36'o000000000000; // 030506 SSRAM[12615] = 36'o000000000000; // 030507 SSRAM[12616] = 36'o000000000000; // 030510 SSRAM[12617] = 36'o000000000000; // 030511 SSRAM[12618] = 36'o000000000000; // 030512 SSRAM[12619] = 36'o000000000000; // 030513 SSRAM[12620] = 36'o000000000000; // 030514 SSRAM[12621] = 36'o000000000000; // 030515 SSRAM[12622] = 36'o000000000000; // 030516 SSRAM[12623] = 36'o000000000000; // 030517 SSRAM[12624] = 36'o000000000000; // 030520 SSRAM[12625] = 36'o000000000000; // 030521 SSRAM[12626] = 36'o000000000000; // 030522 SSRAM[12627] = 36'o000000000000; // 030523 SSRAM[12628] = 36'o777777777777; // 030524 SSRAM[12629] = 36'o000000000000; // 030525 SSRAM[12671] = 36'o000000000000; // 030577 SSRAM[12672] = 36'o064250442606; // 030600 SSRAM[12673] = 36'o516632352212; // 030601 SSRAM[12674] = 36'o465006230144; // 030602 SSRAM[12675] = 36'o301010142254; // 030603 SSRAM[12676] = 36'o406350342610; // 030604 SSRAM[12677] = 36'o202231651650; // 030605 SSRAM[12678] = 36'o512530352222; // 030606 SSRAM[12679] = 36'o476344042222; // 030607 SSRAM[12680] = 36'o406171647646; // 030610 SSRAM[12681] = 36'o522230320106; // 030611 SSRAM[12682] = 36'o331013342246; // 030612 SSRAM[12683] = 36'o456070656432; // 030613 SSRAM[12684] = 36'o052111752604; // 030614 SSRAM[12685] = 36'o462124050244; // 030615 SSRAM[12686] = 36'o426071151622; // 030616 SSRAM[12687] = 36'o476344044634; // 030617 SSRAM[12688] = 36'o516512252606; // 030620 SSRAM[12689] = 36'o522231747246; // 030621 SSRAM[12690] = 36'o064240000000; // 030622 SSRAM[12691] = 36'o265000030011; // 030623 SSRAM[12692] = 36'o200640041024; // 030624 SSRAM[12693] = 36'o120040041020; // 030625 SSRAM[12694] = 36'o114040041022; // 030626 SSRAM[12695] = 36'o400540000000; // 030627 SSRAM[12696] = 36'o312040041020; // 030630 SSRAM[12697] = 36'o254000030635; // 030631 SSRAM[12698] = 36'o201540000001; // 030632 SSRAM[12699] = 36'o316100041021; // 030633 SSRAM[12700] = 36'o254000030640; // 030634 SSRAM[12701] = 36'o200613000001; // 030635 SSRAM[12702] = 36'o200553041020; // 030636 SSRAM[12703] = 36'o036600041033; // 030637 SSRAM[12704] = 36'o255000000000; // 030640 SSRAM[12705] = 36'o200640041036; // 030641 SSRAM[12706] = 36'o120040041021; // 030642 SSRAM[12707] = 36'o114040041022; // 030643 SSRAM[12708] = 36'o400540000000; // 030644 SSRAM[12709] = 36'o312040041021; // 030645 SSRAM[12710] = 36'o254000030652; // 030646 SSRAM[12711] = 36'o201540000001; // 030647 SSRAM[12712] = 36'o316100041020; // 030650 SSRAM[12713] = 36'o254000030655; // 030651 SSRAM[12714] = 36'o200613000001; // 030652 SSRAM[12715] = 36'o200553041021; // 030653 SSRAM[12716] = 36'o036600041044; // 030654 SSRAM[12717] = 36'o255000000000; // 030655 SSRAM[12718] = 36'o200640041051; // 030656 SSRAM[12719] = 36'o120040041047; // 030657 SSRAM[12720] = 36'o114040041022; // 030660 SSRAM[12721] = 36'o400540000000; // 030661 SSRAM[12722] = 36'o312040041021; // 030662 SSRAM[12723] = 36'o254000030667; // 030663 SSRAM[12724] = 36'o201540000001; // 030664 SSRAM[12725] = 36'o316100041021; // 030665 SSRAM[12726] = 36'o254000030672; // 030666 SSRAM[12727] = 36'o200613000001; // 030667 SSRAM[12728] = 36'o200553041047; // 030670 SSRAM[12729] = 36'o036600041057; // 030671 SSRAM[12730] = 36'o255000000000; // 030672 SSRAM[12731] = 36'o200640041062; // 030673 SSRAM[12732] = 36'o403040000002; // 030674 SSRAM[12733] = 36'o114040041020; // 030675 SSRAM[12734] = 36'o400540000000; // 030676 SSRAM[12735] = 36'o312040041020; // 030677 SSRAM[12736] = 36'o254000030704; // 030700 SSRAM[12737] = 36'o201540000001; // 030701 SSRAM[12738] = 36'o316100041021; // 030702 SSRAM[12739] = 36'o254000030707; // 030703 SSRAM[12740] = 36'o200613000001; // 030704 SSRAM[12741] = 36'o200553041020; // 030705 SSRAM[12742] = 36'o036600041070; // 030706 SSRAM[12743] = 36'o255000000000; // 030707 SSRAM[12744] = 36'o200640041073; // 030710 SSRAM[12745] = 36'o403040000002; // 030711 SSRAM[12746] = 36'o114040041021; // 030712 SSRAM[12747] = 36'o400540000000; // 030713 SSRAM[12748] = 36'o312040041021; // 030714 SSRAM[12749] = 36'o254000030721; // 030715 SSRAM[12750] = 36'o201540000001; // 030716 SSRAM[12751] = 36'o316100041020; // 030717 SSRAM[12752] = 36'o254000030724; // 030720 SSRAM[12753] = 36'o200613000001; // 030721 SSRAM[12754] = 36'o200553041021; // 030722 SSRAM[12755] = 36'o036600041101; // 030723 SSRAM[12756] = 36'o255000000000; // 030724 SSRAM[12757] = 36'o200640041104; // 030725 SSRAM[12758] = 36'o403040000002; // 030726 SSRAM[12759] = 36'o114040041047; // 030727 SSRAM[12760] = 36'o400540000000; // 030730 SSRAM[12761] = 36'o312040041021; // 030731 SSRAM[12762] = 36'o254000030736; // 030732 SSRAM[12763] = 36'o201540000001; // 030733 SSRAM[12764] = 36'o316100041021; // 030734 SSRAM[12765] = 36'o254000030741; // 030735 SSRAM[12766] = 36'o200613000001; // 030736 SSRAM[12767] = 36'o200553041047; // 030737 SSRAM[12768] = 36'o036600041112; // 030740 SSRAM[12769] = 36'o255000000000; // 030741 SSRAM[12770] = 36'o200640041115; // 030742 SSRAM[12771] = 36'o403040000002; // 030743 SSRAM[12772] = 36'o114040000001; // 030744 SSRAM[12773] = 36'o400540000000; // 030745 SSRAM[12774] = 36'o312040041020; // 030746 SSRAM[12775] = 36'o254000030753; // 030747 SSRAM[12776] = 36'o201540000001; // 030750 SSRAM[12777] = 36'o316100041020; // 030751 SSRAM[12778] = 36'o254000030756; // 030752 SSRAM[12779] = 36'o200613000001; // 030753 SSRAM[12780] = 36'o200553041022; // 030754 SSRAM[12781] = 36'o036600041123; // 030755 SSRAM[12782] = 36'o255000000000; // 030756 SSRAM[12783] = 36'o200640041130; // 030757 SSRAM[12784] = 36'o120040041126; // 030760 SSRAM[12785] = 36'o114040041022; // 030761 SSRAM[12786] = 36'o400540000000; // 030762 SSRAM[12787] = 36'o312040041020; // 030763 SSRAM[12788] = 36'o254000030770; // 030764 SSRAM[12789] = 36'o201540000001; // 030765 SSRAM[12790] = 36'o316100041127; // 030766 SSRAM[12791] = 36'o254000030773; // 030767 SSRAM[12792] = 36'o200613000001; // 030770 SSRAM[12793] = 36'o200553041126; // 030771 SSRAM[12794] = 36'o036600041136; // 030772 SSRAM[12795] = 36'o255000000000; // 030773 SSRAM[12796] = 36'o403040000002; // 030774 SSRAM[12797] = 36'o200640041141; // 030775 SSRAM[12798] = 36'o114040041126; // 030776 SSRAM[12799] = 36'o400540000000; // 030777 SSRAM[12800] = 36'o312040041020; // 031000 SSRAM[12801] = 36'o254000031005; // 031001 SSRAM[12802] = 36'o201540000001; // 031002 SSRAM[12803] = 36'o316100041127; // 031003 SSRAM[12804] = 36'o254000031010; // 031004 SSRAM[12805] = 36'o200613000001; // 031005 SSRAM[12806] = 36'o200553041126; // 031006 SSRAM[12807] = 36'o036600041147; // 031007 SSRAM[12808] = 36'o255000000000; // 031010 SSRAM[12809] = 36'o200640041154; // 031011 SSRAM[12810] = 36'o120040041152; // 031012 SSRAM[12811] = 36'o114040041022; // 031013 SSRAM[12812] = 36'o400540000000; // 031014 SSRAM[12813] = 36'o312040041020; // 031015 SSRAM[12814] = 36'o254000031022; // 031016 SSRAM[12815] = 36'o201540000001; // 031017 SSRAM[12816] = 36'o316100041153; // 031020 SSRAM[12817] = 36'o254000031025; // 031021 SSRAM[12818] = 36'o200613000001; // 031022 SSRAM[12819] = 36'o200553041152; // 031023 SSRAM[12820] = 36'o036600041136; // 031024 SSRAM[12821] = 36'o255000000000; // 031025 SSRAM[12822] = 36'o403040000002; // 031026 SSRAM[12823] = 36'o200640041155; // 031027 SSRAM[12824] = 36'o114040041152; // 031030 SSRAM[12825] = 36'o400540000000; // 031031 SSRAM[12826] = 36'o312040041020; // 031032 SSRAM[12827] = 36'o254000031037; // 031033 SSRAM[12828] = 36'o201540000001; // 031034 SSRAM[12829] = 36'o316100041153; // 031035 SSRAM[12830] = 36'o254000031042; // 031036 SSRAM[12831] = 36'o200613000001; // 031037 SSRAM[12832] = 36'o200553041152; // 031040 SSRAM[12833] = 36'o036600041147; // 031041 SSRAM[12834] = 36'o255000000000; // 031042 SSRAM[12835] = 36'o200640041160; // 031043 SSRAM[12836] = 36'o120040041156; // 031044 SSRAM[12837] = 36'o114040041022; // 031045 SSRAM[12838] = 36'o400540000000; // 031046 SSRAM[12839] = 36'o312040041127; // 031047 SSRAM[12840] = 36'o254000031054; // 031050 SSRAM[12841] = 36'o201540000001; // 031051 SSRAM[12842] = 36'o316100041020; // 031052 SSRAM[12843] = 36'o254000031057; // 031053 SSRAM[12844] = 36'o200613000001; // 031054 SSRAM[12845] = 36'o200553041156; // 031055 SSRAM[12846] = 36'o036600041136; // 031056 SSRAM[12847] = 36'o255000000000; // 031057 SSRAM[12848] = 36'o403040000002; // 031060 SSRAM[12849] = 36'o200640041161; // 031061 SSRAM[12850] = 36'o114040041156; // 031062 SSRAM[12851] = 36'o400540000000; // 031063 SSRAM[12852] = 36'o312040041127; // 031064 SSRAM[12853] = 36'o254000031071; // 031065 SSRAM[12854] = 36'o201540000001; // 031066 SSRAM[12855] = 36'o316100041020; // 031067 SSRAM[12856] = 36'o254000031074; // 031070 SSRAM[12857] = 36'o200613000001; // 031071 SSRAM[12858] = 36'o200553041156; // 031072 SSRAM[12859] = 36'o036600041147; // 031073 SSRAM[12860] = 36'o255000000000; // 031074 SSRAM[12861] = 36'o200640041164; // 031075 SSRAM[12862] = 36'o120040041162; // 031076 SSRAM[12863] = 36'o114040041022; // 031077 SSRAM[12864] = 36'o400540000000; // 031100 SSRAM[12865] = 36'o312040041153; // 031101 SSRAM[12866] = 36'o254000031106; // 031102 SSRAM[12867] = 36'o201540000001; // 031103 SSRAM[12868] = 36'o316100041020; // 031104 SSRAM[12869] = 36'o254000031111; // 031105 SSRAM[12870] = 36'o200613000001; // 031106 SSRAM[12871] = 36'o200553041162; // 031107 SSRAM[12872] = 36'o036600041136; // 031110 SSRAM[12873] = 36'o255000000000; // 031111 SSRAM[12874] = 36'o403040000002; // 031112 SSRAM[12875] = 36'o200640041165; // 031113 SSRAM[12876] = 36'o114040041162; // 031114 SSRAM[12877] = 36'o400540000000; // 031115 SSRAM[12878] = 36'o312040041153; // 031116 SSRAM[12879] = 36'o254000031123; // 031117 SSRAM[12880] = 36'o201540000001; // 031120 SSRAM[12881] = 36'o316100041020; // 031121 SSRAM[12882] = 36'o254000031126; // 031122 SSRAM[12883] = 36'o200613000001; // 031123 SSRAM[12884] = 36'o200553041162; // 031124 SSRAM[12885] = 36'o036600041147; // 031125 SSRAM[12886] = 36'o255000000000; // 031126 SSRAM[12887] = 36'o200640041170; // 031127 SSRAM[12888] = 36'o120040041166; // 031130 SSRAM[12889] = 36'o114040041022; // 031131 SSRAM[12890] = 36'o400540000000; // 031132 SSRAM[12891] = 36'o312040041166; // 031133 SSRAM[12892] = 36'o254000031140; // 031134 SSRAM[12893] = 36'o201540000001; // 031135 SSRAM[12894] = 36'o316100041167; // 031136 SSRAM[12895] = 36'o254000031143; // 031137 SSRAM[12896] = 36'o200613000001; // 031140 SSRAM[12897] = 36'o200553041166; // 031141 SSRAM[12898] = 36'o036600041136; // 031142 SSRAM[12899] = 36'o255000000000; // 031143 SSRAM[12900] = 36'o403040000002; // 031144 SSRAM[12901] = 36'o200640041171; // 031145 SSRAM[12902] = 36'o114040041166; // 031146 SSRAM[12903] = 36'o400540000000; // 031147 SSRAM[12904] = 36'o312040041166; // 031150 SSRAM[12905] = 36'o254000031155; // 031151 SSRAM[12906] = 36'o201540000001; // 031152 SSRAM[12907] = 36'o316100041167; // 031153 SSRAM[12908] = 36'o254000031160; // 031154 SSRAM[12909] = 36'o200613000001; // 031155 SSRAM[12910] = 36'o200553041166; // 031156 SSRAM[12911] = 36'o036600041147; // 031157 SSRAM[12912] = 36'o255000000000; // 031160 SSRAM[12913] = 36'o200640041174; // 031161 SSRAM[12914] = 36'o120040041172; // 031162 SSRAM[12915] = 36'o114040041022; // 031163 SSRAM[12916] = 36'o400540000000; // 031164 SSRAM[12917] = 36'o312040041166; // 031165 SSRAM[12918] = 36'o254000031172; // 031166 SSRAM[12919] = 36'o201540000001; // 031167 SSRAM[12920] = 36'o316100041173; // 031170 SSRAM[12921] = 36'o254000031175; // 031171 SSRAM[12922] = 36'o200613000001; // 031172 SSRAM[12923] = 36'o200553041172; // 031173 SSRAM[12924] = 36'o036600041136; // 031174 SSRAM[12925] = 36'o255000000000; // 031175 SSRAM[12926] = 36'o403040000002; // 031176 SSRAM[12927] = 36'o200640041175; // 031177 SSRAM[12928] = 36'o114040041172; // 031200 SSRAM[12929] = 36'o400540000000; // 031201 SSRAM[12930] = 36'o312040041166; // 031202 SSRAM[12931] = 36'o254000031207; // 031203 SSRAM[12932] = 36'o201540000001; // 031204 SSRAM[12933] = 36'o316100041173; // 031205 SSRAM[12934] = 36'o254000031212; // 031206 SSRAM[12935] = 36'o200613000001; // 031207 SSRAM[12936] = 36'o200553041172; // 031210 SSRAM[12937] = 36'o036600041147; // 031211 SSRAM[12938] = 36'o255000000000; // 031212 SSRAM[12939] = 36'o200640041200; // 031213 SSRAM[12940] = 36'o120040041176; // 031214 SSRAM[12941] = 36'o114040041022; // 031215 SSRAM[12942] = 36'o400540000000; // 031216 SSRAM[12943] = 36'o312040041167; // 031217 SSRAM[12944] = 36'o254000031224; // 031220 SSRAM[12945] = 36'o201540000001; // 031221 SSRAM[12946] = 36'o316100041166; // 031222 SSRAM[12947] = 36'o254000031227; // 031223 SSRAM[12948] = 36'o200613000001; // 031224 SSRAM[12949] = 36'o200553041176; // 031225 SSRAM[12950] = 36'o036600041136; // 031226 SSRAM[12951] = 36'o255000000000; // 031227 SSRAM[12952] = 36'o403040000002; // 031230 SSRAM[12953] = 36'o200640041201; // 031231 SSRAM[12954] = 36'o114040041176; // 031232 SSRAM[12955] = 36'o400540000000; // 031233 SSRAM[12956] = 36'o312040041167; // 031234 SSRAM[12957] = 36'o254000031241; // 031235 SSRAM[12958] = 36'o201540000001; // 031236 SSRAM[12959] = 36'o316100041166; // 031237 SSRAM[12960] = 36'o254000031244; // 031240 SSRAM[12961] = 36'o200613000001; // 031241 SSRAM[12962] = 36'o200553041176; // 031242 SSRAM[12963] = 36'o036600041147; // 031243 SSRAM[12964] = 36'o255000000000; // 031244 SSRAM[12965] = 36'o200640041204; // 031245 SSRAM[12966] = 36'o120040041202; // 031246 SSRAM[12967] = 36'o114040041022; // 031247 SSRAM[12968] = 36'o400540000000; // 031250 SSRAM[12969] = 36'o312040041173; // 031251 SSRAM[12970] = 36'o254000031256; // 031252 SSRAM[12971] = 36'o201540000001; // 031253 SSRAM[12972] = 36'o316100041166; // 031254 SSRAM[12973] = 36'o254000031261; // 031255 SSRAM[12974] = 36'o200613000001; // 031256 SSRAM[12975] = 36'o200553041202; // 031257 SSRAM[12976] = 36'o036600041136; // 031260 SSRAM[12977] = 36'o255000000000; // 031261 SSRAM[12978] = 36'o403040000002; // 031262 SSRAM[12979] = 36'o200640041205; // 031263 SSRAM[12980] = 36'o114040041202; // 031264 SSRAM[12981] = 36'o400540000000; // 031265 SSRAM[12982] = 36'o312040041173; // 031266 SSRAM[12983] = 36'o254000031273; // 031267 SSRAM[12984] = 36'o201540000001; // 031270 SSRAM[12985] = 36'o316100041166; // 031271 SSRAM[12986] = 36'o254000031276; // 031272 SSRAM[12987] = 36'o200613000001; // 031273 SSRAM[12988] = 36'o200553041202; // 031274 SSRAM[12989] = 36'o036600041147; // 031275 SSRAM[12990] = 36'o255000000000; // 031276 SSRAM[12991] = 36'o400440000000; // 031277 SSRAM[12992] = 36'o120040041126; // 031300 SSRAM[12993] = 36'o137440031333; // 031301 SSRAM[12994] = 36'o256000031333; // 031302 SSRAM[12995] = 36'o124040031327; // 031303 SSRAM[12996] = 36'o200640041206; // 031304 SSRAM[12997] = 36'o244040000001; // 031305 SSRAM[12998] = 36'o124040031331; // 031306 SSRAM[12999] = 36'o120040031327; // 031307 SSRAM[13000] = 36'o114040000001; // 031310 SSRAM[13001] = 36'o400540000000; // 031311 SSRAM[13002] = 36'o312040031331; // 031312 SSRAM[13003] = 36'o254000031317; // 031313 SSRAM[13004] = 36'o201540000001; // 031314 SSRAM[13005] = 36'o316100031332; // 031315 SSRAM[13006] = 36'o254000031322; // 031316 SSRAM[13007] = 36'o200613031331; // 031317 SSRAM[13008] = 36'o200553000001; // 031320 SSRAM[13009] = 36'o036600041214; // 031321 SSRAM[13010] = 36'o255000000000; // 031322 SSRAM[13011] = 36'o350000000011; // 031323 SSRAM[13012] = 36'o302440000105; // 031324 SSRAM[13013] = 36'o254000031301; // 031325 SSRAM[13014] = 36'o254000031335; // 031326 SSRAM[13019] = 36'o431000031334; // 031333 SSRAM[13020] = 36'o244040000000; // 031334 SSRAM[13021] = 36'o200640041221; // 031335 SSRAM[13022] = 36'o120040041217; // 031336 SSRAM[13023] = 36'o114040041126; // 031337 SSRAM[13024] = 36'o400540000000; // 031340 SSRAM[13025] = 36'o312040041127; // 031341 SSRAM[13026] = 36'o254000031346; // 031342 SSRAM[13027] = 36'o201540000001; // 031343 SSRAM[13028] = 36'o316100041020; // 031344 SSRAM[13029] = 36'o254000031351; // 031345 SSRAM[13030] = 36'o200613000001; // 031346 SSRAM[13031] = 36'o200553041156; // 031347 SSRAM[13032] = 36'o036600041227; // 031350 SSRAM[13033] = 36'o255000000000; // 031351 SSRAM[13034] = 36'o200640041232; // 031352 SSRAM[13035] = 36'o120040041126; // 031353 SSRAM[13036] = 36'o114040041217; // 031354 SSRAM[13037] = 36'o400540000000; // 031355 SSRAM[13038] = 36'o312040041127; // 031356 SSRAM[13039] = 36'o254000031363; // 031357 SSRAM[13040] = 36'o201540000001; // 031360 SSRAM[13041] = 36'o316100041020; // 031361 SSRAM[13042] = 36'o254000031366; // 031362 SSRAM[13043] = 36'o200613000001; // 031363 SSRAM[13044] = 36'o200553041156; // 031364 SSRAM[13045] = 36'o036600041240; // 031365 SSRAM[13046] = 36'o255000000000; // 031366 SSRAM[13047] = 36'o120040031602; // 031367 SSRAM[13048] = 36'o255740031371; // 031370 SSRAM[13049] = 36'o505640031602; // 031371 SSRAM[13050] = 36'o541640041126; // 031372 SSRAM[13051] = 36'o114040041126; // 031373 SSRAM[13052] = 36'o264000031375; // 031374 SSRAM[13053] = 36'o000000000000; // 031375 SSRAM[13054] = 36'o400540000000; // 031376 SSRAM[13055] = 36'o312040031604; // 031377 SSRAM[13056] = 36'o254000031404; // 031400 SSRAM[13057] = 36'o201540000001; // 031401 SSRAM[13058] = 36'o316100031605; // 031402 SSRAM[13059] = 36'o254000031407; // 031403 SSRAM[13060] = 36'o200613000001; // 031404 SSRAM[13061] = 36'o200553031604; // 031405 SSRAM[13062] = 36'o036600041250; // 031406 SSRAM[13063] = 36'o255000000000; // 031407 SSRAM[13064] = 36'o200540031375; // 031410 SSRAM[13065] = 36'o200600041020; // 031411 SSRAM[13066] = 36'o430540000014; // 031412 SSRAM[13067] = 36'o603540740000; // 031413 SSRAM[13068] = 36'o036540041262; // 031414 SSRAM[13069] = 36'o255000000000; // 031415 SSRAM[13070] = 36'o120040031606; // 031416 SSRAM[13071] = 36'o255740031420; // 031417 SSRAM[13072] = 36'o505640031606; // 031420 SSRAM[13073] = 36'o541640041126; // 031421 SSRAM[13074] = 36'o114040041126; // 031422 SSRAM[13075] = 36'o264000031424; // 031423 SSRAM[13076] = 36'o000000000000; // 031424 SSRAM[13077] = 36'o400540000000; // 031425 SSRAM[13078] = 36'o312040031610; // 031426 SSRAM[13079] = 36'o254000031433; // 031427 SSRAM[13080] = 36'o201540000001; // 031430 SSRAM[13081] = 36'o316100031611; // 031431 SSRAM[13082] = 36'o254000031436; // 031432 SSRAM[13083] = 36'o200613000001; // 031433 SSRAM[13084] = 36'o200553031610; // 031434 SSRAM[13085] = 36'o036600041250; // 031435 SSRAM[13086] = 36'o255000000000; // 031436 SSRAM[13087] = 36'o200540031424; // 031437 SSRAM[13088] = 36'o200600041020; // 031440 SSRAM[13089] = 36'o430540000014; // 031441 SSRAM[13090] = 36'o603540740000; // 031442 SSRAM[13091] = 36'o036540041265; // 031443 SSRAM[13092] = 36'o255000000000; // 031444 SSRAM[13093] = 36'o120040031612; // 031445 SSRAM[13094] = 36'o255740031447; // 031446 SSRAM[13095] = 36'o505640031612; // 031447 SSRAM[13096] = 36'o541640041126; // 031450 SSRAM[13097] = 36'o114040041126; // 031451 SSRAM[13098] = 36'o264000031453; // 031452 SSRAM[13099] = 36'o000000000000; // 031453 SSRAM[13100] = 36'o400540000000; // 031454 SSRAM[13101] = 36'o312040031614; // 031455 SSRAM[13102] = 36'o254000031462; // 031456 SSRAM[13103] = 36'o201540000001; // 031457 SSRAM[13104] = 36'o316100031615; // 031460 SSRAM[13105] = 36'o254000031465; // 031461 SSRAM[13106] = 36'o200613000001; // 031462 SSRAM[13107] = 36'o200553031614; // 031463 SSRAM[13108] = 36'o036600041250; // 031464 SSRAM[13109] = 36'o255000000000; // 031465 SSRAM[13110] = 36'o200540031453; // 031466 SSRAM[13111] = 36'o200600041020; // 031467 SSRAM[13112] = 36'o430540000014; // 031470 SSRAM[13113] = 36'o603540740000; // 031471 SSRAM[13114] = 36'o036540041270; // 031472 SSRAM[13115] = 36'o255000000000; // 031473 SSRAM[13116] = 36'o120040031616; // 031474 SSRAM[13117] = 36'o255740031476; // 031475 SSRAM[13118] = 36'o505640031616; // 031476 SSRAM[13119] = 36'o541640041126; // 031477 SSRAM[13120] = 36'o114040041126; // 031500 SSRAM[13121] = 36'o264000031502; // 031501 SSRAM[13122] = 36'o000000000000; // 031502 SSRAM[13123] = 36'o400540000000; // 031503 SSRAM[13124] = 36'o312040031620; // 031504 SSRAM[13125] = 36'o254000031511; // 031505 SSRAM[13126] = 36'o201540000001; // 031506 SSRAM[13127] = 36'o316100031621; // 031507 SSRAM[13128] = 36'o254000031514; // 031510 SSRAM[13129] = 36'o200613000001; // 031511 SSRAM[13130] = 36'o200553031620; // 031512 SSRAM[13131] = 36'o036600041250; // 031513 SSRAM[13132] = 36'o255000000000; // 031514 SSRAM[13133] = 36'o200540031502; // 031515 SSRAM[13134] = 36'o200600041020; // 031516 SSRAM[13135] = 36'o430540000014; // 031517 SSRAM[13136] = 36'o603540740000; // 031520 SSRAM[13137] = 36'o036540041273; // 031521 SSRAM[13138] = 36'o255000000000; // 031522 SSRAM[13139] = 36'o120040031622; // 031523 SSRAM[13140] = 36'o255740031525; // 031524 SSRAM[13141] = 36'o505640031622; // 031525 SSRAM[13142] = 36'o541640041126; // 031526 SSRAM[13143] = 36'o114040041126; // 031527 SSRAM[13144] = 36'o264000031531; // 031530 SSRAM[13145] = 36'o000000000000; // 031531 SSRAM[13146] = 36'o400540000000; // 031532 SSRAM[13147] = 36'o312040031624; // 031533 SSRAM[13148] = 36'o254000031540; // 031534 SSRAM[13149] = 36'o201540000001; // 031535 SSRAM[13150] = 36'o316100031625; // 031536 SSRAM[13151] = 36'o254000031543; // 031537 SSRAM[13152] = 36'o200613000001; // 031540 SSRAM[13153] = 36'o200553031624; // 031541 SSRAM[13154] = 36'o036600041250; // 031542 SSRAM[13155] = 36'o255000000000; // 031543 SSRAM[13156] = 36'o200540031531; // 031544 SSRAM[13157] = 36'o200600041020; // 031545 SSRAM[13158] = 36'o430540000014; // 031546 SSRAM[13159] = 36'o603540740000; // 031547 SSRAM[13160] = 36'o036540041276; // 031550 SSRAM[13161] = 36'o255000000000; // 031551 SSRAM[13162] = 36'o120040031626; // 031552 SSRAM[13163] = 36'o255740031554; // 031553 SSRAM[13164] = 36'o505640031626; // 031554 SSRAM[13165] = 36'o541640041126; // 031555 SSRAM[13166] = 36'o114040041126; // 031556 SSRAM[13167] = 36'o264000031560; // 031557 SSRAM[13168] = 36'o000000000000; // 031560 SSRAM[13169] = 36'o400540000000; // 031561 SSRAM[13170] = 36'o312040031630; // 031562 SSRAM[13171] = 36'o254000031567; // 031563 SSRAM[13172] = 36'o201540000001; // 031564 SSRAM[13173] = 36'o316100031631; // 031565 SSRAM[13174] = 36'o254000031572; // 031566 SSRAM[13175] = 36'o200613000001; // 031567 SSRAM[13176] = 36'o200553031630; // 031570 SSRAM[13177] = 36'o036600041250; // 031571 SSRAM[13178] = 36'o255000000000; // 031572 SSRAM[13179] = 36'o200540031560; // 031573 SSRAM[13180] = 36'o200600041020; // 031574 SSRAM[13181] = 36'o430540000014; // 031575 SSRAM[13182] = 36'o603540740000; // 031576 SSRAM[13183] = 36'o036540041301; // 031577 SSRAM[13184] = 36'o255000000000; // 031600 SSRAM[13185] = 36'o254000031632; // 031601 SSRAM[13186] = 36'o777777777777; // 031602 SSRAM[13187] = 36'o577777777777; // 031603 SSRAM[13188] = 36'o777777777777; // 031604 SSRAM[13189] = 36'o600000000000; // 031605 SSRAM[13190] = 36'o777777777776; // 031606 SSRAM[13191] = 36'o777777777777; // 031607 SSRAM[13192] = 36'o777777777777; // 031610 SSRAM[13193] = 36'o400000000000; // 031611 SSRAM[13194] = 36'o577777777777; // 031612 SSRAM[13195] = 36'o777777777777; // 031613 SSRAM[13196] = 36'o600000000000; // 031614 SSRAM[13197] = 36'o400000000000; // 031615 SSRAM[13198] = 36'o377777777777; // 031616 SSRAM[13199] = 36'o177777777777; // 031617 SSRAM[13200] = 36'o377777777777; // 031620 SSRAM[13201] = 36'o200000000000; // 031621 SSRAM[13202] = 36'o377777777776; // 031622 SSRAM[13203] = 36'o377777777777; // 031623 SSRAM[13204] = 36'o377777777777; // 031624 SSRAM[13205] = 36'o000000000000; // 031625 SSRAM[13206] = 36'o177777777777; // 031626 SSRAM[13207] = 36'o377777777777; // 031627 SSRAM[13208] = 36'o200000000000; // 031630 SSRAM[13209] = 36'o000000000000; // 031631 SSRAM[13210] = 36'o200640041304; // 031632 SSRAM[13211] = 36'o120040033057; // 031633 SSRAM[13212] = 36'o255740031635; // 031634 SSRAM[13213] = 36'o114040033061; // 031635 SSRAM[13214] = 36'o264000031637; // 031636 SSRAM[13215] = 36'o000000000000; // 031637 SSRAM[13216] = 36'o400540000000; // 031640 SSRAM[13217] = 36'o312040041020; // 031641 SSRAM[13218] = 36'o254000031646; // 031642 SSRAM[13219] = 36'o201540000001; // 031643 SSRAM[13220] = 36'o316100041127; // 031644 SSRAM[13221] = 36'o254000031651; // 031645 SSRAM[13222] = 36'o200613000001; // 031646 SSRAM[13223] = 36'o200553041126; // 031647 SSRAM[13224] = 36'o036600041312; // 031650 SSRAM[13225] = 36'o255000000000; // 031651 SSRAM[13226] = 36'o200540031637; // 031652 SSRAM[13227] = 36'o200600041020; // 031653 SSRAM[13228] = 36'o430540000014; // 031654 SSRAM[13229] = 36'o603540740000; // 031655 SSRAM[13230] = 36'o036540041325; // 031656 SSRAM[13231] = 36'o255000000000; // 031657 SSRAM[13232] = 36'o200640041330; // 031660 SSRAM[13233] = 36'o120040033063; // 031661 SSRAM[13234] = 36'o255740031663; // 031662 SSRAM[13235] = 36'o114040033065; // 031663 SSRAM[13236] = 36'o264000031665; // 031664 SSRAM[13237] = 36'o000000000000; // 031665 SSRAM[13238] = 36'o400540000000; // 031666 SSRAM[13239] = 36'o312040041020; // 031667 SSRAM[13240] = 36'o254000031674; // 031670 SSRAM[13241] = 36'o201540000001; // 031671 SSRAM[13242] = 36'o316100041127; // 031672 SSRAM[13243] = 36'o254000031677; // 031673 SSRAM[13244] = 36'o200613000001; // 031674 SSRAM[13245] = 36'o200553041126; // 031675 SSRAM[13246] = 36'o036600041312; // 031676 SSRAM[13247] = 36'o255000000000; // 031677 SSRAM[13248] = 36'o200540031665; // 031700 SSRAM[13249] = 36'o200600041020; // 031701 SSRAM[13250] = 36'o430540000014; // 031702 SSRAM[13251] = 36'o603540740000; // 031703 SSRAM[13252] = 36'o036540041331; // 031704 SSRAM[13253] = 36'o255000000000; // 031705 SSRAM[13254] = 36'o200640041334; // 031706 SSRAM[13255] = 36'o120040033067; // 031707 SSRAM[13256] = 36'o255740031711; // 031710 SSRAM[13257] = 36'o114040033071; // 031711 SSRAM[13258] = 36'o264000031713; // 031712 SSRAM[13259] = 36'o000000000000; // 031713 SSRAM[13260] = 36'o400540000000; // 031714 SSRAM[13261] = 36'o312040041020; // 031715 SSRAM[13262] = 36'o254000031722; // 031716 SSRAM[13263] = 36'o201540000001; // 031717 SSRAM[13264] = 36'o316100041127; // 031720 SSRAM[13265] = 36'o254000031725; // 031721 SSRAM[13266] = 36'o200613000001; // 031722 SSRAM[13267] = 36'o200553041126; // 031723 SSRAM[13268] = 36'o036600041312; // 031724 SSRAM[13269] = 36'o255000000000; // 031725 SSRAM[13270] = 36'o200540031713; // 031726 SSRAM[13271] = 36'o200600041020; // 031727 SSRAM[13272] = 36'o430540000014; // 031730 SSRAM[13273] = 36'o603540740000; // 031731 SSRAM[13274] = 36'o036540041335; // 031732 SSRAM[13275] = 36'o255000000000; // 031733 SSRAM[13276] = 36'o200640041340; // 031734 SSRAM[13277] = 36'o120040033073; // 031735 SSRAM[13278] = 36'o255740031737; // 031736 SSRAM[13279] = 36'o114040033075; // 031737 SSRAM[13280] = 36'o264000031741; // 031740 SSRAM[13281] = 36'o000000000000; // 031741 SSRAM[13282] = 36'o400540000000; // 031742 SSRAM[13283] = 36'o312040041166; // 031743 SSRAM[13284] = 36'o254000031750; // 031744 SSRAM[13285] = 36'o201540000001; // 031745 SSRAM[13286] = 36'o316100041166; // 031746 SSRAM[13287] = 36'o254000031753; // 031747 SSRAM[13288] = 36'o200613000001; // 031750 SSRAM[13289] = 36'o200553041341; // 031751 SSRAM[13290] = 36'o036600041312; // 031752 SSRAM[13291] = 36'o255000000000; // 031753 SSRAM[13292] = 36'o200540031741; // 031754 SSRAM[13293] = 36'o200600041020; // 031755 SSRAM[13294] = 36'o430540000014; // 031756 SSRAM[13295] = 36'o603540740000; // 031757 SSRAM[13296] = 36'o036540041343; // 031760 SSRAM[13297] = 36'o255000000000; // 031761 SSRAM[13298] = 36'o200640041346; // 031762 SSRAM[13299] = 36'o120040033077; // 031763 SSRAM[13300] = 36'o255740031765; // 031764 SSRAM[13301] = 36'o114040033101; // 031765 SSRAM[13302] = 36'o264000031767; // 031766 SSRAM[13303] = 36'o000000000000; // 031767 SSRAM[13304] = 36'o400540000000; // 031770 SSRAM[13305] = 36'o312040041166; // 031771 SSRAM[13306] = 36'o254000031776; // 031772 SSRAM[13307] = 36'o201540000001; // 031773 SSRAM[13308] = 36'o316100041166; // 031774 SSRAM[13309] = 36'o254000032001; // 031775 SSRAM[13310] = 36'o200613000001; // 031776 SSRAM[13311] = 36'o200553041341; // 031777 SSRAM[13312] = 36'o036600041312; // 032000 SSRAM[13313] = 36'o255000000000; // 032001 SSRAM[13314] = 36'o200540031767; // 032002 SSRAM[13315] = 36'o200600041020; // 032003 SSRAM[13316] = 36'o430540000014; // 032004 SSRAM[13317] = 36'o603540740000; // 032005 SSRAM[13318] = 36'o036540041347; // 032006 SSRAM[13319] = 36'o255000000000; // 032007 SSRAM[13320] = 36'o200640041352; // 032010 SSRAM[13321] = 36'o120040033103; // 032011 SSRAM[13322] = 36'o255740032013; // 032012 SSRAM[13323] = 36'o114040033105; // 032013 SSRAM[13324] = 36'o264000032015; // 032014 SSRAM[13325] = 36'o000000000000; // 032015 SSRAM[13326] = 36'o400540000000; // 032016 SSRAM[13327] = 36'o312040041166; // 032017 SSRAM[13328] = 36'o254000032024; // 032020 SSRAM[13329] = 36'o201540000001; // 032021 SSRAM[13330] = 36'o316100041166; // 032022 SSRAM[13331] = 36'o254000032027; // 032023 SSRAM[13332] = 36'o200613000001; // 032024 SSRAM[13333] = 36'o200553041341; // 032025 SSRAM[13334] = 36'o036600041312; // 032026 SSRAM[13335] = 36'o255000000000; // 032027 SSRAM[13336] = 36'o200540032015; // 032030 SSRAM[13337] = 36'o200600041020; // 032031 SSRAM[13338] = 36'o430540000014; // 032032 SSRAM[13339] = 36'o603540740000; // 032033 SSRAM[13340] = 36'o036540041353; // 032034 SSRAM[13341] = 36'o255000000000; // 032035 SSRAM[13342] = 36'o200640041356; // 032036 SSRAM[13343] = 36'o120040033107; // 032037 SSRAM[13344] = 36'o255740032041; // 032040 SSRAM[13345] = 36'o114040033111; // 032041 SSRAM[13346] = 36'o264000032043; // 032042 SSRAM[13347] = 36'o000000000000; // 032043 SSRAM[13348] = 36'o400540000000; // 032044 SSRAM[13349] = 36'o312040041167; // 032045 SSRAM[13350] = 36'o254000032052; // 032046 SSRAM[13351] = 36'o201540000001; // 032047 SSRAM[13352] = 36'o316100041167; // 032050 SSRAM[13353] = 36'o254000032055; // 032051 SSRAM[13354] = 36'o200613000001; // 032052 SSRAM[13355] = 36'o200553041357; // 032053 SSRAM[13356] = 36'o036600041366; // 032054 SSRAM[13357] = 36'o255000000000; // 032055 SSRAM[13358] = 36'o200540032043; // 032056 SSRAM[13359] = 36'o200600041371; // 032057 SSRAM[13360] = 36'o430540000014; // 032060 SSRAM[13361] = 36'o603540740000; // 032061 SSRAM[13362] = 36'o036540041402; // 032062 SSRAM[13363] = 36'o255000000000; // 032063 SSRAM[13364] = 36'o200640041405; // 032064 SSRAM[13365] = 36'o120040033113; // 032065 SSRAM[13366] = 36'o255740032067; // 032066 SSRAM[13367] = 36'o114040033115; // 032067 SSRAM[13368] = 36'o264000032071; // 032070 SSRAM[13369] = 36'o000000000000; // 032071 SSRAM[13370] = 36'o400540000000; // 032072 SSRAM[13371] = 36'o312040041167; // 032073 SSRAM[13372] = 36'o254000032100; // 032074 SSRAM[13373] = 36'o201540000001; // 032075 SSRAM[13374] = 36'o316100041167; // 032076 SSRAM[13375] = 36'o254000032103; // 032077 SSRAM[13376] = 36'o200613000001; // 032100 SSRAM[13377] = 36'o200553041357; // 032101 SSRAM[13378] = 36'o036600041366; // 032102 SSRAM[13379] = 36'o255000000000; // 032103 SSRAM[13380] = 36'o200540032071; // 032104 SSRAM[13381] = 36'o200600041371; // 032105 SSRAM[13382] = 36'o430540000014; // 032106 SSRAM[13383] = 36'o603540740000; // 032107 SSRAM[13384] = 36'o036540041406; // 032110 SSRAM[13385] = 36'o255000000000; // 032111 SSRAM[13386] = 36'o200640041411; // 032112 SSRAM[13387] = 36'o120040033117; // 032113 SSRAM[13388] = 36'o255740032115; // 032114 SSRAM[13389] = 36'o114040033121; // 032115 SSRAM[13390] = 36'o264000032117; // 032116 SSRAM[13391] = 36'o000000000000; // 032117 SSRAM[13392] = 36'o400540000000; // 032120 SSRAM[13393] = 36'o312040041167; // 032121 SSRAM[13394] = 36'o254000032126; // 032122 SSRAM[13395] = 36'o201540000001; // 032123 SSRAM[13396] = 36'o316100041167; // 032124 SSRAM[13397] = 36'o254000032131; // 032125 SSRAM[13398] = 36'o200613000001; // 032126 SSRAM[13399] = 36'o200553041357; // 032127 SSRAM[13400] = 36'o036600041366; // 032130 SSRAM[13401] = 36'o255000000000; // 032131 SSRAM[13402] = 36'o200540032117; // 032132 SSRAM[13403] = 36'o200600041371; // 032133 SSRAM[13404] = 36'o430540000014; // 032134 SSRAM[13405] = 36'o603540740000; // 032135 SSRAM[13406] = 36'o036540041412; // 032136 SSRAM[13407] = 36'o255000000000; // 032137 SSRAM[13408] = 36'o200640041415; // 032140 SSRAM[13409] = 36'o120040033123; // 032141 SSRAM[13410] = 36'o255740032143; // 032142 SSRAM[13411] = 36'o114040033125; // 032143 SSRAM[13412] = 36'o264000032145; // 032144 SSRAM[13413] = 36'o000000000000; // 032145 SSRAM[13414] = 36'o400540000000; // 032146 SSRAM[13415] = 36'o312040041167; // 032147 SSRAM[13416] = 36'o254000032154; // 032150 SSRAM[13417] = 36'o201540000001; // 032151 SSRAM[13418] = 36'o316100041167; // 032152 SSRAM[13419] = 36'o254000032157; // 032153 SSRAM[13420] = 36'o200613000001; // 032154 SSRAM[13421] = 36'o200553041357; // 032155 SSRAM[13422] = 36'o036600041366; // 032156 SSRAM[13423] = 36'o255000000000; // 032157 SSRAM[13424] = 36'o200540032145; // 032160 SSRAM[13425] = 36'o200600041371; // 032161 SSRAM[13426] = 36'o430540000014; // 032162 SSRAM[13427] = 36'o603540740000; // 032163 SSRAM[13428] = 36'o036540041416; // 032164 SSRAM[13429] = 36'o255000000000; // 032165 SSRAM[13430] = 36'o200640041421; // 032166 SSRAM[13431] = 36'o120040033127; // 032167 SSRAM[13432] = 36'o255740032171; // 032170 SSRAM[13433] = 36'o114040033131; // 032171 SSRAM[13434] = 36'o264000032173; // 032172 SSRAM[13435] = 36'o000000000000; // 032173 SSRAM[13436] = 36'o400540000000; // 032174 SSRAM[13437] = 36'o312040041167; // 032175 SSRAM[13438] = 36'o254000032202; // 032176 SSRAM[13439] = 36'o201540000001; // 032177 SSRAM[13440] = 36'o316100041167; // 032200 SSRAM[13441] = 36'o254000032205; // 032201 SSRAM[13442] = 36'o200613000001; // 032202 SSRAM[13443] = 36'o200553041357; // 032203 SSRAM[13444] = 36'o036600041366; // 032204 SSRAM[13445] = 36'o255000000000; // 032205 SSRAM[13446] = 36'o200540032173; // 032206 SSRAM[13447] = 36'o200600041371; // 032207 SSRAM[13448] = 36'o430540000014; // 032210 SSRAM[13449] = 36'o603540740000; // 032211 SSRAM[13450] = 36'o036540041422; // 032212 SSRAM[13451] = 36'o255000000000; // 032213 SSRAM[13452] = 36'o200640041425; // 032214 SSRAM[13453] = 36'o120040033133; // 032215 SSRAM[13454] = 36'o255740032217; // 032216 SSRAM[13455] = 36'o114040033135; // 032217 SSRAM[13456] = 36'o264000032221; // 032220 SSRAM[13457] = 36'o000000000000; // 032221 SSRAM[13458] = 36'o400540000000; // 032222 SSRAM[13459] = 36'o312040041167; // 032223 SSRAM[13460] = 36'o254000032230; // 032224 SSRAM[13461] = 36'o201540000001; // 032225 SSRAM[13462] = 36'o316100041167; // 032226 SSRAM[13463] = 36'o254000032233; // 032227 SSRAM[13464] = 36'o200613000001; // 032230 SSRAM[13465] = 36'o200553041357; // 032231 SSRAM[13466] = 36'o036600041366; // 032232 SSRAM[13467] = 36'o255000000000; // 032233 SSRAM[13468] = 36'o200540032221; // 032234 SSRAM[13469] = 36'o200600041371; // 032235 SSRAM[13470] = 36'o430540000014; // 032236 SSRAM[13471] = 36'o603540740000; // 032237 SSRAM[13472] = 36'o036540041426; // 032240 SSRAM[13473] = 36'o255000000000; // 032241 SSRAM[13474] = 36'o200640041431; // 032242 SSRAM[13475] = 36'o120040033137; // 032243 SSRAM[13476] = 36'o255740032245; // 032244 SSRAM[13477] = 36'o114040033141; // 032245 SSRAM[13478] = 36'o264000032247; // 032246 SSRAM[13479] = 36'o000000000000; // 032247 SSRAM[13480] = 36'o400540000000; // 032250 SSRAM[13481] = 36'o312040041127; // 032251 SSRAM[13482] = 36'o254000032256; // 032252 SSRAM[13483] = 36'o201540000001; // 032253 SSRAM[13484] = 36'o316100041127; // 032254 SSRAM[13485] = 36'o254000032261; // 032255 SSRAM[13486] = 36'o200613000001; // 032256 SSRAM[13487] = 36'o200553041432; // 032257 SSRAM[13488] = 36'o036600041441; // 032260 SSRAM[13489] = 36'o255000000000; // 032261 SSRAM[13490] = 36'o200540032247; // 032262 SSRAM[13491] = 36'o200600041020; // 032263 SSRAM[13492] = 36'o430540000014; // 032264 SSRAM[13493] = 36'o603540740000; // 032265 SSRAM[13494] = 36'o036540041454; // 032266 SSRAM[13495] = 36'o255000000000; // 032267 SSRAM[13496] = 36'o200640041457; // 032270 SSRAM[13497] = 36'o120040033143; // 032271 SSRAM[13498] = 36'o255740032273; // 032272 SSRAM[13499] = 36'o114040033145; // 032273 SSRAM[13500] = 36'o264000032275; // 032274 SSRAM[13501] = 36'o000000000000; // 032275 SSRAM[13502] = 36'o400540000000; // 032276 SSRAM[13503] = 36'o312040041127; // 032277 SSRAM[13504] = 36'o254000032304; // 032300 SSRAM[13505] = 36'o201540000001; // 032301 SSRAM[13506] = 36'o316100041127; // 032302 SSRAM[13507] = 36'o254000032307; // 032303 SSRAM[13508] = 36'o200613000001; // 032304 SSRAM[13509] = 36'o200553041432; // 032305 SSRAM[13510] = 36'o036600041441; // 032306 SSRAM[13511] = 36'o255000000000; // 032307 SSRAM[13512] = 36'o200540032275; // 032310 SSRAM[13513] = 36'o200600041020; // 032311 SSRAM[13514] = 36'o430540000014; // 032312 SSRAM[13515] = 36'o603540740000; // 032313 SSRAM[13516] = 36'o036540041460; // 032314 SSRAM[13517] = 36'o255000000000; // 032315 SSRAM[13518] = 36'o200640041463; // 032316 SSRAM[13519] = 36'o120040033147; // 032317 SSRAM[13520] = 36'o255740032321; // 032320 SSRAM[13521] = 36'o114040033151; // 032321 SSRAM[13522] = 36'o264000032323; // 032322 SSRAM[13523] = 36'o000000000000; // 032323 SSRAM[13524] = 36'o400540000000; // 032324 SSRAM[13525] = 36'o312040041127; // 032325 SSRAM[13526] = 36'o254000032332; // 032326 SSRAM[13527] = 36'o201540000001; // 032327 SSRAM[13528] = 36'o316100041127; // 032330 SSRAM[13529] = 36'o254000032335; // 032331 SSRAM[13530] = 36'o200613000001; // 032332 SSRAM[13531] = 36'o200553041432; // 032333 SSRAM[13532] = 36'o036600041441; // 032334 SSRAM[13533] = 36'o255000000000; // 032335 SSRAM[13534] = 36'o200540032323; // 032336 SSRAM[13535] = 36'o200600041020; // 032337 SSRAM[13536] = 36'o430540000014; // 032340 SSRAM[13537] = 36'o603540740000; // 032341 SSRAM[13538] = 36'o036540041464; // 032342 SSRAM[13539] = 36'o255000000000; // 032343 SSRAM[13540] = 36'o200640041467; // 032344 SSRAM[13541] = 36'o120040033153; // 032345 SSRAM[13542] = 36'o255740032347; // 032346 SSRAM[13543] = 36'o114040033155; // 032347 SSRAM[13544] = 36'o264000032351; // 032350 SSRAM[13545] = 36'o000000000000; // 032351 SSRAM[13546] = 36'o400540000000; // 032352 SSRAM[13547] = 36'o312040041127; // 032353 SSRAM[13548] = 36'o254000032360; // 032354 SSRAM[13549] = 36'o201540000001; // 032355 SSRAM[13550] = 36'o316100041127; // 032356 SSRAM[13551] = 36'o254000032363; // 032357 SSRAM[13552] = 36'o200613000001; // 032360 SSRAM[13553] = 36'o200553041432; // 032361 SSRAM[13554] = 36'o036600041441; // 032362 SSRAM[13555] = 36'o255000000000; // 032363 SSRAM[13556] = 36'o200540032351; // 032364 SSRAM[13557] = 36'o200600041020; // 032365 SSRAM[13558] = 36'o430540000014; // 032366 SSRAM[13559] = 36'o603540740000; // 032367 SSRAM[13560] = 36'o036540041470; // 032370 SSRAM[13561] = 36'o255000000000; // 032371 SSRAM[13562] = 36'o200640041473; // 032372 SSRAM[13563] = 36'o120040033157; // 032373 SSRAM[13564] = 36'o255740032375; // 032374 SSRAM[13565] = 36'o114040033161; // 032375 SSRAM[13566] = 36'o264000032377; // 032376 SSRAM[13567] = 36'o000000000000; // 032377 SSRAM[13568] = 36'o400540000000; // 032400 SSRAM[13569] = 36'o312040041127; // 032401 SSRAM[13570] = 36'o254000032406; // 032402 SSRAM[13571] = 36'o201540000001; // 032403 SSRAM[13572] = 36'o316100041127; // 032404 SSRAM[13573] = 36'o254000032411; // 032405 SSRAM[13574] = 36'o200613000001; // 032406 SSRAM[13575] = 36'o200553041432; // 032407 SSRAM[13576] = 36'o036600041441; // 032410 SSRAM[13577] = 36'o255000000000; // 032411 SSRAM[13578] = 36'o200540032377; // 032412 SSRAM[13579] = 36'o200600041020; // 032413 SSRAM[13580] = 36'o430540000014; // 032414 SSRAM[13581] = 36'o603540740000; // 032415 SSRAM[13582] = 36'o036540041474; // 032416 SSRAM[13583] = 36'o255000000000; // 032417 SSRAM[13584] = 36'o200640041477; // 032420 SSRAM[13585] = 36'o120040033163; // 032421 SSRAM[13586] = 36'o255740032423; // 032422 SSRAM[13587] = 36'o114040033165; // 032423 SSRAM[13588] = 36'o264000032425; // 032424 SSRAM[13589] = 36'o000000000000; // 032425 SSRAM[13590] = 36'o400540000000; // 032426 SSRAM[13591] = 36'o312040041127; // 032427 SSRAM[13592] = 36'o254000032434; // 032430 SSRAM[13593] = 36'o201540000001; // 032431 SSRAM[13594] = 36'o316100041127; // 032432 SSRAM[13595] = 36'o254000032437; // 032433 SSRAM[13596] = 36'o200613000001; // 032434 SSRAM[13597] = 36'o200553041432; // 032435 SSRAM[13598] = 36'o036600041441; // 032436 SSRAM[13599] = 36'o255000000000; // 032437 SSRAM[13600] = 36'o200540032425; // 032440 SSRAM[13601] = 36'o200600041020; // 032441 SSRAM[13602] = 36'o430540000014; // 032442 SSRAM[13603] = 36'o603540740000; // 032443 SSRAM[13604] = 36'o036540041500; // 032444 SSRAM[13605] = 36'o255000000000; // 032445 SSRAM[13606] = 36'o200640041503; // 032446 SSRAM[13607] = 36'o120040033167; // 032447 SSRAM[13608] = 36'o255740032451; // 032450 SSRAM[13609] = 36'o114040033171; // 032451 SSRAM[13610] = 36'o264000032453; // 032452 SSRAM[13611] = 36'o000000000000; // 032453 SSRAM[13612] = 36'o400540000000; // 032454 SSRAM[13613] = 36'o312040041166; // 032455 SSRAM[13614] = 36'o254000032462; // 032456 SSRAM[13615] = 36'o201540000001; // 032457 SSRAM[13616] = 36'o316100041166; // 032460 SSRAM[13617] = 36'o254000032465; // 032461 SSRAM[13618] = 36'o200613000001; // 032462 SSRAM[13619] = 36'o200553041341; // 032463 SSRAM[13620] = 36'o036600041511; // 032464 SSRAM[13621] = 36'o255000000000; // 032465 SSRAM[13622] = 36'o200540032453; // 032466 SSRAM[13623] = 36'o200600041020; // 032467 SSRAM[13624] = 36'o430540000014; // 032470 SSRAM[13625] = 36'o603540740000; // 032471 SSRAM[13626] = 36'o036540041524; // 032472 SSRAM[13627] = 36'o255000000000; // 032473 SSRAM[13628] = 36'o200640041527; // 032474 SSRAM[13629] = 36'o120040033173; // 032475 SSRAM[13630] = 36'o255740032477; // 032476 SSRAM[13631] = 36'o114040033175; // 032477 SSRAM[13632] = 36'o264000032501; // 032500 SSRAM[13633] = 36'o000000000000; // 032501 SSRAM[13634] = 36'o400540000000; // 032502 SSRAM[13635] = 36'o312040041166; // 032503 SSRAM[13636] = 36'o254000032510; // 032504 SSRAM[13637] = 36'o201540000001; // 032505 SSRAM[13638] = 36'o316100041166; // 032506 SSRAM[13639] = 36'o254000032513; // 032507 SSRAM[13640] = 36'o200613000001; // 032510 SSRAM[13641] = 36'o200553041341; // 032511 SSRAM[13642] = 36'o036600041511; // 032512 SSRAM[13643] = 36'o255000000000; // 032513 SSRAM[13644] = 36'o200540032501; // 032514 SSRAM[13645] = 36'o200600041020; // 032515 SSRAM[13646] = 36'o430540000014; // 032516 SSRAM[13647] = 36'o603540740000; // 032517 SSRAM[13648] = 36'o036540041530; // 032520 SSRAM[13649] = 36'o255000000000; // 032521 SSRAM[13650] = 36'o200640041533; // 032522 SSRAM[13651] = 36'o120040033177; // 032523 SSRAM[13652] = 36'o255740032525; // 032524 SSRAM[13653] = 36'o114040033201; // 032525 SSRAM[13654] = 36'o264000032527; // 032526 SSRAM[13655] = 36'o000000000000; // 032527 SSRAM[13656] = 36'o400540000000; // 032530 SSRAM[13657] = 36'o312040041166; // 032531 SSRAM[13658] = 36'o254000032536; // 032532 SSRAM[13659] = 36'o201540000001; // 032533 SSRAM[13660] = 36'o316100041166; // 032534 SSRAM[13661] = 36'o254000032541; // 032535 SSRAM[13662] = 36'o200613000001; // 032536 SSRAM[13663] = 36'o200553041341; // 032537 SSRAM[13664] = 36'o036600041511; // 032540 SSRAM[13665] = 36'o255000000000; // 032541 SSRAM[13666] = 36'o200540032527; // 032542 SSRAM[13667] = 36'o200600041020; // 032543 SSRAM[13668] = 36'o430540000014; // 032544 SSRAM[13669] = 36'o603540740000; // 032545 SSRAM[13670] = 36'o036540041534; // 032546 SSRAM[13671] = 36'o255000000000; // 032547 SSRAM[13672] = 36'o200640041537; // 032550 SSRAM[13673] = 36'o120040033203; // 032551 SSRAM[13674] = 36'o255740032553; // 032552 SSRAM[13675] = 36'o114040033205; // 032553 SSRAM[13676] = 36'o264000032555; // 032554 SSRAM[13677] = 36'o000000000000; // 032555 SSRAM[13678] = 36'o400540000000; // 032556 SSRAM[13679] = 36'o312040041166; // 032557 SSRAM[13680] = 36'o254000032564; // 032560 SSRAM[13681] = 36'o201540000001; // 032561 SSRAM[13682] = 36'o316100041166; // 032562 SSRAM[13683] = 36'o254000032567; // 032563 SSRAM[13684] = 36'o200613000001; // 032564 SSRAM[13685] = 36'o200553041341; // 032565 SSRAM[13686] = 36'o036600041511; // 032566 SSRAM[13687] = 36'o255000000000; // 032567 SSRAM[13688] = 36'o200540032555; // 032570 SSRAM[13689] = 36'o200600041020; // 032571 SSRAM[13690] = 36'o430540000014; // 032572 SSRAM[13691] = 36'o603540740000; // 032573 SSRAM[13692] = 36'o036540041540; // 032574 SSRAM[13693] = 36'o255000000000; // 032575 SSRAM[13694] = 36'o200640041543; // 032576 SSRAM[13695] = 36'o120040033207; // 032577 SSRAM[13696] = 36'o255740032601; // 032600 SSRAM[13697] = 36'o114040033211; // 032601 SSRAM[13698] = 36'o264000032603; // 032602 SSRAM[13699] = 36'o000000000000; // 032603 SSRAM[13700] = 36'o400540000000; // 032604 SSRAM[13701] = 36'o312040041166; // 032605 SSRAM[13702] = 36'o254000032612; // 032606 SSRAM[13703] = 36'o201540000001; // 032607 SSRAM[13704] = 36'o316100041166; // 032610 SSRAM[13705] = 36'o254000032615; // 032611 SSRAM[13706] = 36'o200613000001; // 032612 SSRAM[13707] = 36'o200553041341; // 032613 SSRAM[13708] = 36'o036600041511; // 032614 SSRAM[13709] = 36'o255000000000; // 032615 SSRAM[13710] = 36'o200540032603; // 032616 SSRAM[13711] = 36'o200600041020; // 032617 SSRAM[13712] = 36'o430540000014; // 032620 SSRAM[13713] = 36'o603540740000; // 032621 SSRAM[13714] = 36'o036540041544; // 032622 SSRAM[13715] = 36'o255000000000; // 032623 SSRAM[13716] = 36'o200640041547; // 032624 SSRAM[13717] = 36'o120040033213; // 032625 SSRAM[13718] = 36'o255740032627; // 032626 SSRAM[13719] = 36'o114040033215; // 032627 SSRAM[13720] = 36'o264000032631; // 032630 SSRAM[13721] = 36'o000000000000; // 032631 SSRAM[13722] = 36'o400540000000; // 032632 SSRAM[13723] = 36'o312040041166; // 032633 SSRAM[13724] = 36'o254000032640; // 032634 SSRAM[13725] = 36'o201540000001; // 032635 SSRAM[13726] = 36'o316100041166; // 032636 SSRAM[13727] = 36'o254000032643; // 032637 SSRAM[13728] = 36'o200613000001; // 032640 SSRAM[13729] = 36'o200553041341; // 032641 SSRAM[13730] = 36'o036600041511; // 032642 SSRAM[13731] = 36'o255000000000; // 032643 SSRAM[13732] = 36'o200540032631; // 032644 SSRAM[13733] = 36'o200600041020; // 032645 SSRAM[13734] = 36'o430540000014; // 032646 SSRAM[13735] = 36'o603540740000; // 032647 SSRAM[13736] = 36'o036540041550; // 032650 SSRAM[13737] = 36'o255000000000; // 032651 SSRAM[13738] = 36'o200640041553; // 032652 SSRAM[13739] = 36'o120040033217; // 032653 SSRAM[13740] = 36'o255740032655; // 032654 SSRAM[13741] = 36'o114040033221; // 032655 SSRAM[13742] = 36'o264000032657; // 032656 SSRAM[13743] = 36'o000000000000; // 032657 SSRAM[13744] = 36'o400540000000; // 032660 SSRAM[13745] = 36'o312040041020; // 032661 SSRAM[13746] = 36'o254000032666; // 032662 SSRAM[13747] = 36'o201540000001; // 032663 SSRAM[13748] = 36'o316100041127; // 032664 SSRAM[13749] = 36'o254000032671; // 032665 SSRAM[13750] = 36'o200613000001; // 032666 SSRAM[13751] = 36'o200553041126; // 032667 SSRAM[13752] = 36'o036600041561; // 032670 SSRAM[13753] = 36'o255000000000; // 032671 SSRAM[13754] = 36'o200540032657; // 032672 SSRAM[13755] = 36'o200600041371; // 032673 SSRAM[13756] = 36'o430540000014; // 032674 SSRAM[13757] = 36'o603540740000; // 032675 SSRAM[13758] = 36'o036540041574; // 032676 SSRAM[13759] = 36'o255000000000; // 032677 SSRAM[13760] = 36'o200640041577; // 032700 SSRAM[13761] = 36'o120040033223; // 032701 SSRAM[13762] = 36'o255740032703; // 032702 SSRAM[13763] = 36'o114040033225; // 032703 SSRAM[13764] = 36'o264000032705; // 032704 SSRAM[13765] = 36'o000000000000; // 032705 SSRAM[13766] = 36'o400540000000; // 032706 SSRAM[13767] = 36'o312040041020; // 032707 SSRAM[13768] = 36'o254000032714; // 032710 SSRAM[13769] = 36'o201540000001; // 032711 SSRAM[13770] = 36'o316100041127; // 032712 SSRAM[13771] = 36'o254000032717; // 032713 SSRAM[13772] = 36'o200613000001; // 032714 SSRAM[13773] = 36'o200553041126; // 032715 SSRAM[13774] = 36'o036600041561; // 032716 SSRAM[13775] = 36'o255000000000; // 032717 SSRAM[13776] = 36'o200540032705; // 032720 SSRAM[13777] = 36'o200600041371; // 032721 SSRAM[13778] = 36'o430540000014; // 032722 SSRAM[13779] = 36'o603540740000; // 032723 SSRAM[13780] = 36'o036540041600; // 032724 SSRAM[13781] = 36'o255000000000; // 032725 SSRAM[13782] = 36'o200640041603; // 032726 SSRAM[13783] = 36'o120040033227; // 032727 SSRAM[13784] = 36'o255740032731; // 032730 SSRAM[13785] = 36'o114040033231; // 032731 SSRAM[13786] = 36'o264000032733; // 032732 SSRAM[13787] = 36'o000000000000; // 032733 SSRAM[13788] = 36'o400540000000; // 032734 SSRAM[13789] = 36'o312040041020; // 032735 SSRAM[13790] = 36'o254000032742; // 032736 SSRAM[13791] = 36'o201540000001; // 032737 SSRAM[13792] = 36'o316100041127; // 032740 SSRAM[13793] = 36'o254000032745; // 032741 SSRAM[13794] = 36'o200613000001; // 032742 SSRAM[13795] = 36'o200553041126; // 032743 SSRAM[13796] = 36'o036600041561; // 032744 SSRAM[13797] = 36'o255000000000; // 032745 SSRAM[13798] = 36'o200540032733; // 032746 SSRAM[13799] = 36'o200600041371; // 032747 SSRAM[13800] = 36'o430540000014; // 032750 SSRAM[13801] = 36'o603540740000; // 032751 SSRAM[13802] = 36'o036540041604; // 032752 SSRAM[13803] = 36'o255000000000; // 032753 SSRAM[13804] = 36'o200640041607; // 032754 SSRAM[13805] = 36'o120040033233; // 032755 SSRAM[13806] = 36'o255740032757; // 032756 SSRAM[13807] = 36'o114040033235; // 032757 SSRAM[13808] = 36'o264000032761; // 032760 SSRAM[13809] = 36'o000000000000; // 032761 SSRAM[13810] = 36'o400540000000; // 032762 SSRAM[13811] = 36'o312040041020; // 032763 SSRAM[13812] = 36'o254000032770; // 032764 SSRAM[13813] = 36'o201540000001; // 032765 SSRAM[13814] = 36'o316100041127; // 032766 SSRAM[13815] = 36'o254000032773; // 032767 SSRAM[13816] = 36'o200613000001; // 032770 SSRAM[13817] = 36'o200553041126; // 032771 SSRAM[13818] = 36'o036600041561; // 032772 SSRAM[13819] = 36'o255000000000; // 032773 SSRAM[13820] = 36'o200540032761; // 032774 SSRAM[13821] = 36'o200600041371; // 032775 SSRAM[13822] = 36'o430540000014; // 032776 SSRAM[13823] = 36'o603540740000; // 032777 SSRAM[13824] = 36'o036540041610; // 033000 SSRAM[13825] = 36'o255000000000; // 033001 SSRAM[13826] = 36'o200640041613; // 033002 SSRAM[13827] = 36'o120040033237; // 033003 SSRAM[13828] = 36'o255740033005; // 033004 SSRAM[13829] = 36'o114040033241; // 033005 SSRAM[13830] = 36'o264000033007; // 033006 SSRAM[13831] = 36'o000000000000; // 033007 SSRAM[13832] = 36'o400540000000; // 033010 SSRAM[13833] = 36'o312040041020; // 033011 SSRAM[13834] = 36'o254000033016; // 033012 SSRAM[13835] = 36'o201540000001; // 033013 SSRAM[13836] = 36'o316100041127; // 033014 SSRAM[13837] = 36'o254000033021; // 033015 SSRAM[13838] = 36'o200613000001; // 033016 SSRAM[13839] = 36'o200553041126; // 033017 SSRAM[13840] = 36'o036600041561; // 033020 SSRAM[13841] = 36'o255000000000; // 033021 SSRAM[13842] = 36'o200540033007; // 033022 SSRAM[13843] = 36'o200600041371; // 033023 SSRAM[13844] = 36'o430540000014; // 033024 SSRAM[13845] = 36'o603540740000; // 033025 SSRAM[13846] = 36'o036540041614; // 033026 SSRAM[13847] = 36'o255000000000; // 033027 SSRAM[13848] = 36'o200640041617; // 033030 SSRAM[13849] = 36'o120040033243; // 033031 SSRAM[13850] = 36'o255740033033; // 033032 SSRAM[13851] = 36'o114040033245; // 033033 SSRAM[13852] = 36'o264000033035; // 033034 SSRAM[13853] = 36'o000000000000; // 033035 SSRAM[13854] = 36'o400540000000; // 033036 SSRAM[13855] = 36'o312040041020; // 033037 SSRAM[13856] = 36'o254000033044; // 033040 SSRAM[13857] = 36'o201540000001; // 033041 SSRAM[13858] = 36'o316100041127; // 033042 SSRAM[13859] = 36'o254000033047; // 033043 SSRAM[13860] = 36'o200613000001; // 033044 SSRAM[13861] = 36'o200553041126; // 033045 SSRAM[13862] = 36'o036600041561; // 033046 SSRAM[13863] = 36'o255000000000; // 033047 SSRAM[13864] = 36'o200540033035; // 033050 SSRAM[13865] = 36'o200600041371; // 033051 SSRAM[13866] = 36'o430540000014; // 033052 SSRAM[13867] = 36'o603540740000; // 033053 SSRAM[13868] = 36'o036540041620; // 033054 SSRAM[13869] = 36'o255000000000; // 033055 SSRAM[13870] = 36'o254000033247; // 033056 SSRAM[13871] = 36'o000000000000; // 033057 SSRAM[13872] = 36'o000000000000; // 033060 SSRAM[13873] = 36'o000000000000; // 033061 SSRAM[13874] = 36'o400000000001; // 033062 SSRAM[13875] = 36'o000000000000; // 033063 SSRAM[13876] = 36'o400000000000; // 033064 SSRAM[13877] = 36'o000000000000; // 033065 SSRAM[13878] = 36'o000000000001; // 033066 SSRAM[13879] = 36'o000000000000; // 033067 SSRAM[13880] = 36'o400000000000; // 033070 SSRAM[13881] = 36'o000000000000; // 033071 SSRAM[13882] = 36'o400000000001; // 033072 SSRAM[13883] = 36'o000000000000; // 033073 SSRAM[13884] = 36'o000000000000; // 033074 SSRAM[13885] = 36'o777777777777; // 033075 SSRAM[13886] = 36'o377777777777; // 033076 SSRAM[13887] = 36'o000000000000; // 033077 SSRAM[13888] = 36'o400000000000; // 033100 SSRAM[13889] = 36'o777777777777; // 033101 SSRAM[13890] = 36'o377777777777; // 033102 SSRAM[13891] = 36'o000000000000; // 033103 SSRAM[13892] = 36'o400000000000; // 033104 SSRAM[13893] = 36'o777777777777; // 033105 SSRAM[13894] = 36'o777777777777; // 033106 SSRAM[13895] = 36'o777777777777; // 033107 SSRAM[13896] = 36'o377777777777; // 033110 SSRAM[13897] = 36'o777777777776; // 033111 SSRAM[13898] = 36'o777777777777; // 033112 SSRAM[13899] = 36'o777777777777; // 033113 SSRAM[13900] = 36'o377777777777; // 033114 SSRAM[13901] = 36'o777777777776; // 033115 SSRAM[13902] = 36'o377777777777; // 033116 SSRAM[13903] = 36'o777777777777; // 033117 SSRAM[13904] = 36'o777777777777; // 033120 SSRAM[13905] = 36'o777777777776; // 033121 SSRAM[13906] = 36'o377777777777; // 033122 SSRAM[13907] = 36'o777777777776; // 033123 SSRAM[13908] = 36'o777777777777; // 033124 SSRAM[13909] = 36'o777777777777; // 033125 SSRAM[13910] = 36'o377777777777; // 033126 SSRAM[13911] = 36'o777777777776; // 033127 SSRAM[13912] = 36'o377777777777; // 033130 SSRAM[13913] = 36'o777777777777; // 033131 SSRAM[13914] = 36'o377777777777; // 033132 SSRAM[13915] = 36'o777777777776; // 033133 SSRAM[13916] = 36'o377777777777; // 033134 SSRAM[13917] = 36'o777777777777; // 033135 SSRAM[13918] = 36'o777777777777; // 033136 SSRAM[13919] = 36'o000000000000; // 033137 SSRAM[13920] = 36'o400000000001; // 033140 SSRAM[13921] = 36'o000000000001; // 033141 SSRAM[13922] = 36'o000000000000; // 033142 SSRAM[13923] = 36'o000000000000; // 033143 SSRAM[13924] = 36'o400000000001; // 033144 SSRAM[13925] = 36'o000000000001; // 033145 SSRAM[13926] = 36'o400000000000; // 033146 SSRAM[13927] = 36'o000000000000; // 033147 SSRAM[13928] = 36'o000000000001; // 033150 SSRAM[13929] = 36'o000000000001; // 033151 SSRAM[13930] = 36'o400000000000; // 033152 SSRAM[13931] = 36'o000000000001; // 033153 SSRAM[13932] = 36'o000000000000; // 033154 SSRAM[13933] = 36'o000000000000; // 033155 SSRAM[13934] = 36'o400000000001; // 033156 SSRAM[13935] = 36'o000000000001; // 033157 SSRAM[13936] = 36'o400000000000; // 033160 SSRAM[13937] = 36'o000000000000; // 033161 SSRAM[13938] = 36'o400000000001; // 033162 SSRAM[13939] = 36'o000000000001; // 033163 SSRAM[13940] = 36'o400000000000; // 033164 SSRAM[13941] = 36'o000000000000; // 033165 SSRAM[13942] = 36'o000000000001; // 033166 SSRAM[13943] = 36'o777777777777; // 033167 SSRAM[13944] = 36'o377777777776; // 033170 SSRAM[13945] = 36'o000000000000; // 033171 SSRAM[13946] = 36'o000000000001; // 033172 SSRAM[13947] = 36'o777777777777; // 033173 SSRAM[13948] = 36'o377777777776; // 033174 SSRAM[13949] = 36'o000000000000; // 033175 SSRAM[13950] = 36'o400000000001; // 033176 SSRAM[13951] = 36'o777777777777; // 033177 SSRAM[13952] = 36'o777777777776; // 033200 SSRAM[13953] = 36'o000000000000; // 033201 SSRAM[13954] = 36'o400000000001; // 033202 SSRAM[13955] = 36'o000000000000; // 033203 SSRAM[13956] = 36'o000000000001; // 033204 SSRAM[13957] = 36'o777777777777; // 033205 SSRAM[13958] = 36'o377777777776; // 033206 SSRAM[13959] = 36'o000000000000; // 033207 SSRAM[13960] = 36'o400000000001; // 033210 SSRAM[13961] = 36'o777777777777; // 033211 SSRAM[13962] = 36'o377777777776; // 033212 SSRAM[13963] = 36'o000000000000; // 033213 SSRAM[13964] = 36'o400000000001; // 033214 SSRAM[13965] = 36'o777777777777; // 033215 SSRAM[13966] = 36'o777777777776; // 033216 SSRAM[13967] = 36'o777777777777; // 033217 SSRAM[13968] = 36'o377777777777; // 033220 SSRAM[13969] = 36'o000000000000; // 033221 SSRAM[13970] = 36'o000000000002; // 033222 SSRAM[13971] = 36'o777777777777; // 033223 SSRAM[13972] = 36'o377777777777; // 033224 SSRAM[13973] = 36'o000000000000; // 033225 SSRAM[13974] = 36'o400000000002; // 033226 SSRAM[13975] = 36'o777777777777; // 033227 SSRAM[13976] = 36'o777777777777; // 033230 SSRAM[13977] = 36'o000000000000; // 033231 SSRAM[13978] = 36'o400000000002; // 033232 SSRAM[13979] = 36'o000000000000; // 033233 SSRAM[13980] = 36'o000000000002; // 033234 SSRAM[13981] = 36'o777777777777; // 033235 SSRAM[13982] = 36'o377777777777; // 033236 SSRAM[13983] = 36'o000000000000; // 033237 SSRAM[13984] = 36'o400000000002; // 033240 SSRAM[13985] = 36'o777777777777; // 033241 SSRAM[13986] = 36'o377777777777; // 033242 SSRAM[13987] = 36'o000000000000; // 033243 SSRAM[13988] = 36'o400000000002; // 033244 SSRAM[13989] = 36'o777777777777; // 033245 SSRAM[13990] = 36'o777777777777; // 033246 SSRAM[13991] = 36'o200640041623; // 033247 SSRAM[13992] = 36'o120040033530; // 033250 SSRAM[13993] = 36'o255740033252; // 033251 SSRAM[13994] = 36'o114040033532; // 033252 SSRAM[13995] = 36'o264000033254; // 033253 SSRAM[13996] = 36'o000000000000; // 033254 SSRAM[13997] = 36'o400540000000; // 033255 SSRAM[13998] = 36'o312040033534; // 033256 SSRAM[13999] = 36'o254000033263; // 033257 SSRAM[14000] = 36'o201540000001; // 033260 SSRAM[14001] = 36'o316100033535; // 033261 SSRAM[14002] = 36'o254000033266; // 033262 SSRAM[14003] = 36'o200613000001; // 033263 SSRAM[14004] = 36'o200553033534; // 033264 SSRAM[14005] = 36'o036600041631; // 033265 SSRAM[14006] = 36'o255000000000; // 033266 SSRAM[14007] = 36'o200540033254; // 033267 SSRAM[14008] = 36'o200600041634; // 033270 SSRAM[14009] = 36'o430540000014; // 033271 SSRAM[14010] = 36'o603540740000; // 033272 SSRAM[14011] = 36'o036540041644; // 033273 SSRAM[14012] = 36'o255000000000; // 033274 SSRAM[14013] = 36'o200640041647; // 033275 SSRAM[14014] = 36'o120040033536; // 033276 SSRAM[14015] = 36'o255740033300; // 033277 SSRAM[14016] = 36'o114040033540; // 033300 SSRAM[14017] = 36'o264000033302; // 033301 SSRAM[14018] = 36'o000000000000; // 033302 SSRAM[14019] = 36'o400540000000; // 033303 SSRAM[14020] = 36'o312040033542; // 033304 SSRAM[14021] = 36'o254000033311; // 033305 SSRAM[14022] = 36'o201540000001; // 033306 SSRAM[14023] = 36'o316100033543; // 033307 SSRAM[14024] = 36'o254000033314; // 033310 SSRAM[14025] = 36'o200613000001; // 033311 SSRAM[14026] = 36'o200553033542; // 033312 SSRAM[14027] = 36'o036600041631; // 033313 SSRAM[14028] = 36'o255000000000; // 033314 SSRAM[14029] = 36'o200540033302; // 033315 SSRAM[14030] = 36'o200600041634; // 033316 SSRAM[14031] = 36'o430540000014; // 033317 SSRAM[14032] = 36'o603540740000; // 033320 SSRAM[14033] = 36'o036540041650; // 033321 SSRAM[14034] = 36'o255000000000; // 033322 SSRAM[14035] = 36'o200640041653; // 033323 SSRAM[14036] = 36'o120040033544; // 033324 SSRAM[14037] = 36'o255740033326; // 033325 SSRAM[14038] = 36'o114040033546; // 033326 SSRAM[14039] = 36'o264000033330; // 033327 SSRAM[14040] = 36'o000000000000; // 033330 SSRAM[14041] = 36'o400540000000; // 033331 SSRAM[14042] = 36'o312040033550; // 033332 SSRAM[14043] = 36'o254000033337; // 033333 SSRAM[14044] = 36'o201540000001; // 033334 SSRAM[14045] = 36'o316100033551; // 033335 SSRAM[14046] = 36'o254000033342; // 033336 SSRAM[14047] = 36'o200613000001; // 033337 SSRAM[14048] = 36'o200553033550; // 033340 SSRAM[14049] = 36'o036600041631; // 033341 SSRAM[14050] = 36'o255000000000; // 033342 SSRAM[14051] = 36'o200540033330; // 033343 SSRAM[14052] = 36'o200600041634; // 033344 SSRAM[14053] = 36'o430540000014; // 033345 SSRAM[14054] = 36'o603540740000; // 033346 SSRAM[14055] = 36'o036540041654; // 033347 SSRAM[14056] = 36'o255000000000; // 033350 SSRAM[14057] = 36'o200640041657; // 033351 SSRAM[14058] = 36'o120040033552; // 033352 SSRAM[14059] = 36'o255740033354; // 033353 SSRAM[14060] = 36'o114040033554; // 033354 SSRAM[14061] = 36'o264000033356; // 033355 SSRAM[14062] = 36'o000000000000; // 033356 SSRAM[14063] = 36'o400540000000; // 033357 SSRAM[14064] = 36'o312040033556; // 033360 SSRAM[14065] = 36'o254000033365; // 033361 SSRAM[14066] = 36'o201540000001; // 033362 SSRAM[14067] = 36'o316100033557; // 033363 SSRAM[14068] = 36'o254000033370; // 033364 SSRAM[14069] = 36'o200613000001; // 033365 SSRAM[14070] = 36'o200553033556; // 033366 SSRAM[14071] = 36'o036600041631; // 033367 SSRAM[14072] = 36'o255000000000; // 033370 SSRAM[14073] = 36'o200540033356; // 033371 SSRAM[14074] = 36'o200600041634; // 033372 SSRAM[14075] = 36'o430540000014; // 033373 SSRAM[14076] = 36'o603540740000; // 033374 SSRAM[14077] = 36'o036540041660; // 033375 SSRAM[14078] = 36'o255000000000; // 033376 SSRAM[14079] = 36'o200640041663; // 033377 SSRAM[14080] = 36'o120040033560; // 033400 SSRAM[14081] = 36'o255740033402; // 033401 SSRAM[14082] = 36'o114040033562; // 033402 SSRAM[14083] = 36'o264000033404; // 033403 SSRAM[14084] = 36'o000000000000; // 033404 SSRAM[14085] = 36'o400540000000; // 033405 SSRAM[14086] = 36'o312040033564; // 033406 SSRAM[14087] = 36'o254000033413; // 033407 SSRAM[14088] = 36'o201540000001; // 033410 SSRAM[14089] = 36'o316100033565; // 033411 SSRAM[14090] = 36'o254000033416; // 033412 SSRAM[14091] = 36'o200613000001; // 033413 SSRAM[14092] = 36'o200553033564; // 033414 SSRAM[14093] = 36'o036600041631; // 033415 SSRAM[14094] = 36'o255000000000; // 033416 SSRAM[14095] = 36'o200540033404; // 033417 SSRAM[14096] = 36'o200600041664; // 033420 SSRAM[14097] = 36'o430540000014; // 033421 SSRAM[14098] = 36'o603540740000; // 033422 SSRAM[14099] = 36'o036540041665; // 033423 SSRAM[14100] = 36'o255000000000; // 033424 SSRAM[14101] = 36'o200640041670; // 033425 SSRAM[14102] = 36'o120040033566; // 033426 SSRAM[14103] = 36'o255740033430; // 033427 SSRAM[14104] = 36'o114040033570; // 033430 SSRAM[14105] = 36'o264000033432; // 033431 SSRAM[14106] = 36'o000000000000; // 033432 SSRAM[14107] = 36'o400540000000; // 033433 SSRAM[14108] = 36'o312040033572; // 033434 SSRAM[14109] = 36'o254000033441; // 033435 SSRAM[14110] = 36'o201540000001; // 033436 SSRAM[14111] = 36'o316100033573; // 033437 SSRAM[14112] = 36'o254000033444; // 033440 SSRAM[14113] = 36'o200613000001; // 033441 SSRAM[14114] = 36'o200553033572; // 033442 SSRAM[14115] = 36'o036600041631; // 033443 SSRAM[14116] = 36'o255000000000; // 033444 SSRAM[14117] = 36'o200540033432; // 033445 SSRAM[14118] = 36'o200600041664; // 033446 SSRAM[14119] = 36'o430540000014; // 033447 SSRAM[14120] = 36'o603540740000; // 033450 SSRAM[14121] = 36'o036540041671; // 033451 SSRAM[14122] = 36'o255000000000; // 033452 SSRAM[14123] = 36'o200640041674; // 033453 SSRAM[14124] = 36'o120040033574; // 033454 SSRAM[14125] = 36'o255740033456; // 033455 SSRAM[14126] = 36'o114040033576; // 033456 SSRAM[14127] = 36'o264000033460; // 033457 SSRAM[14128] = 36'o000000000000; // 033460 SSRAM[14129] = 36'o400540000000; // 033461 SSRAM[14130] = 36'o312040033600; // 033462 SSRAM[14131] = 36'o254000033467; // 033463 SSRAM[14132] = 36'o201540000001; // 033464 SSRAM[14133] = 36'o316100033601; // 033465 SSRAM[14134] = 36'o254000033472; // 033466 SSRAM[14135] = 36'o200613000001; // 033467 SSRAM[14136] = 36'o200553033600; // 033470 SSRAM[14137] = 36'o036600041631; // 033471 SSRAM[14138] = 36'o255000000000; // 033472 SSRAM[14139] = 36'o200540033460; // 033473 SSRAM[14140] = 36'o200600041664; // 033474 SSRAM[14141] = 36'o430540000014; // 033475 SSRAM[14142] = 36'o603540740000; // 033476 SSRAM[14143] = 36'o036540041675; // 033477 SSRAM[14144] = 36'o255000000000; // 033500 SSRAM[14145] = 36'o200640041700; // 033501 SSRAM[14146] = 36'o120040033602; // 033502 SSRAM[14147] = 36'o255740033504; // 033503 SSRAM[14148] = 36'o114040033604; // 033504 SSRAM[14149] = 36'o264000033506; // 033505 SSRAM[14150] = 36'o000000000000; // 033506 SSRAM[14151] = 36'o400540000000; // 033507 SSRAM[14152] = 36'o312040033606; // 033510 SSRAM[14153] = 36'o254000033515; // 033511 SSRAM[14154] = 36'o201540000001; // 033512 SSRAM[14155] = 36'o316100033607; // 033513 SSRAM[14156] = 36'o254000033520; // 033514 SSRAM[14157] = 36'o200613000001; // 033515 SSRAM[14158] = 36'o200553033606; // 033516 SSRAM[14159] = 36'o036600041631; // 033517 SSRAM[14160] = 36'o255000000000; // 033520 SSRAM[14161] = 36'o200540033506; // 033521 SSRAM[14162] = 36'o200600041664; // 033522 SSRAM[14163] = 36'o430540000014; // 033523 SSRAM[14164] = 36'o603540740000; // 033524 SSRAM[14165] = 36'o036540041701; // 033525 SSRAM[14166] = 36'o255000000000; // 033526 SSRAM[14167] = 36'o254000033610; // 033527 SSRAM[14168] = 36'o200000000000; // 033530 SSRAM[14169] = 36'o000000000000; // 033531 SSRAM[14170] = 36'o200000000000; // 033532 SSRAM[14171] = 36'o000000000000; // 033533 SSRAM[14172] = 36'o400000000000; // 033534 SSRAM[14173] = 36'o400000000000; // 033535 SSRAM[14174] = 36'o000000000001; // 033536 SSRAM[14175] = 36'o000000000000; // 033537 SSRAM[14176] = 36'o377777777777; // 033540 SSRAM[14177] = 36'o000000000000; // 033541 SSRAM[14178] = 36'o400000000000; // 033542 SSRAM[14179] = 36'o400000000000; // 033543 SSRAM[14180] = 36'o000000000000; // 033544 SSRAM[14181] = 36'o200000000000; // 033545 SSRAM[14182] = 36'o377777777777; // 033546 SSRAM[14183] = 36'o200000000000; // 033547 SSRAM[14184] = 36'o400000000000; // 033550 SSRAM[14185] = 36'o400000000000; // 033551 SSRAM[14186] = 36'o000000000000; // 033552 SSRAM[14187] = 36'o000000000001; // 033553 SSRAM[14188] = 36'o377777777777; // 033554 SSRAM[14189] = 36'o377777777777; // 033555 SSRAM[14190] = 36'o400000000000; // 033556 SSRAM[14191] = 36'o400000000000; // 033557 SSRAM[14192] = 36'o400000000000; // 033560 SSRAM[14193] = 36'o400000000000; // 033561 SSRAM[14194] = 36'o777777777777; // 033562 SSRAM[14195] = 36'o777777777777; // 033563 SSRAM[14196] = 36'o377777777777; // 033564 SSRAM[14197] = 36'o377777777777; // 033565 SSRAM[14198] = 36'o400000000000; // 033566 SSRAM[14199] = 36'o777777777777; // 033567 SSRAM[14200] = 36'o777777777777; // 033570 SSRAM[14201] = 36'o400000000000; // 033571 SSRAM[14202] = 36'o377777777777; // 033572 SSRAM[14203] = 36'o377777777777; // 033573 SSRAM[14204] = 36'o400000000001; // 033574 SSRAM[14205] = 36'o400000000000; // 033575 SSRAM[14206] = 36'o777777777776; // 033576 SSRAM[14207] = 36'o400000000000; // 033577 SSRAM[14208] = 36'o377777777777; // 033600 SSRAM[14209] = 36'o000000000000; // 033601 SSRAM[14210] = 36'o777777777777; // 033602 SSRAM[14211] = 36'o777777777777; // 033603 SSRAM[14212] = 36'o400000000000; // 033604 SSRAM[14213] = 36'o400000000000; // 033605 SSRAM[14214] = 36'o377777777777; // 033606 SSRAM[14215] = 36'o377777777777; // 033607 SSRAM[14216] = 36'o200640041024; // 033610 SSRAM[14217] = 36'o120040041020; // 033611 SSRAM[14218] = 36'o115040041022; // 033612 SSRAM[14219] = 36'o400540000000; // 033613 SSRAM[14220] = 36'o312040041020; // 033614 SSRAM[14221] = 36'o254000033621; // 033615 SSRAM[14222] = 36'o201540000001; // 033616 SSRAM[14223] = 36'o316100041021; // 033617 SSRAM[14224] = 36'o254000033624; // 033620 SSRAM[14225] = 36'o200613000001; // 033621 SSRAM[14226] = 36'o200553041020; // 033622 SSRAM[14227] = 36'o036600041706; // 033623 SSRAM[14228] = 36'o255000000000; // 033624 SSRAM[14229] = 36'o200640041036; // 033625 SSRAM[14230] = 36'o120040041021; // 033626 SSRAM[14231] = 36'o115040041022; // 033627 SSRAM[14232] = 36'o400540000000; // 033630 SSRAM[14233] = 36'o312040041021; // 033631 SSRAM[14234] = 36'o254000033636; // 033632 SSRAM[14235] = 36'o201540000001; // 033633 SSRAM[14236] = 36'o316100041020; // 033634 SSRAM[14237] = 36'o254000033641; // 033635 SSRAM[14238] = 36'o200613000001; // 033636 SSRAM[14239] = 36'o200553041021; // 033637 SSRAM[14240] = 36'o036600041711; // 033640 SSRAM[14241] = 36'o255000000000; // 033641 SSRAM[14242] = 36'o200640041051; // 033642 SSRAM[14243] = 36'o120040041047; // 033643 SSRAM[14244] = 36'o115040041022; // 033644 SSRAM[14245] = 36'o400540000000; // 033645 SSRAM[14246] = 36'o312040041021; // 033646 SSRAM[14247] = 36'o254000033653; // 033647 SSRAM[14248] = 36'o201540000001; // 033650 SSRAM[14249] = 36'o316100041021; // 033651 SSRAM[14250] = 36'o254000033656; // 033652 SSRAM[14251] = 36'o200613000001; // 033653 SSRAM[14252] = 36'o200553041047; // 033654 SSRAM[14253] = 36'o036600041714; // 033655 SSRAM[14254] = 36'o255000000000; // 033656 SSRAM[14255] = 36'o200640041062; // 033657 SSRAM[14256] = 36'o403040000002; // 033660 SSRAM[14257] = 36'o115040041020; // 033661 SSRAM[14258] = 36'o400540000000; // 033662 SSRAM[14259] = 36'o312040041166; // 033663 SSRAM[14260] = 36'o254000033670; // 033664 SSRAM[14261] = 36'o201540000001; // 033665 SSRAM[14262] = 36'o316100041717; // 033666 SSRAM[14263] = 36'o254000033673; // 033667 SSRAM[14264] = 36'o200613000001; // 033670 SSRAM[14265] = 36'o200553041720; // 033671 SSRAM[14266] = 36'o036600041722; // 033672 SSRAM[14267] = 36'o255000000000; // 033673 SSRAM[14268] = 36'o200640041073; // 033674 SSRAM[14269] = 36'o403040000002; // 033675 SSRAM[14270] = 36'o115040041021; // 033676 SSRAM[14271] = 36'o400540000000; // 033677 SSRAM[14272] = 36'o312040041717; // 033700 SSRAM[14273] = 36'o254000033705; // 033701 SSRAM[14274] = 36'o201540000001; // 033702 SSRAM[14275] = 36'o316100041725; // 033703 SSRAM[14276] = 36'o254000033710; // 033704 SSRAM[14277] = 36'o200613000001; // 033705 SSRAM[14278] = 36'o200553041726; // 033706 SSRAM[14279] = 36'o036600041730; // 033707 SSRAM[14280] = 36'o255000000000; // 033710 SSRAM[14281] = 36'o200640041104; // 033711 SSRAM[14282] = 36'o403040000002; // 033712 SSRAM[14283] = 36'o115040041047; // 033713 SSRAM[14284] = 36'o400540000000; // 033714 SSRAM[14285] = 36'o312040041733; // 033715 SSRAM[14286] = 36'o254000033722; // 033716 SSRAM[14287] = 36'o201540000001; // 033717 SSRAM[14288] = 36'o316100041717; // 033720 SSRAM[14289] = 36'o254000033725; // 033721 SSRAM[14290] = 36'o200613000001; // 033722 SSRAM[14291] = 36'o200553041733; // 033723 SSRAM[14292] = 36'o036600041735; // 033724 SSRAM[14293] = 36'o255000000000; // 033725 SSRAM[14294] = 36'o200140041740; // 033726 SSRAM[14295] = 36'o350000000003; // 033727 SSRAM[14296] = 36'o252140034040; // 033730 SSRAM[14297] = 36'o552140034036; // 033731 SSRAM[14298] = 36'o200200041740; // 033732 SSRAM[14299] = 36'o350000000004; // 033733 SSRAM[14300] = 36'o252200033727; // 033734 SSRAM[14301] = 36'o552200034037; // 033735 SSRAM[14302] = 36'o514640000003; // 033736 SSRAM[14303] = 36'o540640000004; // 033737 SSRAM[14304] = 36'o120060034036; // 033740 SSRAM[14305] = 36'o120520034037; // 033741 SSRAM[14306] = 36'o450500000000; // 033742 SSRAM[14307] = 36'o450540000000; // 033743 SSRAM[14308] = 36'o114500000001; // 033744 SSRAM[14309] = 36'o114500041126; // 033745 SSRAM[14310] = 36'o255740033747; // 033746 SSRAM[14311] = 36'o400600000000; // 033747 SSRAM[14312] = 36'o115060034037; // 033750 SSRAM[14313] = 36'o264000033752; // 033751 SSRAM[14314] = 36'o000000000000; // 033752 SSRAM[14315] = 36'o312040000012; // 033753 SSRAM[14316] = 36'o254000033760; // 033754 SSRAM[14317] = 36'o201600000001; // 033755 SSRAM[14318] = 36'o316100000013; // 033756 SSRAM[14319] = 36'o254000033764; // 033757 SSRAM[14320] = 36'o200514000012; // 033760 SSRAM[14321] = 36'o200554000001; // 033761 SSRAM[14322] = 36'o036600041746; // 033762 SSRAM[14323] = 36'o255000000000; // 033763 SSRAM[14324] = 36'o550600033752; // 033764 SSRAM[14325] = 36'o120520034037; // 033765 SSRAM[14326] = 36'o444520034036; // 033766 SSRAM[14327] = 36'o603500400000; // 033767 SSRAM[14328] = 36'o254000033775; // 033770 SSRAM[14329] = 36'o331020034036; // 033771 SSRAM[14330] = 36'o254000034005; // 033772 SSRAM[14331] = 36'o505600300000; // 033773 SSRAM[14332] = 36'o254000034005; // 033774 SSRAM[14333] = 36'o120520034036; // 033775 SSRAM[14334] = 36'o315520034037; // 033776 SSRAM[14335] = 36'o254000034005; // 033777 SSRAM[14336] = 36'o312520034037; // 034000 SSRAM[14337] = 36'o254000033773; // 034001 SSRAM[14338] = 36'o350000034037; // 034002 SSRAM[14339] = 36'o311560034037; // 034003 SSRAM[14340] = 36'o254000033773; // 034004 SSRAM[14341] = 36'o200540033752; // 034005 SSRAM[14342] = 36'o200600000014; // 034006 SSRAM[14343] = 36'o430540000014; // 034007 SSRAM[14344] = 36'o603540740000; // 034010 SSRAM[14345] = 36'o036540041760; // 034011 SSRAM[14346] = 36'o255000000000; // 034012 SSRAM[14347] = 36'o254000033733; // 034013 SSRAM[14348] = 36'o000000000000; // 034014 SSRAM[14349] = 36'o000000000000; // 034015 SSRAM[14350] = 36'o000000000000; // 034016 SSRAM[14351] = 36'o000000000001; // 034017 SSRAM[14352] = 36'o000000000000; // 034020 SSRAM[14353] = 36'o377777777777; // 034021 SSRAM[14354] = 36'o000000000001; // 034022 SSRAM[14355] = 36'o000000000000; // 034023 SSRAM[14356] = 36'o000000000001; // 034024 SSRAM[14357] = 36'o000000000001; // 034025 SSRAM[14358] = 36'o000000000001; // 034026 SSRAM[14359] = 36'o377777777777; // 034027 SSRAM[14360] = 36'o777777777777; // 034030 SSRAM[14361] = 36'o400000000000; // 034031 SSRAM[14362] = 36'o777777777777; // 034032 SSRAM[14363] = 36'o400000000001; // 034033 SSRAM[14364] = 36'o777777777777; // 034034 SSRAM[14365] = 36'o777777777777; // 034035 SSRAM[14366] = 36'o000000000000; // 034036 SSRAM[14367] = 36'o000000000000; // 034037 SSRAM[14368] = 36'o200640041763; // 034040 SSRAM[14369] = 36'o120040034647; // 034041 SSRAM[14370] = 36'o115040034651; // 034042 SSRAM[14371] = 36'o400540000000; // 034043 SSRAM[14372] = 36'o312040034653; // 034044 SSRAM[14373] = 36'o254000034051; // 034045 SSRAM[14374] = 36'o201540000001; // 034046 SSRAM[14375] = 36'o316100034654; // 034047 SSRAM[14376] = 36'o254000034054; // 034050 SSRAM[14377] = 36'o200613000001; // 034051 SSRAM[14378] = 36'o200553034653; // 034052 SSRAM[14379] = 36'o036600041771; // 034053 SSRAM[14380] = 36'o255000000000; // 034054 SSRAM[14381] = 36'o200640041774; // 034055 SSRAM[14382] = 36'o120040034655; // 034056 SSRAM[14383] = 36'o115040034657; // 034057 SSRAM[14384] = 36'o400540000000; // 034060 SSRAM[14385] = 36'o312040034661; // 034061 SSRAM[14386] = 36'o254000034066; // 034062 SSRAM[14387] = 36'o201540000001; // 034063 SSRAM[14388] = 36'o316100034662; // 034064 SSRAM[14389] = 36'o254000034071; // 034065 SSRAM[14390] = 36'o200613000001; // 034066 SSRAM[14391] = 36'o200553034661; // 034067 SSRAM[14392] = 36'o036600041771; // 034070 SSRAM[14393] = 36'o255000000000; // 034071 SSRAM[14394] = 36'o200640041775; // 034072 SSRAM[14395] = 36'o120040034663; // 034073 SSRAM[14396] = 36'o115040034665; // 034074 SSRAM[14397] = 36'o400540000000; // 034075 SSRAM[14398] = 36'o312040034667; // 034076 SSRAM[14399] = 36'o254000034103; // 034077 SSRAM[14400] = 36'o201540000001; // 034100 SSRAM[14401] = 36'o316100034670; // 034101 SSRAM[14402] = 36'o254000034106; // 034102 SSRAM[14403] = 36'o200613000001; // 034103 SSRAM[14404] = 36'o200553034667; // 034104 SSRAM[14405] = 36'o036600041771; // 034105 SSRAM[14406] = 36'o255000000000; // 034106 SSRAM[14407] = 36'o200640041776; // 034107 SSRAM[14408] = 36'o120040034671; // 034110 SSRAM[14409] = 36'o115040034673; // 034111 SSRAM[14410] = 36'o400540000000; // 034112 SSRAM[14411] = 36'o312040034675; // 034113 SSRAM[14412] = 36'o254000034120; // 034114 SSRAM[14413] = 36'o201540000001; // 034115 SSRAM[14414] = 36'o316100034676; // 034116 SSRAM[14415] = 36'o254000034123; // 034117 SSRAM[14416] = 36'o200613000001; // 034120 SSRAM[14417] = 36'o200553034675; // 034121 SSRAM[14418] = 36'o036600041771; // 034122 SSRAM[14419] = 36'o255000000000; // 034123 SSRAM[14420] = 36'o200640041777; // 034124 SSRAM[14421] = 36'o120040034677; // 034125 SSRAM[14422] = 36'o115040034701; // 034126 SSRAM[14423] = 36'o400540000000; // 034127 SSRAM[14424] = 36'o312040034703; // 034130 SSRAM[14425] = 36'o254000034135; // 034131 SSRAM[14426] = 36'o201540000001; // 034132 SSRAM[14427] = 36'o316100034704; // 034133 SSRAM[14428] = 36'o254000034140; // 034134 SSRAM[14429] = 36'o200613000001; // 034135 SSRAM[14430] = 36'o200553034703; // 034136 SSRAM[14431] = 36'o036600041771; // 034137 SSRAM[14432] = 36'o255000000000; // 034140 SSRAM[14433] = 36'o200640042000; // 034141 SSRAM[14434] = 36'o120040034705; // 034142 SSRAM[14435] = 36'o115040034707; // 034143 SSRAM[14436] = 36'o400540000000; // 034144 SSRAM[14437] = 36'o312040034711; // 034145 SSRAM[14438] = 36'o254000034152; // 034146 SSRAM[14439] = 36'o201540000001; // 034147 SSRAM[14440] = 36'o316100034712; // 034150 SSRAM[14441] = 36'o254000034155; // 034151 SSRAM[14442] = 36'o200613000001; // 034152 SSRAM[14443] = 36'o200553034711; // 034153 SSRAM[14444] = 36'o036600041771; // 034154 SSRAM[14445] = 36'o255000000000; // 034155 SSRAM[14446] = 36'o200640042001; // 034156 SSRAM[14447] = 36'o120040034713; // 034157 SSRAM[14448] = 36'o115040034715; // 034160 SSRAM[14449] = 36'o400540000000; // 034161 SSRAM[14450] = 36'o312040034717; // 034162 SSRAM[14451] = 36'o254000034167; // 034163 SSRAM[14452] = 36'o201540000001; // 034164 SSRAM[14453] = 36'o316100034720; // 034165 SSRAM[14454] = 36'o254000034172; // 034166 SSRAM[14455] = 36'o200613000001; // 034167 SSRAM[14456] = 36'o200553034717; // 034170 SSRAM[14457] = 36'o036600042007; // 034171 SSRAM[14458] = 36'o255000000000; // 034172 SSRAM[14459] = 36'o200640042012; // 034173 SSRAM[14460] = 36'o120040034721; // 034174 SSRAM[14461] = 36'o115040034723; // 034175 SSRAM[14462] = 36'o400540000000; // 034176 SSRAM[14463] = 36'o312040034725; // 034177 SSRAM[14464] = 36'o254000034204; // 034200 SSRAM[14465] = 36'o201540000001; // 034201 SSRAM[14466] = 36'o316100034726; // 034202 SSRAM[14467] = 36'o254000034207; // 034203 SSRAM[14468] = 36'o200613000001; // 034204 SSRAM[14469] = 36'o200553034725; // 034205 SSRAM[14470] = 36'o036600042007; // 034206 SSRAM[14471] = 36'o255000000000; // 034207 SSRAM[14472] = 36'o200640042013; // 034210 SSRAM[14473] = 36'o120040034727; // 034211 SSRAM[14474] = 36'o115040034731; // 034212 SSRAM[14475] = 36'o400540000000; // 034213 SSRAM[14476] = 36'o312040034733; // 034214 SSRAM[14477] = 36'o254000034221; // 034215 SSRAM[14478] = 36'o201540000001; // 034216 SSRAM[14479] = 36'o316100034734; // 034217 SSRAM[14480] = 36'o254000034224; // 034220 SSRAM[14481] = 36'o200613000001; // 034221 SSRAM[14482] = 36'o200553034733; // 034222 SSRAM[14483] = 36'o036600042007; // 034223 SSRAM[14484] = 36'o255000000000; // 034224 SSRAM[14485] = 36'o200640042014; // 034225 SSRAM[14486] = 36'o120040034735; // 034226 SSRAM[14487] = 36'o115040034737; // 034227 SSRAM[14488] = 36'o400540000000; // 034230 SSRAM[14489] = 36'o312040034741; // 034231 SSRAM[14490] = 36'o254000034236; // 034232 SSRAM[14491] = 36'o201540000001; // 034233 SSRAM[14492] = 36'o316100034742; // 034234 SSRAM[14493] = 36'o254000034241; // 034235 SSRAM[14494] = 36'o200613000001; // 034236 SSRAM[14495] = 36'o200553034741; // 034237 SSRAM[14496] = 36'o036600042007; // 034240 SSRAM[14497] = 36'o255000000000; // 034241 SSRAM[14498] = 36'o200640042015; // 034242 SSRAM[14499] = 36'o120040034743; // 034243 SSRAM[14500] = 36'o115040034745; // 034244 SSRAM[14501] = 36'o400540000000; // 034245 SSRAM[14502] = 36'o312040034747; // 034246 SSRAM[14503] = 36'o254000034253; // 034247 SSRAM[14504] = 36'o201540000001; // 034250 SSRAM[14505] = 36'o316100034750; // 034251 SSRAM[14506] = 36'o254000034256; // 034252 SSRAM[14507] = 36'o200613000001; // 034253 SSRAM[14508] = 36'o200553034747; // 034254 SSRAM[14509] = 36'o036600042007; // 034255 SSRAM[14510] = 36'o255000000000; // 034256 SSRAM[14511] = 36'o200640042016; // 034257 SSRAM[14512] = 36'o120040034751; // 034260 SSRAM[14513] = 36'o115040034753; // 034261 SSRAM[14514] = 36'o400540000000; // 034262 SSRAM[14515] = 36'o312040034755; // 034263 SSRAM[14516] = 36'o254000034270; // 034264 SSRAM[14517] = 36'o201540000001; // 034265 SSRAM[14518] = 36'o316100034756; // 034266 SSRAM[14519] = 36'o254000034273; // 034267 SSRAM[14520] = 36'o200613000001; // 034270 SSRAM[14521] = 36'o200553034755; // 034271 SSRAM[14522] = 36'o036600042007; // 034272 SSRAM[14523] = 36'o255000000000; // 034273 SSRAM[14524] = 36'o200640042017; // 034274 SSRAM[14525] = 36'o120040034757; // 034275 SSRAM[14526] = 36'o115040034761; // 034276 SSRAM[14527] = 36'o400540000000; // 034277 SSRAM[14528] = 36'o312040034763; // 034300 SSRAM[14529] = 36'o254000034305; // 034301 SSRAM[14530] = 36'o201540000001; // 034302 SSRAM[14531] = 36'o316100034764; // 034303 SSRAM[14532] = 36'o254000034310; // 034304 SSRAM[14533] = 36'o200613000001; // 034305 SSRAM[14534] = 36'o200553034763; // 034306 SSRAM[14535] = 36'o036600042025; // 034307 SSRAM[14536] = 36'o255000000000; // 034310 SSRAM[14537] = 36'o200640042030; // 034311 SSRAM[14538] = 36'o120040034765; // 034312 SSRAM[14539] = 36'o115040034767; // 034313 SSRAM[14540] = 36'o400540000000; // 034314 SSRAM[14541] = 36'o312040034771; // 034315 SSRAM[14542] = 36'o254000034322; // 034316 SSRAM[14543] = 36'o201540000001; // 034317 SSRAM[14544] = 36'o316100034772; // 034320 SSRAM[14545] = 36'o254000034325; // 034321 SSRAM[14546] = 36'o200613000001; // 034322 SSRAM[14547] = 36'o200553034771; // 034323 SSRAM[14548] = 36'o036600042025; // 034324 SSRAM[14549] = 36'o255000000000; // 034325 SSRAM[14550] = 36'o200640042031; // 034326 SSRAM[14551] = 36'o120040034773; // 034327 SSRAM[14552] = 36'o115040034775; // 034330 SSRAM[14553] = 36'o400540000000; // 034331 SSRAM[14554] = 36'o312040034777; // 034332 SSRAM[14555] = 36'o254000034337; // 034333 SSRAM[14556] = 36'o201540000001; // 034334 SSRAM[14557] = 36'o316100035000; // 034335 SSRAM[14558] = 36'o254000034342; // 034336 SSRAM[14559] = 36'o200613000001; // 034337 SSRAM[14560] = 36'o200553034777; // 034340 SSRAM[14561] = 36'o036600042025; // 034341 SSRAM[14562] = 36'o255000000000; // 034342 SSRAM[14563] = 36'o200640042032; // 034343 SSRAM[14564] = 36'o120040035001; // 034344 SSRAM[14565] = 36'o115040035003; // 034345 SSRAM[14566] = 36'o400540000000; // 034346 SSRAM[14567] = 36'o312040035005; // 034347 SSRAM[14568] = 36'o254000034354; // 034350 SSRAM[14569] = 36'o201540000001; // 034351 SSRAM[14570] = 36'o316100035006; // 034352 SSRAM[14571] = 36'o254000034357; // 034353 SSRAM[14572] = 36'o200613000001; // 034354 SSRAM[14573] = 36'o200553035005; // 034355 SSRAM[14574] = 36'o036600042025; // 034356 SSRAM[14575] = 36'o255000000000; // 034357 SSRAM[14576] = 36'o200640042033; // 034360 SSRAM[14577] = 36'o120040035007; // 034361 SSRAM[14578] = 36'o115040035011; // 034362 SSRAM[14579] = 36'o400540000000; // 034363 SSRAM[14580] = 36'o312040035013; // 034364 SSRAM[14581] = 36'o254000034371; // 034365 SSRAM[14582] = 36'o201540000001; // 034366 SSRAM[14583] = 36'o316100035014; // 034367 SSRAM[14584] = 36'o254000034374; // 034370 SSRAM[14585] = 36'o200613000001; // 034371 SSRAM[14586] = 36'o200553035013; // 034372 SSRAM[14587] = 36'o036600042025; // 034373 SSRAM[14588] = 36'o255000000000; // 034374 SSRAM[14589] = 36'o200640042034; // 034375 SSRAM[14590] = 36'o120040035015; // 034376 SSRAM[14591] = 36'o115040035017; // 034377 SSRAM[14592] = 36'o400540000000; // 034400 SSRAM[14593] = 36'o312040035021; // 034401 SSRAM[14594] = 36'o254000034406; // 034402 SSRAM[14595] = 36'o201540000001; // 034403 SSRAM[14596] = 36'o316100035022; // 034404 SSRAM[14597] = 36'o254000034411; // 034405 SSRAM[14598] = 36'o200613000001; // 034406 SSRAM[14599] = 36'o200553035021; // 034407 SSRAM[14600] = 36'o036600042025; // 034410 SSRAM[14601] = 36'o255000000000; // 034411 SSRAM[14602] = 36'o200640042035; // 034412 SSRAM[14603] = 36'o120040035023; // 034413 SSRAM[14604] = 36'o115040035025; // 034414 SSRAM[14605] = 36'o400540000000; // 034415 SSRAM[14606] = 36'o312040041166; // 034416 SSRAM[14607] = 36'o254000034423; // 034417 SSRAM[14608] = 36'o201540000001; // 034420 SSRAM[14609] = 36'o316100042036; // 034421 SSRAM[14610] = 36'o254000034426; // 034422 SSRAM[14611] = 36'o200613000001; // 034423 SSRAM[14612] = 36'o200553042037; // 034424 SSRAM[14613] = 36'o036600042046; // 034425 SSRAM[14614] = 36'o255000000000; // 034426 SSRAM[14615] = 36'o200640042051; // 034427 SSRAM[14616] = 36'o120040035027; // 034430 SSRAM[14617] = 36'o115040035031; // 034431 SSRAM[14618] = 36'o400540000000; // 034432 SSRAM[14619] = 36'o312040041166; // 034433 SSRAM[14620] = 36'o254000034440; // 034434 SSRAM[14621] = 36'o201540000001; // 034435 SSRAM[14622] = 36'o316100042036; // 034436 SSRAM[14623] = 36'o254000034443; // 034437 SSRAM[14624] = 36'o200613000001; // 034440 SSRAM[14625] = 36'o200553042037; // 034441 SSRAM[14626] = 36'o036600042046; // 034442 SSRAM[14627] = 36'o255000000000; // 034443 SSRAM[14628] = 36'o200640042052; // 034444 SSRAM[14629] = 36'o120040035033; // 034445 SSRAM[14630] = 36'o115040035035; // 034446 SSRAM[14631] = 36'o400540000000; // 034447 SSRAM[14632] = 36'o312040041166; // 034450 SSRAM[14633] = 36'o254000034455; // 034451 SSRAM[14634] = 36'o201540000001; // 034452 SSRAM[14635] = 36'o316100042036; // 034453 SSRAM[14636] = 36'o254000034460; // 034454 SSRAM[14637] = 36'o200613000001; // 034455 SSRAM[14638] = 36'o200553042037; // 034456 SSRAM[14639] = 36'o036600042046; // 034457 SSRAM[14640] = 36'o255000000000; // 034460 SSRAM[14641] = 36'o200640042053; // 034461 SSRAM[14642] = 36'o120040035037; // 034462 SSRAM[14643] = 36'o115040035041; // 034463 SSRAM[14644] = 36'o400540000000; // 034464 SSRAM[14645] = 36'o312040041166; // 034465 SSRAM[14646] = 36'o254000034472; // 034466 SSRAM[14647] = 36'o201540000001; // 034467 SSRAM[14648] = 36'o316100042036; // 034470 SSRAM[14649] = 36'o254000034475; // 034471 SSRAM[14650] = 36'o200613000001; // 034472 SSRAM[14651] = 36'o200553042037; // 034473 SSRAM[14652] = 36'o036600042046; // 034474 SSRAM[14653] = 36'o255000000000; // 034475 SSRAM[14654] = 36'o200640042054; // 034476 SSRAM[14655] = 36'o120040035043; // 034477 SSRAM[14656] = 36'o115040035045; // 034500 SSRAM[14657] = 36'o400540000000; // 034501 SSRAM[14658] = 36'o312040041166; // 034502 SSRAM[14659] = 36'o254000034507; // 034503 SSRAM[14660] = 36'o201540000001; // 034504 SSRAM[14661] = 36'o316100042036; // 034505 SSRAM[14662] = 36'o254000034512; // 034506 SSRAM[14663] = 36'o200613000001; // 034507 SSRAM[14664] = 36'o200553042037; // 034510 SSRAM[14665] = 36'o036600042046; // 034511 SSRAM[14666] = 36'o255000000000; // 034512 SSRAM[14667] = 36'o200640042055; // 034513 SSRAM[14668] = 36'o120040035047; // 034514 SSRAM[14669] = 36'o115040035051; // 034515 SSRAM[14670] = 36'o400540000000; // 034516 SSRAM[14671] = 36'o312040041166; // 034517 SSRAM[14672] = 36'o254000034524; // 034520 SSRAM[14673] = 36'o201540000001; // 034521 SSRAM[14674] = 36'o316100042036; // 034522 SSRAM[14675] = 36'o254000034527; // 034523 SSRAM[14676] = 36'o200613000001; // 034524 SSRAM[14677] = 36'o200553042037; // 034525 SSRAM[14678] = 36'o036600042046; // 034526 SSRAM[14679] = 36'o255000000000; // 034527 SSRAM[14680] = 36'o200640042056; // 034530 SSRAM[14681] = 36'o120040035053; // 034531 SSRAM[14682] = 36'o115040035055; // 034532 SSRAM[14683] = 36'o400540000000; // 034533 SSRAM[14684] = 36'o312040041020; // 034534 SSRAM[14685] = 36'o254000034541; // 034535 SSRAM[14686] = 36'o201540000001; // 034536 SSRAM[14687] = 36'o316100042057; // 034537 SSRAM[14688] = 36'o254000034544; // 034540 SSRAM[14689] = 36'o200613000001; // 034541 SSRAM[14690] = 36'o200553042060; // 034542 SSRAM[14691] = 36'o036600042067; // 034543 SSRAM[14692] = 36'o255000000000; // 034544 SSRAM[14693] = 36'o200640042072; // 034545 SSRAM[14694] = 36'o120040035057; // 034546 SSRAM[14695] = 36'o115040035061; // 034547 SSRAM[14696] = 36'o400540000000; // 034550 SSRAM[14697] = 36'o312040041020; // 034551 SSRAM[14698] = 36'o254000034556; // 034552 SSRAM[14699] = 36'o201540000001; // 034553 SSRAM[14700] = 36'o316100042057; // 034554 SSRAM[14701] = 36'o254000034561; // 034555 SSRAM[14702] = 36'o200613000001; // 034556 SSRAM[14703] = 36'o200553042060; // 034557 SSRAM[14704] = 36'o036600042067; // 034560 SSRAM[14705] = 36'o255000000000; // 034561 SSRAM[14706] = 36'o200640042073; // 034562 SSRAM[14707] = 36'o120040035063; // 034563 SSRAM[14708] = 36'o115040035065; // 034564 SSRAM[14709] = 36'o400540000000; // 034565 SSRAM[14710] = 36'o312040041020; // 034566 SSRAM[14711] = 36'o254000034573; // 034567 SSRAM[14712] = 36'o201540000001; // 034570 SSRAM[14713] = 36'o316100042057; // 034571 SSRAM[14714] = 36'o254000034576; // 034572 SSRAM[14715] = 36'o200613000001; // 034573 SSRAM[14716] = 36'o200553042060; // 034574 SSRAM[14717] = 36'o036600042067; // 034575 SSRAM[14718] = 36'o255000000000; // 034576 SSRAM[14719] = 36'o200640042074; // 034577 SSRAM[14720] = 36'o120040035067; // 034600 SSRAM[14721] = 36'o115040035071; // 034601 SSRAM[14722] = 36'o400540000000; // 034602 SSRAM[14723] = 36'o312040041020; // 034603 SSRAM[14724] = 36'o254000034610; // 034604 SSRAM[14725] = 36'o201540000001; // 034605 SSRAM[14726] = 36'o316100042057; // 034606 SSRAM[14727] = 36'o254000034613; // 034607 SSRAM[14728] = 36'o200613000001; // 034610 SSRAM[14729] = 36'o200553042060; // 034611 SSRAM[14730] = 36'o036600042067; // 034612 SSRAM[14731] = 36'o255000000000; // 034613 SSRAM[14732] = 36'o200640042075; // 034614 SSRAM[14733] = 36'o120040035073; // 034615 SSRAM[14734] = 36'o115040035075; // 034616 SSRAM[14735] = 36'o400540000000; // 034617 SSRAM[14736] = 36'o312040041020; // 034620 SSRAM[14737] = 36'o254000034625; // 034621 SSRAM[14738] = 36'o201540000001; // 034622 SSRAM[14739] = 36'o316100042057; // 034623 SSRAM[14740] = 36'o254000034630; // 034624 SSRAM[14741] = 36'o200613000001; // 034625 SSRAM[14742] = 36'o200553042060; // 034626 SSRAM[14743] = 36'o036600042067; // 034627 SSRAM[14744] = 36'o255000000000; // 034630 SSRAM[14745] = 36'o200640042076; // 034631 SSRAM[14746] = 36'o120040035077; // 034632 SSRAM[14747] = 36'o115040035101; // 034633 SSRAM[14748] = 36'o400540000000; // 034634 SSRAM[14749] = 36'o312040041020; // 034635 SSRAM[14750] = 36'o254000034642; // 034636 SSRAM[14751] = 36'o201540000001; // 034637 SSRAM[14752] = 36'o316100042057; // 034640 SSRAM[14753] = 36'o254000034645; // 034641 SSRAM[14754] = 36'o200613000001; // 034642 SSRAM[14755] = 36'o200553042060; // 034643 SSRAM[14756] = 36'o036600042067; // 034644 SSRAM[14757] = 36'o255000000000; // 034645 SSRAM[14758] = 36'o254000035103; // 034646 SSRAM[14759] = 36'o000000000000; // 034647 SSRAM[14760] = 36'o000000000000; // 034650 SSRAM[14761] = 36'o000000000000; // 034651 SSRAM[14762] = 36'o400000000000; // 034652 SSRAM[14763] = 36'o000000000000; // 034653 SSRAM[14764] = 36'o000000000000; // 034654 SSRAM[14765] = 36'o000000000000; // 034655 SSRAM[14766] = 36'o400000000000; // 034656 SSRAM[14767] = 36'o000000000000; // 034657 SSRAM[14768] = 36'o000000000001; // 034660 SSRAM[14769] = 36'o777777777777; // 034661 SSRAM[14770] = 36'o777777777777; // 034662 SSRAM[14771] = 36'o000000000000; // 034663 SSRAM[14772] = 36'o400000000000; // 034664 SSRAM[14773] = 36'o000000000000; // 034665 SSRAM[14774] = 36'o400000000001; // 034666 SSRAM[14775] = 36'o777777777777; // 034667 SSRAM[14776] = 36'o777777777777; // 034670 SSRAM[14777] = 36'o000000000000; // 034671 SSRAM[14778] = 36'o000000000000; // 034672 SSRAM[14779] = 36'o777777777777; // 034673 SSRAM[14780] = 36'o377777777777; // 034674 SSRAM[14781] = 36'o000000000000; // 034675 SSRAM[14782] = 36'o000000000001; // 034676 SSRAM[14783] = 36'o000000000000; // 034677 SSRAM[14784] = 36'o400000000000; // 034700 SSRAM[14785] = 36'o777777777777; // 034701 SSRAM[14786] = 36'o377777777777; // 034702 SSRAM[14787] = 36'o000000000000; // 034703 SSRAM[14788] = 36'o000000000001; // 034704 SSRAM[14789] = 36'o000000000000; // 034705 SSRAM[14790] = 36'o400000000000; // 034706 SSRAM[14791] = 36'o777777777777; // 034707 SSRAM[14792] = 36'o777777777777; // 034710 SSRAM[14793] = 36'o000000000000; // 034711 SSRAM[14794] = 36'o000000000001; // 034712 SSRAM[14795] = 36'o777777777777; // 034713 SSRAM[14796] = 36'o377777777777; // 034714 SSRAM[14797] = 36'o777777777776; // 034715 SSRAM[14798] = 36'o777777777777; // 034716 SSRAM[14799] = 36'o000000000001; // 034717 SSRAM[14800] = 36'o000000000000; // 034720 SSRAM[14801] = 36'o777777777777; // 034721 SSRAM[14802] = 36'o377777777777; // 034722 SSRAM[14803] = 36'o777777777776; // 034723 SSRAM[14804] = 36'o377777777777; // 034724 SSRAM[14805] = 36'o000000000001; // 034725 SSRAM[14806] = 36'o000000000000; // 034726 SSRAM[14807] = 36'o777777777777; // 034727 SSRAM[14808] = 36'o777777777777; // 034730 SSRAM[14809] = 36'o777777777776; // 034731 SSRAM[14810] = 36'o377777777777; // 034732 SSRAM[14811] = 36'o000000000001; // 034733 SSRAM[14812] = 36'o000000000000; // 034734 SSRAM[14813] = 36'o777777777776; // 034735 SSRAM[14814] = 36'o777777777777; // 034736 SSRAM[14815] = 36'o777777777777; // 034737 SSRAM[14816] = 36'o377777777777; // 034740 SSRAM[14817] = 36'o777777777777; // 034741 SSRAM[14818] = 36'o400000000000; // 034742 SSRAM[14819] = 36'o777777777776; // 034743 SSRAM[14820] = 36'o377777777777; // 034744 SSRAM[14821] = 36'o777777777777; // 034745 SSRAM[14822] = 36'o377777777777; // 034746 SSRAM[14823] = 36'o777777777777; // 034747 SSRAM[14824] = 36'o400000000000; // 034750 SSRAM[14825] = 36'o777777777776; // 034751 SSRAM[14826] = 36'o377777777777; // 034752 SSRAM[14827] = 36'o777777777777; // 034753 SSRAM[14828] = 36'o777777777777; // 034754 SSRAM[14829] = 36'o777777777777; // 034755 SSRAM[14830] = 36'o400000000000; // 034756 SSRAM[14831] = 36'o000000000000; // 034757 SSRAM[14832] = 36'o400000000001; // 034760 SSRAM[14833] = 36'o000000000001; // 034761 SSRAM[14834] = 36'o000000000000; // 034762 SSRAM[14835] = 36'o777777777777; // 034763 SSRAM[14836] = 36'o400000000001; // 034764 SSRAM[14837] = 36'o000000000000; // 034765 SSRAM[14838] = 36'o400000000001; // 034766 SSRAM[14839] = 36'o000000000001; // 034767 SSRAM[14840] = 36'o400000000000; // 034770 SSRAM[14841] = 36'o777777777777; // 034771 SSRAM[14842] = 36'o400000000001; // 034772 SSRAM[14843] = 36'o000000000000; // 034773 SSRAM[14844] = 36'o000000000001; // 034774 SSRAM[14845] = 36'o000000000001; // 034775 SSRAM[14846] = 36'o400000000000; // 034776 SSRAM[14847] = 36'o777777777777; // 034777 SSRAM[14848] = 36'o400000000001; // 035000 SSRAM[14849] = 36'o000000000001; // 035001 SSRAM[14850] = 36'o000000000000; // 035002 SSRAM[14851] = 36'o000000000000; // 035003 SSRAM[14852] = 36'o400000000001; // 035004 SSRAM[14853] = 36'o000000000000; // 035005 SSRAM[14854] = 36'o377777777777; // 035006 SSRAM[14855] = 36'o000000000001; // 035007 SSRAM[14856] = 36'o400000000000; // 035010 SSRAM[14857] = 36'o000000000000; // 035011 SSRAM[14858] = 36'o400000000001; // 035012 SSRAM[14859] = 36'o000000000000; // 035013 SSRAM[14860] = 36'o377777777777; // 035014 SSRAM[14861] = 36'o000000000001; // 035015 SSRAM[14862] = 36'o400000000000; // 035016 SSRAM[14863] = 36'o000000000000; // 035017 SSRAM[14864] = 36'o000000000001; // 035020 SSRAM[14865] = 36'o000000000000; // 035021 SSRAM[14866] = 36'o377777777777; // 035022 SSRAM[14867] = 36'o777777777777; // 035023 SSRAM[14868] = 36'o377777777776; // 035024 SSRAM[14869] = 36'o000000000000; // 035025 SSRAM[14870] = 36'o000000000001; // 035026 SSRAM[14871] = 36'o777777777777; // 035027 SSRAM[14872] = 36'o377777777776; // 035030 SSRAM[14873] = 36'o000000000000; // 035031 SSRAM[14874] = 36'o400000000001; // 035032 SSRAM[14875] = 36'o777777777777; // 035033 SSRAM[14876] = 36'o777777777776; // 035034 SSRAM[14877] = 36'o000000000000; // 035035 SSRAM[14878] = 36'o400000000001; // 035036 SSRAM[14879] = 36'o777777777777; // 035037 SSRAM[14880] = 36'o377777777777; // 035040 SSRAM[14881] = 36'o000000000000; // 035041 SSRAM[14882] = 36'o000000000002; // 035042 SSRAM[14883] = 36'o777777777777; // 035043 SSRAM[14884] = 36'o377777777777; // 035044 SSRAM[14885] = 36'o000000000000; // 035045 SSRAM[14886] = 36'o400000000002; // 035046 SSRAM[14887] = 36'o777777777777; // 035047 SSRAM[14888] = 36'o777777777777; // 035050 SSRAM[14889] = 36'o000000000000; // 035051 SSRAM[14890] = 36'o400000000002; // 035052 SSRAM[14891] = 36'o000000000000; // 035053 SSRAM[14892] = 36'o000000000001; // 035054 SSRAM[14893] = 36'o777777777777; // 035055 SSRAM[14894] = 36'o377777777776; // 035056 SSRAM[14895] = 36'o000000000000; // 035057 SSRAM[14896] = 36'o400000000001; // 035060 SSRAM[14897] = 36'o777777777777; // 035061 SSRAM[14898] = 36'o377777777776; // 035062 SSRAM[14899] = 36'o000000000000; // 035063 SSRAM[14900] = 36'o400000000001; // 035064 SSRAM[14901] = 36'o777777777777; // 035065 SSRAM[14902] = 36'o777777777776; // 035066 SSRAM[14903] = 36'o000000000000; // 035067 SSRAM[14904] = 36'o000000000002; // 035070 SSRAM[14905] = 36'o777777777777; // 035071 SSRAM[14906] = 36'o377777777777; // 035072 SSRAM[14907] = 36'o000000000000; // 035073 SSRAM[14908] = 36'o400000000002; // 035074 SSRAM[14909] = 36'o777777777777; // 035075 SSRAM[14910] = 36'o377777777777; // 035076 SSRAM[14911] = 36'o000000000000; // 035077 SSRAM[14912] = 36'o400000000002; // 035100 SSRAM[14913] = 36'o777777777777; // 035101 SSRAM[14914] = 36'o777777777777; // 035102 SSRAM[14915] = 36'o200640042077; // 035103 SSRAM[14916] = 36'o120040035374; // 035104 SSRAM[14917] = 36'o255740035106; // 035105 SSRAM[14918] = 36'o115040035376; // 035106 SSRAM[14919] = 36'o264000035110; // 035107 SSRAM[14920] = 36'o000000000000; // 035110 SSRAM[14921] = 36'o400540000000; // 035111 SSRAM[14922] = 36'o312040041725; // 035112 SSRAM[14923] = 36'o254000035117; // 035113 SSRAM[14924] = 36'o201540000001; // 035114 SSRAM[14925] = 36'o316100041725; // 035115 SSRAM[14926] = 36'o254000035122; // 035116 SSRAM[14927] = 36'o200613000001; // 035117 SSRAM[14928] = 36'o200553042100; // 035120 SSRAM[14929] = 36'o036600042107; // 035121 SSRAM[14930] = 36'o255000000000; // 035122 SSRAM[14931] = 36'o200640042077; // 035123 SSRAM[14932] = 36'o200540035110; // 035124 SSRAM[14933] = 36'o200600041634; // 035125 SSRAM[14934] = 36'o430540000014; // 035126 SSRAM[14935] = 36'o603540740000; // 035127 SSRAM[14936] = 36'o036540042121; // 035130 SSRAM[14937] = 36'o255000000000; // 035131 SSRAM[14938] = 36'o200640042124; // 035132 SSRAM[14939] = 36'o120040035400; // 035133 SSRAM[14940] = 36'o255740035135; // 035134 SSRAM[14941] = 36'o115040035402; // 035135 SSRAM[14942] = 36'o264000035137; // 035136 SSRAM[14943] = 36'o000000000000; // 035137 SSRAM[14944] = 36'o400540000000; // 035140 SSRAM[14945] = 36'o312040041725; // 035141 SSRAM[14946] = 36'o254000035146; // 035142 SSRAM[14947] = 36'o201540000001; // 035143 SSRAM[14948] = 36'o316100041725; // 035144 SSRAM[14949] = 36'o254000035151; // 035145 SSRAM[14950] = 36'o200613000001; // 035146 SSRAM[14951] = 36'o200553042100; // 035147 SSRAM[14952] = 36'o036600042107; // 035150 SSRAM[14953] = 36'o255000000000; // 035151 SSRAM[14954] = 36'o200640042124; // 035152 SSRAM[14955] = 36'o200540035137; // 035153 SSRAM[14956] = 36'o200600041634; // 035154 SSRAM[14957] = 36'o430540000014; // 035155 SSRAM[14958] = 36'o603540740000; // 035156 SSRAM[14959] = 36'o036540042125; // 035157 SSRAM[14960] = 36'o255000000000; // 035160 SSRAM[14961] = 36'o200640042130; // 035161 SSRAM[14962] = 36'o120040035404; // 035162 SSRAM[14963] = 36'o255740035164; // 035163 SSRAM[14964] = 36'o115040035406; // 035164 SSRAM[14965] = 36'o264000035166; // 035165 SSRAM[14966] = 36'o000000000000; // 035166 SSRAM[14967] = 36'o400540000000; // 035167 SSRAM[14968] = 36'o312040041725; // 035170 SSRAM[14969] = 36'o254000035175; // 035171 SSRAM[14970] = 36'o201540000001; // 035172 SSRAM[14971] = 36'o316100041725; // 035173 SSRAM[14972] = 36'o254000035200; // 035174 SSRAM[14973] = 36'o200613000001; // 035175 SSRAM[14974] = 36'o200553042100; // 035176 SSRAM[14975] = 36'o036600042107; // 035177 SSRAM[14976] = 36'o255000000000; // 035200 SSRAM[14977] = 36'o200640042130; // 035201 SSRAM[14978] = 36'o200540035166; // 035202 SSRAM[14979] = 36'o200600041634; // 035203 SSRAM[14980] = 36'o430540000014; // 035204 SSRAM[14981] = 36'o603540740000; // 035205 SSRAM[14982] = 36'o036540042131; // 035206 SSRAM[14983] = 36'o255000000000; // 035207 SSRAM[14984] = 36'o200640042134; // 035210 SSRAM[14985] = 36'o120040035410; // 035211 SSRAM[14986] = 36'o255740035213; // 035212 SSRAM[14987] = 36'o115040035412; // 035213 SSRAM[14988] = 36'o264000035215; // 035214 SSRAM[14989] = 36'o000000000000; // 035215 SSRAM[14990] = 36'o400540000000; // 035216 SSRAM[14991] = 36'o312040041725; // 035217 SSRAM[14992] = 36'o254000035224; // 035220 SSRAM[14993] = 36'o201540000001; // 035221 SSRAM[14994] = 36'o316100041725; // 035222 SSRAM[14995] = 36'o254000035227; // 035223 SSRAM[14996] = 36'o200613000001; // 035224 SSRAM[14997] = 36'o200553042100; // 035225 SSRAM[14998] = 36'o036600042107; // 035226 SSRAM[14999] = 36'o255000000000; // 035227 SSRAM[15000] = 36'o200640042134; // 035230 SSRAM[15001] = 36'o200540035215; // 035231 SSRAM[15002] = 36'o200600041634; // 035232 SSRAM[15003] = 36'o430540000014; // 035233 SSRAM[15004] = 36'o603540740000; // 035234 SSRAM[15005] = 36'o036540042135; // 035235 SSRAM[15006] = 36'o255000000000; // 035236 SSRAM[15007] = 36'o200640042140; // 035237 SSRAM[15008] = 36'o120040035414; // 035240 SSRAM[15009] = 36'o255740035242; // 035241 SSRAM[15010] = 36'o115040035416; // 035242 SSRAM[15011] = 36'o264000035244; // 035243 SSRAM[15012] = 36'o000000000000; // 035244 SSRAM[15013] = 36'o400540000000; // 035245 SSRAM[15014] = 36'o312040042141; // 035246 SSRAM[15015] = 36'o254000035253; // 035247 SSRAM[15016] = 36'o201540000001; // 035250 SSRAM[15017] = 36'o316100042141; // 035251 SSRAM[15018] = 36'o254000035256; // 035252 SSRAM[15019] = 36'o200613000001; // 035253 SSRAM[15020] = 36'o200553042141; // 035254 SSRAM[15021] = 36'o036600042107; // 035255 SSRAM[15022] = 36'o255000000000; // 035256 SSRAM[15023] = 36'o200640042140; // 035257 SSRAM[15024] = 36'o200540035244; // 035260 SSRAM[15025] = 36'o200600041664; // 035261 SSRAM[15026] = 36'o430540000014; // 035262 SSRAM[15027] = 36'o603540740000; // 035263 SSRAM[15028] = 36'o036540042143; // 035264 SSRAM[15029] = 36'o255000000000; // 035265 SSRAM[15030] = 36'o200640042146; // 035266 SSRAM[15031] = 36'o120040035420; // 035267 SSRAM[15032] = 36'o255740035271; // 035270 SSRAM[15033] = 36'o115040035422; // 035271 SSRAM[15034] = 36'o264000035273; // 035272 SSRAM[15035] = 36'o000000000000; // 035273 SSRAM[15036] = 36'o400540000000; // 035274 SSRAM[15037] = 36'o312040042141; // 035275 SSRAM[15038] = 36'o254000035302; // 035276 SSRAM[15039] = 36'o201540000001; // 035277 SSRAM[15040] = 36'o316100042141; // 035300 SSRAM[15041] = 36'o254000035305; // 035301 SSRAM[15042] = 36'o200613000001; // 035302 SSRAM[15043] = 36'o200553042141; // 035303 SSRAM[15044] = 36'o036600042107; // 035304 SSRAM[15045] = 36'o255000000000; // 035305 SSRAM[15046] = 36'o200640042146; // 035306 SSRAM[15047] = 36'o200540035273; // 035307 SSRAM[15048] = 36'o200600041664; // 035310 SSRAM[15049] = 36'o430540000014; // 035311 SSRAM[15050] = 36'o603540740000; // 035312 SSRAM[15051] = 36'o036540042147; // 035313 SSRAM[15052] = 36'o255000000000; // 035314 SSRAM[15053] = 36'o200640042152; // 035315 SSRAM[15054] = 36'o120040035424; // 035316 SSRAM[15055] = 36'o255740035320; // 035317 SSRAM[15056] = 36'o115040035426; // 035320 SSRAM[15057] = 36'o264000035322; // 035321 SSRAM[15058] = 36'o000000000000; // 035322 SSRAM[15059] = 36'o400540000000; // 035323 SSRAM[15060] = 36'o312040042141; // 035324 SSRAM[15061] = 36'o254000035331; // 035325 SSRAM[15062] = 36'o201540000001; // 035326 SSRAM[15063] = 36'o316100042141; // 035327 SSRAM[15064] = 36'o254000035334; // 035330 SSRAM[15065] = 36'o200613000001; // 035331 SSRAM[15066] = 36'o200553042141; // 035332 SSRAM[15067] = 36'o036600042107; // 035333 SSRAM[15068] = 36'o255000000000; // 035334 SSRAM[15069] = 36'o200640042152; // 035335 SSRAM[15070] = 36'o200540035322; // 035336 SSRAM[15071] = 36'o200600041664; // 035337 SSRAM[15072] = 36'o430540000014; // 035340 SSRAM[15073] = 36'o603540740000; // 035341 SSRAM[15074] = 36'o036540042153; // 035342 SSRAM[15075] = 36'o255000000000; // 035343 SSRAM[15076] = 36'o200640042156; // 035344 SSRAM[15077] = 36'o120040035430; // 035345 SSRAM[15078] = 36'o255740035347; // 035346 SSRAM[15079] = 36'o115040035432; // 035347 SSRAM[15080] = 36'o264000035351; // 035350 SSRAM[15081] = 36'o000000000000; // 035351 SSRAM[15082] = 36'o400540000000; // 035352 SSRAM[15083] = 36'o312040042141; // 035353 SSRAM[15084] = 36'o254000035360; // 035354 SSRAM[15085] = 36'o201540000001; // 035355 SSRAM[15086] = 36'o316100042141; // 035356 SSRAM[15087] = 36'o254000035363; // 035357 SSRAM[15088] = 36'o200613000001; // 035360 SSRAM[15089] = 36'o200553042141; // 035361 SSRAM[15090] = 36'o036600042107; // 035362 SSRAM[15091] = 36'o255000000000; // 035363 SSRAM[15092] = 36'o200640042156; // 035364 SSRAM[15093] = 36'o200540035351; // 035365 SSRAM[15094] = 36'o200600041664; // 035366 SSRAM[15095] = 36'o430540000014; // 035367 SSRAM[15096] = 36'o603540740000; // 035370 SSRAM[15097] = 36'o036540042157; // 035371 SSRAM[15098] = 36'o200740030303; // 035372 SSRAM[15099] = 36'o254000035434; // 035373 SSRAM[15100] = 36'o200000000000; // 035374 SSRAM[15101] = 36'o000000000000; // 035375 SSRAM[15102] = 36'o600000000000; // 035376 SSRAM[15103] = 36'o000000000000; // 035377 SSRAM[15104] = 36'o000000000001; // 035400 SSRAM[15105] = 36'o000000000000; // 035401 SSRAM[15106] = 36'o400000000001; // 035402 SSRAM[15107] = 36'o000000000000; // 035403 SSRAM[15108] = 36'o000000000000; // 035404 SSRAM[15109] = 36'o200000000000; // 035405 SSRAM[15110] = 36'o400000000000; // 035406 SSRAM[15111] = 36'o200000000000; // 035407 SSRAM[15112] = 36'o000000000000; // 035410 SSRAM[15113] = 36'o000000000001; // 035411 SSRAM[15114] = 36'o400000000000; // 035412 SSRAM[15115] = 36'o000000000001; // 035413 SSRAM[15116] = 36'o577777777777; // 035414 SSRAM[15117] = 36'o777777777777; // 035415 SSRAM[15118] = 36'o200000000000; // 035416 SSRAM[15119] = 36'o000000000000; // 035417 SSRAM[15120] = 36'o777777777776; // 035420 SSRAM[15121] = 36'o777777777777; // 035421 SSRAM[15122] = 36'o377777777777; // 035422 SSRAM[15123] = 36'o000000000000; // 035423 SSRAM[15124] = 36'o777777777777; // 035424 SSRAM[15125] = 36'o577777777777; // 035425 SSRAM[15126] = 36'o377777777777; // 035426 SSRAM[15127] = 36'o600000000000; // 035427 SSRAM[15128] = 36'o777777777777; // 035430 SSRAM[15129] = 36'o777777777776; // 035431 SSRAM[15130] = 36'o377777777777; // 035432 SSRAM[15131] = 36'o777777777777; // 035433 SSRAM[15132] = 36'o200040042174; // 035434 SSRAM[15133] = 36'o251040040511; // 035435 SSRAM[15134] = 36'o260740040451; // 035436 SSRAM[15135] = 36'o036600042204; // 035437 SSRAM[15136] = 36'o255000000000; // 035440 SSRAM[15137] = 36'o200040042217; // 035441 SSRAM[15138] = 36'o251040040511; // 035442 SSRAM[15139] = 36'o260740040451; // 035443 SSRAM[15140] = 36'o036600042204; // 035444 SSRAM[15141] = 36'o255000000000; // 035445 SSRAM[15142] = 36'o200040042230; // 035446 SSRAM[15143] = 36'o251040040511; // 035447 SSRAM[15144] = 36'o260740040451; // 035450 SSRAM[15145] = 36'o036600042204; // 035451 SSRAM[15146] = 36'o255000000000; // 035452 SSRAM[15147] = 36'o200040042241; // 035453 SSRAM[15148] = 36'o251040040511; // 035454 SSRAM[15149] = 36'o260740040451; // 035455 SSRAM[15150] = 36'o036600042204; // 035456 SSRAM[15151] = 36'o255000000000; // 035457 SSRAM[15152] = 36'o200040042252; // 035460 SSRAM[15153] = 36'o251040040511; // 035461 SSRAM[15154] = 36'o260740040451; // 035462 SSRAM[15155] = 36'o036600042204; // 035463 SSRAM[15156] = 36'o255000000000; // 035464 SSRAM[15157] = 36'o200040042263; // 035465 SSRAM[15158] = 36'o251040040511; // 035466 SSRAM[15159] = 36'o260740040451; // 035467 SSRAM[15160] = 36'o036600042204; // 035470 SSRAM[15161] = 36'o255000000000; // 035471 SSRAM[15162] = 36'o200040042274; // 035472 SSRAM[15163] = 36'o251040040511; // 035473 SSRAM[15164] = 36'o260740040451; // 035474 SSRAM[15165] = 36'o036600042204; // 035475 SSRAM[15166] = 36'o255000000000; // 035476 SSRAM[15167] = 36'o200040042305; // 035477 SSRAM[15168] = 36'o251040040511; // 035500 SSRAM[15169] = 36'o260740040451; // 035501 SSRAM[15170] = 36'o036600042204; // 035502 SSRAM[15171] = 36'o255000000000; // 035503 SSRAM[15172] = 36'o200040042316; // 035504 SSRAM[15173] = 36'o251040040511; // 035505 SSRAM[15174] = 36'o260740040451; // 035506 SSRAM[15175] = 36'o036600042204; // 035507 SSRAM[15176] = 36'o255000000000; // 035510 SSRAM[15177] = 36'o200040042327; // 035511 SSRAM[15178] = 36'o251040040511; // 035512 SSRAM[15179] = 36'o260740040451; // 035513 SSRAM[15180] = 36'o036600042204; // 035514 SSRAM[15181] = 36'o255000000000; // 035515 SSRAM[15182] = 36'o200040042340; // 035516 SSRAM[15183] = 36'o251040040511; // 035517 SSRAM[15184] = 36'o260740040451; // 035520 SSRAM[15185] = 36'o036600042204; // 035521 SSRAM[15186] = 36'o255000000000; // 035522 SSRAM[15187] = 36'o200040042351; // 035523 SSRAM[15188] = 36'o251040040511; // 035524 SSRAM[15189] = 36'o260740040451; // 035525 SSRAM[15190] = 36'o036600042204; // 035526 SSRAM[15191] = 36'o255000000000; // 035527 SSRAM[15192] = 36'o200040042362; // 035530 SSRAM[15193] = 36'o251040040511; // 035531 SSRAM[15194] = 36'o260740040451; // 035532 SSRAM[15195] = 36'o036600042372; // 035533 SSRAM[15196] = 36'o255000000000; // 035534 SSRAM[15197] = 36'o200040042405; // 035535 SSRAM[15198] = 36'o251040040511; // 035536 SSRAM[15199] = 36'o260740040451; // 035537 SSRAM[15200] = 36'o036600042415; // 035540 SSRAM[15201] = 36'o255000000000; // 035541 SSRAM[15202] = 36'o200040042430; // 035542 SSRAM[15203] = 36'o251040040511; // 035543 SSRAM[15204] = 36'o260740040451; // 035544 SSRAM[15205] = 36'o036600042415; // 035545 SSRAM[15206] = 36'o255000000000; // 035546 SSRAM[15207] = 36'o200040042441; // 035547 SSRAM[15208] = 36'o251040040511; // 035550 SSRAM[15209] = 36'o260740040451; // 035551 SSRAM[15210] = 36'o036600042415; // 035552 SSRAM[15211] = 36'o255000000000; // 035553 SSRAM[15212] = 36'o200040042452; // 035554 SSRAM[15213] = 36'o251040040511; // 035555 SSRAM[15214] = 36'o260740040451; // 035556 SSRAM[15215] = 36'o036600042415; // 035557 SSRAM[15216] = 36'o255000000000; // 035560 SSRAM[15217] = 36'o200040042463; // 035561 SSRAM[15218] = 36'o251040040511; // 035562 SSRAM[15219] = 36'o260740040451; // 035563 SSRAM[15220] = 36'o036600042415; // 035564 SSRAM[15221] = 36'o255000000000; // 035565 SSRAM[15222] = 36'o200040042474; // 035566 SSRAM[15223] = 36'o251040040511; // 035567 SSRAM[15224] = 36'o260740040451; // 035570 SSRAM[15225] = 36'o036600042415; // 035571 SSRAM[15226] = 36'o255000000000; // 035572 SSRAM[15227] = 36'o200040042505; // 035573 SSRAM[15228] = 36'o251040040511; // 035574 SSRAM[15229] = 36'o260740040451; // 035575 SSRAM[15230] = 36'o036600042415; // 035576 SSRAM[15231] = 36'o255000000000; // 035577 SSRAM[15232] = 36'o200040042516; // 035600 SSRAM[15233] = 36'o251040040511; // 035601 SSRAM[15234] = 36'o260740040451; // 035602 SSRAM[15235] = 36'o036600042415; // 035603 SSRAM[15236] = 36'o255000000000; // 035604 SSRAM[15237] = 36'o200040042527; // 035605 SSRAM[15238] = 36'o251040040511; // 035606 SSRAM[15239] = 36'o260740040451; // 035607 SSRAM[15240] = 36'o036600042415; // 035610 SSRAM[15241] = 36'o255000000000; // 035611 SSRAM[15242] = 36'o200040042540; // 035612 SSRAM[15243] = 36'o251040040511; // 035613 SSRAM[15244] = 36'o260740040451; // 035614 SSRAM[15245] = 36'o036600042415; // 035615 SSRAM[15246] = 36'o255000000000; // 035616 SSRAM[15247] = 36'o200040042551; // 035617 SSRAM[15248] = 36'o251040040511; // 035620 SSRAM[15249] = 36'o260740040451; // 035621 SSRAM[15250] = 36'o036600042415; // 035622 SSRAM[15251] = 36'o255000000000; // 035623 SSRAM[15252] = 36'o200040042562; // 035624 SSRAM[15253] = 36'o251040040511; // 035625 SSRAM[15254] = 36'o260740040451; // 035626 SSRAM[15255] = 36'o036600042415; // 035627 SSRAM[15256] = 36'o255000000000; // 035630 SSRAM[15257] = 36'o200040042573; // 035631 SSRAM[15258] = 36'o251040040511; // 035632 SSRAM[15259] = 36'o260740040451; // 035633 SSRAM[15260] = 36'o036600042603; // 035634 SSRAM[15261] = 36'o255000000000; // 035635 SSRAM[15262] = 36'o200600040457; // 035636 SSRAM[15263] = 36'o623600400000; // 035637 SSRAM[15264] = 36'o036540042615; // 035640 SSRAM[15265] = 36'o255000000000; // 035641 SSRAM[15266] = 36'o200040042630; // 035642 SSRAM[15267] = 36'o251040040511; // 035643 SSRAM[15268] = 36'o260740040451; // 035644 SSRAM[15269] = 36'o036600042603; // 035645 SSRAM[15270] = 36'o255000000000; // 035646 SSRAM[15271] = 36'o200600040457; // 035647 SSRAM[15272] = 36'o623600400000; // 035650 SSRAM[15273] = 36'o036540042615; // 035651 SSRAM[15274] = 36'o255000000000; // 035652 SSRAM[15275] = 36'o200040042641; // 035653 SSRAM[15276] = 36'o251040040511; // 035654 SSRAM[15277] = 36'o260740040451; // 035655 SSRAM[15278] = 36'o036600042603; // 035656 SSRAM[15279] = 36'o255000000000; // 035657 SSRAM[15280] = 36'o200600040457; // 035660 SSRAM[15281] = 36'o623600400000; // 035661 SSRAM[15282] = 36'o036540042615; // 035662 SSRAM[15283] = 36'o255000000000; // 035663 SSRAM[15284] = 36'o200040042652; // 035664 SSRAM[15285] = 36'o251040040511; // 035665 SSRAM[15286] = 36'o260740040451; // 035666 SSRAM[15287] = 36'o036600042603; // 035667 SSRAM[15288] = 36'o255000000000; // 035670 SSRAM[15289] = 36'o200600040457; // 035671 SSRAM[15290] = 36'o623600400000; // 035672 SSRAM[15291] = 36'o036540042615; // 035673 SSRAM[15292] = 36'o255000000000; // 035674 SSRAM[15293] = 36'o200040042663; // 035675 SSRAM[15294] = 36'o251040040511; // 035676 SSRAM[15295] = 36'o260740040451; // 035677 SSRAM[15296] = 36'o036600042603; // 035700 SSRAM[15297] = 36'o255000000000; // 035701 SSRAM[15298] = 36'o200600040457; // 035702 SSRAM[15299] = 36'o623600400000; // 035703 SSRAM[15300] = 36'o036540042615; // 035704 SSRAM[15301] = 36'o255000000000; // 035705 SSRAM[15302] = 36'o200040042674; // 035706 SSRAM[15303] = 36'o251040040511; // 035707 SSRAM[15304] = 36'o260740040451; // 035710 SSRAM[15305] = 36'o036600042603; // 035711 SSRAM[15306] = 36'o255000000000; // 035712 SSRAM[15307] = 36'o200600040457; // 035713 SSRAM[15308] = 36'o623600400000; // 035714 SSRAM[15309] = 36'o036540042615; // 035715 SSRAM[15310] = 36'o255000000000; // 035716 SSRAM[15311] = 36'o200040042705; // 035717 SSRAM[15312] = 36'o251040040511; // 035720 SSRAM[15313] = 36'o260740040451; // 035721 SSRAM[15314] = 36'o036600042603; // 035722 SSRAM[15315] = 36'o255000000000; // 035723 SSRAM[15316] = 36'o200600040457; // 035724 SSRAM[15317] = 36'o623600400000; // 035725 SSRAM[15318] = 36'o036540042615; // 035726 SSRAM[15319] = 36'o255000000000; // 035727 SSRAM[15320] = 36'o200040042716; // 035730 SSRAM[15321] = 36'o251040040511; // 035731 SSRAM[15322] = 36'o260740040451; // 035732 SSRAM[15323] = 36'o036600042603; // 035733 SSRAM[15324] = 36'o255000000000; // 035734 SSRAM[15325] = 36'o200600040457; // 035735 SSRAM[15326] = 36'o623600400000; // 035736 SSRAM[15327] = 36'o036540042615; // 035737 SSRAM[15328] = 36'o255000000000; // 035740 SSRAM[15329] = 36'o200040042727; // 035741 SSRAM[15330] = 36'o251040040511; // 035742 SSRAM[15331] = 36'o260740040451; // 035743 SSRAM[15332] = 36'o036600042603; // 035744 SSRAM[15333] = 36'o255000000000; // 035745 SSRAM[15334] = 36'o200600040457; // 035746 SSRAM[15335] = 36'o623600400000; // 035747 SSRAM[15336] = 36'o036540042615; // 035750 SSRAM[15337] = 36'o255000000000; // 035751 SSRAM[15338] = 36'o200040042740; // 035752 SSRAM[15339] = 36'o251040040511; // 035753 SSRAM[15340] = 36'o260740040451; // 035754 SSRAM[15341] = 36'o036600042603; // 035755 SSRAM[15342] = 36'o255000000000; // 035756 SSRAM[15343] = 36'o200600040457; // 035757 SSRAM[15344] = 36'o623600400000; // 035760 SSRAM[15345] = 36'o036540042615; // 035761 SSRAM[15346] = 36'o255000000000; // 035762 SSRAM[15347] = 36'o200040042751; // 035763 SSRAM[15348] = 36'o251040040511; // 035764 SSRAM[15349] = 36'o260740040451; // 035765 SSRAM[15350] = 36'o036600042603; // 035766 SSRAM[15351] = 36'o255000000000; // 035767 SSRAM[15352] = 36'o200600040457; // 035770 SSRAM[15353] = 36'o623600400000; // 035771 SSRAM[15354] = 36'o036540042615; // 035772 SSRAM[15355] = 36'o255000000000; // 035773 SSRAM[15356] = 36'o200040042762; // 035774 SSRAM[15357] = 36'o251040040511; // 035775 SSRAM[15358] = 36'o260740040451; // 035776 SSRAM[15359] = 36'o036600042603; // 035777 SSRAM[15360] = 36'o255000000000; // 036000 SSRAM[15361] = 36'o200600040457; // 036001 SSRAM[15362] = 36'o623600400000; // 036002 SSRAM[15363] = 36'o036540042615; // 036003 SSRAM[15364] = 36'o255000000000; // 036004 SSRAM[15365] = 36'o200040042773; // 036005 SSRAM[15366] = 36'o251040040511; // 036006 SSRAM[15367] = 36'o260740040451; // 036007 SSRAM[15368] = 36'o036600042603; // 036010 SSRAM[15369] = 36'o255000000000; // 036011 SSRAM[15370] = 36'o200600040457; // 036012 SSRAM[15371] = 36'o623600400000; // 036013 SSRAM[15372] = 36'o036540042615; // 036014 SSRAM[15373] = 36'o255000000000; // 036015 SSRAM[15374] = 36'o200040043004; // 036016 SSRAM[15375] = 36'o251040040511; // 036017 SSRAM[15376] = 36'o260740040451; // 036020 SSRAM[15377] = 36'o036600042603; // 036021 SSRAM[15378] = 36'o255000000000; // 036022 SSRAM[15379] = 36'o200600040457; // 036023 SSRAM[15380] = 36'o623600400000; // 036024 SSRAM[15381] = 36'o036540042615; // 036025 SSRAM[15382] = 36'o255000000000; // 036026 SSRAM[15383] = 36'o200040043015; // 036027 SSRAM[15384] = 36'o251040040511; // 036030 SSRAM[15385] = 36'o260740040451; // 036031 SSRAM[15386] = 36'o036600042603; // 036032 SSRAM[15387] = 36'o255000000000; // 036033 SSRAM[15388] = 36'o200600040457; // 036034 SSRAM[15389] = 36'o623600400000; // 036035 SSRAM[15390] = 36'o036540042615; // 036036 SSRAM[15391] = 36'o255000000000; // 036037 SSRAM[15392] = 36'o200040043026; // 036040 SSRAM[15393] = 36'o251040040511; // 036041 SSRAM[15394] = 36'o260740040451; // 036042 SSRAM[15395] = 36'o036600042603; // 036043 SSRAM[15396] = 36'o255000000000; // 036044 SSRAM[15397] = 36'o200600040457; // 036045 SSRAM[15398] = 36'o623600400000; // 036046 SSRAM[15399] = 36'o036540042615; // 036047 SSRAM[15400] = 36'o255000000000; // 036050 SSRAM[15401] = 36'o200040043037; // 036051 SSRAM[15402] = 36'o251040040511; // 036052 SSRAM[15403] = 36'o260740040451; // 036053 SSRAM[15404] = 36'o036600042603; // 036054 SSRAM[15405] = 36'o255000000000; // 036055 SSRAM[15406] = 36'o200600040457; // 036056 SSRAM[15407] = 36'o623600400000; // 036057 SSRAM[15408] = 36'o036540042615; // 036060 SSRAM[15409] = 36'o255000000000; // 036061 SSRAM[15410] = 36'o200040043050; // 036062 SSRAM[15411] = 36'o251040040511; // 036063 SSRAM[15412] = 36'o260740040451; // 036064 SSRAM[15413] = 36'o036600042603; // 036065 SSRAM[15414] = 36'o255000000000; // 036066 SSRAM[15415] = 36'o200600040457; // 036067 SSRAM[15416] = 36'o623600400000; // 036070 SSRAM[15417] = 36'o036540042615; // 036071 SSRAM[15418] = 36'o255000000000; // 036072 SSRAM[15419] = 36'o200040043061; // 036073 SSRAM[15420] = 36'o251040040511; // 036074 SSRAM[15421] = 36'o260740040451; // 036075 SSRAM[15422] = 36'o036600042603; // 036076 SSRAM[15423] = 36'o255000000000; // 036077 SSRAM[15424] = 36'o200600040457; // 036100 SSRAM[15425] = 36'o623600400000; // 036101 SSRAM[15426] = 36'o036540042615; // 036102 SSRAM[15427] = 36'o255000000000; // 036103 SSRAM[15428] = 36'o200040043072; // 036104 SSRAM[15429] = 36'o251040040511; // 036105 SSRAM[15430] = 36'o260740040451; // 036106 SSRAM[15431] = 36'o036600042603; // 036107 SSRAM[15432] = 36'o255000000000; // 036110 SSRAM[15433] = 36'o200600040457; // 036111 SSRAM[15434] = 36'o623600400000; // 036112 SSRAM[15435] = 36'o036540042615; // 036113 SSRAM[15436] = 36'o255000000000; // 036114 SSRAM[15437] = 36'o200040043103; // 036115 SSRAM[15438] = 36'o251040040511; // 036116 SSRAM[15439] = 36'o260740040451; // 036117 SSRAM[15440] = 36'o036600043113; // 036120 SSRAM[15441] = 36'o255000000000; // 036121 SSRAM[15442] = 36'o200600040457; // 036122 SSRAM[15443] = 36'o623600400000; // 036123 SSRAM[15444] = 36'o036540043125; // 036124 SSRAM[15445] = 36'o255000000000; // 036125 SSRAM[15446] = 36'o200040043140; // 036126 SSRAM[15447] = 36'o251040040511; // 036127 SSRAM[15448] = 36'o260740040451; // 036130 SSRAM[15449] = 36'o036600043113; // 036131 SSRAM[15450] = 36'o255000000000; // 036132 SSRAM[15451] = 36'o200600040457; // 036133 SSRAM[15452] = 36'o623600400000; // 036134 SSRAM[15453] = 36'o036540043125; // 036135 SSRAM[15454] = 36'o255000000000; // 036136 SSRAM[15455] = 36'o200040043151; // 036137 SSRAM[15456] = 36'o251040040511; // 036140 SSRAM[15457] = 36'o260740040451; // 036141 SSRAM[15458] = 36'o036600043113; // 036142 SSRAM[15459] = 36'o255000000000; // 036143 SSRAM[15460] = 36'o200600040457; // 036144 SSRAM[15461] = 36'o623600400000; // 036145 SSRAM[15462] = 36'o036540043125; // 036146 SSRAM[15463] = 36'o255000000000; // 036147 SSRAM[15464] = 36'o200040043162; // 036150 SSRAM[15465] = 36'o251040040511; // 036151 SSRAM[15466] = 36'o260740040451; // 036152 SSRAM[15467] = 36'o036600043113; // 036153 SSRAM[15468] = 36'o255000000000; // 036154 SSRAM[15469] = 36'o200600040457; // 036155 SSRAM[15470] = 36'o623600400000; // 036156 SSRAM[15471] = 36'o036540043125; // 036157 SSRAM[15472] = 36'o255000000000; // 036160 SSRAM[15473] = 36'o200040043173; // 036161 SSRAM[15474] = 36'o251040040511; // 036162 SSRAM[15475] = 36'o260740040451; // 036163 SSRAM[15476] = 36'o036600043113; // 036164 SSRAM[15477] = 36'o255000000000; // 036165 SSRAM[15478] = 36'o200600040457; // 036166 SSRAM[15479] = 36'o623600400000; // 036167 SSRAM[15480] = 36'o036540043125; // 036170 SSRAM[15481] = 36'o255000000000; // 036171 SSRAM[15482] = 36'o200040043204; // 036172 SSRAM[15483] = 36'o251040040511; // 036173 SSRAM[15484] = 36'o260740040451; // 036174 SSRAM[15485] = 36'o036600043113; // 036175 SSRAM[15486] = 36'o255000000000; // 036176 SSRAM[15487] = 36'o200600040457; // 036177 SSRAM[15488] = 36'o623600400000; // 036200 SSRAM[15489] = 36'o036540043125; // 036201 SSRAM[15490] = 36'o255000000000; // 036202 SSRAM[15491] = 36'o200040043215; // 036203 SSRAM[15492] = 36'o251040040511; // 036204 SSRAM[15493] = 36'o260740040451; // 036205 SSRAM[15494] = 36'o036600043113; // 036206 SSRAM[15495] = 36'o255000000000; // 036207 SSRAM[15496] = 36'o200600040457; // 036210 SSRAM[15497] = 36'o623600400000; // 036211 SSRAM[15498] = 36'o036540043125; // 036212 SSRAM[15499] = 36'o255000000000; // 036213 SSRAM[15500] = 36'o200040043226; // 036214 SSRAM[15501] = 36'o251040040511; // 036215 SSRAM[15502] = 36'o260740040451; // 036216 SSRAM[15503] = 36'o036600043113; // 036217 SSRAM[15504] = 36'o255000000000; // 036220 SSRAM[15505] = 36'o200600040457; // 036221 SSRAM[15506] = 36'o623600400000; // 036222 SSRAM[15507] = 36'o036540043125; // 036223 SSRAM[15508] = 36'o255000000000; // 036224 SSRAM[15509] = 36'o200040043237; // 036225 SSRAM[15510] = 36'o251040040511; // 036226 SSRAM[15511] = 36'o260740040451; // 036227 SSRAM[15512] = 36'o036600043113; // 036230 SSRAM[15513] = 36'o255000000000; // 036231 SSRAM[15514] = 36'o200600040457; // 036232 SSRAM[15515] = 36'o623600400000; // 036233 SSRAM[15516] = 36'o036540043125; // 036234 SSRAM[15517] = 36'o255000000000; // 036235 SSRAM[15518] = 36'o200040043250; // 036236 SSRAM[15519] = 36'o251040040511; // 036237 SSRAM[15520] = 36'o260740040451; // 036240 SSRAM[15521] = 36'o036600043113; // 036241 SSRAM[15522] = 36'o255000000000; // 036242 SSRAM[15523] = 36'o200600040457; // 036243 SSRAM[15524] = 36'o623600400000; // 036244 SSRAM[15525] = 36'o036540043125; // 036245 SSRAM[15526] = 36'o255000000000; // 036246 SSRAM[15527] = 36'o200040043261; // 036247 SSRAM[15528] = 36'o251040040511; // 036250 SSRAM[15529] = 36'o260740040451; // 036251 SSRAM[15530] = 36'o036600043113; // 036252 SSRAM[15531] = 36'o255000000000; // 036253 SSRAM[15532] = 36'o200600040457; // 036254 SSRAM[15533] = 36'o623600400000; // 036255 SSRAM[15534] = 36'o036540043125; // 036256 SSRAM[15535] = 36'o255000000000; // 036257 SSRAM[15536] = 36'o200040043272; // 036260 SSRAM[15537] = 36'o251040040511; // 036261 SSRAM[15538] = 36'o260740040451; // 036262 SSRAM[15539] = 36'o036600043113; // 036263 SSRAM[15540] = 36'o255000000000; // 036264 SSRAM[15541] = 36'o200600040457; // 036265 SSRAM[15542] = 36'o623600400000; // 036266 SSRAM[15543] = 36'o036540043125; // 036267 SSRAM[15544] = 36'o255000000000; // 036270 SSRAM[15545] = 36'o200040043303; // 036271 SSRAM[15546] = 36'o251040040511; // 036272 SSRAM[15547] = 36'o260740040451; // 036273 SSRAM[15548] = 36'o036600043113; // 036274 SSRAM[15549] = 36'o255000000000; // 036275 SSRAM[15550] = 36'o200600040457; // 036276 SSRAM[15551] = 36'o623600400000; // 036277 SSRAM[15552] = 36'o036540043125; // 036300 SSRAM[15553] = 36'o255000000000; // 036301 SSRAM[15554] = 36'o200040043314; // 036302 SSRAM[15555] = 36'o251040040511; // 036303 SSRAM[15556] = 36'o260740040451; // 036304 SSRAM[15557] = 36'o036600043113; // 036305 SSRAM[15558] = 36'o255000000000; // 036306 SSRAM[15559] = 36'o200600040457; // 036307 SSRAM[15560] = 36'o623600400000; // 036310 SSRAM[15561] = 36'o036540043125; // 036311 SSRAM[15562] = 36'o255000000000; // 036312 SSRAM[15563] = 36'o200040043325; // 036313 SSRAM[15564] = 36'o251040040511; // 036314 SSRAM[15565] = 36'o260740040451; // 036315 SSRAM[15566] = 36'o036600043113; // 036316 SSRAM[15567] = 36'o255000000000; // 036317 SSRAM[15568] = 36'o200600040457; // 036320 SSRAM[15569] = 36'o623600400000; // 036321 SSRAM[15570] = 36'o036540043125; // 036322 SSRAM[15571] = 36'o255000000000; // 036323 SSRAM[15572] = 36'o200040043336; // 036324 SSRAM[15573] = 36'o251040040511; // 036325 SSRAM[15574] = 36'o260740040451; // 036326 SSRAM[15575] = 36'o036600043113; // 036327 SSRAM[15576] = 36'o255000000000; // 036330 SSRAM[15577] = 36'o200600040457; // 036331 SSRAM[15578] = 36'o623600400000; // 036332 SSRAM[15579] = 36'o036540043125; // 036333 SSRAM[15580] = 36'o255000000000; // 036334 SSRAM[15581] = 36'o200040043347; // 036335 SSRAM[15582] = 36'o251040040511; // 036336 SSRAM[15583] = 36'o260740040451; // 036337 SSRAM[15584] = 36'o036600043113; // 036340 SSRAM[15585] = 36'o255000000000; // 036341 SSRAM[15586] = 36'o200600040457; // 036342 SSRAM[15587] = 36'o623600400000; // 036343 SSRAM[15588] = 36'o036540043125; // 036344 SSRAM[15589] = 36'o255000000000; // 036345 SSRAM[15590] = 36'o200040043360; // 036346 SSRAM[15591] = 36'o251040040511; // 036347 SSRAM[15592] = 36'o260740040451; // 036350 SSRAM[15593] = 36'o036600043113; // 036351 SSRAM[15594] = 36'o255000000000; // 036352 SSRAM[15595] = 36'o200600040457; // 036353 SSRAM[15596] = 36'o623600400000; // 036354 SSRAM[15597] = 36'o036540043125; // 036355 SSRAM[15598] = 36'o255000000000; // 036356 SSRAM[15599] = 36'o200040043371; // 036357 SSRAM[15600] = 36'o251040040511; // 036360 SSRAM[15601] = 36'o260740040451; // 036361 SSRAM[15602] = 36'o036600043113; // 036362 SSRAM[15603] = 36'o255000000000; // 036363 SSRAM[15604] = 36'o200600040457; // 036364 SSRAM[15605] = 36'o623600400000; // 036365 SSRAM[15606] = 36'o036540043125; // 036366 SSRAM[15607] = 36'o255000000000; // 036367 SSRAM[15608] = 36'o200040043402; // 036370 SSRAM[15609] = 36'o251040040511; // 036371 SSRAM[15610] = 36'o260740040451; // 036372 SSRAM[15611] = 36'o036600043113; // 036373 SSRAM[15612] = 36'o255000000000; // 036374 SSRAM[15613] = 36'o200600040457; // 036375 SSRAM[15614] = 36'o623600400000; // 036376 SSRAM[15615] = 36'o036540043125; // 036377 SSRAM[15616] = 36'o255000000000; // 036400 SSRAM[15617] = 36'o120040042100; // 036401 SSRAM[15618] = 36'o120140043403; // 036402 SSRAM[15619] = 36'o400540000000; // 036403 SSRAM[15620] = 36'o255740036405; // 036404 SSRAM[15621] = 36'o116040000001; // 036405 SSRAM[15622] = 36'o264000036407; // 036406 SSRAM[15623] = 36'o000000000000; // 036407 SSRAM[15624] = 36'o312040041725; // 036410 SSRAM[15625] = 36'o254000036423; // 036411 SSRAM[15626] = 36'o201540000001; // 036412 SSRAM[15627] = 36'o312100041725; // 036413 SSRAM[15628] = 36'o254000036423; // 036414 SSRAM[15629] = 36'o201540000002; // 036415 SSRAM[15630] = 36'o312140041725; // 036416 SSRAM[15631] = 36'o254000036423; // 036417 SSRAM[15632] = 36'o201540000003; // 036420 SSRAM[15633] = 36'o316200041725; // 036421 SSRAM[15634] = 36'o254000036426; // 036422 SSRAM[15635] = 36'o200553000001; // 036423 SSRAM[15636] = 36'o036540043412; // 036424 SSRAM[15637] = 36'o255000000000; // 036425 SSRAM[15638] = 36'o255400036432; // 036426 SSRAM[15639] = 36'o201640042100; // 036427 SSRAM[15640] = 36'o504640000015; // 036430 SSRAM[15641] = 36'o036540043424; // 036431 SSRAM[15642] = 36'o255000000000; // 036432 SSRAM[15643] = 36'o200040043437; // 036433 SSRAM[15644] = 36'o251040040511; // 036434 SSRAM[15645] = 36'o260740040451; // 036435 SSRAM[15646] = 36'o036600043447; // 036436 SSRAM[15647] = 36'o255000000000; // 036437 SSRAM[15648] = 36'o200600040457; // 036440 SSRAM[15649] = 36'o623600400000; // 036441 SSRAM[15650] = 36'o036540043461; // 036442 SSRAM[15651] = 36'o255000000000; // 036443 SSRAM[15652] = 36'o200040043474; // 036444 SSRAM[15653] = 36'o251040040511; // 036445 SSRAM[15654] = 36'o260740040451; // 036446 SSRAM[15655] = 36'o036600043447; // 036447 SSRAM[15656] = 36'o255000000000; // 036450 SSRAM[15657] = 36'o200600040457; // 036451 SSRAM[15658] = 36'o623600400000; // 036452 SSRAM[15659] = 36'o036540043461; // 036453 SSRAM[15660] = 36'o255000000000; // 036454 SSRAM[15661] = 36'o200040043505; // 036455 SSRAM[15662] = 36'o251040040511; // 036456 SSRAM[15663] = 36'o260740040451; // 036457 SSRAM[15664] = 36'o036600043447; // 036460 SSRAM[15665] = 36'o255000000000; // 036461 SSRAM[15666] = 36'o200600040457; // 036462 SSRAM[15667] = 36'o623600400000; // 036463 SSRAM[15668] = 36'o036540043461; // 036464 SSRAM[15669] = 36'o255000000000; // 036465 SSRAM[15670] = 36'o200040043516; // 036466 SSRAM[15671] = 36'o251040040511; // 036467 SSRAM[15672] = 36'o260740040451; // 036470 SSRAM[15673] = 36'o036600043447; // 036471 SSRAM[15674] = 36'o255000000000; // 036472 SSRAM[15675] = 36'o200600040457; // 036473 SSRAM[15676] = 36'o623600400000; // 036474 SSRAM[15677] = 36'o036540043461; // 036475 SSRAM[15678] = 36'o255000000000; // 036476 SSRAM[15679] = 36'o200040043527; // 036477 SSRAM[15680] = 36'o251040040511; // 036500 SSRAM[15681] = 36'o260740040451; // 036501 SSRAM[15682] = 36'o036600043537; // 036502 SSRAM[15683] = 36'o255000000000; // 036503 SSRAM[15684] = 36'o200600040457; // 036504 SSRAM[15685] = 36'o623600400000; // 036505 SSRAM[15686] = 36'o036540043551; // 036506 SSRAM[15687] = 36'o255000000000; // 036507 SSRAM[15688] = 36'o200040043564; // 036510 SSRAM[15689] = 36'o251040040511; // 036511 SSRAM[15690] = 36'o260740040451; // 036512 SSRAM[15691] = 36'o036600043537; // 036513 SSRAM[15692] = 36'o255000000000; // 036514 SSRAM[15693] = 36'o200600040457; // 036515 SSRAM[15694] = 36'o623600400000; // 036516 SSRAM[15695] = 36'o036540043551; // 036517 SSRAM[15696] = 36'o255000000000; // 036520 SSRAM[15697] = 36'o200040043575; // 036521 SSRAM[15698] = 36'o251040040511; // 036522 SSRAM[15699] = 36'o260740040451; // 036523 SSRAM[15700] = 36'o036600043537; // 036524 SSRAM[15701] = 36'o255000000000; // 036525 SSRAM[15702] = 36'o200600040457; // 036526 SSRAM[15703] = 36'o623600400000; // 036527 SSRAM[15704] = 36'o036540043551; // 036530 SSRAM[15705] = 36'o255000000000; // 036531 SSRAM[15706] = 36'o200040043606; // 036532 SSRAM[15707] = 36'o251040040511; // 036533 SSRAM[15708] = 36'o260740040451; // 036534 SSRAM[15709] = 36'o036600043537; // 036535 SSRAM[15710] = 36'o255000000000; // 036536 SSRAM[15711] = 36'o200600040457; // 036537 SSRAM[15712] = 36'o623600400000; // 036540 SSRAM[15713] = 36'o036540043551; // 036541 SSRAM[15714] = 36'o255000000000; // 036542 SSRAM[15715] = 36'o200040043617; // 036543 SSRAM[15716] = 36'o251040040511; // 036544 SSRAM[15717] = 36'o260740040451; // 036545 SSRAM[15718] = 36'o036600043537; // 036546 SSRAM[15719] = 36'o255000000000; // 036547 SSRAM[15720] = 36'o200600040457; // 036550 SSRAM[15721] = 36'o623600400000; // 036551 SSRAM[15722] = 36'o036540043551; // 036552 SSRAM[15723] = 36'o255000000000; // 036553 SSRAM[15724] = 36'o200040043630; // 036554 SSRAM[15725] = 36'o251040040511; // 036555 SSRAM[15726] = 36'o260740040451; // 036556 SSRAM[15727] = 36'o036600043537; // 036557 SSRAM[15728] = 36'o255000000000; // 036560 SSRAM[15729] = 36'o200600040457; // 036561 SSRAM[15730] = 36'o623600400000; // 036562 SSRAM[15731] = 36'o036540043551; // 036563 SSRAM[15732] = 36'o255000000000; // 036564 SSRAM[15733] = 36'o200040043641; // 036565 SSRAM[15734] = 36'o251040040511; // 036566 SSRAM[15735] = 36'o260740040451; // 036567 SSRAM[15736] = 36'o036600043537; // 036570 SSRAM[15737] = 36'o255000000000; // 036571 SSRAM[15738] = 36'o200600040457; // 036572 SSRAM[15739] = 36'o623600400000; // 036573 SSRAM[15740] = 36'o036540043551; // 036574 SSRAM[15741] = 36'o255000000000; // 036575 SSRAM[15742] = 36'o200040043652; // 036576 SSRAM[15743] = 36'o251040040511; // 036577 SSRAM[15744] = 36'o260740040451; // 036600 SSRAM[15745] = 36'o036600043537; // 036601 SSRAM[15746] = 36'o255000000000; // 036602 SSRAM[15747] = 36'o200600040457; // 036603 SSRAM[15748] = 36'o623600400000; // 036604 SSRAM[15749] = 36'o036540043551; // 036605 SSRAM[15750] = 36'o255000000000; // 036606 SSRAM[15751] = 36'o200040043663; // 036607 SSRAM[15752] = 36'o251040040511; // 036610 SSRAM[15753] = 36'o260740040451; // 036611 SSRAM[15754] = 36'o036600043537; // 036612 SSRAM[15755] = 36'o255000000000; // 036613 SSRAM[15756] = 36'o200600040457; // 036614 SSRAM[15757] = 36'o623600400000; // 036615 SSRAM[15758] = 36'o036540043551; // 036616 SSRAM[15759] = 36'o255000000000; // 036617 SSRAM[15760] = 36'o200040043674; // 036620 SSRAM[15761] = 36'o251040040511; // 036621 SSRAM[15762] = 36'o260740040451; // 036622 SSRAM[15763] = 36'o036600043537; // 036623 SSRAM[15764] = 36'o255000000000; // 036624 SSRAM[15765] = 36'o200600040457; // 036625 SSRAM[15766] = 36'o623600400000; // 036626 SSRAM[15767] = 36'o036540043551; // 036627 SSRAM[15768] = 36'o255000000000; // 036630 SSRAM[15769] = 36'o200040043705; // 036631 SSRAM[15770] = 36'o251040040511; // 036632 SSRAM[15771] = 36'o260740040451; // 036633 SSRAM[15772] = 36'o036600043537; // 036634 SSRAM[15773] = 36'o255000000000; // 036635 SSRAM[15774] = 36'o200600040457; // 036636 SSRAM[15775] = 36'o623600400000; // 036637 SSRAM[15776] = 36'o036540043551; // 036640 SSRAM[15777] = 36'o255000000000; // 036641 SSRAM[15778] = 36'o200040043716; // 036642 SSRAM[15779] = 36'o251040040511; // 036643 SSRAM[15780] = 36'o260740040451; // 036644 SSRAM[15781] = 36'o036600043537; // 036645 SSRAM[15782] = 36'o255000000000; // 036646 SSRAM[15783] = 36'o200600040457; // 036647 SSRAM[15784] = 36'o623600400000; // 036650 SSRAM[15785] = 36'o036540043551; // 036651 SSRAM[15786] = 36'o255000000000; // 036652 SSRAM[15787] = 36'o200040043727; // 036653 SSRAM[15788] = 36'o251040040511; // 036654 SSRAM[15789] = 36'o260740040451; // 036655 SSRAM[15790] = 36'o036600043537; // 036656 SSRAM[15791] = 36'o255000000000; // 036657 SSRAM[15792] = 36'o200600040457; // 036660 SSRAM[15793] = 36'o623600400000; // 036661 SSRAM[15794] = 36'o036540043551; // 036662 SSRAM[15795] = 36'o255000000000; // 036663 SSRAM[15796] = 36'o200040043740; // 036664 SSRAM[15797] = 36'o251040040511; // 036665 SSRAM[15798] = 36'o260740040451; // 036666 SSRAM[15799] = 36'o036600043537; // 036667 SSRAM[15800] = 36'o255000000000; // 036670 SSRAM[15801] = 36'o200600040457; // 036671 SSRAM[15802] = 36'o623600400000; // 036672 SSRAM[15803] = 36'o036540043551; // 036673 SSRAM[15804] = 36'o255000000000; // 036674 SSRAM[15805] = 36'o200040043751; // 036675 SSRAM[15806] = 36'o251040040511; // 036676 SSRAM[15807] = 36'o260740040451; // 036677 SSRAM[15808] = 36'o036600043537; // 036700 SSRAM[15809] = 36'o255000000000; // 036701 SSRAM[15810] = 36'o200600040457; // 036702 SSRAM[15811] = 36'o623600400000; // 036703 SSRAM[15812] = 36'o036540043551; // 036704 SSRAM[15813] = 36'o255000000000; // 036705 SSRAM[15814] = 36'o200040043762; // 036706 SSRAM[15815] = 36'o251040040511; // 036707 SSRAM[15816] = 36'o260740040451; // 036710 SSRAM[15817] = 36'o036600043537; // 036711 SSRAM[15818] = 36'o255000000000; // 036712 SSRAM[15819] = 36'o200600040457; // 036713 SSRAM[15820] = 36'o623600400000; // 036714 SSRAM[15821] = 36'o036540043551; // 036715 SSRAM[15822] = 36'o255000000000; // 036716 SSRAM[15823] = 36'o200040043773; // 036717 SSRAM[15824] = 36'o251040040511; // 036720 SSRAM[15825] = 36'o260740040451; // 036721 SSRAM[15826] = 36'o036600043537; // 036722 SSRAM[15827] = 36'o255000000000; // 036723 SSRAM[15828] = 36'o200600040457; // 036724 SSRAM[15829] = 36'o623600400000; // 036725 SSRAM[15830] = 36'o036540043551; // 036726 SSRAM[15831] = 36'o255000000000; // 036727 SSRAM[15832] = 36'o200040044004; // 036730 SSRAM[15833] = 36'o251040040511; // 036731 SSRAM[15834] = 36'o260740040451; // 036732 SSRAM[15835] = 36'o036600043537; // 036733 SSRAM[15836] = 36'o255000000000; // 036734 SSRAM[15837] = 36'o200600040457; // 036735 SSRAM[15838] = 36'o623600400000; // 036736 SSRAM[15839] = 36'o036540043551; // 036737 SSRAM[15840] = 36'o255000000000; // 036740 SSRAM[15841] = 36'o200040044015; // 036741 SSRAM[15842] = 36'o251040040511; // 036742 SSRAM[15843] = 36'o260740040451; // 036743 SSRAM[15844] = 36'o036600043537; // 036744 SSRAM[15845] = 36'o255000000000; // 036745 SSRAM[15846] = 36'o200600040457; // 036746 SSRAM[15847] = 36'o623600400000; // 036747 SSRAM[15848] = 36'o036540043551; // 036750 SSRAM[15849] = 36'o255000000000; // 036751 SSRAM[15850] = 36'o200040044026; // 036752 SSRAM[15851] = 36'o251040040511; // 036753 SSRAM[15852] = 36'o260740040451; // 036754 SSRAM[15853] = 36'o036600043537; // 036755 SSRAM[15854] = 36'o255000000000; // 036756 SSRAM[15855] = 36'o200600040457; // 036757 SSRAM[15856] = 36'o623600400000; // 036760 SSRAM[15857] = 36'o036540043551; // 036761 SSRAM[15858] = 36'o255000000000; // 036762 SSRAM[15859] = 36'o200040044037; // 036763 SSRAM[15860] = 36'o251040040511; // 036764 SSRAM[15861] = 36'o260740040451; // 036765 SSRAM[15862] = 36'o036600043537; // 036766 SSRAM[15863] = 36'o255000000000; // 036767 SSRAM[15864] = 36'o200600040457; // 036770 SSRAM[15865] = 36'o623600400000; // 036771 SSRAM[15866] = 36'o036540043551; // 036772 SSRAM[15867] = 36'o255000000000; // 036773 SSRAM[15868] = 36'o200040044050; // 036774 SSRAM[15869] = 36'o251040040511; // 036775 SSRAM[15870] = 36'o260740040451; // 036776 SSRAM[15871] = 36'o036600043537; // 036777 SSRAM[15872] = 36'o255000000000; // 037000 SSRAM[15873] = 36'o200600040457; // 037001 SSRAM[15874] = 36'o623600400000; // 037002 SSRAM[15875] = 36'o036540043551; // 037003 SSRAM[15876] = 36'o255000000000; // 037004 SSRAM[15877] = 36'o200040044061; // 037005 SSRAM[15878] = 36'o251040040511; // 037006 SSRAM[15879] = 36'o260740040451; // 037007 SSRAM[15880] = 36'o036600043537; // 037010 SSRAM[15881] = 36'o255000000000; // 037011 SSRAM[15882] = 36'o200600040457; // 037012 SSRAM[15883] = 36'o623600400000; // 037013 SSRAM[15884] = 36'o036540043551; // 037014 SSRAM[15885] = 36'o255000000000; // 037015 SSRAM[15886] = 36'o200040044072; // 037016 SSRAM[15887] = 36'o251040040511; // 037017 SSRAM[15888] = 36'o260740040451; // 037020 SSRAM[15889] = 36'o036600043537; // 037021 SSRAM[15890] = 36'o255000000000; // 037022 SSRAM[15891] = 36'o200600040457; // 037023 SSRAM[15892] = 36'o623600400000; // 037024 SSRAM[15893] = 36'o036540043551; // 037025 SSRAM[15894] = 36'o255000000000; // 037026 SSRAM[15895] = 36'o200040044107; // 037027 SSRAM[15896] = 36'o251040040555; // 037030 SSRAM[15897] = 36'o260740040513; // 037031 SSRAM[15898] = 36'o036600044117; // 037032 SSRAM[15899] = 36'o255000000000; // 037033 SSRAM[15900] = 36'o200040044134; // 037034 SSRAM[15901] = 36'o251040040555; // 037035 SSRAM[15902] = 36'o260740040513; // 037036 SSRAM[15903] = 36'o036600044117; // 037037 SSRAM[15904] = 36'o255000000000; // 037040 SSRAM[15905] = 36'o200040044147; // 037041 SSRAM[15906] = 36'o251040040555; // 037042 SSRAM[15907] = 36'o260740040513; // 037043 SSRAM[15908] = 36'o036600044157; // 037044 SSRAM[15909] = 36'o255000000000; // 037045 SSRAM[15910] = 36'o200040044174; // 037046 SSRAM[15911] = 36'o251040040555; // 037047 SSRAM[15912] = 36'o260740040513; // 037050 SSRAM[15913] = 36'o036600044157; // 037051 SSRAM[15914] = 36'o255000000000; // 037052 SSRAM[15915] = 36'o200040044207; // 037053 SSRAM[15916] = 36'o251040040555; // 037054 SSRAM[15917] = 36'o260740040513; // 037055 SSRAM[15918] = 36'o036600044217; // 037056 SSRAM[15919] = 36'o255000000000; // 037057 SSRAM[15920] = 36'o200040044234; // 037060 SSRAM[15921] = 36'o251040040555; // 037061 SSRAM[15922] = 36'o260740040513; // 037062 SSRAM[15923] = 36'o036600044217; // 037063 SSRAM[15924] = 36'o255000000000; // 037064 SSRAM[15925] = 36'o200040044247; // 037065 SSRAM[15926] = 36'o251040040555; // 037066 SSRAM[15927] = 36'o260740040513; // 037067 SSRAM[15928] = 36'o036600044217; // 037070 SSRAM[15929] = 36'o255000000000; // 037071 SSRAM[15930] = 36'o200040044262; // 037072 SSRAM[15931] = 36'o251040040555; // 037073 SSRAM[15932] = 36'o260740040513; // 037074 SSRAM[15933] = 36'o036600044217; // 037075 SSRAM[15934] = 36'o255000000000; // 037076 SSRAM[15935] = 36'o200040044275; // 037077 SSRAM[15936] = 36'o251040040555; // 037100 SSRAM[15937] = 36'o260740040513; // 037101 SSRAM[15938] = 36'o036600044217; // 037102 SSRAM[15939] = 36'o255000000000; // 037103 SSRAM[15940] = 36'o200040044310; // 037104 SSRAM[15941] = 36'o251040040555; // 037105 SSRAM[15942] = 36'o260740040513; // 037106 SSRAM[15943] = 36'o036600044217; // 037107 SSRAM[15944] = 36'o255000000000; // 037110 SSRAM[15945] = 36'o200040044323; // 037111 SSRAM[15946] = 36'o251040040555; // 037112 SSRAM[15947] = 36'o260740040513; // 037113 SSRAM[15948] = 36'o036600044217; // 037114 SSRAM[15949] = 36'o255000000000; // 037115 SSRAM[15950] = 36'o200040044336; // 037116 SSRAM[15951] = 36'o251040040555; // 037117 SSRAM[15952] = 36'o260740040513; // 037120 SSRAM[15953] = 36'o036600044217; // 037121 SSRAM[15954] = 36'o255000000000; // 037122 SSRAM[15955] = 36'o200040044351; // 037123 SSRAM[15956] = 36'o251040040555; // 037124 SSRAM[15957] = 36'o260740040513; // 037125 SSRAM[15958] = 36'o036600044217; // 037126 SSRAM[15959] = 36'o255000000000; // 037127 SSRAM[15960] = 36'o200040044364; // 037130 SSRAM[15961] = 36'o251040040555; // 037131 SSRAM[15962] = 36'o260740040513; // 037132 SSRAM[15963] = 36'o036600044217; // 037133 SSRAM[15964] = 36'o255000000000; // 037134 SSRAM[15965] = 36'o200040044377; // 037135 SSRAM[15966] = 36'o251040040555; // 037136 SSRAM[15967] = 36'o260740040513; // 037137 SSRAM[15968] = 36'o036600044217; // 037140 SSRAM[15969] = 36'o255000000000; // 037141 SSRAM[15970] = 36'o200040044412; // 037142 SSRAM[15971] = 36'o251040040555; // 037143 SSRAM[15972] = 36'o260740040513; // 037144 SSRAM[15973] = 36'o036600044217; // 037145 SSRAM[15974] = 36'o255000000000; // 037146 SSRAM[15975] = 36'o200040044425; // 037147 SSRAM[15976] = 36'o251040040555; // 037150 SSRAM[15977] = 36'o260740040513; // 037151 SSRAM[15978] = 36'o036600044217; // 037152 SSRAM[15979] = 36'o255000000000; // 037153 SSRAM[15980] = 36'o200040044440; // 037154 SSRAM[15981] = 36'o251040040555; // 037155 SSRAM[15982] = 36'o260740040513; // 037156 SSRAM[15983] = 36'o036600044217; // 037157 SSRAM[15984] = 36'o255000000000; // 037160 SSRAM[15985] = 36'o200040044453; // 037161 SSRAM[15986] = 36'o251040040555; // 037162 SSRAM[15987] = 36'o260740040513; // 037163 SSRAM[15988] = 36'o036600044217; // 037164 SSRAM[15989] = 36'o255000000000; // 037165 SSRAM[15990] = 36'o200040044466; // 037166 SSRAM[15991] = 36'o251040040555; // 037167 SSRAM[15992] = 36'o260740040513; // 037170 SSRAM[15993] = 36'o036600044217; // 037171 SSRAM[15994] = 36'o255000000000; // 037172 SSRAM[15995] = 36'o200040044501; // 037173 SSRAM[15996] = 36'o251040040555; // 037174 SSRAM[15997] = 36'o260740040513; // 037175 SSRAM[15998] = 36'o036600044217; // 037176 SSRAM[15999] = 36'o255000000000; // 037177 SSRAM[16000] = 36'o200040044514; // 037200 SSRAM[16001] = 36'o251040040555; // 037201 SSRAM[16002] = 36'o260740040513; // 037202 SSRAM[16003] = 36'o036600044217; // 037203 SSRAM[16004] = 36'o255000000000; // 037204 SSRAM[16005] = 36'o200040044527; // 037205 SSRAM[16006] = 36'o251040040555; // 037206 SSRAM[16007] = 36'o260740040513; // 037207 SSRAM[16008] = 36'o036600044217; // 037210 SSRAM[16009] = 36'o255000000000; // 037211 SSRAM[16010] = 36'o200040044542; // 037212 SSRAM[16011] = 36'o251040040555; // 037213 SSRAM[16012] = 36'o260740040513; // 037214 SSRAM[16013] = 36'o036600044217; // 037215 SSRAM[16014] = 36'o255000000000; // 037216 SSRAM[16015] = 36'o200040044555; // 037217 SSRAM[16016] = 36'o251040040555; // 037220 SSRAM[16017] = 36'o260740040513; // 037221 SSRAM[16018] = 36'o036600044217; // 037222 SSRAM[16019] = 36'o255000000000; // 037223 SSRAM[16020] = 36'o200040044570; // 037224 SSRAM[16021] = 36'o251040040555; // 037225 SSRAM[16022] = 36'o260740040513; // 037226 SSRAM[16023] = 36'o036600044217; // 037227 SSRAM[16024] = 36'o255000000000; // 037230 SSRAM[16025] = 36'o200040044603; // 037231 SSRAM[16026] = 36'o251040040555; // 037232 SSRAM[16027] = 36'o260740040513; // 037233 SSRAM[16028] = 36'o036600044217; // 037234 SSRAM[16029] = 36'o255000000000; // 037235 SSRAM[16030] = 36'o200040044616; // 037236 SSRAM[16031] = 36'o251040040555; // 037237 SSRAM[16032] = 36'o260740040513; // 037240 SSRAM[16033] = 36'o036600044217; // 037241 SSRAM[16034] = 36'o255000000000; // 037242 SSRAM[16035] = 36'o200040044631; // 037243 SSRAM[16036] = 36'o251040040555; // 037244 SSRAM[16037] = 36'o260740040513; // 037245 SSRAM[16038] = 36'o036600044641; // 037246 SSRAM[16039] = 36'o255000000000; // 037247 SSRAM[16040] = 36'o200600040521; // 037250 SSRAM[16041] = 36'o623600400040; // 037251 SSRAM[16042] = 36'o036540044653; // 037252 SSRAM[16043] = 36'o255000000000; // 037253 SSRAM[16044] = 36'o200040044670; // 037254 SSRAM[16045] = 36'o251040040555; // 037255 SSRAM[16046] = 36'o260740040513; // 037256 SSRAM[16047] = 36'o036600044641; // 037257 SSRAM[16048] = 36'o255000000000; // 037260 SSRAM[16049] = 36'o200600040521; // 037261 SSRAM[16050] = 36'o623600400040; // 037262 SSRAM[16051] = 36'o036540044653; // 037263 SSRAM[16052] = 36'o255000000000; // 037264 SSRAM[16053] = 36'o200040044703; // 037265 SSRAM[16054] = 36'o251040040555; // 037266 SSRAM[16055] = 36'o260740040513; // 037267 SSRAM[16056] = 36'o036600044641; // 037270 SSRAM[16057] = 36'o255000000000; // 037271 SSRAM[16058] = 36'o200600040521; // 037272 SSRAM[16059] = 36'o623600400040; // 037273 SSRAM[16060] = 36'o036540044653; // 037274 SSRAM[16061] = 36'o255000000000; // 037275 SSRAM[16062] = 36'o200040044716; // 037276 SSRAM[16063] = 36'o251040040555; // 037277 SSRAM[16064] = 36'o260740040513; // 037300 SSRAM[16065] = 36'o036600044641; // 037301 SSRAM[16066] = 36'o255000000000; // 037302 SSRAM[16067] = 36'o200600040521; // 037303 SSRAM[16068] = 36'o623600400040; // 037304 SSRAM[16069] = 36'o036540044653; // 037305 SSRAM[16070] = 36'o255000000000; // 037306 SSRAM[16071] = 36'o200040044731; // 037307 SSRAM[16072] = 36'o251040040555; // 037310 SSRAM[16073] = 36'o260740040513; // 037311 SSRAM[16074] = 36'o036600044641; // 037312 SSRAM[16075] = 36'o255000000000; // 037313 SSRAM[16076] = 36'o200600040521; // 037314 SSRAM[16077] = 36'o623600400040; // 037315 SSRAM[16078] = 36'o036540044653; // 037316 SSRAM[16079] = 36'o255000000000; // 037317 SSRAM[16080] = 36'o200040044744; // 037320 SSRAM[16081] = 36'o251040040555; // 037321 SSRAM[16082] = 36'o260740040513; // 037322 SSRAM[16083] = 36'o036600044641; // 037323 SSRAM[16084] = 36'o255000000000; // 037324 SSRAM[16085] = 36'o200600040521; // 037325 SSRAM[16086] = 36'o623600400040; // 037326 SSRAM[16087] = 36'o036540044653; // 037327 SSRAM[16088] = 36'o255000000000; // 037330 SSRAM[16089] = 36'o200040044757; // 037331 SSRAM[16090] = 36'o251040040555; // 037332 SSRAM[16091] = 36'o260740040513; // 037333 SSRAM[16092] = 36'o036600044641; // 037334 SSRAM[16093] = 36'o255000000000; // 037335 SSRAM[16094] = 36'o200600040521; // 037336 SSRAM[16095] = 36'o623600400040; // 037337 SSRAM[16096] = 36'o036540044653; // 037340 SSRAM[16097] = 36'o255000000000; // 037341 SSRAM[16098] = 36'o200040044772; // 037342 SSRAM[16099] = 36'o251040040555; // 037343 SSRAM[16100] = 36'o260740040513; // 037344 SSRAM[16101] = 36'o036600044641; // 037345 SSRAM[16102] = 36'o255000000000; // 037346 SSRAM[16103] = 36'o200600040521; // 037347 SSRAM[16104] = 36'o623600400040; // 037350 SSRAM[16105] = 36'o036540044653; // 037351 SSRAM[16106] = 36'o255000000000; // 037352 SSRAM[16107] = 36'o200040045005; // 037353 SSRAM[16108] = 36'o251040040555; // 037354 SSRAM[16109] = 36'o260740040513; // 037355 SSRAM[16110] = 36'o036600044641; // 037356 SSRAM[16111] = 36'o255000000000; // 037357 SSRAM[16112] = 36'o200600040521; // 037360 SSRAM[16113] = 36'o623600400040; // 037361 SSRAM[16114] = 36'o036540044653; // 037362 SSRAM[16115] = 36'o255000000000; // 037363 SSRAM[16116] = 36'o200040045020; // 037364 SSRAM[16117] = 36'o251040040555; // 037365 SSRAM[16118] = 36'o260740040513; // 037366 SSRAM[16119] = 36'o036600044641; // 037367 SSRAM[16120] = 36'o255000000000; // 037370 SSRAM[16121] = 36'o200600040521; // 037371 SSRAM[16122] = 36'o623600400040; // 037372 SSRAM[16123] = 36'o036540044653; // 037373 SSRAM[16124] = 36'o255000000000; // 037374 SSRAM[16125] = 36'o200040045033; // 037375 SSRAM[16126] = 36'o251040040555; // 037376 SSRAM[16127] = 36'o260740040513; // 037377 SSRAM[16128] = 36'o036600044641; // 037400 SSRAM[16129] = 36'o255000000000; // 037401 SSRAM[16130] = 36'o200600040521; // 037402 SSRAM[16131] = 36'o623600400040; // 037403 SSRAM[16132] = 36'o036540044653; // 037404 SSRAM[16133] = 36'o255000000000; // 037405 SSRAM[16134] = 36'o200040045046; // 037406 SSRAM[16135] = 36'o251040040555; // 037407 SSRAM[16136] = 36'o260740040513; // 037410 SSRAM[16137] = 36'o036600045056; // 037411 SSRAM[16138] = 36'o255000000000; // 037412 SSRAM[16139] = 36'o200600040521; // 037413 SSRAM[16140] = 36'o623600400040; // 037414 SSRAM[16141] = 36'o036540045070; // 037415 SSRAM[16142] = 36'o255000000000; // 037416 SSRAM[16143] = 36'o200040045105; // 037417 SSRAM[16144] = 36'o251040040555; // 037420 SSRAM[16145] = 36'o260740040513; // 037421 SSRAM[16146] = 36'o036600045056; // 037422 SSRAM[16147] = 36'o255000000000; // 037423 SSRAM[16148] = 36'o200600040521; // 037424 SSRAM[16149] = 36'o623600400040; // 037425 SSRAM[16150] = 36'o036540045070; // 037426 SSRAM[16151] = 36'o255000000000; // 037427 SSRAM[16152] = 36'o200040045120; // 037430 SSRAM[16153] = 36'o251040040555; // 037431 SSRAM[16154] = 36'o260740040513; // 037432 SSRAM[16155] = 36'o036600045056; // 037433 SSRAM[16156] = 36'o255000000000; // 037434 SSRAM[16157] = 36'o200600040521; // 037435 SSRAM[16158] = 36'o623600400040; // 037436 SSRAM[16159] = 36'o036540045070; // 037437 SSRAM[16160] = 36'o255000000000; // 037440 SSRAM[16161] = 36'o200040045133; // 037441 SSRAM[16162] = 36'o251040040555; // 037442 SSRAM[16163] = 36'o260740040513; // 037443 SSRAM[16164] = 36'o036600045056; // 037444 SSRAM[16165] = 36'o255000000000; // 037445 SSRAM[16166] = 36'o200600040521; // 037446 SSRAM[16167] = 36'o623600400040; // 037447 SSRAM[16168] = 36'o036540045070; // 037450 SSRAM[16169] = 36'o255000000000; // 037451 SSRAM[16170] = 36'o200040045146; // 037452 SSRAM[16171] = 36'o251040040555; // 037453 SSRAM[16172] = 36'o260740040513; // 037454 SSRAM[16173] = 36'o036600045056; // 037455 SSRAM[16174] = 36'o255000000000; // 037456 SSRAM[16175] = 36'o200600040521; // 037457 SSRAM[16176] = 36'o623600400040; // 037460 SSRAM[16177] = 36'o036540045070; // 037461 SSRAM[16178] = 36'o255000000000; // 037462 SSRAM[16179] = 36'o200040045161; // 037463 SSRAM[16180] = 36'o251040040555; // 037464 SSRAM[16181] = 36'o260740040513; // 037465 SSRAM[16182] = 36'o036600045056; // 037466 SSRAM[16183] = 36'o255000000000; // 037467 SSRAM[16184] = 36'o200600040521; // 037470 SSRAM[16185] = 36'o623600400040; // 037471 SSRAM[16186] = 36'o036540045070; // 037472 SSRAM[16187] = 36'o255000000000; // 037473 SSRAM[16188] = 36'o200040045174; // 037474 SSRAM[16189] = 36'o251040040555; // 037475 SSRAM[16190] = 36'o260740040513; // 037476 SSRAM[16191] = 36'o036600045056; // 037477 SSRAM[16192] = 36'o255000000000; // 037500 SSRAM[16193] = 36'o200600040521; // 037501 SSRAM[16194] = 36'o623600400040; // 037502 SSRAM[16195] = 36'o036540045070; // 037503 SSRAM[16196] = 36'o255000000000; // 037504 SSRAM[16197] = 36'o200040045207; // 037505 SSRAM[16198] = 36'o251040040555; // 037506 SSRAM[16199] = 36'o260740040513; // 037507 SSRAM[16200] = 36'o036600045056; // 037510 SSRAM[16201] = 36'o255000000000; // 037511 SSRAM[16202] = 36'o200600040521; // 037512 SSRAM[16203] = 36'o623600400040; // 037513 SSRAM[16204] = 36'o036540045070; // 037514 SSRAM[16205] = 36'o255000000000; // 037515 SSRAM[16206] = 36'o200040045222; // 037516 SSRAM[16207] = 36'o251040040555; // 037517 SSRAM[16208] = 36'o260740040513; // 037520 SSRAM[16209] = 36'o036600045056; // 037521 SSRAM[16210] = 36'o255000000000; // 037522 SSRAM[16211] = 36'o200600040521; // 037523 SSRAM[16212] = 36'o623600400040; // 037524 SSRAM[16213] = 36'o036540045070; // 037525 SSRAM[16214] = 36'o255000000000; // 037526 SSRAM[16215] = 36'o200040045235; // 037527 SSRAM[16216] = 36'o251040040555; // 037530 SSRAM[16217] = 36'o260740040513; // 037531 SSRAM[16218] = 36'o036600045056; // 037532 SSRAM[16219] = 36'o255000000000; // 037533 SSRAM[16220] = 36'o200600040521; // 037534 SSRAM[16221] = 36'o623600400040; // 037535 SSRAM[16222] = 36'o036540045070; // 037536 SSRAM[16223] = 36'o255000000000; // 037537 SSRAM[16224] = 36'o200040045250; // 037540 SSRAM[16225] = 36'o251040040555; // 037541 SSRAM[16226] = 36'o260740040513; // 037542 SSRAM[16227] = 36'o036600045056; // 037543 SSRAM[16228] = 36'o255000000000; // 037544 SSRAM[16229] = 36'o200600040521; // 037545 SSRAM[16230] = 36'o623600400040; // 037546 SSRAM[16231] = 36'o036540045070; // 037547 SSRAM[16232] = 36'o255000000000; // 037550 SSRAM[16233] = 36'o200040045263; // 037551 SSRAM[16234] = 36'o251040040555; // 037552 SSRAM[16235] = 36'o260740040513; // 037553 SSRAM[16236] = 36'o036600045056; // 037554 SSRAM[16237] = 36'o255000000000; // 037555 SSRAM[16238] = 36'o200600040521; // 037556 SSRAM[16239] = 36'o623600400040; // 037557 SSRAM[16240] = 36'o036540045070; // 037560 SSRAM[16241] = 36'o255000000000; // 037561 SSRAM[16242] = 36'o200040045276; // 037562 SSRAM[16243] = 36'o251040040555; // 037563 SSRAM[16244] = 36'o260740040513; // 037564 SSRAM[16245] = 36'o036600045056; // 037565 SSRAM[16246] = 36'o255000000000; // 037566 SSRAM[16247] = 36'o200600040521; // 037567 SSRAM[16248] = 36'o623600400040; // 037570 SSRAM[16249] = 36'o036540045070; // 037571 SSRAM[16250] = 36'o255000000000; // 037572 SSRAM[16251] = 36'o200040045311; // 037573 SSRAM[16252] = 36'o251040040555; // 037574 SSRAM[16253] = 36'o260740040513; // 037575 SSRAM[16254] = 36'o036600045056; // 037576 SSRAM[16255] = 36'o255000000000; // 037577 SSRAM[16256] = 36'o200600040521; // 037600 SSRAM[16257] = 36'o623600400040; // 037601 SSRAM[16258] = 36'o036540045070; // 037602 SSRAM[16259] = 36'o255000000000; // 037603 SSRAM[16260] = 36'o200040045324; // 037604 SSRAM[16261] = 36'o251040040555; // 037605 SSRAM[16262] = 36'o260740040513; // 037606 SSRAM[16263] = 36'o036600045056; // 037607 SSRAM[16264] = 36'o255000000000; // 037610 SSRAM[16265] = 36'o200600040521; // 037611 SSRAM[16266] = 36'o623600400040; // 037612 SSRAM[16267] = 36'o036540045070; // 037613 SSRAM[16268] = 36'o255000000000; // 037614 SSRAM[16269] = 36'o200040045337; // 037615 SSRAM[16270] = 36'o251040040555; // 037616 SSRAM[16271] = 36'o260740040513; // 037617 SSRAM[16272] = 36'o036600045056; // 037620 SSRAM[16273] = 36'o255000000000; // 037621 SSRAM[16274] = 36'o200600040521; // 037622 SSRAM[16275] = 36'o623600400040; // 037623 SSRAM[16276] = 36'o036540045070; // 037624 SSRAM[16277] = 36'o255000000000; // 037625 SSRAM[16278] = 36'o200040045352; // 037626 SSRAM[16279] = 36'o251040040555; // 037627 SSRAM[16280] = 36'o260740040513; // 037630 SSRAM[16281] = 36'o036600045362; // 037631 SSRAM[16282] = 36'o255000000000; // 037632 SSRAM[16283] = 36'o200600040521; // 037633 SSRAM[16284] = 36'o623600400040; // 037634 SSRAM[16285] = 36'o036540045374; // 037635 SSRAM[16286] = 36'o255000000000; // 037636 SSRAM[16287] = 36'o200040045411; // 037637 SSRAM[16288] = 36'o251040040555; // 037640 SSRAM[16289] = 36'o260740040513; // 037641 SSRAM[16290] = 36'o036600045362; // 037642 SSRAM[16291] = 36'o255000000000; // 037643 SSRAM[16292] = 36'o200600040521; // 037644 SSRAM[16293] = 36'o623600400040; // 037645 SSRAM[16294] = 36'o036540045374; // 037646 SSRAM[16295] = 36'o255000000000; // 037647 SSRAM[16296] = 36'o200040045424; // 037650 SSRAM[16297] = 36'o251040040555; // 037651 SSRAM[16298] = 36'o260740040513; // 037652 SSRAM[16299] = 36'o036600045362; // 037653 SSRAM[16300] = 36'o255000000000; // 037654 SSRAM[16301] = 36'o200600040521; // 037655 SSRAM[16302] = 36'o623600400040; // 037656 SSRAM[16303] = 36'o036540045374; // 037657 SSRAM[16304] = 36'o255000000000; // 037660 SSRAM[16305] = 36'o200040045437; // 037661 SSRAM[16306] = 36'o251040040555; // 037662 SSRAM[16307] = 36'o260740040513; // 037663 SSRAM[16308] = 36'o036600045362; // 037664 SSRAM[16309] = 36'o255000000000; // 037665 SSRAM[16310] = 36'o200600040521; // 037666 SSRAM[16311] = 36'o623600400040; // 037667 SSRAM[16312] = 36'o036540045374; // 037670 SSRAM[16313] = 36'o255000000000; // 037671 SSRAM[16314] = 36'o200040045452; // 037672 SSRAM[16315] = 36'o251040040555; // 037673 SSRAM[16316] = 36'o260740040513; // 037674 SSRAM[16317] = 36'o036600045362; // 037675 SSRAM[16318] = 36'o255000000000; // 037676 SSRAM[16319] = 36'o200600040521; // 037677 SSRAM[16320] = 36'o623600400040; // 037700 SSRAM[16321] = 36'o036540045374; // 037701 SSRAM[16322] = 36'o255000000000; // 037702 SSRAM[16323] = 36'o200040045465; // 037703 SSRAM[16324] = 36'o251040040555; // 037704 SSRAM[16325] = 36'o260740040513; // 037705 SSRAM[16326] = 36'o036600045362; // 037706 SSRAM[16327] = 36'o255000000000; // 037707 SSRAM[16328] = 36'o200600040521; // 037710 SSRAM[16329] = 36'o623600400040; // 037711 SSRAM[16330] = 36'o036540045374; // 037712 SSRAM[16331] = 36'o255000000000; // 037713 SSRAM[16332] = 36'o200040045500; // 037714 SSRAM[16333] = 36'o251040040555; // 037715 SSRAM[16334] = 36'o260740040513; // 037716 SSRAM[16335] = 36'o036600045362; // 037717 SSRAM[16336] = 36'o255000000000; // 037720 SSRAM[16337] = 36'o200600040521; // 037721 SSRAM[16338] = 36'o623600400040; // 037722 SSRAM[16339] = 36'o036540045374; // 037723 SSRAM[16340] = 36'o255000000000; // 037724 SSRAM[16341] = 36'o200040045513; // 037725 SSRAM[16342] = 36'o251040040555; // 037726 SSRAM[16343] = 36'o260740040513; // 037727 SSRAM[16344] = 36'o036600045362; // 037730 SSRAM[16345] = 36'o255000000000; // 037731 SSRAM[16346] = 36'o200600040521; // 037732 SSRAM[16347] = 36'o623600400040; // 037733 SSRAM[16348] = 36'o036540045374; // 037734 SSRAM[16349] = 36'o255000000000; // 037735 SSRAM[16350] = 36'o200040045522; // 037736 SSRAM[16351] = 36'o251040040635; // 037737 SSRAM[16352] = 36'o260740040557; // 037740 SSRAM[16353] = 36'o036600045532; // 037741 SSRAM[16354] = 36'o255000000000; // 037742 SSRAM[16355] = 36'o200600040567; // 037743 SSRAM[16356] = 36'o434600045535; // 037744 SSRAM[16357] = 36'o312600040567; // 037745 SSRAM[16358] = 36'o036540045545; // 037746 SSRAM[16359] = 36'o255000000000; // 037747 SSRAM[16360] = 36'o200040045556; // 037750 SSRAM[16361] = 36'o251040040635; // 037751 SSRAM[16362] = 36'o260740040557; // 037752 SSRAM[16363] = 36'o036600045532; // 037753 SSRAM[16364] = 36'o255000000000; // 037754 SSRAM[16365] = 36'o200600040567; // 037755 SSRAM[16366] = 36'o434600045535; // 037756 SSRAM[16367] = 36'o312600040567; // 037757 SSRAM[16368] = 36'o036540045545; // 037760 SSRAM[16369] = 36'o255000000000; // 037761 SSRAM[16370] = 36'o200040045565; // 037762 SSRAM[16371] = 36'o251040040635; // 037763 SSRAM[16372] = 36'o260740040557; // 037764 SSRAM[16373] = 36'o036600045532; // 037765 SSRAM[16374] = 36'o255000000000; // 037766 SSRAM[16375] = 36'o200600040567; // 037767 SSRAM[16376] = 36'o434600045535; // 037770 SSRAM[16377] = 36'o312600040567; // 037771 SSRAM[16378] = 36'o036540045545; // 037772 SSRAM[16379] = 36'o255000000000; // 037773 SSRAM[16380] = 36'o200040045574; // 037774 SSRAM[16381] = 36'o251040040635; // 037775 SSRAM[16382] = 36'o260740040557; // 037776 SSRAM[16383] = 36'o036600045532; // 037777 SSRAM[16384] = 36'o255000000000; // 040000 SSRAM[16385] = 36'o200600040567; // 040001 SSRAM[16386] = 36'o434600045535; // 040002 SSRAM[16387] = 36'o312600040567; // 040003 SSRAM[16388] = 36'o036540045545; // 040004 SSRAM[16389] = 36'o255000000000; // 040005 SSRAM[16390] = 36'o200040045603; // 040006 SSRAM[16391] = 36'o251040040635; // 040007 SSRAM[16392] = 36'o260740040557; // 040010 SSRAM[16393] = 36'o036600045532; // 040011 SSRAM[16394] = 36'o255000000000; // 040012 SSRAM[16395] = 36'o200600040567; // 040013 SSRAM[16396] = 36'o434600045535; // 040014 SSRAM[16397] = 36'o312600040567; // 040015 SSRAM[16398] = 36'o036540045545; // 040016 SSRAM[16399] = 36'o255000000000; // 040017 SSRAM[16400] = 36'o200040045612; // 040020 SSRAM[16401] = 36'o251040040635; // 040021 SSRAM[16402] = 36'o260740040557; // 040022 SSRAM[16403] = 36'o036600045532; // 040023 SSRAM[16404] = 36'o255000000000; // 040024 SSRAM[16405] = 36'o200600040567; // 040025 SSRAM[16406] = 36'o434600045535; // 040026 SSRAM[16407] = 36'o312600040567; // 040027 SSRAM[16408] = 36'o036540045545; // 040030 SSRAM[16409] = 36'o255000000000; // 040031 SSRAM[16410] = 36'o200040045621; // 040032 SSRAM[16411] = 36'o251040040635; // 040033 SSRAM[16412] = 36'o260740040557; // 040034 SSRAM[16413] = 36'o036600045532; // 040035 SSRAM[16414] = 36'o255000000000; // 040036 SSRAM[16415] = 36'o200600040567; // 040037 SSRAM[16416] = 36'o434600045535; // 040040 SSRAM[16417] = 36'o312600040567; // 040041 SSRAM[16418] = 36'o036540045545; // 040042 SSRAM[16419] = 36'o255000000000; // 040043 SSRAM[16420] = 36'o200040045630; // 040044 SSRAM[16421] = 36'o251040040635; // 040045 SSRAM[16422] = 36'o260740040557; // 040046 SSRAM[16423] = 36'o036600045532; // 040047 SSRAM[16424] = 36'o255000000000; // 040050 SSRAM[16425] = 36'o200600040567; // 040051 SSRAM[16426] = 36'o434600045535; // 040052 SSRAM[16427] = 36'o312600040567; // 040053 SSRAM[16428] = 36'o036540045545; // 040054 SSRAM[16429] = 36'o255000000000; // 040055 SSRAM[16430] = 36'o200040045637; // 040056 SSRAM[16431] = 36'o251040040635; // 040057 SSRAM[16432] = 36'o260740040557; // 040060 SSRAM[16433] = 36'o036600045532; // 040061 SSRAM[16434] = 36'o255000000000; // 040062 SSRAM[16435] = 36'o200600040567; // 040063 SSRAM[16436] = 36'o434600045535; // 040064 SSRAM[16437] = 36'o312600040567; // 040065 SSRAM[16438] = 36'o036540045545; // 040066 SSRAM[16439] = 36'o255000000000; // 040067 SSRAM[16440] = 36'o200040045646; // 040070 SSRAM[16441] = 36'o251040040635; // 040071 SSRAM[16442] = 36'o260740040557; // 040072 SSRAM[16443] = 36'o036600045532; // 040073 SSRAM[16444] = 36'o255000000000; // 040074 SSRAM[16445] = 36'o200600040567; // 040075 SSRAM[16446] = 36'o434600045535; // 040076 SSRAM[16447] = 36'o312600040567; // 040077 SSRAM[16448] = 36'o036540045545; // 040100 SSRAM[16449] = 36'o255000000000; // 040101 SSRAM[16450] = 36'o200040045655; // 040102 SSRAM[16451] = 36'o251040040635; // 040103 SSRAM[16452] = 36'o260740040557; // 040104 SSRAM[16453] = 36'o036600045532; // 040105 SSRAM[16454] = 36'o255000000000; // 040106 SSRAM[16455] = 36'o200600040567; // 040107 SSRAM[16456] = 36'o434600045535; // 040110 SSRAM[16457] = 36'o312600040567; // 040111 SSRAM[16458] = 36'o036540045545; // 040112 SSRAM[16459] = 36'o255000000000; // 040113 SSRAM[16460] = 36'o200040045664; // 040114 SSRAM[16461] = 36'o251040040635; // 040115 SSRAM[16462] = 36'o260740040557; // 040116 SSRAM[16463] = 36'o036600045532; // 040117 SSRAM[16464] = 36'o255000000000; // 040120 SSRAM[16465] = 36'o200600040567; // 040121 SSRAM[16466] = 36'o434600045535; // 040122 SSRAM[16467] = 36'o312600040567; // 040123 SSRAM[16468] = 36'o036540045545; // 040124 SSRAM[16469] = 36'o255000000000; // 040125 SSRAM[16470] = 36'o200040045673; // 040126 SSRAM[16471] = 36'o251040040635; // 040127 SSRAM[16472] = 36'o260740040557; // 040130 SSRAM[16473] = 36'o036600045532; // 040131 SSRAM[16474] = 36'o255000000000; // 040132 SSRAM[16475] = 36'o200600040567; // 040133 SSRAM[16476] = 36'o434600045535; // 040134 SSRAM[16477] = 36'o312600040567; // 040135 SSRAM[16478] = 36'o036540045545; // 040136 SSRAM[16479] = 36'o255000000000; // 040137 SSRAM[16480] = 36'o200040045702; // 040140 SSRAM[16481] = 36'o251040040635; // 040141 SSRAM[16482] = 36'o260740040557; // 040142 SSRAM[16483] = 36'o036600045532; // 040143 SSRAM[16484] = 36'o255000000000; // 040144 SSRAM[16485] = 36'o200600040567; // 040145 SSRAM[16486] = 36'o434600045535; // 040146 SSRAM[16487] = 36'o312600040567; // 040147 SSRAM[16488] = 36'o036540045545; // 040150 SSRAM[16489] = 36'o255000000000; // 040151 SSRAM[16490] = 36'o200040045711; // 040152 SSRAM[16491] = 36'o251040040635; // 040153 SSRAM[16492] = 36'o260740040557; // 040154 SSRAM[16493] = 36'o036600045532; // 040155 SSRAM[16494] = 36'o255000000000; // 040156 SSRAM[16495] = 36'o200600040567; // 040157 SSRAM[16496] = 36'o434600045535; // 040160 SSRAM[16497] = 36'o312600040567; // 040161 SSRAM[16498] = 36'o036540045545; // 040162 SSRAM[16499] = 36'o255000000000; // 040163 SSRAM[16500] = 36'o200040045720; // 040164 SSRAM[16501] = 36'o251040040635; // 040165 SSRAM[16502] = 36'o260740040557; // 040166 SSRAM[16503] = 36'o036600045532; // 040167 SSRAM[16504] = 36'o255000000000; // 040170 SSRAM[16505] = 36'o200600040567; // 040171 SSRAM[16506] = 36'o434600045535; // 040172 SSRAM[16507] = 36'o312600040567; // 040173 SSRAM[16508] = 36'o036540045545; // 040174 SSRAM[16509] = 36'o255000000000; // 040175 SSRAM[16510] = 36'o200040045727; // 040176 SSRAM[16511] = 36'o251040040635; // 040177 SSRAM[16512] = 36'o260740040557; // 040200 SSRAM[16513] = 36'o036600045532; // 040201 SSRAM[16514] = 36'o255000000000; // 040202 SSRAM[16515] = 36'o200600040567; // 040203 SSRAM[16516] = 36'o434600045535; // 040204 SSRAM[16517] = 36'o312600040567; // 040205 SSRAM[16518] = 36'o036540045545; // 040206 SSRAM[16519] = 36'o255000000000; // 040207 SSRAM[16520] = 36'o200040045736; // 040210 SSRAM[16521] = 36'o251040040635; // 040211 SSRAM[16522] = 36'o260740040557; // 040212 SSRAM[16523] = 36'o036600045532; // 040213 SSRAM[16524] = 36'o255000000000; // 040214 SSRAM[16525] = 36'o200600040567; // 040215 SSRAM[16526] = 36'o434600045535; // 040216 SSRAM[16527] = 36'o312600040567; // 040217 SSRAM[16528] = 36'o036540045545; // 040220 SSRAM[16529] = 36'o255000000000; // 040221 SSRAM[16530] = 36'o200040045745; // 040222 SSRAM[16531] = 36'o251040040635; // 040223 SSRAM[16532] = 36'o260740040557; // 040224 SSRAM[16533] = 36'o036600045532; // 040225 SSRAM[16534] = 36'o255000000000; // 040226 SSRAM[16535] = 36'o200600040567; // 040227 SSRAM[16536] = 36'o434600045535; // 040230 SSRAM[16537] = 36'o312600040567; // 040231 SSRAM[16538] = 36'o036540045545; // 040232 SSRAM[16539] = 36'o255000000000; // 040233 SSRAM[16540] = 36'o200040045746; // 040234 SSRAM[16541] = 36'o251040040635; // 040235 SSRAM[16542] = 36'o260740040557; // 040236 SSRAM[16543] = 36'o036600045532; // 040237 SSRAM[16544] = 36'o255000000000; // 040240 SSRAM[16545] = 36'o200600040567; // 040241 SSRAM[16546] = 36'o434600045535; // 040242 SSRAM[16547] = 36'o312600040567; // 040243 SSRAM[16548] = 36'o036540045545; // 040244 SSRAM[16549] = 36'o255000000000; // 040245 SSRAM[16550] = 36'o200040045755; // 040246 SSRAM[16551] = 36'o251040040635; // 040247 SSRAM[16552] = 36'o260740040557; // 040250 SSRAM[16553] = 36'o036600045532; // 040251 SSRAM[16554] = 36'o255000000000; // 040252 SSRAM[16555] = 36'o200600040567; // 040253 SSRAM[16556] = 36'o434600045535; // 040254 SSRAM[16557] = 36'o312600040567; // 040255 SSRAM[16558] = 36'o036540045545; // 040256 SSRAM[16559] = 36'o255000000000; // 040257 SSRAM[16560] = 36'o200040045756; // 040260 SSRAM[16561] = 36'o251040040635; // 040261 SSRAM[16562] = 36'o260740040557; // 040262 SSRAM[16563] = 36'o036600045532; // 040263 SSRAM[16564] = 36'o255000000000; // 040264 SSRAM[16565] = 36'o200600040567; // 040265 SSRAM[16566] = 36'o434600045535; // 040266 SSRAM[16567] = 36'o312600040567; // 040267 SSRAM[16568] = 36'o036540045545; // 040270 SSRAM[16569] = 36'o255000000000; // 040271 SSRAM[16570] = 36'o200040045765; // 040272 SSRAM[16571] = 36'o251040040635; // 040273 SSRAM[16572] = 36'o260740040557; // 040274 SSRAM[16573] = 36'o036600045532; // 040275 SSRAM[16574] = 36'o255000000000; // 040276 SSRAM[16575] = 36'o200600040567; // 040277 SSRAM[16576] = 36'o434600045535; // 040300 SSRAM[16577] = 36'o312600040567; // 040301 SSRAM[16578] = 36'o036540045545; // 040302 SSRAM[16579] = 36'o255000000000; // 040303 SSRAM[16580] = 36'o200040045774; // 040304 SSRAM[16581] = 36'o251040040635; // 040305 SSRAM[16582] = 36'o260740040557; // 040306 SSRAM[16583] = 36'o036600045532; // 040307 SSRAM[16584] = 36'o255000000000; // 040310 SSRAM[16585] = 36'o200600040567; // 040311 SSRAM[16586] = 36'o434600045535; // 040312 SSRAM[16587] = 36'o312600040567; // 040313 SSRAM[16588] = 36'o036540045545; // 040314 SSRAM[16589] = 36'o255000000000; // 040315 SSRAM[16590] = 36'o200040046003; // 040316 SSRAM[16591] = 36'o251040040635; // 040317 SSRAM[16592] = 36'o260740040557; // 040320 SSRAM[16593] = 36'o036600045532; // 040321 SSRAM[16594] = 36'o255000000000; // 040322 SSRAM[16595] = 36'o200600040567; // 040323 SSRAM[16596] = 36'o434600045535; // 040324 SSRAM[16597] = 36'o312600040567; // 040325 SSRAM[16598] = 36'o036540045545; // 040326 SSRAM[16599] = 36'o255000000000; // 040327 SSRAM[16600] = 36'o200040046012; // 040330 SSRAM[16601] = 36'o251040040635; // 040331 SSRAM[16602] = 36'o260740040557; // 040332 SSRAM[16603] = 36'o036600045532; // 040333 SSRAM[16604] = 36'o255000000000; // 040334 SSRAM[16605] = 36'o200600040567; // 040335 SSRAM[16606] = 36'o434600045535; // 040336 SSRAM[16607] = 36'o312600040567; // 040337 SSRAM[16608] = 36'o036540045545; // 040340 SSRAM[16609] = 36'o255000000000; // 040341 SSRAM[16610] = 36'o200040046021; // 040342 SSRAM[16611] = 36'o251040040635; // 040343 SSRAM[16612] = 36'o260740040557; // 040344 SSRAM[16613] = 36'o036600045532; // 040345 SSRAM[16614] = 36'o255000000000; // 040346 SSRAM[16615] = 36'o200600040567; // 040347 SSRAM[16616] = 36'o434600045535; // 040350 SSRAM[16617] = 36'o312600040567; // 040351 SSRAM[16618] = 36'o036540045545; // 040352 SSRAM[16619] = 36'o255000000000; // 040353 SSRAM[16620] = 36'o200040046030; // 040354 SSRAM[16621] = 36'o251040040635; // 040355 SSRAM[16622] = 36'o260740040557; // 040356 SSRAM[16623] = 36'o036600045532; // 040357 SSRAM[16624] = 36'o255000000000; // 040360 SSRAM[16625] = 36'o200600040567; // 040361 SSRAM[16626] = 36'o434600045535; // 040362 SSRAM[16627] = 36'o312600040567; // 040363 SSRAM[16628] = 36'o036540045545; // 040364 SSRAM[16629] = 36'o255000000000; // 040365 SSRAM[16630] = 36'o200040046037; // 040366 SSRAM[16631] = 36'o251040040635; // 040367 SSRAM[16632] = 36'o260740040557; // 040370 SSRAM[16633] = 36'o036600045532; // 040371 SSRAM[16634] = 36'o255000000000; // 040372 SSRAM[16635] = 36'o200600040567; // 040373 SSRAM[16636] = 36'o434600045535; // 040374 SSRAM[16637] = 36'o312600040567; // 040375 SSRAM[16638] = 36'o036540045545; // 040376 SSRAM[16639] = 36'o255000000000; // 040377 SSRAM[16640] = 36'o200040046046; // 040400 SSRAM[16641] = 36'o251040040635; // 040401 SSRAM[16642] = 36'o260740040557; // 040402 SSRAM[16643] = 36'o036600045532; // 040403 SSRAM[16644] = 36'o255000000000; // 040404 SSRAM[16645] = 36'o200600040567; // 040405 SSRAM[16646] = 36'o434600045535; // 040406 SSRAM[16647] = 36'o312600040567; // 040407 SSRAM[16648] = 36'o036540045545; // 040410 SSRAM[16649] = 36'o255000000000; // 040411 SSRAM[16650] = 36'o200040046055; // 040412 SSRAM[16651] = 36'o251040040635; // 040413 SSRAM[16652] = 36'o260740040557; // 040414 SSRAM[16653] = 36'o036600045532; // 040415 SSRAM[16654] = 36'o255000000000; // 040416 SSRAM[16655] = 36'o200600040567; // 040417 SSRAM[16656] = 36'o434600045535; // 040420 SSRAM[16657] = 36'o312600040567; // 040421 SSRAM[16658] = 36'o036540045545; // 040422 SSRAM[16659] = 36'o255000000000; // 040423 SSRAM[16660] = 36'o200040046064; // 040424 SSRAM[16661] = 36'o251040040635; // 040425 SSRAM[16662] = 36'o260740040557; // 040426 SSRAM[16663] = 36'o036600045532; // 040427 SSRAM[16664] = 36'o255000000000; // 040430 SSRAM[16665] = 36'o200600040567; // 040431 SSRAM[16666] = 36'o434600045535; // 040432 SSRAM[16667] = 36'o312600040567; // 040433 SSRAM[16668] = 36'o036540045545; // 040434 SSRAM[16669] = 36'o255000000000; // 040435 SSRAM[16670] = 36'o200040046073; // 040436 SSRAM[16671] = 36'o251040040635; // 040437 SSRAM[16672] = 36'o260740040557; // 040440 SSRAM[16673] = 36'o036600045532; // 040441 SSRAM[16674] = 36'o255000000000; // 040442 SSRAM[16675] = 36'o200600040567; // 040443 SSRAM[16676] = 36'o434600045535; // 040444 SSRAM[16677] = 36'o312600040567; // 040445 SSRAM[16678] = 36'o036540045545; // 040446 SSRAM[16679] = 36'o255000000000; // 040447 SSRAM[16680] = 36'o254000030057; // 040450 SSRAM[16681] = 36'o200640046074; // 040451 SSRAM[16682] = 36'o120040040502; // 040452 SSRAM[16683] = 36'o120140043403; // 040453 SSRAM[16684] = 36'o255740040455; // 040454 SSRAM[16685] = 36'o116040040504; // 040455 SSRAM[16686] = 36'o264000040457; // 040456 SSRAM[16687] = 36'o000000000000; // 040457 SSRAM[16688] = 36'o400540000000; // 040460 SSRAM[16689] = 36'o312040040506; // 040461 SSRAM[16690] = 36'o254000040474; // 040462 SSRAM[16691] = 36'o201540000001; // 040463 SSRAM[16692] = 36'o312100040507; // 040464 SSRAM[16693] = 36'o254000040474; // 040465 SSRAM[16694] = 36'o201540000002; // 040466 SSRAM[16695] = 36'o312140040510; // 040467 SSRAM[16696] = 36'o254000040474; // 040470 SSRAM[16697] = 36'o201540000003; // 040471 SSRAM[16698] = 36'o316200040511; // 040472 SSRAM[16699] = 36'o254000040477; // 040473 SSRAM[16700] = 36'o200613000001; // 040474 SSRAM[16701] = 36'o200553040506; // 040475 SSRAM[16702] = 36'o263740000000; // 040476 SSRAM[16703] = 36'o262740040512; // 040477 SSRAM[16704] = 36'o350000040512; // 040500 SSRAM[16705] = 36'o254020040512; // 040501 SSRAM[16715] = 36'o200640046075; // 040513 SSRAM[16716] = 36'o120040040544; // 040514 SSRAM[16717] = 36'o120140040546; // 040515 SSRAM[16718] = 36'o254120046076; // 040516 SSRAM[16719] = 36'o117040040550; // 040517 SSRAM[16720] = 36'o264000040521; // 040520 SSRAM[16721] = 36'o000000000000; // 040521 SSRAM[16722] = 36'o400540000000; // 040522 SSRAM[16723] = 36'o312040040552; // 040523 SSRAM[16724] = 36'o254000040536; // 040524 SSRAM[16725] = 36'o201540000001; // 040525 SSRAM[16726] = 36'o312100040553; // 040526 SSRAM[16727] = 36'o254000040536; // 040527 SSRAM[16728] = 36'o201540000002; // 040530 SSRAM[16729] = 36'o312140040554; // 040531 SSRAM[16730] = 36'o254000040536; // 040532 SSRAM[16731] = 36'o201540000003; // 040533 SSRAM[16732] = 36'o316200040555; // 040534 SSRAM[16733] = 36'o254000040541; // 040535 SSRAM[16734] = 36'o200613000001; // 040536 SSRAM[16735] = 36'o200553040552; // 040537 SSRAM[16736] = 36'o263740000000; // 040540 SSRAM[16737] = 36'o262740040512; // 040541 SSRAM[16738] = 36'o350000040512; // 040542 SSRAM[16739] = 36'o254020040512; // 040543 SSRAM[16751] = 36'o200640046077; // 040557 SSRAM[16752] = 36'o120040040630; // 040560 SSRAM[16753] = 36'o120140040632; // 040561 SSRAM[16754] = 36'o124040040636; // 040562 SSRAM[16755] = 36'o124140040640; // 040563 SSRAM[16756] = 36'o254120046100; // 040564 SSRAM[16757] = 36'o117040040634; // 040565 SSRAM[16758] = 36'o264000040567; // 040566 SSRAM[16759] = 36'o000000000000; // 040567 SSRAM[16760] = 36'o336000030524; // 040570 SSRAM[16761] = 36'o254000040600; // 040571 SSRAM[16762] = 36'o135540040622; // 040572 SSRAM[16763] = 36'o137540040625; // 040573 SSRAM[16764] = 36'o135540040623; // 040574 SSRAM[16765] = 36'o137540040626; // 040575 SSRAM[16766] = 36'o135540040624; // 040576 SSRAM[16767] = 36'o137540040627; // 040577 SSRAM[16768] = 36'o400540000000; // 040600 SSRAM[16769] = 36'o312040040636; // 040601 SSRAM[16770] = 36'o254000040614; // 040602 SSRAM[16771] = 36'o201540000001; // 040603 SSRAM[16772] = 36'o312100040637; // 040604 SSRAM[16773] = 36'o254000040614; // 040605 SSRAM[16774] = 36'o201540000002; // 040606 SSRAM[16775] = 36'o312140040640; // 040607 SSRAM[16776] = 36'o254000040614; // 040610 SSRAM[16777] = 36'o201540000003; // 040611 SSRAM[16778] = 36'o316200040641; // 040612 SSRAM[16779] = 36'o254000040617; // 040613 SSRAM[16780] = 36'o200613000001; // 040614 SSRAM[16781] = 36'o200553040636; // 040615 SSRAM[16782] = 36'o263740000000; // 040616 SSRAM[16783] = 36'o262740040512; // 040617 SSRAM[16784] = 36'o350000040512; // 040620 SSRAM[16785] = 36'o254020040512; // 040621 SSRAM[16786] = 36'o430100000002; // 040622 SSRAM[16787] = 36'o430100000003; // 040623 SSRAM[16788] = 36'o430100000004; // 040624 SSRAM[16789] = 36'o430100040637; // 040625 SSRAM[16790] = 36'o430100040640; // 040626 SSRAM[16791] = 36'o430100040641; // 040627 SSRAM[16803] = 36'o037100046101; // 040643 SSRAM[16804] = 36'o554540000015; // 040644 SSRAM[16805] = 36'o200020000013; // 040645 SSRAM[16806] = 36'o037600000000; // 040646 SSRAM[16807] = 36'o340540000000; // 040647 SSRAM[16808] = 36'o200020000013; // 040650 SSRAM[16809] = 36'o037600000000; // 040651 SSRAM[16810] = 36'o037000030242; // 040652 SSRAM[16811] = 36'o037100046103; // 040653 SSRAM[16812] = 36'o550540000015; // 040654 SSRAM[16813] = 36'o200020000013; // 040655 SSRAM[16814] = 36'o037600000000; // 040656 SSRAM[16815] = 36'o340540000000; // 040657 SSRAM[16816] = 36'o200020000013; // 040660 SSRAM[16817] = 36'o037600000000; // 040661 SSRAM[16818] = 36'o037000030242; // 040662 SSRAM[16819] = 36'o037100046105; // 040663 SSRAM[16820] = 36'o200000000001; // 040664 SSRAM[16821] = 36'o037600000000; // 040665 SSRAM[16822] = 36'o200000000002; // 040666 SSRAM[16823] = 36'o037600000000; // 040667 SSRAM[16824] = 36'o037000030242; // 040670 SSRAM[16825] = 36'o263740000000; // 040671 SSRAM[16826] = 36'o037100046107; // 040672 SSRAM[16827] = 36'o554540000015; // 040673 SSRAM[16828] = 36'o200020000013; // 040674 SSRAM[16829] = 36'o037600000000; // 040675 SSRAM[16830] = 36'o340540000000; // 040676 SSRAM[16831] = 36'o200020000013; // 040677 SSRAM[16832] = 36'o037600000000; // 040700 SSRAM[16833] = 36'o037000030242; // 040701 SSRAM[16834] = 36'o037100046112; // 040702 SSRAM[16835] = 36'o550540000015; // 040703 SSRAM[16836] = 36'o200020000013; // 040704 SSRAM[16837] = 36'o037600000000; // 040705 SSRAM[16838] = 36'o340540000000; // 040706 SSRAM[16839] = 36'o200020000013; // 040707 SSRAM[16840] = 36'o037600000000; // 040710 SSRAM[16841] = 36'o037000030242; // 040711 SSRAM[16842] = 36'o037100046115; // 040712 SSRAM[16843] = 36'o200000000001; // 040713 SSRAM[16844] = 36'o037600000000; // 040714 SSRAM[16845] = 36'o200000000002; // 040715 SSRAM[16846] = 36'o037600000000; // 040716 SSRAM[16847] = 36'o037000030242; // 040717 SSRAM[16848] = 36'o263740000000; // 040720 SSRAM[16849] = 36'o037100046120; // 040721 SSRAM[16850] = 36'o554540000015; // 040722 SSRAM[16851] = 36'o200020000013; // 040723 SSRAM[16852] = 36'o037600000000; // 040724 SSRAM[16853] = 36'o340540000000; // 040725 SSRAM[16854] = 36'o200020000013; // 040726 SSRAM[16855] = 36'o037600000000; // 040727 SSRAM[16856] = 36'o037000030242; // 040730 SSRAM[16857] = 36'o037100046123; // 040731 SSRAM[16858] = 36'o550540000015; // 040732 SSRAM[16859] = 36'o200020000013; // 040733 SSRAM[16860] = 36'o037600000000; // 040734 SSRAM[16861] = 36'o340540000000; // 040735 SSRAM[16862] = 36'o200020000013; // 040736 SSRAM[16863] = 36'o037600000000; // 040737 SSRAM[16864] = 36'o037000030242; // 040740 SSRAM[16865] = 36'o037100046126; // 040741 SSRAM[16866] = 36'o200000000001; // 040742 SSRAM[16867] = 36'o037600000000; // 040743 SSRAM[16868] = 36'o200000000002; // 040744 SSRAM[16869] = 36'o037600000000; // 040745 SSRAM[16870] = 36'o200000000003; // 040746 SSRAM[16871] = 36'o037600000000; // 040747 SSRAM[16872] = 36'o200000000004; // 040750 SSRAM[16873] = 36'o037600000000; // 040751 SSRAM[16874] = 36'o037000030242; // 040752 SSRAM[16875] = 36'o263740000000; // 040753 SSRAM[16876] = 36'o037100046131; // 040754 SSRAM[16877] = 36'o554540000015; // 040755 SSRAM[16878] = 36'o200020000013; // 040756 SSRAM[16879] = 36'o037600000000; // 040757 SSRAM[16880] = 36'o340540000000; // 040760 SSRAM[16881] = 36'o200020000013; // 040761 SSRAM[16882] = 36'o037600000000; // 040762 SSRAM[16883] = 36'o340540000000; // 040763 SSRAM[16884] = 36'o200020000013; // 040764 SSRAM[16885] = 36'o037600000000; // 040765 SSRAM[16886] = 36'o340540000000; // 040766 SSRAM[16887] = 36'o200020000013; // 040767 SSRAM[16888] = 36'o037600000000; // 040770 SSRAM[16889] = 36'o037000030242; // 040771 SSRAM[16890] = 36'o037100046133; // 040772 SSRAM[16891] = 36'o550540000015; // 040773 SSRAM[16892] = 36'o200020000013; // 040774 SSRAM[16893] = 36'o037600000000; // 040775 SSRAM[16894] = 36'o340540000000; // 040776 SSRAM[16895] = 36'o200020000013; // 040777 SSRAM[16896] = 36'o037600000000; // 041000 SSRAM[16897] = 36'o037000030242; // 041001 SSRAM[16898] = 36'o037100046135; // 041002 SSRAM[16899] = 36'o200000000001; // 041003 SSRAM[16900] = 36'o037600000000; // 041004 SSRAM[16901] = 36'o200000000002; // 041005 SSRAM[16902] = 36'o037600000000; // 041006 SSRAM[16903] = 36'o037100046137; // 041007 SSRAM[16904] = 36'o200000000003; // 041010 SSRAM[16905] = 36'o037600000000; // 041011 SSRAM[16906] = 36'o200000000004; // 041012 SSRAM[16907] = 36'o037600000000; // 041013 SSRAM[16908] = 36'o037000030242; // 041014 SSRAM[16909] = 36'o263740000000; // 041015 SSRAM[16910] = 36'o444144440064; // 041016 SSRAM[16911] = 36'o456364770000; // 041017 SSRAM[16912] = 36'o000000000000; // 041020 SSRAM[16913] = 36'o123456765432; // 041021 SSRAM[16914] = 36'o000000000000; // 041022 SSRAM[16915] = 36'o000000000000; // 041023 SSRAM[16916] = 36'o041020041022; // 041024 SSRAM[16917] = 36'o770000000000; // 041025 SSRAM[16918] = 36'o644563640041; // 041026 SSRAM[16919] = 36'o210015006245; // 041027 SSRAM[16920] = 36'o636554640051; // 041030 SSRAM[16921] = 36'o630051564357; // 041031 SSRAM[16922] = 36'o626245436477; // 041032 SSRAM[16923] = 36'o041016041025; // 041033 SSRAM[16924] = 36'o000013000014; // 041034 SSRAM[16925] = 36'o041026040643; // 041035 SSRAM[16926] = 36'o041021041022; // 041036 SSRAM[16927] = 36'o644563640041; // 041037 SSRAM[16928] = 36'o220015006245; // 041040 SSRAM[16929] = 36'o636554640051; // 041041 SSRAM[16930] = 36'o630051564357; // 041042 SSRAM[16931] = 36'o626245436477; // 041043 SSRAM[16932] = 36'o041016041025; // 041044 SSRAM[16933] = 36'o000013000014; // 041045 SSRAM[16934] = 36'o041037040643; // 041046 SSRAM[16935] = 36'o123456765432; // 041047 SSRAM[16936] = 36'o123456765432; // 041050 SSRAM[16937] = 36'o041047041022; // 041051 SSRAM[16938] = 36'o644563640041; // 041052 SSRAM[16939] = 36'o230015006245; // 041053 SSRAM[16940] = 36'o636554640051; // 041054 SSRAM[16941] = 36'o630051564357; // 041055 SSRAM[16942] = 36'o626245436477; // 041056 SSRAM[16943] = 36'o041016041025; // 041057 SSRAM[16944] = 36'o000013000014; // 041060 SSRAM[16945] = 36'o041052040643; // 041061 SSRAM[16946] = 36'o041022041020; // 041062 SSRAM[16947] = 36'o644563640041; // 041063 SSRAM[16948] = 36'o240015006245; // 041064 SSRAM[16949] = 36'o636554640051; // 041065 SSRAM[16950] = 36'o630051564357; // 041066 SSRAM[16951] = 36'o626245436477; // 041067 SSRAM[16952] = 36'o041016041025; // 041070 SSRAM[16953] = 36'o000013000014; // 041071 SSRAM[16954] = 36'o041063040643; // 041072 SSRAM[16955] = 36'o041022041021; // 041073 SSRAM[16956] = 36'o644563640041; // 041074 SSRAM[16957] = 36'o250015006245; // 041075 SSRAM[16958] = 36'o636554640051; // 041076 SSRAM[16959] = 36'o630051564357; // 041077 SSRAM[16960] = 36'o626245436477; // 041100 SSRAM[16961] = 36'o041016041025; // 041101 SSRAM[16962] = 36'o000013000014; // 041102 SSRAM[16963] = 36'o041074040643; // 041103 SSRAM[16964] = 36'o041022041047; // 041104 SSRAM[16965] = 36'o644563640041; // 041105 SSRAM[16966] = 36'o260015006245; // 041106 SSRAM[16967] = 36'o636554640051; // 041107 SSRAM[16968] = 36'o630051564357; // 041110 SSRAM[16969] = 36'o626245436477; // 041111 SSRAM[16970] = 36'o041016041025; // 041112 SSRAM[16971] = 36'o000013000014; // 041113 SSRAM[16972] = 36'o041105040643; // 041114 SSRAM[16973] = 36'o041022041022; // 041115 SSRAM[16974] = 36'o644563640041; // 041116 SSRAM[16975] = 36'o270015006245; // 041117 SSRAM[16976] = 36'o636554640051; // 041120 SSRAM[16977] = 36'o630051564357; // 041121 SSRAM[16978] = 36'o626245436477; // 041122 SSRAM[16979] = 36'o041016041025; // 041123 SSRAM[16980] = 36'o000013000014; // 041124 SSRAM[16981] = 36'o041116040643; // 041125 SSRAM[16982] = 36'o000000000000; // 041126 SSRAM[16983] = 36'o000000000001; // 041127 SSRAM[16984] = 36'o041126041022; // 041130 SSRAM[16985] = 36'o644563640042; // 041131 SSRAM[16986] = 36'o210015006245; // 041132 SSRAM[16987] = 36'o636554640051; // 041133 SSRAM[16988] = 36'o630051564357; // 041134 SSRAM[16989] = 36'o626245436477; // 041135 SSRAM[16990] = 36'o041016041025; // 041136 SSRAM[16991] = 36'o000013000014; // 041137 SSRAM[16992] = 36'o041131040643; // 041140 SSRAM[16993] = 36'o041022041126; // 041141 SSRAM[16994] = 36'o644563640042; // 041142 SSRAM[16995] = 36'o220015006245; // 041143 SSRAM[16996] = 36'o636554640051; // 041144 SSRAM[16997] = 36'o630051564357; // 041145 SSRAM[16998] = 36'o626245436477; // 041146 SSRAM[16999] = 36'o041016041025; // 041147 SSRAM[17000] = 36'o000013000014; // 041150 SSRAM[17001] = 36'o041142040643; // 041151 SSRAM[17002] = 36'o000000000000; // 041152 SSRAM[17003] = 36'o200000000000; // 041153 SSRAM[17004] = 36'o041152041022; // 041154 SSRAM[17005] = 36'o041022041152; // 041155 SSRAM[17006] = 36'o000000000001; // 041156 SSRAM[17007] = 36'o000000000000; // 041157 SSRAM[17008] = 36'o041156041022; // 041160 SSRAM[17009] = 36'o041022041156; // 041161 SSRAM[17010] = 36'o200000000000; // 041162 SSRAM[17011] = 36'o000000000000; // 041163 SSRAM[17012] = 36'o041162041022; // 041164 SSRAM[17013] = 36'o041022041162; // 041165 SSRAM[17014] = 36'o777777777777; // 041166 SSRAM[17015] = 36'o777777777776; // 041167 SSRAM[17016] = 36'o041166041022; // 041170 SSRAM[17017] = 36'o041022041166; // 041171 SSRAM[17018] = 36'o777777777777; // 041172 SSRAM[17019] = 36'o577777777777; // 041173 SSRAM[17020] = 36'o041172041022; // 041174 SSRAM[17021] = 36'o041022041172; // 041175 SSRAM[17022] = 36'o777777777776; // 041176 SSRAM[17023] = 36'o777777777777; // 041177 SSRAM[17024] = 36'o041176041022; // 041200 SSRAM[17025] = 36'o041022041176; // 041201 SSRAM[17026] = 36'o577777777777; // 041202 SSRAM[17027] = 36'o777777777777; // 041203 SSRAM[17028] = 36'o041202041022; // 041204 SSRAM[17029] = 36'o041022041202; // 041205 SSRAM[17030] = 36'o031327031327; // 041206 SSRAM[17031] = 36'o644563640043; // 041207 SSRAM[17032] = 36'o001500624563; // 041210 SSRAM[17033] = 36'o655464005156; // 041211 SSRAM[17034] = 36'o435762624543; // 041212 SSRAM[17035] = 36'o647700000000; // 041213 SSRAM[17036] = 36'o041016041025; // 041214 SSRAM[17037] = 36'o000014000013; // 041215 SSRAM[17038] = 36'o041207040643; // 041216 SSRAM[17039] = 36'o000000000000; // 041217 SSRAM[17040] = 36'o777777777777; // 041220 SSRAM[17041] = 36'o041217041126; // 041221 SSRAM[17042] = 36'o644563640044; // 041222 SSRAM[17043] = 36'o210015006245; // 041223 SSRAM[17044] = 36'o636554640051; // 041224 SSRAM[17045] = 36'o630051564357; // 041225 SSRAM[17046] = 36'o626245436477; // 041226 SSRAM[17047] = 36'o041016041025; // 041227 SSRAM[17048] = 36'o000013000014; // 041230 SSRAM[17049] = 36'o041222040643; // 041231 SSRAM[17050] = 36'o041126041217; // 041232 SSRAM[17051] = 36'o644563640044; // 041233 SSRAM[17052] = 36'o220015006245; // 041234 SSRAM[17053] = 36'o636554640051; // 041235 SSRAM[17054] = 36'o630051564357; // 041236 SSRAM[17055] = 36'o626245436477; // 041237 SSRAM[17056] = 36'o041016041025; // 041240 SSRAM[17057] = 36'o000013000014; // 041241 SSRAM[17058] = 36'o041233040643; // 041242 SSRAM[17059] = 36'o644563640045; // 041243 SSRAM[17060] = 36'o001500624563; // 041244 SSRAM[17061] = 36'o655464005163; // 041245 SSRAM[17062] = 36'o005156435762; // 041246 SSRAM[17063] = 36'o624543647700; // 041247 SSRAM[17064] = 36'o041016041025; // 041250 SSRAM[17065] = 36'o000013000014; // 041251 SSRAM[17066] = 36'o041243040643; // 041252 SSRAM[17067] = 36'o644563640045; // 041253 SSRAM[17068] = 36'o001500604300; // 041254 SSRAM[17069] = 36'o465441476300; // 041255 SSRAM[17070] = 36'o515643576262; // 041256 SSRAM[17071] = 36'o454364001054; // 041257 SSRAM[17072] = 36'o454664002400; // 041260 SSRAM[17073] = 36'o425164631177; // 041261 SSRAM[17074] = 36'o041016041025; // 041262 SSRAM[17075] = 36'o000014031375; // 041263 SSRAM[17076] = 36'o041253040643; // 041264 SSRAM[17077] = 36'o041016041025; // 041265 SSRAM[17078] = 36'o000014031424; // 041266 SSRAM[17079] = 36'o041253040643; // 041267 SSRAM[17080] = 36'o041016041025; // 041270 SSRAM[17081] = 36'o000014031453; // 041271 SSRAM[17082] = 36'o041253040643; // 041272 SSRAM[17083] = 36'o041016041025; // 041273 SSRAM[17084] = 36'o000014031502; // 041274 SSRAM[17085] = 36'o041253040643; // 041275 SSRAM[17086] = 36'o041016041025; // 041276 SSRAM[17087] = 36'o000014031531; // 041277 SSRAM[17088] = 36'o041253040643; // 041300 SSRAM[17089] = 36'o041016041025; // 041301 SSRAM[17090] = 36'o000014031560; // 041302 SSRAM[17091] = 36'o041253040643; // 041303 SSRAM[17092] = 36'o033057033061; // 041304 SSRAM[17093] = 36'o644563640046; // 041305 SSRAM[17094] = 36'o210015006245; // 041306 SSRAM[17095] = 36'o636554640051; // 041307 SSRAM[17096] = 36'o630051564357; // 041310 SSRAM[17097] = 36'o626245436477; // 041311 SSRAM[17098] = 36'o041016041025; // 041312 SSRAM[17099] = 36'o000013000014; // 041313 SSRAM[17100] = 36'o041305040643; // 041314 SSRAM[17101] = 36'o644563640046; // 041315 SSRAM[17102] = 36'o210015006043; // 041316 SSRAM[17103] = 36'o004654414763; // 041317 SSRAM[17104] = 36'o005156435762; // 041320 SSRAM[17105] = 36'o624543640010; // 041321 SSRAM[17106] = 36'o544546640024; // 041322 SSRAM[17107] = 36'o004251646311; // 041323 SSRAM[17108] = 36'o770000000000; // 041324 SSRAM[17109] = 36'o041016041025; // 041325 SSRAM[17110] = 36'o000014031637; // 041326 SSRAM[17111] = 36'o041315040643; // 041327 SSRAM[17112] = 36'o033063033065; // 041330 SSRAM[17113] = 36'o041016041025; // 041331 SSRAM[17114] = 36'o000014031665; // 041332 SSRAM[17115] = 36'o041315040643; // 041333 SSRAM[17116] = 36'o033067033071; // 041334 SSRAM[17117] = 36'o041016041025; // 041335 SSRAM[17118] = 36'o000014031713; // 041336 SSRAM[17119] = 36'o041315040643; // 041337 SSRAM[17120] = 36'o033073033075; // 041340 SSRAM[17121] = 36'o777777777777; // 041341 SSRAM[17122] = 36'o777777777777; // 041342 SSRAM[17123] = 36'o041016041025; // 041343 SSRAM[17124] = 36'o000014031741; // 041344 SSRAM[17125] = 36'o041315040643; // 041345 SSRAM[17126] = 36'o033077033101; // 041346 SSRAM[17127] = 36'o041016041025; // 041347 SSRAM[17128] = 36'o000014031767; // 041350 SSRAM[17129] = 36'o041315040643; // 041351 SSRAM[17130] = 36'o033103033105; // 041352 SSRAM[17131] = 36'o041016041025; // 041353 SSRAM[17132] = 36'o000014032015; // 041354 SSRAM[17133] = 36'o041315040643; // 041355 SSRAM[17134] = 36'o033107033111; // 041356 SSRAM[17135] = 36'o777777777776; // 041357 SSRAM[17136] = 36'o777777777776; // 041360 SSRAM[17137] = 36'o644563640046; // 041361 SSRAM[17138] = 36'o220015006245; // 041362 SSRAM[17139] = 36'o636554640051; // 041363 SSRAM[17140] = 36'o630051564357; // 041364 SSRAM[17141] = 36'o626245436477; // 041365 SSRAM[17142] = 36'o041016041025; // 041366 SSRAM[17143] = 36'o000013000014; // 041367 SSRAM[17144] = 36'o041361040643; // 041370 SSRAM[17145] = 36'o300000000000; // 041371 SSRAM[17146] = 36'o644563640046; // 041372 SSRAM[17147] = 36'o220015006043; // 041373 SSRAM[17148] = 36'o004654414763; // 041374 SSRAM[17149] = 36'o005156435762; // 041375 SSRAM[17150] = 36'o624543640010; // 041376 SSRAM[17151] = 36'o544546640024; // 041377 SSRAM[17152] = 36'o004251646311; // 041400 SSRAM[17153] = 36'o770000000000; // 041401 SSRAM[17154] = 36'o041016041025; // 041402 SSRAM[17155] = 36'o000014032043; // 041403 SSRAM[17156] = 36'o041372040643; // 041404 SSRAM[17157] = 36'o033113033115; // 041405 SSRAM[17158] = 36'o041016041025; // 041406 SSRAM[17159] = 36'o000014032071; // 041407 SSRAM[17160] = 36'o041372040643; // 041410 SSRAM[17161] = 36'o033117033121; // 041411 SSRAM[17162] = 36'o041016041025; // 041412 SSRAM[17163] = 36'o000014032117; // 041413 SSRAM[17164] = 36'o041372040643; // 041414 SSRAM[17165] = 36'o033123033125; // 041415 SSRAM[17166] = 36'o041016041025; // 041416 SSRAM[17167] = 36'o000014032145; // 041417 SSRAM[17168] = 36'o041372040643; // 041420 SSRAM[17169] = 36'o033127033131; // 041421 SSRAM[17170] = 36'o041016041025; // 041422 SSRAM[17171] = 36'o000014032173; // 041423 SSRAM[17172] = 36'o041372040643; // 041424 SSRAM[17173] = 36'o033133033135; // 041425 SSRAM[17174] = 36'o041016041025; // 041426 SSRAM[17175] = 36'o000014032221; // 041427 SSRAM[17176] = 36'o041372040643; // 041430 SSRAM[17177] = 36'o033137033141; // 041431 SSRAM[17178] = 36'o000000000001; // 041432 SSRAM[17179] = 36'o000000000001; // 041433 SSRAM[17180] = 36'o644563640046; // 041434 SSRAM[17181] = 36'o230015006245; // 041435 SSRAM[17182] = 36'o636554640051; // 041436 SSRAM[17183] = 36'o630051564357; // 041437 SSRAM[17184] = 36'o626245436477; // 041440 SSRAM[17185] = 36'o041016041025; // 041441 SSRAM[17186] = 36'o000013000014; // 041442 SSRAM[17187] = 36'o041434040643; // 041443 SSRAM[17188] = 36'o644563640046; // 041444 SSRAM[17189] = 36'o230015006043; // 041445 SSRAM[17190] = 36'o004654414763; // 041446 SSRAM[17191] = 36'o005156435762; // 041447 SSRAM[17192] = 36'o624543640010; // 041450 SSRAM[17193] = 36'o544546640024; // 041451 SSRAM[17194] = 36'o004251646311; // 041452 SSRAM[17195] = 36'o770000000000; // 041453 SSRAM[17196] = 36'o041016041025; // 041454 SSRAM[17197] = 36'o000014032247; // 041455 SSRAM[17198] = 36'o041444040643; // 041456 SSRAM[17199] = 36'o033143033145; // 041457 SSRAM[17200] = 36'o041016041025; // 041460 SSRAM[17201] = 36'o000014032275; // 041461 SSRAM[17202] = 36'o041444040643; // 041462 SSRAM[17203] = 36'o033147033151; // 041463 SSRAM[17204] = 36'o041016041025; // 041464 SSRAM[17205] = 36'o000014032323; // 041465 SSRAM[17206] = 36'o041444040643; // 041466 SSRAM[17207] = 36'o033153033155; // 041467 SSRAM[17208] = 36'o041016041025; // 041470 SSRAM[17209] = 36'o000014032351; // 041471 SSRAM[17210] = 36'o041444040643; // 041472 SSRAM[17211] = 36'o033157033161; // 041473 SSRAM[17212] = 36'o041016041025; // 041474 SSRAM[17213] = 36'o000014032377; // 041475 SSRAM[17214] = 36'o041444040643; // 041476 SSRAM[17215] = 36'o033163033165; // 041477 SSRAM[17216] = 36'o041016041025; // 041500 SSRAM[17217] = 36'o000014032425; // 041501 SSRAM[17218] = 36'o041444040643; // 041502 SSRAM[17219] = 36'o033167033171; // 041503 SSRAM[17220] = 36'o644563640046; // 041504 SSRAM[17221] = 36'o240015006245; // 041505 SSRAM[17222] = 36'o636554640051; // 041506 SSRAM[17223] = 36'o630051564357; // 041507 SSRAM[17224] = 36'o626245436477; // 041510 SSRAM[17225] = 36'o041016041025; // 041511 SSRAM[17226] = 36'o000013000014; // 041512 SSRAM[17227] = 36'o041504040643; // 041513 SSRAM[17228] = 36'o644563640046; // 041514 SSRAM[17229] = 36'o240015006043; // 041515 SSRAM[17230] = 36'o004654414763; // 041516 SSRAM[17231] = 36'o005156435762; // 041517 SSRAM[17232] = 36'o624543640010; // 041520 SSRAM[17233] = 36'o544546640024; // 041521 SSRAM[17234] = 36'o004251646311; // 041522 SSRAM[17235] = 36'o770000000000; // 041523 SSRAM[17236] = 36'o041016041025; // 041524 SSRAM[17237] = 36'o000014032453; // 041525 SSRAM[17238] = 36'o041514040643; // 041526 SSRAM[17239] = 36'o033173033175; // 041527 SSRAM[17240] = 36'o041016041025; // 041530 SSRAM[17241] = 36'o000014032501; // 041531 SSRAM[17242] = 36'o041514040643; // 041532 SSRAM[17243] = 36'o033177033201; // 041533 SSRAM[17244] = 36'o041016041025; // 041534 SSRAM[17245] = 36'o000014032527; // 041535 SSRAM[17246] = 36'o041514040643; // 041536 SSRAM[17247] = 36'o033203033205; // 041537 SSRAM[17248] = 36'o041016041025; // 041540 SSRAM[17249] = 36'o000014032555; // 041541 SSRAM[17250] = 36'o041514040643; // 041542 SSRAM[17251] = 36'o033207033211; // 041543 SSRAM[17252] = 36'o041016041025; // 041544 SSRAM[17253] = 36'o000014032603; // 041545 SSRAM[17254] = 36'o041514040643; // 041546 SSRAM[17255] = 36'o033213033215; // 041547 SSRAM[17256] = 36'o041016041025; // 041550 SSRAM[17257] = 36'o000014032631; // 041551 SSRAM[17258] = 36'o041514040643; // 041552 SSRAM[17259] = 36'o033217033221; // 041553 SSRAM[17260] = 36'o644563640046; // 041554 SSRAM[17261] = 36'o250015006245; // 041555 SSRAM[17262] = 36'o636554640051; // 041556 SSRAM[17263] = 36'o630051564357; // 041557 SSRAM[17264] = 36'o626245436477; // 041560 SSRAM[17265] = 36'o041016041025; // 041561 SSRAM[17266] = 36'o000013000014; // 041562 SSRAM[17267] = 36'o041554040643; // 041563 SSRAM[17268] = 36'o644563640046; // 041564 SSRAM[17269] = 36'o250015006043; // 041565 SSRAM[17270] = 36'o004654414763; // 041566 SSRAM[17271] = 36'o005156435762; // 041567 SSRAM[17272] = 36'o624543640010; // 041570 SSRAM[17273] = 36'o544546640024; // 041571 SSRAM[17274] = 36'o004251646311; // 041572 SSRAM[17275] = 36'o770000000000; // 041573 SSRAM[17276] = 36'o041016041025; // 041574 SSRAM[17277] = 36'o000014032657; // 041575 SSRAM[17278] = 36'o041564040643; // 041576 SSRAM[17279] = 36'o033223033225; // 041577 SSRAM[17280] = 36'o041016041025; // 041600 SSRAM[17281] = 36'o000014032705; // 041601 SSRAM[17282] = 36'o041564040643; // 041602 SSRAM[17283] = 36'o033227033231; // 041603 SSRAM[17284] = 36'o041016041025; // 041604 SSRAM[17285] = 36'o000014032733; // 041605 SSRAM[17286] = 36'o041564040643; // 041606 SSRAM[17287] = 36'o033233033235; // 041607 SSRAM[17288] = 36'o041016041025; // 041610 SSRAM[17289] = 36'o000014032761; // 041611 SSRAM[17290] = 36'o041564040643; // 041612 SSRAM[17291] = 36'o033237033241; // 041613 SSRAM[17292] = 36'o041016041025; // 041614 SSRAM[17293] = 36'o000014033007; // 041615 SSRAM[17294] = 36'o041564040643; // 041616 SSRAM[17295] = 36'o033243033245; // 041617 SSRAM[17296] = 36'o041016041025; // 041620 SSRAM[17297] = 36'o000014033035; // 041621 SSRAM[17298] = 36'o041564040643; // 041622 SSRAM[17299] = 36'o033530033532; // 041623 SSRAM[17300] = 36'o644563640047; // 041624 SSRAM[17301] = 36'o001500624563; // 041625 SSRAM[17302] = 36'o655464005163; // 041626 SSRAM[17303] = 36'o005156435762; // 041627 SSRAM[17304] = 36'o624543647700; // 041630 SSRAM[17305] = 36'o041016041025; // 041631 SSRAM[17306] = 36'o000013000014; // 041632 SSRAM[17307] = 36'o041624040643; // 041633 SSRAM[17308] = 36'o500000000000; // 041634 SSRAM[17309] = 36'o644563640047; // 041635 SSRAM[17310] = 36'o001500604300; // 041636 SSRAM[17311] = 36'o465441476300; // 041637 SSRAM[17312] = 36'o515643576262; // 041640 SSRAM[17313] = 36'o454364001054; // 041641 SSRAM[17314] = 36'o454664002400; // 041642 SSRAM[17315] = 36'o425164631177; // 041643 SSRAM[17316] = 36'o041016041025; // 041644 SSRAM[17317] = 36'o000014033254; // 041645 SSRAM[17318] = 36'o041635040643; // 041646 SSRAM[17319] = 36'o033536033540; // 041647 SSRAM[17320] = 36'o041016041025; // 041650 SSRAM[17321] = 36'o000014033302; // 041651 SSRAM[17322] = 36'o041635040643; // 041652 SSRAM[17323] = 36'o033544033546; // 041653 SSRAM[17324] = 36'o041016041025; // 041654 SSRAM[17325] = 36'o000014033330; // 041655 SSRAM[17326] = 36'o041635040643; // 041656 SSRAM[17327] = 36'o033552033554; // 041657 SSRAM[17328] = 36'o041016041025; // 041660 SSRAM[17329] = 36'o000014033356; // 041661 SSRAM[17330] = 36'o041635040643; // 041662 SSRAM[17331] = 36'o033560033562; // 041663 SSRAM[17332] = 36'o600000000000; // 041664 SSRAM[17333] = 36'o041016041025; // 041665 SSRAM[17334] = 36'o000014033404; // 041666 SSRAM[17335] = 36'o041635040643; // 041667 SSRAM[17336] = 36'o033566033570; // 041670 SSRAM[17337] = 36'o041016041025; // 041671 SSRAM[17338] = 36'o000014033432; // 041672 SSRAM[17339] = 36'o041635040643; // 041673 SSRAM[17340] = 36'o033574033576; // 041674 SSRAM[17341] = 36'o041016041025; // 041675 SSRAM[17342] = 36'o000014033460; // 041676 SSRAM[17343] = 36'o041635040643; // 041677 SSRAM[17344] = 36'o033602033604; // 041700 SSRAM[17345] = 36'o041016041025; // 041701 SSRAM[17346] = 36'o000014033506; // 041702 SSRAM[17347] = 36'o041635040643; // 041703 SSRAM[17348] = 36'o446365420064; // 041704 SSRAM[17349] = 36'o456364770000; // 041705 SSRAM[17350] = 36'o041704041025; // 041706 SSRAM[17351] = 36'o000013000014; // 041707 SSRAM[17352] = 36'o041026040672; // 041710 SSRAM[17353] = 36'o041704041025; // 041711 SSRAM[17354] = 36'o000013000014; // 041712 SSRAM[17355] = 36'o041037040672; // 041713 SSRAM[17356] = 36'o041704041025; // 041714 SSRAM[17357] = 36'o000013000014; // 041715 SSRAM[17358] = 36'o041052040672; // 041716 SSRAM[17359] = 36'o654321012346; // 041717 SSRAM[17360] = 36'o777777777777; // 041720 SSRAM[17361] = 36'o654321012346; // 041721 SSRAM[17362] = 36'o041704041025; // 041722 SSRAM[17363] = 36'o000013000014; // 041723 SSRAM[17364] = 36'o041063040672; // 041724 SSRAM[17365] = 36'o400000000000; // 041725 SSRAM[17366] = 36'o654321012346; // 041726 SSRAM[17367] = 36'o400000000000; // 041727 SSRAM[17368] = 36'o041704041025; // 041730 SSRAM[17369] = 36'o000013000014; // 041731 SSRAM[17370] = 36'o041074040672; // 041732 SSRAM[17371] = 36'o654321012345; // 041733 SSRAM[17372] = 36'o654321012346; // 041734 SSRAM[17373] = 36'o041704041025; // 041735 SSRAM[17374] = 36'o000013000014; // 041736 SSRAM[17375] = 36'o041105040672; // 041737 SSRAM[17376] = 36'o777766034012; // 041740 SSRAM[17377] = 36'o644563640042; // 041741 SSRAM[17378] = 36'o001500624563; // 041742 SSRAM[17379] = 36'o655464005156; // 041743 SSRAM[17380] = 36'o435762624543; // 041744 SSRAM[17381] = 36'o647700000000; // 041745 SSRAM[17382] = 36'o041704041025; // 041746 SSRAM[17383] = 36'o000012000013; // 041747 SSRAM[17384] = 36'o041741040672; // 041750 SSRAM[17385] = 36'o644563640042; // 041751 SSRAM[17386] = 36'o001500604300; // 041752 SSRAM[17387] = 36'o465441476300; // 041753 SSRAM[17388] = 36'o515643576262; // 041754 SSRAM[17389] = 36'o454364001054; // 041755 SSRAM[17390] = 36'o454664002400; // 041756 SSRAM[17391] = 36'o425164631177; // 041757 SSRAM[17392] = 36'o041704041025; // 041760 SSRAM[17393] = 36'o000014033752; // 041761 SSRAM[17394] = 36'o041751040672; // 041762 SSRAM[17395] = 36'o034647034651; // 041763 SSRAM[17396] = 36'o644563640043; // 041764 SSRAM[17397] = 36'o210015006245; // 041765 SSRAM[17398] = 36'o636554640051; // 041766 SSRAM[17399] = 36'o630051564357; // 041767 SSRAM[17400] = 36'o626245436477; // 041770 SSRAM[17401] = 36'o041704041025; // 041771 SSRAM[17402] = 36'o000013000014; // 041772 SSRAM[17403] = 36'o041764040672; // 041773 SSRAM[17404] = 36'o034655034657; // 041774 SSRAM[17405] = 36'o034663034665; // 041775 SSRAM[17406] = 36'o034671034673; // 041776 SSRAM[17407] = 36'o034677034701; // 041777 SSRAM[17408] = 36'o034705034707; // 042000 SSRAM[17409] = 36'o034713034715; // 042001 SSRAM[17410] = 36'o644563640043; // 042002 SSRAM[17411] = 36'o220015006245; // 042003 SSRAM[17412] = 36'o636554640051; // 042004 SSRAM[17413] = 36'o630051564357; // 042005 SSRAM[17414] = 36'o626245436477; // 042006 SSRAM[17415] = 36'o041704041025; // 042007 SSRAM[17416] = 36'o000013000014; // 042010 SSRAM[17417] = 36'o042002040672; // 042011 SSRAM[17418] = 36'o034721034723; // 042012 SSRAM[17419] = 36'o034727034731; // 042013 SSRAM[17420] = 36'o034735034737; // 042014 SSRAM[17421] = 36'o034743034745; // 042015 SSRAM[17422] = 36'o034751034753; // 042016 SSRAM[17423] = 36'o034757034761; // 042017 SSRAM[17424] = 36'o644563640043; // 042020 SSRAM[17425] = 36'o230015006245; // 042021 SSRAM[17426] = 36'o636554640051; // 042022 SSRAM[17427] = 36'o630051564357; // 042023 SSRAM[17428] = 36'o626245436477; // 042024 SSRAM[17429] = 36'o041704041025; // 042025 SSRAM[17430] = 36'o000013000014; // 042026 SSRAM[17431] = 36'o042020040672; // 042027 SSRAM[17432] = 36'o034765034767; // 042030 SSRAM[17433] = 36'o034773034775; // 042031 SSRAM[17434] = 36'o035001035003; // 042032 SSRAM[17435] = 36'o035007035011; // 042033 SSRAM[17436] = 36'o035015035017; // 042034 SSRAM[17437] = 36'o035023035025; // 042035 SSRAM[17438] = 36'o777777777775; // 042036 SSRAM[17439] = 36'o777777777777; // 042037 SSRAM[17440] = 36'o777777777775; // 042040 SSRAM[17441] = 36'o644563640043; // 042041 SSRAM[17442] = 36'o240015006245; // 042042 SSRAM[17443] = 36'o636554640051; // 042043 SSRAM[17444] = 36'o630051564357; // 042044 SSRAM[17445] = 36'o626245436477; // 042045 SSRAM[17446] = 36'o041704041025; // 042046 SSRAM[17447] = 36'o000013000014; // 042047 SSRAM[17448] = 36'o042041040672; // 042050 SSRAM[17449] = 36'o035027035031; // 042051 SSRAM[17450] = 36'o035033035035; // 042052 SSRAM[17451] = 36'o035037035041; // 042053 SSRAM[17452] = 36'o035043035045; // 042054 SSRAM[17453] = 36'o035047035051; // 042055 SSRAM[17454] = 36'o035053035055; // 042056 SSRAM[17455] = 36'o000000000003; // 042057 SSRAM[17456] = 36'o000000000000; // 042060 SSRAM[17457] = 36'o000000000003; // 042061 SSRAM[17458] = 36'o644563640043; // 042062 SSRAM[17459] = 36'o250015006245; // 042063 SSRAM[17460] = 36'o636554640051; // 042064 SSRAM[17461] = 36'o630051564357; // 042065 SSRAM[17462] = 36'o626245436477; // 042066 SSRAM[17463] = 36'o041704041025; // 042067 SSRAM[17464] = 36'o000013000014; // 042070 SSRAM[17465] = 36'o042062040672; // 042071 SSRAM[17466] = 36'o035057035061; // 042072 SSRAM[17467] = 36'o035063035065; // 042073 SSRAM[17468] = 36'o035067035071; // 042074 SSRAM[17469] = 36'o035073035075; // 042075 SSRAM[17470] = 36'o035077035101; // 042076 SSRAM[17471] = 36'o035374035376; // 042077 SSRAM[17472] = 36'o400000000000; // 042100 SSRAM[17473] = 36'o400000000000; // 042101 SSRAM[17474] = 36'o644563640044; // 042102 SSRAM[17475] = 36'o001500624563; // 042103 SSRAM[17476] = 36'o655464005163; // 042104 SSRAM[17477] = 36'o005156435762; // 042105 SSRAM[17478] = 36'o624543647700; // 042106 SSRAM[17479] = 36'o041704041025; // 042107 SSRAM[17480] = 36'o000013000014; // 042110 SSRAM[17481] = 36'o042102040672; // 042111 SSRAM[17482] = 36'o644563640044; // 042112 SSRAM[17483] = 36'o001500604300; // 042113 SSRAM[17484] = 36'o465441476300; // 042114 SSRAM[17485] = 36'o515643576262; // 042115 SSRAM[17486] = 36'o454364001054; // 042116 SSRAM[17487] = 36'o454664002400; // 042117 SSRAM[17488] = 36'o425164631177; // 042120 SSRAM[17489] = 36'o041704041025; // 042121 SSRAM[17490] = 36'o000014035110; // 042122 SSRAM[17491] = 36'o042112040672; // 042123 SSRAM[17492] = 36'o035400035402; // 042124 SSRAM[17493] = 36'o041704041025; // 042125 SSRAM[17494] = 36'o000014035137; // 042126 SSRAM[17495] = 36'o042112040672; // 042127 SSRAM[17496] = 36'o035404035406; // 042130 SSRAM[17497] = 36'o041704041025; // 042131 SSRAM[17498] = 36'o000014035166; // 042132 SSRAM[17499] = 36'o042112040672; // 042133 SSRAM[17500] = 36'o035410035412; // 042134 SSRAM[17501] = 36'o041704041025; // 042135 SSRAM[17502] = 36'o000014035215; // 042136 SSRAM[17503] = 36'o042112040672; // 042137 SSRAM[17504] = 36'o035414035416; // 042140 SSRAM[17505] = 36'o377777777777; // 042141 SSRAM[17506] = 36'o377777777777; // 042142 SSRAM[17507] = 36'o041704041025; // 042143 SSRAM[17508] = 36'o000014035244; // 042144 SSRAM[17509] = 36'o042112040672; // 042145 SSRAM[17510] = 36'o035420035422; // 042146 SSRAM[17511] = 36'o041704041025; // 042147 SSRAM[17512] = 36'o000014035273; // 042150 SSRAM[17513] = 36'o042112040672; // 042151 SSRAM[17514] = 36'o035424035426; // 042152 SSRAM[17515] = 36'o041704041025; // 042153 SSRAM[17516] = 36'o000014035322; // 042154 SSRAM[17517] = 36'o042112040672; // 042155 SSRAM[17518] = 36'o035430035432; // 042156 SSRAM[17519] = 36'o041704041025; // 042157 SSRAM[17520] = 36'o000014035351; // 042160 SSRAM[17521] = 36'o042112040672; // 042161 SSRAM[17522] = 36'o445565540064; // 042162 SSRAM[17523] = 36'o456364770000; // 042163 SSRAM[17524] = 36'o000000000000; // 042164 SSRAM[17525] = 36'o123456765432; // 042165 SSRAM[17526] = 36'o000000000000; // 042166 SSRAM[17527] = 36'o000000000000; // 042167 SSRAM[17528] = 36'o000000000000; // 042170 SSRAM[17529] = 36'o000000000000; // 042171 SSRAM[17530] = 36'o000000000000; // 042172 SSRAM[17531] = 36'o000000000000; // 042173 SSRAM[17532] = 36'o042164040502; // 042174 SSRAM[17533] = 36'o644563640041; // 042175 SSRAM[17534] = 36'o001500624563; // 042176 SSRAM[17535] = 36'o655464004341; // 042177 SSRAM[17536] = 36'o544365544164; // 042200 SSRAM[17537] = 36'o454400515643; // 042201 SSRAM[17538] = 36'o576262454364; // 042202 SSRAM[17539] = 36'o547177000000; // 042203 SSRAM[17540] = 36'o042162041025; // 042204 SSRAM[17541] = 36'o000013000014; // 042205 SSRAM[17542] = 36'o042175040721; // 042206 SSRAM[17543] = 36'o123456765432; // 042207 SSRAM[17544] = 36'o000000000000; // 042210 SSRAM[17545] = 36'o000000000000; // 042211 SSRAM[17546] = 36'o000000000000; // 042212 SSRAM[17547] = 36'o000000000000; // 042213 SSRAM[17548] = 36'o000000000000; // 042214 SSRAM[17549] = 36'o000000000000; // 042215 SSRAM[17550] = 36'o000000000000; // 042216 SSRAM[17551] = 36'o042207040502; // 042217 SSRAM[17552] = 36'o123456765432; // 042220 SSRAM[17553] = 36'o123456765432; // 042221 SSRAM[17554] = 36'o000000000000; // 042222 SSRAM[17555] = 36'o000000000000; // 042223 SSRAM[17556] = 36'o000000000000; // 042224 SSRAM[17557] = 36'o000000000000; // 042225 SSRAM[17558] = 36'o000000000000; // 042226 SSRAM[17559] = 36'o000000000000; // 042227 SSRAM[17560] = 36'o042220040502; // 042230 SSRAM[17561] = 36'o000000000000; // 042231 SSRAM[17562] = 36'o000000000000; // 042232 SSRAM[17563] = 36'o000000000000; // 042233 SSRAM[17564] = 36'o123456765432; // 042234 SSRAM[17565] = 36'o000000000000; // 042235 SSRAM[17566] = 36'o000000000000; // 042236 SSRAM[17567] = 36'o000000000000; // 042237 SSRAM[17568] = 36'o000000000000; // 042240 SSRAM[17569] = 36'o042231040502; // 042241 SSRAM[17570] = 36'o000000000000; // 042242 SSRAM[17571] = 36'o000000000000; // 042243 SSRAM[17572] = 36'o123456765432; // 042244 SSRAM[17573] = 36'o000000000000; // 042245 SSRAM[17574] = 36'o000000000000; // 042246 SSRAM[17575] = 36'o000000000000; // 042247 SSRAM[17576] = 36'o000000000000; // 042250 SSRAM[17577] = 36'o000000000000; // 042251 SSRAM[17578] = 36'o042242040502; // 042252 SSRAM[17579] = 36'o000000000000; // 042253 SSRAM[17580] = 36'o000000000000; // 042254 SSRAM[17581] = 36'o123456765432; // 042255 SSRAM[17582] = 36'o123456765432; // 042256 SSRAM[17583] = 36'o000000000000; // 042257 SSRAM[17584] = 36'o000000000000; // 042260 SSRAM[17585] = 36'o000000000000; // 042261 SSRAM[17586] = 36'o000000000000; // 042262 SSRAM[17587] = 36'o042253040502; // 042263 SSRAM[17588] = 36'o777777777777; // 042264 SSRAM[17589] = 36'o654321012346; // 042265 SSRAM[17590] = 36'o000000000000; // 042266 SSRAM[17591] = 36'o000000000000; // 042267 SSRAM[17592] = 36'o000000000000; // 042270 SSRAM[17593] = 36'o000000000000; // 042271 SSRAM[17594] = 36'o000000000000; // 042272 SSRAM[17595] = 36'o000000000000; // 042273 SSRAM[17596] = 36'o042264040502; // 042274 SSRAM[17597] = 36'o654321012346; // 042275 SSRAM[17598] = 36'o777777777777; // 042276 SSRAM[17599] = 36'o000000000000; // 042277 SSRAM[17600] = 36'o000000000000; // 042300 SSRAM[17601] = 36'o000000000000; // 042301 SSRAM[17602] = 36'o000000000000; // 042302 SSRAM[17603] = 36'o000000000000; // 042303 SSRAM[17604] = 36'o000000000000; // 042304 SSRAM[17605] = 36'o042275040502; // 042305 SSRAM[17606] = 36'o654321012346; // 042306 SSRAM[17607] = 36'o654321012346; // 042307 SSRAM[17608] = 36'o000000000000; // 042310 SSRAM[17609] = 36'o000000000000; // 042311 SSRAM[17610] = 36'o000000000000; // 042312 SSRAM[17611] = 36'o000000000000; // 042313 SSRAM[17612] = 36'o000000000000; // 042314 SSRAM[17613] = 36'o000000000000; // 042315 SSRAM[17614] = 36'o042306040502; // 042316 SSRAM[17615] = 36'o000000000000; // 042317 SSRAM[17616] = 36'o000000000000; // 042320 SSRAM[17617] = 36'o777777777777; // 042321 SSRAM[17618] = 36'o654321012346; // 042322 SSRAM[17619] = 36'o000000000000; // 042323 SSRAM[17620] = 36'o000000000000; // 042324 SSRAM[17621] = 36'o000000000000; // 042325 SSRAM[17622] = 36'o000000000000; // 042326 SSRAM[17623] = 36'o042317040502; // 042327 SSRAM[17624] = 36'o000000000000; // 042330 SSRAM[17625] = 36'o000000000000; // 042331 SSRAM[17626] = 36'o654321012346; // 042332 SSRAM[17627] = 36'o777777777777; // 042333 SSRAM[17628] = 36'o000000000000; // 042334 SSRAM[17629] = 36'o000000000000; // 042335 SSRAM[17630] = 36'o000000000000; // 042336 SSRAM[17631] = 36'o000000000000; // 042337 SSRAM[17632] = 36'o042330040502; // 042340 SSRAM[17633] = 36'o000000000000; // 042341 SSRAM[17634] = 36'o000000000000; // 042342 SSRAM[17635] = 36'o654321012346; // 042343 SSRAM[17636] = 36'o654321012346; // 042344 SSRAM[17637] = 36'o000000000000; // 042345 SSRAM[17638] = 36'o000000000000; // 042346 SSRAM[17639] = 36'o000000000000; // 042347 SSRAM[17640] = 36'o000000000000; // 042350 SSRAM[17641] = 36'o042341040502; // 042351 SSRAM[17642] = 36'o000000000000; // 042352 SSRAM[17643] = 36'o000000000000; // 042353 SSRAM[17644] = 36'o000000000000; // 042354 SSRAM[17645] = 36'o000000000000; // 042355 SSRAM[17646] = 36'o000000000000; // 042356 SSRAM[17647] = 36'o000000000000; // 042357 SSRAM[17648] = 36'o000000000000; // 042360 SSRAM[17649] = 36'o000000000000; // 042361 SSRAM[17650] = 36'o042352040502; // 042362 SSRAM[17651] = 36'o644563640000; // 042363 SSRAM[17652] = 36'o150062456365; // 042364 SSRAM[17653] = 36'o546400434154; // 042365 SSRAM[17654] = 36'o436554416445; // 042366 SSRAM[17655] = 36'o440051564357; // 042367 SSRAM[17656] = 36'o626245436454; // 042370 SSRAM[17657] = 36'o717700000000; // 042371 SSRAM[17658] = 36'o042162041025; // 042372 SSRAM[17659] = 36'o000013000014; // 042373 SSRAM[17660] = 36'o042363040721; // 042374 SSRAM[17661] = 36'o000000000000; // 042375 SSRAM[17662] = 36'o123456765432; // 042376 SSRAM[17663] = 36'o000000000000; // 042377 SSRAM[17664] = 36'o000000000001; // 042400 SSRAM[17665] = 36'o000000000000; // 042401 SSRAM[17666] = 36'o000000000000; // 042402 SSRAM[17667] = 36'o000000000000; // 042403 SSRAM[17668] = 36'o123456765432; // 042404 SSRAM[17669] = 36'o042375040502; // 042405 SSRAM[17670] = 36'o644563640042; // 042406 SSRAM[17671] = 36'o001500624563; // 042407 SSRAM[17672] = 36'o655464004341; // 042410 SSRAM[17673] = 36'o544365544164; // 042411 SSRAM[17674] = 36'o454400515643; // 042412 SSRAM[17675] = 36'o576262454364; // 042413 SSRAM[17676] = 36'o547177000000; // 042414 SSRAM[17677] = 36'o042162041025; // 042415 SSRAM[17678] = 36'o000013000014; // 042416 SSRAM[17679] = 36'o042406040721; // 042417 SSRAM[17680] = 36'o123456765432; // 042420 SSRAM[17681] = 36'o000000000000; // 042421 SSRAM[17682] = 36'o000000000000; // 042422 SSRAM[17683] = 36'o000000000001; // 042423 SSRAM[17684] = 36'o000000000000; // 042424 SSRAM[17685] = 36'o000000000000; // 042425 SSRAM[17686] = 36'o123456765432; // 042426 SSRAM[17687] = 36'o000000000000; // 042427 SSRAM[17688] = 36'o042420040502; // 042430 SSRAM[17689] = 36'o123456765432; // 042431 SSRAM[17690] = 36'o123456765432; // 042432 SSRAM[17691] = 36'o000000000000; // 042433 SSRAM[17692] = 36'o000000000001; // 042434 SSRAM[17693] = 36'o000000000000; // 042435 SSRAM[17694] = 36'o000000000000; // 042436 SSRAM[17695] = 36'o123456765432; // 042437 SSRAM[17696] = 36'o123456765432; // 042440 SSRAM[17697] = 36'o042431040502; // 042441 SSRAM[17698] = 36'o000000000000; // 042442 SSRAM[17699] = 36'o000000000001; // 042443 SSRAM[17700] = 36'o000000000000; // 042444 SSRAM[17701] = 36'o123456765432; // 042445 SSRAM[17702] = 36'o000000000000; // 042446 SSRAM[17703] = 36'o000000000000; // 042447 SSRAM[17704] = 36'o000000000000; // 042450 SSRAM[17705] = 36'o123456765432; // 042451 SSRAM[17706] = 36'o042442040502; // 042452 SSRAM[17707] = 36'o000000000000; // 042453 SSRAM[17708] = 36'o000000000001; // 042454 SSRAM[17709] = 36'o123456765432; // 042455 SSRAM[17710] = 36'o000000000000; // 042456 SSRAM[17711] = 36'o000000000000; // 042457 SSRAM[17712] = 36'o000000000000; // 042460 SSRAM[17713] = 36'o123456765432; // 042461 SSRAM[17714] = 36'o000000000000; // 042462 SSRAM[17715] = 36'o042453040502; // 042463 SSRAM[17716] = 36'o000000000000; // 042464 SSRAM[17717] = 36'o000000000001; // 042465 SSRAM[17718] = 36'o123456765432; // 042466 SSRAM[17719] = 36'o123456765432; // 042467 SSRAM[17720] = 36'o000000000000; // 042470 SSRAM[17721] = 36'o000000000000; // 042471 SSRAM[17722] = 36'o123456765432; // 042472 SSRAM[17723] = 36'o123456765432; // 042473 SSRAM[17724] = 36'o042464040502; // 042474 SSRAM[17725] = 36'o777777777777; // 042475 SSRAM[17726] = 36'o654321012346; // 042476 SSRAM[17727] = 36'o000000000000; // 042477 SSRAM[17728] = 36'o000000000001; // 042500 SSRAM[17729] = 36'o777777777777; // 042501 SSRAM[17730] = 36'o777777777777; // 042502 SSRAM[17731] = 36'o777777777777; // 042503 SSRAM[17732] = 36'o654321012346; // 042504 SSRAM[17733] = 36'o042475040502; // 042505 SSRAM[17734] = 36'o654321012346; // 042506 SSRAM[17735] = 36'o777777777777; // 042507 SSRAM[17736] = 36'o000000000000; // 042510 SSRAM[17737] = 36'o000000000001; // 042511 SSRAM[17738] = 36'o777777777777; // 042512 SSRAM[17739] = 36'o777777777777; // 042513 SSRAM[17740] = 36'o654321012346; // 042514 SSRAM[17741] = 36'o777777777777; // 042515 SSRAM[17742] = 36'o042506040502; // 042516 SSRAM[17743] = 36'o654321012346; // 042517 SSRAM[17744] = 36'o654321012346; // 042520 SSRAM[17745] = 36'o000000000000; // 042521 SSRAM[17746] = 36'o000000000001; // 042522 SSRAM[17747] = 36'o777777777777; // 042523 SSRAM[17748] = 36'o777777777777; // 042524 SSRAM[17749] = 36'o654321012346; // 042525 SSRAM[17750] = 36'o654321012346; // 042526 SSRAM[17751] = 36'o042517040502; // 042527 SSRAM[17752] = 36'o000000000000; // 042530 SSRAM[17753] = 36'o000000000001; // 042531 SSRAM[17754] = 36'o777777777777; // 042532 SSRAM[17755] = 36'o654321012346; // 042533 SSRAM[17756] = 36'o777777777777; // 042534 SSRAM[17757] = 36'o777777777777; // 042535 SSRAM[17758] = 36'o777777777777; // 042536 SSRAM[17759] = 36'o654321012346; // 042537 SSRAM[17760] = 36'o042530040502; // 042540 SSRAM[17761] = 36'o000000000000; // 042541 SSRAM[17762] = 36'o000000000001; // 042542 SSRAM[17763] = 36'o654321012346; // 042543 SSRAM[17764] = 36'o777777777777; // 042544 SSRAM[17765] = 36'o777777777777; // 042545 SSRAM[17766] = 36'o777777777777; // 042546 SSRAM[17767] = 36'o654321012346; // 042547 SSRAM[17768] = 36'o777777777777; // 042550 SSRAM[17769] = 36'o042541040502; // 042551 SSRAM[17770] = 36'o000000000000; // 042552 SSRAM[17771] = 36'o000000000001; // 042553 SSRAM[17772] = 36'o654321012346; // 042554 SSRAM[17773] = 36'o654321012346; // 042555 SSRAM[17774] = 36'o777777777777; // 042556 SSRAM[17775] = 36'o777777777777; // 042557 SSRAM[17776] = 36'o654321012346; // 042560 SSRAM[17777] = 36'o654321012346; // 042561 SSRAM[17778] = 36'o042552040502; // 042562 SSRAM[17779] = 36'o000000000000; // 042563 SSRAM[17780] = 36'o177777777777; // 042564 SSRAM[17781] = 36'o000000000000; // 042565 SSRAM[17782] = 36'o000000000002; // 042566 SSRAM[17783] = 36'o000000000000; // 042567 SSRAM[17784] = 36'o000000000000; // 042570 SSRAM[17785] = 36'o000000000000; // 042571 SSRAM[17786] = 36'o377777777776; // 042572 SSRAM[17787] = 36'o042563040502; // 042573 SSRAM[17788] = 36'o644563640043; // 042574 SSRAM[17789] = 36'o001500624563; // 042575 SSRAM[17790] = 36'o655464004341; // 042576 SSRAM[17791] = 36'o544365544164; // 042577 SSRAM[17792] = 36'o454400515643; // 042600 SSRAM[17793] = 36'o576262454364; // 042601 SSRAM[17794] = 36'o547177000000; // 042602 SSRAM[17795] = 36'o042162041025; // 042603 SSRAM[17796] = 36'o000013000014; // 042604 SSRAM[17797] = 36'o042574040721; // 042605 SSRAM[17798] = 36'o644563640043; // 042606 SSRAM[17799] = 36'o001500604300; // 042607 SSRAM[17800] = 36'o465441476300; // 042610 SSRAM[17801] = 36'o515643576262; // 042611 SSRAM[17802] = 36'o454364001500; // 042612 SSRAM[17803] = 36'o425164630020; // 042613 SSRAM[17804] = 36'o006457002477; // 042614 SSRAM[17805] = 36'o042162041025; // 042615 SSRAM[17806] = 36'o000014040457; // 042616 SSRAM[17807] = 36'o042606040721; // 042617 SSRAM[17808] = 36'o000000000000; // 042620 SSRAM[17809] = 36'o377777777777; // 042621 SSRAM[17810] = 36'o000000000000; // 042622 SSRAM[17811] = 36'o000000000002; // 042623 SSRAM[17812] = 36'o000000000000; // 042624 SSRAM[17813] = 36'o000000000000; // 042625 SSRAM[17814] = 36'o000000000001; // 042626 SSRAM[17815] = 36'o377777777776; // 042627 SSRAM[17816] = 36'o042620040502; // 042630 SSRAM[17817] = 36'o177777777777; // 042631 SSRAM[17818] = 36'o377777777777; // 042632 SSRAM[17819] = 36'o000000000000; // 042633 SSRAM[17820] = 36'o000000000002; // 042634 SSRAM[17821] = 36'o000000000000; // 042635 SSRAM[17822] = 36'o000000000000; // 042636 SSRAM[17823] = 36'o377777777777; // 042637 SSRAM[17824] = 36'o377777777776; // 042640 SSRAM[17825] = 36'o042631040502; // 042641 SSRAM[17826] = 36'o377777777777; // 042642 SSRAM[17827] = 36'o377777777777; // 042643 SSRAM[17828] = 36'o000000000000; // 042644 SSRAM[17829] = 36'o000000000002; // 042645 SSRAM[17830] = 36'o000000000000; // 042646 SSRAM[17831] = 36'o000000000001; // 042647 SSRAM[17832] = 36'o377777777777; // 042650 SSRAM[17833] = 36'o377777777776; // 042651 SSRAM[17834] = 36'o042642040502; // 042652 SSRAM[17835] = 36'o000000000000; // 042653 SSRAM[17836] = 36'o377777777777; // 042654 SSRAM[17837] = 36'o000000000001; // 042655 SSRAM[17838] = 36'o000000000000; // 042656 SSRAM[17839] = 36'o000000000000; // 042657 SSRAM[17840] = 36'o000000000000; // 042660 SSRAM[17841] = 36'o377777777777; // 042661 SSRAM[17842] = 36'o000000000000; // 042662 SSRAM[17843] = 36'o042653040502; // 042663 SSRAM[17844] = 36'o000000000001; // 042664 SSRAM[17845] = 36'o377777777777; // 042665 SSRAM[17846] = 36'o000000000001; // 042666 SSRAM[17847] = 36'o000000000000; // 042667 SSRAM[17848] = 36'o000000000000; // 042670 SSRAM[17849] = 36'o000000000001; // 042671 SSRAM[17850] = 36'o377777777777; // 042672 SSRAM[17851] = 36'o000000000000; // 042673 SSRAM[17852] = 36'o042664040502; // 042674 SSRAM[17853] = 36'o377777777777; // 042675 SSRAM[17854] = 36'o377777777777; // 042676 SSRAM[17855] = 36'o000000000001; // 042677 SSRAM[17856] = 36'o000000000000; // 042700 SSRAM[17857] = 36'o000000000000; // 042701 SSRAM[17858] = 36'o377777777777; // 042702 SSRAM[17859] = 36'o377777777777; // 042703 SSRAM[17860] = 36'o000000000000; // 042704 SSRAM[17861] = 36'o042675040502; // 042705 SSRAM[17862] = 36'o000000000000; // 042706 SSRAM[17863] = 36'o177777777777; // 042707 SSRAM[17864] = 36'o000000000002; // 042710 SSRAM[17865] = 36'o000000000000; // 042711 SSRAM[17866] = 36'o000000000000; // 042712 SSRAM[17867] = 36'o000000000000; // 042713 SSRAM[17868] = 36'o377777777776; // 042714 SSRAM[17869] = 36'o000000000000; // 042715 SSRAM[17870] = 36'o042706040502; // 042716 SSRAM[17871] = 36'o000000000000; // 042717 SSRAM[17872] = 36'o377777777777; // 042720 SSRAM[17873] = 36'o000000000002; // 042721 SSRAM[17874] = 36'o000000000000; // 042722 SSRAM[17875] = 36'o000000000000; // 042723 SSRAM[17876] = 36'o000000000001; // 042724 SSRAM[17877] = 36'o377777777776; // 042725 SSRAM[17878] = 36'o000000000000; // 042726 SSRAM[17879] = 36'o042717040502; // 042727 SSRAM[17880] = 36'o377777777777; // 042730 SSRAM[17881] = 36'o377777777777; // 042731 SSRAM[17882] = 36'o000000000002; // 042732 SSRAM[17883] = 36'o000000000000; // 042733 SSRAM[17884] = 36'o000000000001; // 042734 SSRAM[17885] = 36'o377777777777; // 042735 SSRAM[17886] = 36'o377777777776; // 042736 SSRAM[17887] = 36'o000000000000; // 042737 SSRAM[17888] = 36'o042730040502; // 042740 SSRAM[17889] = 36'o000000000000; // 042741 SSRAM[17890] = 36'o000000000002; // 042742 SSRAM[17891] = 36'o000000000000; // 042743 SSRAM[17892] = 36'o177777777777; // 042744 SSRAM[17893] = 36'o000000000000; // 042745 SSRAM[17894] = 36'o000000000000; // 042746 SSRAM[17895] = 36'o000000000000; // 042747 SSRAM[17896] = 36'o377777777776; // 042750 SSRAM[17897] = 36'o042741040502; // 042751 SSRAM[17898] = 36'o000000000000; // 042752 SSRAM[17899] = 36'o000000000002; // 042753 SSRAM[17900] = 36'o000000000000; // 042754 SSRAM[17901] = 36'o377777777777; // 042755 SSRAM[17902] = 36'o000000000000; // 042756 SSRAM[17903] = 36'o000000000000; // 042757 SSRAM[17904] = 36'o000000000001; // 042760 SSRAM[17905] = 36'o377777777776; // 042761 SSRAM[17906] = 36'o042752040502; // 042762 SSRAM[17907] = 36'o000000000000; // 042763 SSRAM[17908] = 36'o000000000002; // 042764 SSRAM[17909] = 36'o177777777777; // 042765 SSRAM[17910] = 36'o377777777777; // 042766 SSRAM[17911] = 36'o000000000000; // 042767 SSRAM[17912] = 36'o000000000000; // 042770 SSRAM[17913] = 36'o377777777777; // 042771 SSRAM[17914] = 36'o377777777776; // 042772 SSRAM[17915] = 36'o042763040502; // 042773 SSRAM[17916] = 36'o000000000000; // 042774 SSRAM[17917] = 36'o000000000002; // 042775 SSRAM[17918] = 36'o377777777777; // 042776 SSRAM[17919] = 36'o377777777777; // 042777 SSRAM[17920] = 36'o000000000000; // 043000 SSRAM[17921] = 36'o000000000001; // 043001 SSRAM[17922] = 36'o377777777777; // 043002 SSRAM[17923] = 36'o377777777776; // 043003 SSRAM[17924] = 36'o042774040502; // 043004 SSRAM[17925] = 36'o000000000001; // 043005 SSRAM[17926] = 36'o000000000000; // 043006 SSRAM[17927] = 36'o000000000000; // 043007 SSRAM[17928] = 36'o377777777777; // 043010 SSRAM[17929] = 36'o000000000000; // 043011 SSRAM[17930] = 36'o000000000000; // 043012 SSRAM[17931] = 36'o377777777777; // 043013 SSRAM[17932] = 36'o000000000000; // 043014 SSRAM[17933] = 36'o043005040502; // 043015 SSRAM[17934] = 36'o000000000001; // 043016 SSRAM[17935] = 36'o000000000000; // 043017 SSRAM[17936] = 36'o000000000001; // 043020 SSRAM[17937] = 36'o377777777777; // 043021 SSRAM[17938] = 36'o000000000000; // 043022 SSRAM[17939] = 36'o000000000001; // 043023 SSRAM[17940] = 36'o377777777777; // 043024 SSRAM[17941] = 36'o000000000000; // 043025 SSRAM[17942] = 36'o043016040502; // 043026 SSRAM[17943] = 36'o000000000001; // 043027 SSRAM[17944] = 36'o000000000000; // 043030 SSRAM[17945] = 36'o377777777777; // 043031 SSRAM[17946] = 36'o377777777777; // 043032 SSRAM[17947] = 36'o000000000000; // 043033 SSRAM[17948] = 36'o377777777777; // 043034 SSRAM[17949] = 36'o377777777777; // 043035 SSRAM[17950] = 36'o000000000000; // 043036 SSRAM[17951] = 36'o043027040502; // 043037 SSRAM[17952] = 36'o000000000002; // 043040 SSRAM[17953] = 36'o000000000000; // 043041 SSRAM[17954] = 36'o000000000000; // 043042 SSRAM[17955] = 36'o177777777777; // 043043 SSRAM[17956] = 36'o000000000000; // 043044 SSRAM[17957] = 36'o000000000000; // 043045 SSRAM[17958] = 36'o377777777776; // 043046 SSRAM[17959] = 36'o000000000000; // 043047 SSRAM[17960] = 36'o043040040502; // 043050 SSRAM[17961] = 36'o000000000002; // 043051 SSRAM[17962] = 36'o000000000000; // 043052 SSRAM[17963] = 36'o000000000000; // 043053 SSRAM[17964] = 36'o377777777777; // 043054 SSRAM[17965] = 36'o000000000000; // 043055 SSRAM[17966] = 36'o000000000001; // 043056 SSRAM[17967] = 36'o377777777776; // 043057 SSRAM[17968] = 36'o000000000000; // 043060 SSRAM[17969] = 36'o043051040502; // 043061 SSRAM[17970] = 36'o000000000002; // 043062 SSRAM[17971] = 36'o000000000000; // 043063 SSRAM[17972] = 36'o377777777777; // 043064 SSRAM[17973] = 36'o377777777777; // 043065 SSRAM[17974] = 36'o000000000001; // 043066 SSRAM[17975] = 36'o377777777777; // 043067 SSRAM[17976] = 36'o377777777776; // 043070 SSRAM[17977] = 36'o000000000000; // 043071 SSRAM[17978] = 36'o043062040502; // 043072 SSRAM[17979] = 36'o777777777777; // 043073 SSRAM[17980] = 36'o600000000000; // 043074 SSRAM[17981] = 36'o000000000000; // 043075 SSRAM[17982] = 36'o000000000002; // 043076 SSRAM[17983] = 36'o777777777777; // 043077 SSRAM[17984] = 36'o777777777777; // 043100 SSRAM[17985] = 36'o777777777777; // 043101 SSRAM[17986] = 36'o400000000000; // 043102 SSRAM[17987] = 36'o043073040502; // 043103 SSRAM[17988] = 36'o644563640044; // 043104 SSRAM[17989] = 36'o001500624563; // 043105 SSRAM[17990] = 36'o655464004341; // 043106 SSRAM[17991] = 36'o544365544164; // 043107 SSRAM[17992] = 36'o454400515643; // 043110 SSRAM[17993] = 36'o576262454364; // 043111 SSRAM[17994] = 36'o547177000000; // 043112 SSRAM[17995] = 36'o042162041025; // 043113 SSRAM[17996] = 36'o000013000014; // 043114 SSRAM[17997] = 36'o043104040721; // 043115 SSRAM[17998] = 36'o644563640044; // 043116 SSRAM[17999] = 36'o001500604300; // 043117 SSRAM[18000] = 36'o465441476300; // 043120 SSRAM[18001] = 36'o515643576262; // 043121 SSRAM[18002] = 36'o454364001500; // 043122 SSRAM[18003] = 36'o425164630020; // 043123 SSRAM[18004] = 36'o006457002477; // 043124 SSRAM[18005] = 36'o042162041025; // 043125 SSRAM[18006] = 36'o000014040457; // 043126 SSRAM[18007] = 36'o043116040721; // 043127 SSRAM[18008] = 36'o777777777777; // 043130 SSRAM[18009] = 36'o400000000000; // 043131 SSRAM[18010] = 36'o000000000000; // 043132 SSRAM[18011] = 36'o000000000002; // 043133 SSRAM[18012] = 36'o777777777777; // 043134 SSRAM[18013] = 36'o777777777777; // 043135 SSRAM[18014] = 36'o777777777776; // 043136 SSRAM[18015] = 36'o400000000000; // 043137 SSRAM[18016] = 36'o043130040502; // 043140 SSRAM[18017] = 36'o600000000000; // 043141 SSRAM[18018] = 36'o400000000000; // 043142 SSRAM[18019] = 36'o000000000000; // 043143 SSRAM[18020] = 36'o000000000002; // 043144 SSRAM[18021] = 36'o777777777777; // 043145 SSRAM[18022] = 36'o777777777777; // 043146 SSRAM[18023] = 36'o400000000000; // 043147 SSRAM[18024] = 36'o400000000000; // 043150 SSRAM[18025] = 36'o043141040502; // 043151 SSRAM[18026] = 36'o400000000000; // 043152 SSRAM[18027] = 36'o400000000000; // 043153 SSRAM[18028] = 36'o000000000000; // 043154 SSRAM[18029] = 36'o000000000002; // 043155 SSRAM[18030] = 36'o777777777777; // 043156 SSRAM[18031] = 36'o777777777776; // 043157 SSRAM[18032] = 36'o400000000000; // 043160 SSRAM[18033] = 36'o400000000000; // 043161 SSRAM[18034] = 36'o043152040502; // 043162 SSRAM[18035] = 36'o777777777777; // 043163 SSRAM[18036] = 36'o400000000000; // 043164 SSRAM[18037] = 36'o000000000001; // 043165 SSRAM[18038] = 36'o000000000000; // 043166 SSRAM[18039] = 36'o777777777777; // 043167 SSRAM[18040] = 36'o777777777777; // 043170 SSRAM[18041] = 36'o400000000000; // 043171 SSRAM[18042] = 36'o400000000000; // 043172 SSRAM[18043] = 36'o043163040502; // 043173 SSRAM[18044] = 36'o777777777776; // 043174 SSRAM[18045] = 36'o400000000000; // 043175 SSRAM[18046] = 36'o000000000001; // 043176 SSRAM[18047] = 36'o000000000000; // 043177 SSRAM[18048] = 36'o777777777777; // 043200 SSRAM[18049] = 36'o777777777776; // 043201 SSRAM[18050] = 36'o400000000000; // 043202 SSRAM[18051] = 36'o400000000000; // 043203 SSRAM[18052] = 36'o043174040502; // 043204 SSRAM[18053] = 36'o400000000000; // 043205 SSRAM[18054] = 36'o400000000000; // 043206 SSRAM[18055] = 36'o000000000001; // 043207 SSRAM[18056] = 36'o000000000000; // 043210 SSRAM[18057] = 36'o777777777777; // 043211 SSRAM[18058] = 36'o400000000000; // 043212 SSRAM[18059] = 36'o400000000000; // 043213 SSRAM[18060] = 36'o400000000000; // 043214 SSRAM[18061] = 36'o043205040502; // 043215 SSRAM[18062] = 36'o777777777777; // 043216 SSRAM[18063] = 36'o600000000000; // 043217 SSRAM[18064] = 36'o000000000002; // 043220 SSRAM[18065] = 36'o000000000000; // 043221 SSRAM[18066] = 36'o777777777777; // 043222 SSRAM[18067] = 36'o777777777777; // 043223 SSRAM[18068] = 36'o400000000000; // 043224 SSRAM[18069] = 36'o400000000000; // 043225 SSRAM[18070] = 36'o043216040502; // 043226 SSRAM[18071] = 36'o777777777777; // 043227 SSRAM[18072] = 36'o400000000000; // 043230 SSRAM[18073] = 36'o000000000002; // 043231 SSRAM[18074] = 36'o000000000000; // 043232 SSRAM[18075] = 36'o777777777777; // 043233 SSRAM[18076] = 36'o777777777776; // 043234 SSRAM[18077] = 36'o400000000000; // 043235 SSRAM[18078] = 36'o400000000000; // 043236 SSRAM[18079] = 36'o043227040502; // 043237 SSRAM[18080] = 36'o400000000000; // 043240 SSRAM[18081] = 36'o400000000000; // 043241 SSRAM[18082] = 36'o000000000002; // 043242 SSRAM[18083] = 36'o000000000000; // 043243 SSRAM[18084] = 36'o777777777776; // 043244 SSRAM[18085] = 36'o400000000000; // 043245 SSRAM[18086] = 36'o400000000000; // 043246 SSRAM[18087] = 36'o400000000000; // 043247 SSRAM[18088] = 36'o043240040502; // 043250 SSRAM[18089] = 36'o000000000000; // 043251 SSRAM[18090] = 36'o000000000002; // 043252 SSRAM[18091] = 36'o777777777777; // 043253 SSRAM[18092] = 36'o600000000000; // 043254 SSRAM[18093] = 36'o777777777777; // 043255 SSRAM[18094] = 36'o777777777777; // 043256 SSRAM[18095] = 36'o777777777777; // 043257 SSRAM[18096] = 36'o400000000000; // 043260 SSRAM[18097] = 36'o043251040502; // 043261 SSRAM[18098] = 36'o000000000000; // 043262 SSRAM[18099] = 36'o000000000002; // 043263 SSRAM[18100] = 36'o777777777777; // 043264 SSRAM[18101] = 36'o400000000000; // 043265 SSRAM[18102] = 36'o777777777777; // 043266 SSRAM[18103] = 36'o777777777777; // 043267 SSRAM[18104] = 36'o777777777776; // 043270 SSRAM[18105] = 36'o400000000000; // 043271 SSRAM[18106] = 36'o043262040502; // 043272 SSRAM[18107] = 36'o000000000000; // 043273 SSRAM[18108] = 36'o000000000002; // 043274 SSRAM[18109] = 36'o600000000000; // 043275 SSRAM[18110] = 36'o400000000000; // 043276 SSRAM[18111] = 36'o777777777777; // 043277 SSRAM[18112] = 36'o777777777777; // 043300 SSRAM[18113] = 36'o400000000000; // 043301 SSRAM[18114] = 36'o400000000000; // 043302 SSRAM[18115] = 36'o043273040502; // 043303 SSRAM[18116] = 36'o000000000000; // 043304 SSRAM[18117] = 36'o000000000002; // 043305 SSRAM[18118] = 36'o400000000000; // 043306 SSRAM[18119] = 36'o400000000000; // 043307 SSRAM[18120] = 36'o777777777777; // 043310 SSRAM[18121] = 36'o777777777776; // 043311 SSRAM[18122] = 36'o400000000000; // 043312 SSRAM[18123] = 36'o400000000000; // 043313 SSRAM[18124] = 36'o043304040502; // 043314 SSRAM[18125] = 36'o000000000001; // 043315 SSRAM[18126] = 36'o000000000000; // 043316 SSRAM[18127] = 36'o777777777777; // 043317 SSRAM[18128] = 36'o400000000000; // 043320 SSRAM[18129] = 36'o777777777777; // 043321 SSRAM[18130] = 36'o777777777777; // 043322 SSRAM[18131] = 36'o400000000000; // 043323 SSRAM[18132] = 36'o400000000000; // 043324 SSRAM[18133] = 36'o043315040502; // 043325 SSRAM[18134] = 36'o000000000001; // 043326 SSRAM[18135] = 36'o000000000000; // 043327 SSRAM[18136] = 36'o777777777776; // 043330 SSRAM[18137] = 36'o400000000000; // 043331 SSRAM[18138] = 36'o777777777777; // 043332 SSRAM[18139] = 36'o777777777776; // 043333 SSRAM[18140] = 36'o400000000000; // 043334 SSRAM[18141] = 36'o400000000000; // 043335 SSRAM[18142] = 36'o043326040502; // 043336 SSRAM[18143] = 36'o000000000001; // 043337 SSRAM[18144] = 36'o000000000000; // 043340 SSRAM[18145] = 36'o400000000000; // 043341 SSRAM[18146] = 36'o400000000000; // 043342 SSRAM[18147] = 36'o777777777777; // 043343 SSRAM[18148] = 36'o400000000000; // 043344 SSRAM[18149] = 36'o400000000000; // 043345 SSRAM[18150] = 36'o400000000000; // 043346 SSRAM[18151] = 36'o043337040502; // 043347 SSRAM[18152] = 36'o000000000002; // 043350 SSRAM[18153] = 36'o000000000000; // 043351 SSRAM[18154] = 36'o777777777777; // 043352 SSRAM[18155] = 36'o600000000000; // 043353 SSRAM[18156] = 36'o777777777777; // 043354 SSRAM[18157] = 36'o777777777777; // 043355 SSRAM[18158] = 36'o400000000000; // 043356 SSRAM[18159] = 36'o400000000000; // 043357 SSRAM[18160] = 36'o043350040502; // 043360 SSRAM[18161] = 36'o000000000002; // 043361 SSRAM[18162] = 36'o000000000000; // 043362 SSRAM[18163] = 36'o777777777777; // 043363 SSRAM[18164] = 36'o400000000000; // 043364 SSRAM[18165] = 36'o777777777777; // 043365 SSRAM[18166] = 36'o777777777776; // 043366 SSRAM[18167] = 36'o400000000000; // 043367 SSRAM[18168] = 36'o400000000000; // 043370 SSRAM[18169] = 36'o043361040502; // 043371 SSRAM[18170] = 36'o000000000002; // 043372 SSRAM[18171] = 36'o000000000000; // 043373 SSRAM[18172] = 36'o400000000000; // 043374 SSRAM[18173] = 36'o400000000000; // 043375 SSRAM[18174] = 36'o777777777776; // 043376 SSRAM[18175] = 36'o400000000000; // 043377 SSRAM[18176] = 36'o400000000000; // 043400 SSRAM[18177] = 36'o400000000000; // 043401 SSRAM[18178] = 36'o043372040502; // 043402 SSRAM[18179] = 36'o525252525252; // 043403 SSRAM[18180] = 36'o252525252525; // 043404 SSRAM[18181] = 36'o644563640045; // 043405 SSRAM[18182] = 36'o001500624563; // 043406 SSRAM[18183] = 36'o655464005156; // 043407 SSRAM[18184] = 36'o435762624543; // 043410 SSRAM[18185] = 36'o647700000000; // 043411 SSRAM[18186] = 36'o042162041025; // 043412 SSRAM[18187] = 36'o041725000013; // 043413 SSRAM[18188] = 36'o043405040721; // 043414 SSRAM[18189] = 36'o644563640045; // 043415 SSRAM[18190] = 36'o001500604300; // 043416 SSRAM[18191] = 36'o465441476300; // 043417 SSRAM[18192] = 36'o515643576262; // 043420 SSRAM[18193] = 36'o454364001500; // 043421 SSRAM[18194] = 36'o544546640024; // 043422 SSRAM[18195] = 36'o004251646377; // 043423 SSRAM[18196] = 36'o042162041025; // 043424 SSRAM[18197] = 36'o000001036407; // 043425 SSRAM[18198] = 36'o043415040721; // 043426 SSRAM[18199] = 36'o777777777777; // 043427 SSRAM[18200] = 36'o777777777776; // 043430 SSRAM[18201] = 36'o777777777777; // 043431 SSRAM[18202] = 36'o777777777775; // 043432 SSRAM[18203] = 36'o000000000000; // 043433 SSRAM[18204] = 36'o000000000000; // 043434 SSRAM[18205] = 36'o000000000000; // 043435 SSRAM[18206] = 36'o000000000006; // 043436 SSRAM[18207] = 36'o043427040502; // 043437 SSRAM[18208] = 36'o644563640046; // 043440 SSRAM[18209] = 36'o001500624563; // 043441 SSRAM[18210] = 36'o655464004341; // 043442 SSRAM[18211] = 36'o544365544164; // 043443 SSRAM[18212] = 36'o454400515643; // 043444 SSRAM[18213] = 36'o576262454364; // 043445 SSRAM[18214] = 36'o547177000000; // 043446 SSRAM[18215] = 36'o042162041025; // 043447 SSRAM[18216] = 36'o000013000014; // 043450 SSRAM[18217] = 36'o043440040721; // 043451 SSRAM[18218] = 36'o644563640046; // 043452 SSRAM[18219] = 36'o001500604300; // 043453 SSRAM[18220] = 36'o465441476300; // 043454 SSRAM[18221] = 36'o515643576262; // 043455 SSRAM[18222] = 36'o454364001500; // 043456 SSRAM[18223] = 36'o425164630020; // 043457 SSRAM[18224] = 36'o006457002477; // 043460 SSRAM[18225] = 36'o042162041025; // 043461 SSRAM[18226] = 36'o000014040457; // 043462 SSRAM[18227] = 36'o043452040721; // 043463 SSRAM[18228] = 36'o777777777776; // 043464 SSRAM[18229] = 36'o400000000000; // 043465 SSRAM[18230] = 36'o777777777777; // 043466 SSRAM[18231] = 36'o777777777775; // 043467 SSRAM[18232] = 36'o000000000000; // 043470 SSRAM[18233] = 36'o000000000000; // 043471 SSRAM[18234] = 36'o000000000006; // 043472 SSRAM[18235] = 36'o000000000000; // 043473 SSRAM[18236] = 36'o043464040502; // 043474 SSRAM[18237] = 36'o777777777777; // 043475 SSRAM[18238] = 36'o777777777776; // 043476 SSRAM[18239] = 36'o777777777775; // 043477 SSRAM[18240] = 36'o400000000000; // 043500 SSRAM[18241] = 36'o000000000000; // 043501 SSRAM[18242] = 36'o000000000000; // 043502 SSRAM[18243] = 36'o000000000006; // 043503 SSRAM[18244] = 36'o000000000000; // 043504 SSRAM[18245] = 36'o043475040502; // 043505 SSRAM[18246] = 36'o777777777776; // 043506 SSRAM[18247] = 36'o400000000000; // 043507 SSRAM[18248] = 36'o777777777775; // 043510 SSRAM[18249] = 36'o400000000000; // 043511 SSRAM[18250] = 36'o000000000000; // 043512 SSRAM[18251] = 36'o000000000006; // 043513 SSRAM[18252] = 36'o000000000000; // 043514 SSRAM[18253] = 36'o000000000000; // 043515 SSRAM[18254] = 36'o043506040502; // 043516 SSRAM[18255] = 36'o000000000000; // 043517 SSRAM[18256] = 36'o000000000002; // 043520 SSRAM[18257] = 36'o000000000000; // 043521 SSRAM[18258] = 36'o400000000003; // 043522 SSRAM[18259] = 36'o000000000000; // 043523 SSRAM[18260] = 36'o000000000000; // 043524 SSRAM[18261] = 36'o000000000000; // 043525 SSRAM[18262] = 36'o000000000006; // 043526 SSRAM[18263] = 36'o043517040502; // 043527 SSRAM[18264] = 36'o644563640047; // 043530 SSRAM[18265] = 36'o001500624563; // 043531 SSRAM[18266] = 36'o655464004341; // 043532 SSRAM[18267] = 36'o544365544164; // 043533 SSRAM[18268] = 36'o454400515643; // 043534 SSRAM[18269] = 36'o576262454364; // 043535 SSRAM[18270] = 36'o547177000000; // 043536 SSRAM[18271] = 36'o042162041025; // 043537 SSRAM[18272] = 36'o000013000014; // 043540 SSRAM[18273] = 36'o043530040721; // 043541 SSRAM[18274] = 36'o644563640047; // 043542 SSRAM[18275] = 36'o001500604300; // 043543 SSRAM[18276] = 36'o465441476300; // 043544 SSRAM[18277] = 36'o515643576262; // 043545 SSRAM[18278] = 36'o454364001500; // 043546 SSRAM[18279] = 36'o425164630020; // 043547 SSRAM[18280] = 36'o006457002477; // 043550 SSRAM[18281] = 36'o042162041025; // 043551 SSRAM[18282] = 36'o000014040457; // 043552 SSRAM[18283] = 36'o043542040721; // 043553 SSRAM[18284] = 36'o000000000000; // 043554 SSRAM[18285] = 36'o400000000002; // 043555 SSRAM[18286] = 36'o000000000000; // 043556 SSRAM[18287] = 36'o400000000003; // 043557 SSRAM[18288] = 36'o000000000000; // 043560 SSRAM[18289] = 36'o000000000000; // 043561 SSRAM[18290] = 36'o000000000000; // 043562 SSRAM[18291] = 36'o000000000006; // 043563 SSRAM[18292] = 36'o043554040502; // 043564 SSRAM[18293] = 36'o000000000000; // 043565 SSRAM[18294] = 36'o400000000002; // 043566 SSRAM[18295] = 36'o000000000000; // 043567 SSRAM[18296] = 36'o000000000003; // 043570 SSRAM[18297] = 36'o000000000000; // 043571 SSRAM[18298] = 36'o000000000000; // 043572 SSRAM[18299] = 36'o000000000000; // 043573 SSRAM[18300] = 36'o000000000006; // 043574 SSRAM[18301] = 36'o043565040502; // 043575 SSRAM[18302] = 36'o000000000000; // 043576 SSRAM[18303] = 36'o000000000002; // 043577 SSRAM[18304] = 36'o777777777777; // 043600 SSRAM[18305] = 36'o377777777775; // 043601 SSRAM[18306] = 36'o777777777777; // 043602 SSRAM[18307] = 36'o777777777777; // 043603 SSRAM[18308] = 36'o777777777777; // 043604 SSRAM[18309] = 36'o777777777772; // 043605 SSRAM[18310] = 36'o043576040502; // 043606 SSRAM[18311] = 36'o000000000000; // 043607 SSRAM[18312] = 36'o400000000002; // 043610 SSRAM[18313] = 36'o777777777777; // 043611 SSRAM[18314] = 36'o377777777775; // 043612 SSRAM[18315] = 36'o777777777777; // 043613 SSRAM[18316] = 36'o777777777777; // 043614 SSRAM[18317] = 36'o777777777777; // 043615 SSRAM[18318] = 36'o777777777772; // 043616 SSRAM[18319] = 36'o043607040502; // 043617 SSRAM[18320] = 36'o000000000000; // 043620 SSRAM[18321] = 36'o400000000002; // 043621 SSRAM[18322] = 36'o777777777777; // 043622 SSRAM[18323] = 36'o777777777775; // 043623 SSRAM[18324] = 36'o777777777777; // 043624 SSRAM[18325] = 36'o777777777777; // 043625 SSRAM[18326] = 36'o777777777777; // 043626 SSRAM[18327] = 36'o777777777772; // 043627 SSRAM[18328] = 36'o043620040502; // 043630 SSRAM[18329] = 36'o777777777777; // 043631 SSRAM[18330] = 36'o777777777776; // 043632 SSRAM[18331] = 36'o000000000000; // 043633 SSRAM[18332] = 36'o400000000003; // 043634 SSRAM[18333] = 36'o777777777777; // 043635 SSRAM[18334] = 36'o777777777777; // 043636 SSRAM[18335] = 36'o777777777777; // 043637 SSRAM[18336] = 36'o777777777772; // 043640 SSRAM[18337] = 36'o043631040502; // 043641 SSRAM[18338] = 36'o777777777777; // 043642 SSRAM[18339] = 36'o377777777776; // 043643 SSRAM[18340] = 36'o000000000000; // 043644 SSRAM[18341] = 36'o400000000003; // 043645 SSRAM[18342] = 36'o777777777777; // 043646 SSRAM[18343] = 36'o777777777777; // 043647 SSRAM[18344] = 36'o777777777777; // 043650 SSRAM[18345] = 36'o777777777772; // 043651 SSRAM[18346] = 36'o043642040502; // 043652 SSRAM[18347] = 36'o777777777777; // 043653 SSRAM[18348] = 36'o377777777776; // 043654 SSRAM[18349] = 36'o000000000000; // 043655 SSRAM[18350] = 36'o000000000003; // 043656 SSRAM[18351] = 36'o777777777777; // 043657 SSRAM[18352] = 36'o777777777777; // 043660 SSRAM[18353] = 36'o777777777777; // 043661 SSRAM[18354] = 36'o777777777772; // 043662 SSRAM[18355] = 36'o043653040502; // 043663 SSRAM[18356] = 36'o777777777777; // 043664 SSRAM[18357] = 36'o777777777776; // 043665 SSRAM[18358] = 36'o777777777777; // 043666 SSRAM[18359] = 36'o377777777775; // 043667 SSRAM[18360] = 36'o000000000000; // 043670 SSRAM[18361] = 36'o000000000000; // 043671 SSRAM[18362] = 36'o000000000000; // 043672 SSRAM[18363] = 36'o000000000006; // 043673 SSRAM[18364] = 36'o043664040502; // 043674 SSRAM[18365] = 36'o777777777777; // 043675 SSRAM[18366] = 36'o377777777776; // 043676 SSRAM[18367] = 36'o777777777777; // 043677 SSRAM[18368] = 36'o377777777775; // 043700 SSRAM[18369] = 36'o000000000000; // 043701 SSRAM[18370] = 36'o000000000000; // 043702 SSRAM[18371] = 36'o000000000000; // 043703 SSRAM[18372] = 36'o000000000006; // 043704 SSRAM[18373] = 36'o043675040502; // 043705 SSRAM[18374] = 36'o777777777777; // 043706 SSRAM[18375] = 36'o377777777776; // 043707 SSRAM[18376] = 36'o777777777777; // 043710 SSRAM[18377] = 36'o777777777775; // 043711 SSRAM[18378] = 36'o000000000000; // 043712 SSRAM[18379] = 36'o000000000000; // 043713 SSRAM[18380] = 36'o000000000000; // 043714 SSRAM[18381] = 36'o000000000006; // 043715 SSRAM[18382] = 36'o043706040502; // 043716 SSRAM[18383] = 36'o000000000002; // 043717 SSRAM[18384] = 36'o000000000000; // 043720 SSRAM[18385] = 36'o000000000003; // 043721 SSRAM[18386] = 36'o400000000000; // 043722 SSRAM[18387] = 36'o000000000000; // 043723 SSRAM[18388] = 36'o000000000006; // 043724 SSRAM[18389] = 36'o000000000000; // 043725 SSRAM[18390] = 36'o000000000000; // 043726 SSRAM[18391] = 36'o043717040502; // 043727 SSRAM[18392] = 36'o000000000002; // 043730 SSRAM[18393] = 36'o400000000000; // 043731 SSRAM[18394] = 36'o000000000003; // 043732 SSRAM[18395] = 36'o400000000000; // 043733 SSRAM[18396] = 36'o000000000000; // 043734 SSRAM[18397] = 36'o000000000006; // 043735 SSRAM[18398] = 36'o000000000000; // 043736 SSRAM[18399] = 36'o000000000000; // 043737 SSRAM[18400] = 36'o043730040502; // 043740 SSRAM[18401] = 36'o000000000002; // 043741 SSRAM[18402] = 36'o400000000000; // 043742 SSRAM[18403] = 36'o000000000003; // 043743 SSRAM[18404] = 36'o000000000000; // 043744 SSRAM[18405] = 36'o000000000000; // 043745 SSRAM[18406] = 36'o000000000006; // 043746 SSRAM[18407] = 36'o000000000000; // 043747 SSRAM[18408] = 36'o000000000000; // 043750 SSRAM[18409] = 36'o043741040502; // 043751 SSRAM[18410] = 36'o000000000002; // 043752 SSRAM[18411] = 36'o000000000000; // 043753 SSRAM[18412] = 36'o777777777775; // 043754 SSRAM[18413] = 36'o000000000000; // 043755 SSRAM[18414] = 36'o777777777777; // 043756 SSRAM[18415] = 36'o777777777772; // 043757 SSRAM[18416] = 36'o400000000000; // 043760 SSRAM[18417] = 36'o400000000000; // 043761 SSRAM[18418] = 36'o043752040502; // 043762 SSRAM[18419] = 36'o000000000002; // 043763 SSRAM[18420] = 36'o400000000000; // 043764 SSRAM[18421] = 36'o777777777775; // 043765 SSRAM[18422] = 36'o000000000000; // 043766 SSRAM[18423] = 36'o777777777777; // 043767 SSRAM[18424] = 36'o777777777772; // 043770 SSRAM[18425] = 36'o400000000000; // 043771 SSRAM[18426] = 36'o400000000000; // 043772 SSRAM[18427] = 36'o043763040502; // 043773 SSRAM[18428] = 36'o000000000002; // 043774 SSRAM[18429] = 36'o400000000000; // 043775 SSRAM[18430] = 36'o777777777775; // 043776 SSRAM[18431] = 36'o400000000000; // 043777 SSRAM[18432] = 36'o777777777777; // 044000 SSRAM[18433] = 36'o777777777772; // 044001 SSRAM[18434] = 36'o400000000000; // 044002 SSRAM[18435] = 36'o400000000000; // 044003 SSRAM[18436] = 36'o043774040502; // 044004 SSRAM[18437] = 36'o777777777776; // 044005 SSRAM[18438] = 36'o400000000000; // 044006 SSRAM[18439] = 36'o000000000003; // 044007 SSRAM[18440] = 36'o400000000000; // 044010 SSRAM[18441] = 36'o777777777777; // 044011 SSRAM[18442] = 36'o777777777772; // 044012 SSRAM[18443] = 36'o400000000000; // 044013 SSRAM[18444] = 36'o400000000000; // 044014 SSRAM[18445] = 36'o044005040502; // 044015 SSRAM[18446] = 36'o777777777776; // 044016 SSRAM[18447] = 36'o000000000000; // 044017 SSRAM[18448] = 36'o000000000003; // 044020 SSRAM[18449] = 36'o400000000000; // 044021 SSRAM[18450] = 36'o777777777777; // 044022 SSRAM[18451] = 36'o777777777772; // 044023 SSRAM[18452] = 36'o400000000000; // 044024 SSRAM[18453] = 36'o400000000000; // 044025 SSRAM[18454] = 36'o044016040502; // 044026 SSRAM[18455] = 36'o777777777776; // 044027 SSRAM[18456] = 36'o000000000000; // 044030 SSRAM[18457] = 36'o000000000003; // 044031 SSRAM[18458] = 36'o000000000000; // 044032 SSRAM[18459] = 36'o777777777777; // 044033 SSRAM[18460] = 36'o777777777772; // 044034 SSRAM[18461] = 36'o400000000000; // 044035 SSRAM[18462] = 36'o400000000000; // 044036 SSRAM[18463] = 36'o044027040502; // 044037 SSRAM[18464] = 36'o777777777776; // 044040 SSRAM[18465] = 36'o400000000000; // 044041 SSRAM[18466] = 36'o777777777775; // 044042 SSRAM[18467] = 36'o000000000000; // 044043 SSRAM[18468] = 36'o000000000000; // 044044 SSRAM[18469] = 36'o000000000006; // 044045 SSRAM[18470] = 36'o000000000000; // 044046 SSRAM[18471] = 36'o000000000000; // 044047 SSRAM[18472] = 36'o044040040502; // 044050 SSRAM[18473] = 36'o777777777776; // 044051 SSRAM[18474] = 36'o000000000000; // 044052 SSRAM[18475] = 36'o777777777775; // 044053 SSRAM[18476] = 36'o000000000000; // 044054 SSRAM[18477] = 36'o000000000000; // 044055 SSRAM[18478] = 36'o000000000006; // 044056 SSRAM[18479] = 36'o000000000000; // 044057 SSRAM[18480] = 36'o000000000000; // 044060 SSRAM[18481] = 36'o044051040502; // 044061 SSRAM[18482] = 36'o777777777776; // 044062 SSRAM[18483] = 36'o000000000000; // 044063 SSRAM[18484] = 36'o777777777775; // 044064 SSRAM[18485] = 36'o400000000000; // 044065 SSRAM[18486] = 36'o000000000000; // 044066 SSRAM[18487] = 36'o000000000006; // 044067 SSRAM[18488] = 36'o000000000000; // 044070 SSRAM[18489] = 36'o000000000000; // 044071 SSRAM[18490] = 36'o044062040502; // 044072 SSRAM[18491] = 36'o444451660064; // 044073 SSRAM[18492] = 36'o456364770000; // 044074 SSRAM[18493] = 36'o000000000000; // 044075 SSRAM[18494] = 36'o000000000000; // 044076 SSRAM[18495] = 36'o000000000000; // 044077 SSRAM[18496] = 36'o123456765432; // 044100 SSRAM[18497] = 36'o000000000000; // 044101 SSRAM[18498] = 36'o000000000001; // 044102 SSRAM[18499] = 36'o000000000000; // 044103 SSRAM[18500] = 36'o123456765432; // 044104 SSRAM[18501] = 36'o000000000000; // 044105 SSRAM[18502] = 36'o000000000000; // 044106 SSRAM[18503] = 36'o044075040544; // 044107 SSRAM[18504] = 36'o644563640041; // 044110 SSRAM[18505] = 36'o001500616557; // 044111 SSRAM[18506] = 36'o645145566417; // 044112 SSRAM[18507] = 36'o624555415156; // 044113 SSRAM[18508] = 36'o444562005156; // 044114 SSRAM[18509] = 36'o435762624543; // 044115 SSRAM[18510] = 36'o647700000000; // 044116 SSRAM[18511] = 36'o044073041025; // 044117 SSRAM[18512] = 36'o000013000014; // 044120 SSRAM[18513] = 36'o044110040754; // 044121 SSRAM[18514] = 36'o000000000000; // 044122 SSRAM[18515] = 36'o000000000000; // 044123 SSRAM[18516] = 36'o123456765432; // 044124 SSRAM[18517] = 36'o000000000000; // 044125 SSRAM[18518] = 36'o000000000000; // 044126 SSRAM[18519] = 36'o000000000001; // 044127 SSRAM[18520] = 36'o123456765432; // 044130 SSRAM[18521] = 36'o000000000000; // 044131 SSRAM[18522] = 36'o000000000000; // 044132 SSRAM[18523] = 36'o000000000000; // 044133 SSRAM[18524] = 36'o044122040544; // 044134 SSRAM[18525] = 36'o000000000000; // 044135 SSRAM[18526] = 36'o000000000000; // 044136 SSRAM[18527] = 36'o000000000000; // 044137 SSRAM[18528] = 36'o123456765432; // 044140 SSRAM[18529] = 36'o000000000000; // 044141 SSRAM[18530] = 36'o123456765432; // 044142 SSRAM[18531] = 36'o000000000000; // 044143 SSRAM[18532] = 36'o000000000001; // 044144 SSRAM[18533] = 36'o000000000000; // 044145 SSRAM[18534] = 36'o000000000000; // 044146 SSRAM[18535] = 36'o044135040544; // 044147 SSRAM[18536] = 36'o644563640042; // 044150 SSRAM[18537] = 36'o001500616557; // 044151 SSRAM[18538] = 36'o645145566417; // 044152 SSRAM[18539] = 36'o624555415156; // 044153 SSRAM[18540] = 36'o444562005156; // 044154 SSRAM[18541] = 36'o435762624543; // 044155 SSRAM[18542] = 36'o647700000000; // 044156 SSRAM[18543] = 36'o044073041025; // 044157 SSRAM[18544] = 36'o000013000014; // 044160 SSRAM[18545] = 36'o044150040754; // 044161 SSRAM[18546] = 36'o000000000000; // 044162 SSRAM[18547] = 36'o000000000000; // 044163 SSRAM[18548] = 36'o123456765432; // 044164 SSRAM[18549] = 36'o000000000000; // 044165 SSRAM[18550] = 36'o123456765432; // 044166 SSRAM[18551] = 36'o000000000000; // 044167 SSRAM[18552] = 36'o000000000000; // 044170 SSRAM[18553] = 36'o000000000001; // 044171 SSRAM[18554] = 36'o000000000000; // 044172 SSRAM[18555] = 36'o000000000000; // 044173 SSRAM[18556] = 36'o044162040544; // 044174 SSRAM[18557] = 36'o000000000000; // 044175 SSRAM[18558] = 36'o000000000000; // 044176 SSRAM[18559] = 36'o000000000000; // 044177 SSRAM[18560] = 36'o000000000001; // 044200 SSRAM[18561] = 36'o000000000000; // 044201 SSRAM[18562] = 36'o000000000002; // 044202 SSRAM[18563] = 36'o000000000000; // 044203 SSRAM[18564] = 36'o000000000000; // 044204 SSRAM[18565] = 36'o000000000000; // 044205 SSRAM[18566] = 36'o000000000001; // 044206 SSRAM[18567] = 36'o044175040544; // 044207 SSRAM[18568] = 36'o644563640043; // 044210 SSRAM[18569] = 36'o001500616557; // 044211 SSRAM[18570] = 36'o645145566417; // 044212 SSRAM[18571] = 36'o624555415156; // 044213 SSRAM[18572] = 36'o444562005156; // 044214 SSRAM[18573] = 36'o435762624543; // 044215 SSRAM[18574] = 36'o647700000000; // 044216 SSRAM[18575] = 36'o044073041025; // 044217 SSRAM[18576] = 36'o000013000014; // 044220 SSRAM[18577] = 36'o044210040754; // 044221 SSRAM[18578] = 36'o000000000000; // 044222 SSRAM[18579] = 36'o000000000000; // 044223 SSRAM[18580] = 36'o000000000001; // 044224 SSRAM[18581] = 36'o000000000000; // 044225 SSRAM[18582] = 36'o000000000000; // 044226 SSRAM[18583] = 36'o000000000002; // 044227 SSRAM[18584] = 36'o000000000000; // 044230 SSRAM[18585] = 36'o200000000000; // 044231 SSRAM[18586] = 36'o000000000000; // 044232 SSRAM[18587] = 36'o000000000000; // 044233 SSRAM[18588] = 36'o044222040544; // 044234 SSRAM[18589] = 36'o000000000000; // 044235 SSRAM[18590] = 36'o000000000000; // 044236 SSRAM[18591] = 36'o000000000001; // 044237 SSRAM[18592] = 36'o000000000000; // 044240 SSRAM[18593] = 36'o000000000002; // 044241 SSRAM[18594] = 36'o000000000000; // 044242 SSRAM[18595] = 36'o000000000000; // 044243 SSRAM[18596] = 36'o000000000000; // 044244 SSRAM[18597] = 36'o000000000001; // 044245 SSRAM[18598] = 36'o000000000000; // 044246 SSRAM[18599] = 36'o044235040544; // 044247 SSRAM[18600] = 36'o000000000000; // 044250 SSRAM[18601] = 36'o000000000001; // 044251 SSRAM[18602] = 36'o000000000000; // 044252 SSRAM[18603] = 36'o000000000000; // 044253 SSRAM[18604] = 36'o000000000000; // 044254 SSRAM[18605] = 36'o000000000002; // 044255 SSRAM[18606] = 36'o200000000000; // 044256 SSRAM[18607] = 36'o000000000000; // 044257 SSRAM[18608] = 36'o000000000000; // 044260 SSRAM[18609] = 36'o000000000000; // 044261 SSRAM[18610] = 36'o044250040544; // 044262 SSRAM[18611] = 36'o000000000000; // 044263 SSRAM[18612] = 36'o000000000001; // 044264 SSRAM[18613] = 36'o000000000000; // 044265 SSRAM[18614] = 36'o000000000000; // 044266 SSRAM[18615] = 36'o000000000002; // 044267 SSRAM[18616] = 36'o000000000000; // 044270 SSRAM[18617] = 36'o000000000000; // 044271 SSRAM[18618] = 36'o200000000000; // 044272 SSRAM[18619] = 36'o000000000000; // 044273 SSRAM[18620] = 36'o000000000000; // 044274 SSRAM[18621] = 36'o044263040544; // 044275 SSRAM[18622] = 36'o000000000001; // 044276 SSRAM[18623] = 36'o000000000000; // 044277 SSRAM[18624] = 36'o000000000000; // 044300 SSRAM[18625] = 36'o000000000000; // 044301 SSRAM[18626] = 36'o000000000002; // 044302 SSRAM[18627] = 36'o000000000000; // 044303 SSRAM[18628] = 36'o200000000000; // 044304 SSRAM[18629] = 36'o000000000000; // 044305 SSRAM[18630] = 36'o000000000000; // 044306 SSRAM[18631] = 36'o000000000000; // 044307 SSRAM[18632] = 36'o044276040544; // 044310 SSRAM[18633] = 36'o777777777777; // 044311 SSRAM[18634] = 36'o777777777777; // 044312 SSRAM[18635] = 36'o777777777777; // 044313 SSRAM[18636] = 36'o777777777777; // 044314 SSRAM[18637] = 36'o000000000000; // 044315 SSRAM[18638] = 36'o000000000002; // 044316 SSRAM[18639] = 36'o000000000000; // 044317 SSRAM[18640] = 36'o000000000000; // 044320 SSRAM[18641] = 36'o777777777777; // 044321 SSRAM[18642] = 36'o777777777777; // 044322 SSRAM[18643] = 36'o044311040544; // 044323 SSRAM[18644] = 36'o777777777777; // 044324 SSRAM[18645] = 36'o777777777777; // 044325 SSRAM[18646] = 36'o777777777777; // 044326 SSRAM[18647] = 36'o400000000000; // 044327 SSRAM[18648] = 36'o000000000000; // 044330 SSRAM[18649] = 36'o000000000002; // 044331 SSRAM[18650] = 36'o777777777777; // 044332 SSRAM[18651] = 36'o600000000000; // 044333 SSRAM[18652] = 36'o000000000000; // 044334 SSRAM[18653] = 36'o000000000000; // 044335 SSRAM[18654] = 36'o044324040544; // 044336 SSRAM[18655] = 36'o777777777777; // 044337 SSRAM[18656] = 36'o777777777777; // 044340 SSRAM[18657] = 36'o777777777777; // 044341 SSRAM[18658] = 36'o400000000000; // 044342 SSRAM[18659] = 36'o000000000002; // 044343 SSRAM[18660] = 36'o000000000000; // 044344 SSRAM[18661] = 36'o000000000000; // 044345 SSRAM[18662] = 36'o000000000000; // 044346 SSRAM[18663] = 36'o777777777777; // 044347 SSRAM[18664] = 36'o400000000000; // 044350 SSRAM[18665] = 36'o044337040544; // 044351 SSRAM[18666] = 36'o777777777777; // 044352 SSRAM[18667] = 36'o777777777777; // 044353 SSRAM[18668] = 36'o400000000000; // 044354 SSRAM[18669] = 36'o400000000000; // 044355 SSRAM[18670] = 36'o000000000000; // 044356 SSRAM[18671] = 36'o000000000002; // 044357 SSRAM[18672] = 36'o600000000000; // 044360 SSRAM[18673] = 36'o400000000000; // 044361 SSRAM[18674] = 36'o000000000000; // 044362 SSRAM[18675] = 36'o000000000000; // 044363 SSRAM[18676] = 36'o044352040544; // 044364 SSRAM[18677] = 36'o777777777777; // 044365 SSRAM[18678] = 36'o777777777777; // 044366 SSRAM[18679] = 36'o400000000000; // 044367 SSRAM[18680] = 36'o400000000000; // 044370 SSRAM[18681] = 36'o000000000002; // 044371 SSRAM[18682] = 36'o000000000000; // 044372 SSRAM[18683] = 36'o777777777777; // 044373 SSRAM[18684] = 36'o600000000000; // 044374 SSRAM[18685] = 36'o000000000000; // 044375 SSRAM[18686] = 36'o000000000000; // 044376 SSRAM[18687] = 36'o044365040544; // 044377 SSRAM[18688] = 36'o777777777777; // 044400 SSRAM[18689] = 36'o400000000000; // 044401 SSRAM[18690] = 36'o400000000000; // 044402 SSRAM[18691] = 36'o400000000000; // 044403 SSRAM[18692] = 36'o000000000002; // 044404 SSRAM[18693] = 36'o000000000000; // 044405 SSRAM[18694] = 36'o600000000000; // 044406 SSRAM[18695] = 36'o400000000000; // 044407 SSRAM[18696] = 36'o000000000000; // 044410 SSRAM[18697] = 36'o000000000000; // 044411 SSRAM[18698] = 36'o044400040544; // 044412 SSRAM[18699] = 36'o000000000000; // 044413 SSRAM[18700] = 36'o000000000000; // 044414 SSRAM[18701] = 36'o000000000000; // 044415 SSRAM[18702] = 36'o000000000001; // 044416 SSRAM[18703] = 36'o777777777777; // 044417 SSRAM[18704] = 36'o777777777776; // 044420 SSRAM[18705] = 36'o000000000000; // 044421 SSRAM[18706] = 36'o000000000000; // 044422 SSRAM[18707] = 36'o000000000000; // 044423 SSRAM[18708] = 36'o000000000001; // 044424 SSRAM[18709] = 36'o044413040544; // 044425 SSRAM[18710] = 36'o000000000000; // 044426 SSRAM[18711] = 36'o000000000000; // 044427 SSRAM[18712] = 36'o000000000001; // 044430 SSRAM[18713] = 36'o000000000000; // 044431 SSRAM[18714] = 36'o777777777777; // 044432 SSRAM[18715] = 36'o777777777776; // 044433 SSRAM[18716] = 36'o777777777777; // 044434 SSRAM[18717] = 36'o600000000000; // 044435 SSRAM[18718] = 36'o000000000000; // 044436 SSRAM[18719] = 36'o000000000000; // 044437 SSRAM[18720] = 36'o044426040544; // 044440 SSRAM[18721] = 36'o000000000000; // 044441 SSRAM[18722] = 36'o000000000000; // 044442 SSRAM[18723] = 36'o000000000001; // 044443 SSRAM[18724] = 36'o000000000000; // 044444 SSRAM[18725] = 36'o777777777776; // 044445 SSRAM[18726] = 36'o400000000000; // 044446 SSRAM[18727] = 36'o000000000000; // 044447 SSRAM[18728] = 36'o000000000000; // 044450 SSRAM[18729] = 36'o000000000001; // 044451 SSRAM[18730] = 36'o000000000000; // 044452 SSRAM[18731] = 36'o044441040544; // 044453 SSRAM[18732] = 36'o000000000000; // 044454 SSRAM[18733] = 36'o000000000001; // 044455 SSRAM[18734] = 36'o000000000000; // 044456 SSRAM[18735] = 36'o000000000000; // 044457 SSRAM[18736] = 36'o777777777777; // 044460 SSRAM[18737] = 36'o777777777776; // 044461 SSRAM[18738] = 36'o600000000000; // 044462 SSRAM[18739] = 36'o400000000000; // 044463 SSRAM[18740] = 36'o000000000000; // 044464 SSRAM[18741] = 36'o000000000000; // 044465 SSRAM[18742] = 36'o044454040544; // 044466 SSRAM[18743] = 36'o000000000000; // 044467 SSRAM[18744] = 36'o000000000001; // 044470 SSRAM[18745] = 36'o000000000000; // 044471 SSRAM[18746] = 36'o000000000000; // 044472 SSRAM[18747] = 36'o777777777776; // 044473 SSRAM[18748] = 36'o400000000000; // 044474 SSRAM[18749] = 36'o777777777777; // 044475 SSRAM[18750] = 36'o600000000000; // 044476 SSRAM[18751] = 36'o000000000000; // 044477 SSRAM[18752] = 36'o000000000000; // 044500 SSRAM[18753] = 36'o044467040544; // 044501 SSRAM[18754] = 36'o000000000001; // 044502 SSRAM[18755] = 36'o000000000000; // 044503 SSRAM[18756] = 36'o000000000000; // 044504 SSRAM[18757] = 36'o000000000000; // 044505 SSRAM[18758] = 36'o777777777776; // 044506 SSRAM[18759] = 36'o400000000000; // 044507 SSRAM[18760] = 36'o600000000000; // 044510 SSRAM[18761] = 36'o400000000000; // 044511 SSRAM[18762] = 36'o000000000000; // 044512 SSRAM[18763] = 36'o000000000000; // 044513 SSRAM[18764] = 36'o044502040544; // 044514 SSRAM[18765] = 36'o777777777777; // 044515 SSRAM[18766] = 36'o777777777777; // 044516 SSRAM[18767] = 36'o777777777777; // 044517 SSRAM[18768] = 36'o777777777777; // 044520 SSRAM[18769] = 36'o777777777777; // 044521 SSRAM[18770] = 36'o777777777776; // 044522 SSRAM[18771] = 36'o000000000000; // 044523 SSRAM[18772] = 36'o000000000000; // 044524 SSRAM[18773] = 36'o777777777777; // 044525 SSRAM[18774] = 36'o777777777777; // 044526 SSRAM[18775] = 36'o044515040544; // 044527 SSRAM[18776] = 36'o777777777777; // 044530 SSRAM[18777] = 36'o777777777777; // 044531 SSRAM[18778] = 36'o777777777777; // 044532 SSRAM[18779] = 36'o400000000000; // 044533 SSRAM[18780] = 36'o777777777777; // 044534 SSRAM[18781] = 36'o777777777776; // 044535 SSRAM[18782] = 36'o000000000000; // 044536 SSRAM[18783] = 36'o200000000000; // 044537 SSRAM[18784] = 36'o000000000000; // 044540 SSRAM[18785] = 36'o000000000000; // 044541 SSRAM[18786] = 36'o044530040544; // 044542 SSRAM[18787] = 36'o777777777777; // 044543 SSRAM[18788] = 36'o777777777777; // 044544 SSRAM[18789] = 36'o777777777777; // 044545 SSRAM[18790] = 36'o400000000000; // 044546 SSRAM[18791] = 36'o777777777776; // 044547 SSRAM[18792] = 36'o400000000000; // 044550 SSRAM[18793] = 36'o000000000000; // 044551 SSRAM[18794] = 36'o000000000000; // 044552 SSRAM[18795] = 36'o777777777777; // 044553 SSRAM[18796] = 36'o400000000000; // 044554 SSRAM[18797] = 36'o044543040544; // 044555 SSRAM[18798] = 36'o777777777777; // 044556 SSRAM[18799] = 36'o777777777777; // 044557 SSRAM[18800] = 36'o400000000000; // 044560 SSRAM[18801] = 36'o400000000000; // 044561 SSRAM[18802] = 36'o777777777777; // 044562 SSRAM[18803] = 36'o777777777776; // 044563 SSRAM[18804] = 36'o200000000000; // 044564 SSRAM[18805] = 36'o000000000000; // 044565 SSRAM[18806] = 36'o000000000000; // 044566 SSRAM[18807] = 36'o000000000000; // 044567 SSRAM[18808] = 36'o044556040544; // 044570 SSRAM[18809] = 36'o777777777777; // 044571 SSRAM[18810] = 36'o777777777777; // 044572 SSRAM[18811] = 36'o400000000000; // 044573 SSRAM[18812] = 36'o400000000000; // 044574 SSRAM[18813] = 36'o777777777776; // 044575 SSRAM[18814] = 36'o400000000000; // 044576 SSRAM[18815] = 36'o000000000000; // 044577 SSRAM[18816] = 36'o200000000000; // 044600 SSRAM[18817] = 36'o000000000000; // 044601 SSRAM[18818] = 36'o000000000000; // 044602 SSRAM[18819] = 36'o044571040544; // 044603 SSRAM[18820] = 36'o777777777777; // 044604 SSRAM[18821] = 36'o400000000000; // 044605 SSRAM[18822] = 36'o400000000000; // 044606 SSRAM[18823] = 36'o400000000000; // 044607 SSRAM[18824] = 36'o777777777776; // 044610 SSRAM[18825] = 36'o400000000000; // 044611 SSRAM[18826] = 36'o200000000000; // 044612 SSRAM[18827] = 36'o000000000000; // 044613 SSRAM[18828] = 36'o000000000000; // 044614 SSRAM[18829] = 36'o000000000000; // 044615 SSRAM[18830] = 36'o044604040544; // 044616 SSRAM[18831] = 36'o333333333333; // 044617 SSRAM[18832] = 36'o333333333333; // 044620 SSRAM[18833] = 36'o333333333333; // 044621 SSRAM[18834] = 36'o333333333333; // 044622 SSRAM[18835] = 36'o344444444444; // 044623 SSRAM[18836] = 36'o444444444444; // 044624 SSRAM[18837] = 36'o365605075342; // 044625 SSRAM[18838] = 36'o070414545131; // 044626 SSRAM[18839] = 36'o055632516360; // 044627 SSRAM[18840] = 36'o373564760527; // 044630 SSRAM[18841] = 36'o044617040544; // 044631 SSRAM[18842] = 36'o644563640044; // 044632 SSRAM[18843] = 36'o001500616557; // 044633 SSRAM[18844] = 36'o645145566417; // 044634 SSRAM[18845] = 36'o624555415156; // 044635 SSRAM[18846] = 36'o444562005156; // 044636 SSRAM[18847] = 36'o435762624543; // 044637 SSRAM[18848] = 36'o647700000000; // 044640 SSRAM[18849] = 36'o044073041025; // 044641 SSRAM[18850] = 36'o000013000014; // 044642 SSRAM[18851] = 36'o044632040754; // 044643 SSRAM[18852] = 36'o644563640044; // 044644 SSRAM[18853] = 36'o001500604300; // 044645 SSRAM[18854] = 36'o465441476300; // 044646 SSRAM[18855] = 36'o515643576262; // 044647 SSRAM[18856] = 36'o454364001500; // 044650 SSRAM[18857] = 36'o425164630020; // 044651 SSRAM[18858] = 36'o000600212277; // 044652 SSRAM[18859] = 36'o044073041025; // 044653 SSRAM[18860] = 36'o000014040521; // 044654 SSRAM[18861] = 36'o044644040754; // 044655 SSRAM[18862] = 36'o333333333333; // 044656 SSRAM[18863] = 36'o444444444444; // 044657 SSRAM[18864] = 36'o333333333333; // 044660 SSRAM[18865] = 36'o444444444444; // 044661 SSRAM[18866] = 36'o344444444444; // 044662 SSRAM[18867] = 36'o333333333333; // 044663 SSRAM[18868] = 36'o365605075340; // 044664 SSRAM[18869] = 36'o247073632327; // 044665 SSRAM[18870] = 36'o213672200375; // 044666 SSRAM[18871] = 36'o376365035467; // 044667 SSRAM[18872] = 36'o044656040544; // 044670 SSRAM[18873] = 36'o222222222222; // 044671 SSRAM[18874] = 36'o222222222222; // 044672 SSRAM[18875] = 36'o222222222222; // 044673 SSRAM[18876] = 36'o222222222222; // 044674 SSRAM[18877] = 36'o333333333333; // 044675 SSRAM[18878] = 36'o333333333333; // 044676 SSRAM[18879] = 36'o252525252525; // 044677 SSRAM[18880] = 36'o125252525253; // 044700 SSRAM[18881] = 36'o111111111111; // 044701 SSRAM[18882] = 36'o111111111111; // 044702 SSRAM[18883] = 36'o044671040544; // 044703 SSRAM[18884] = 36'o222222222222; // 044704 SSRAM[18885] = 36'o333333333333; // 044705 SSRAM[18886] = 36'o222222222222; // 044706 SSRAM[18887] = 36'o333333333333; // 044707 SSRAM[18888] = 36'o333333333333; // 044710 SSRAM[18889] = 36'o444444444444; // 044711 SSRAM[18890] = 36'o252525252526; // 044712 SSRAM[18891] = 36'o070707070710; // 044713 SSRAM[18892] = 36'o004040404041; // 044714 SSRAM[18893] = 36'o327272727273; // 044715 SSRAM[18894] = 36'o044704040544; // 044716 SSRAM[18895] = 36'o255555555555; // 044717 SSRAM[18896] = 36'o555555555555; // 044720 SSRAM[18897] = 36'o555555555555; // 044721 SSRAM[18898] = 36'o555555555555; // 044722 SSRAM[18899] = 36'o311111111111; // 044723 SSRAM[18900] = 36'o111111111111; // 044724 SSRAM[18901] = 36'o335056427213; // 044725 SSRAM[18902] = 36'o035475265746; // 044726 SSRAM[18903] = 36'o144375704605; // 044727 SSRAM[18904] = 36'o004166365327; // 044730 SSRAM[18905] = 36'o044717040544; // 044731 SSRAM[18906] = 36'o255555555555; // 044732 SSRAM[18907] = 36'o222222222222; // 044733 SSRAM[18908] = 36'o555555555555; // 044734 SSRAM[18909] = 36'o222222222222; // 044735 SSRAM[18910] = 36'o311111111111; // 044736 SSRAM[18911] = 36'o666666666666; // 044737 SSRAM[18912] = 36'o335056427212; // 044740 SSRAM[18913] = 36'o323443757047; // 044741 SSRAM[18914] = 36'o240023257716; // 044742 SSRAM[18915] = 36'o107503314730; // 044743 SSRAM[18916] = 36'o044732040544; // 044744 SSRAM[18917] = 36'o123456123456; // 044745 SSRAM[18918] = 36'o123456123456; // 044746 SSRAM[18919] = 36'o123456123456; // 044747 SSRAM[18920] = 36'o123456123456; // 044750 SSRAM[18921] = 36'o234567234567; // 044751 SSRAM[18922] = 36'o234567234567; // 044752 SSRAM[18923] = 36'o210420323476; // 044753 SSRAM[18924] = 36'o136703233600; // 044754 SSRAM[18925] = 36'o055256055256; // 044755 SSRAM[18926] = 36'o055256055256; // 044756 SSRAM[18927] = 36'o044745040544; // 044757 SSRAM[18928] = 36'o444444444444; // 044760 SSRAM[18929] = 36'o444444444444; // 044761 SSRAM[18930] = 36'o444444444444; // 044762 SSRAM[18931] = 36'o444444444444; // 044763 SSRAM[18932] = 36'o333333333333; // 044764 SSRAM[18933] = 36'o333333333334; // 044765 SSRAM[18934] = 36'o400000000000; // 044766 SSRAM[18935] = 36'o400000000001; // 044767 SSRAM[18936] = 36'o511111111110; // 044770 SSRAM[18937] = 36'o511111111110; // 044771 SSRAM[18938] = 36'o044760040544; // 044772 SSRAM[18939] = 36'o555555555555; // 044773 SSRAM[18940] = 36'o555555555555; // 044774 SSRAM[18941] = 36'o555555555555; // 044775 SSRAM[18942] = 36'o555555555555; // 044776 SSRAM[18943] = 36'o444444444444; // 044777 SSRAM[18944] = 36'o444444444444; // 045000 SSRAM[18945] = 36'o252525252525; // 045001 SSRAM[18946] = 36'o125252525252; // 045002 SSRAM[18947] = 36'o606060606060; // 045003 SSRAM[18948] = 36'o460606060605; // 045004 SSRAM[18949] = 36'o044773040544; // 045005 SSRAM[18950] = 36'o444444444444; // 045006 SSRAM[18951] = 36'o555555555555; // 045007 SSRAM[18952] = 36'o444444444444; // 045010 SSRAM[18953] = 36'o555555555555; // 045011 SSRAM[18954] = 36'o432123456765; // 045012 SSRAM[18955] = 36'o432123456765; // 045013 SSRAM[18956] = 36'o364320315052; // 045014 SSRAM[18957] = 36'o247020761620; // 045015 SSRAM[18958] = 36'o473571652245; // 045016 SSRAM[18959] = 36'o600514541235; // 045017 SSRAM[18960] = 36'o045006040544; // 045020 SSRAM[18961] = 36'o555555555555; // 045021 SSRAM[18962] = 36'o222222222222; // 045022 SSRAM[18963] = 36'o555555555555; // 045023 SSRAM[18964] = 36'o222222222222; // 045024 SSRAM[18965] = 36'o543210123456; // 045025 SSRAM[18966] = 36'o543210123456; // 045026 SSRAM[18967] = 36'o356736272460; // 045027 SSRAM[18968] = 36'o271326656374; // 045030 SSRAM[18969] = 36'o763153710465; // 045031 SSRAM[18970] = 36'o406655405512; // 045032 SSRAM[18971] = 36'o045021040544; // 045033 SSRAM[18972] = 36'o777777777777; // 045034 SSRAM[18973] = 36'o377777777777; // 045035 SSRAM[18974] = 36'o377777777777; // 045036 SSRAM[18975] = 36'o377777777774; // 045037 SSRAM[18976] = 36'o777777777777; // 045040 SSRAM[18977] = 36'o377777777776; // 045041 SSRAM[18978] = 36'o000000000000; // 045042 SSRAM[18979] = 36'o000000000002; // 045043 SSRAM[18980] = 36'o000000000000; // 045044 SSRAM[18981] = 36'o000000000000; // 045045 SSRAM[18982] = 36'o045034040544; // 045046 SSRAM[18983] = 36'o644563640045; // 045047 SSRAM[18984] = 36'o001500616557; // 045050 SSRAM[18985] = 36'o645145566417; // 045051 SSRAM[18986] = 36'o624555415156; // 045052 SSRAM[18987] = 36'o444562005156; // 045053 SSRAM[18988] = 36'o435762624543; // 045054 SSRAM[18989] = 36'o647700000000; // 045055 SSRAM[18990] = 36'o044073041025; // 045056 SSRAM[18991] = 36'o000013000014; // 045057 SSRAM[18992] = 36'o045047040754; // 045060 SSRAM[18993] = 36'o644563640045; // 045061 SSRAM[18994] = 36'o001500604300; // 045062 SSRAM[18995] = 36'o465441476300; // 045063 SSRAM[18996] = 36'o515643576262; // 045064 SSRAM[18997] = 36'o454364001500; // 045065 SSRAM[18998] = 36'o425164630020; // 045066 SSRAM[18999] = 36'o000600212277; // 045067 SSRAM[19000] = 36'o044073041025; // 045070 SSRAM[19001] = 36'o000014040521; // 045071 SSRAM[19002] = 36'o045061040754; // 045072 SSRAM[19003] = 36'o777777777777; // 045073 SSRAM[19004] = 36'o377777777777; // 045074 SSRAM[19005] = 36'o377777777777; // 045075 SSRAM[19006] = 36'o777777777774; // 045076 SSRAM[19007] = 36'o777777777777; // 045077 SSRAM[19008] = 36'o777777777776; // 045100 SSRAM[19009] = 36'o000000000000; // 045101 SSRAM[19010] = 36'o000000000002; // 045102 SSRAM[19011] = 36'o000000000000; // 045103 SSRAM[19012] = 36'o000000000000; // 045104 SSRAM[19013] = 36'o045073040544; // 045105 SSRAM[19014] = 36'o777777777777; // 045106 SSRAM[19015] = 36'o377777777777; // 045107 SSRAM[19016] = 36'o377777777777; // 045110 SSRAM[19017] = 36'o377777777774; // 045111 SSRAM[19018] = 36'o000000000000; // 045112 SSRAM[19019] = 36'o400000000002; // 045113 SSRAM[19020] = 36'o777777777777; // 045114 SSRAM[19021] = 36'o777777777776; // 045115 SSRAM[19022] = 36'o000000000000; // 045116 SSRAM[19023] = 36'o000000000000; // 045117 SSRAM[19024] = 36'o045106040544; // 045120 SSRAM[19025] = 36'o777777777777; // 045121 SSRAM[19026] = 36'o777777777777; // 045122 SSRAM[19027] = 36'o777777777777; // 045123 SSRAM[19028] = 36'o777777777774; // 045124 SSRAM[19029] = 36'o000000000000; // 045125 SSRAM[19030] = 36'o400000000002; // 045126 SSRAM[19031] = 36'o777777777777; // 045127 SSRAM[19032] = 36'o777777777776; // 045130 SSRAM[19033] = 36'o000000000000; // 045131 SSRAM[19034] = 36'o000000000000; // 045132 SSRAM[19035] = 36'o045121040544; // 045133 SSRAM[19036] = 36'o000000000000; // 045134 SSRAM[19037] = 36'o400000000000; // 045135 SSRAM[19038] = 36'o400000000000; // 045136 SSRAM[19039] = 36'o400000000004; // 045137 SSRAM[19040] = 36'o777777777777; // 045140 SSRAM[19041] = 36'o377777777776; // 045141 SSRAM[19042] = 36'o777777777777; // 045142 SSRAM[19043] = 36'o777777777776; // 045143 SSRAM[19044] = 36'o000000000000; // 045144 SSRAM[19045] = 36'o000000000000; // 045145 SSRAM[19046] = 36'o045134040544; // 045146 SSRAM[19047] = 36'o000000000000; // 045147 SSRAM[19048] = 36'o400000000000; // 045150 SSRAM[19049] = 36'o400000000000; // 045151 SSRAM[19050] = 36'o400000000004; // 045152 SSRAM[19051] = 36'o777777777777; // 045153 SSRAM[19052] = 36'o777777777776; // 045154 SSRAM[19053] = 36'o777777777777; // 045155 SSRAM[19054] = 36'o777777777776; // 045156 SSRAM[19055] = 36'o000000000000; // 045157 SSRAM[19056] = 36'o000000000000; // 045160 SSRAM[19057] = 36'o045147040544; // 045161 SSRAM[19058] = 36'o000000000000; // 045162 SSRAM[19059] = 36'o000000000000; // 045163 SSRAM[19060] = 36'o000000000000; // 045164 SSRAM[19061] = 36'o400000000004; // 045165 SSRAM[19062] = 36'o000000000000; // 045166 SSRAM[19063] = 36'o000000000002; // 045167 SSRAM[19064] = 36'o000000000000; // 045170 SSRAM[19065] = 36'o000000000002; // 045171 SSRAM[19066] = 36'o000000000000; // 045172 SSRAM[19067] = 36'o000000000000; // 045173 SSRAM[19068] = 36'o045162040544; // 045174 SSRAM[19069] = 36'o000000000000; // 045175 SSRAM[19070] = 36'o000000000000; // 045176 SSRAM[19071] = 36'o000000000000; // 045177 SSRAM[19072] = 36'o400000000004; // 045200 SSRAM[19073] = 36'o000000000000; // 045201 SSRAM[19074] = 36'o400000000002; // 045202 SSRAM[19075] = 36'o000000000000; // 045203 SSRAM[19076] = 36'o000000000002; // 045204 SSRAM[19077] = 36'o000000000000; // 045205 SSRAM[19078] = 36'o000000000000; // 045206 SSRAM[19079] = 36'o045175040544; // 045207 SSRAM[19080] = 36'o777777777775; // 045210 SSRAM[19081] = 36'o400000000000; // 045211 SSRAM[19082] = 36'o400000000000; // 045212 SSRAM[19083] = 36'o400000000000; // 045213 SSRAM[19084] = 36'o777777777772; // 045214 SSRAM[19085] = 36'o400000000000; // 045215 SSRAM[19086] = 36'o200000000000; // 045216 SSRAM[19087] = 36'o000000000000; // 045217 SSRAM[19088] = 36'o000000000000; // 045220 SSRAM[19089] = 36'o000000000000; // 045221 SSRAM[19090] = 36'o045210040544; // 045222 SSRAM[19091] = 36'o777777777775; // 045223 SSRAM[19092] = 36'o400000000000; // 045224 SSRAM[19093] = 36'o400000000000; // 045225 SSRAM[19094] = 36'o000000000000; // 045226 SSRAM[19095] = 36'o777777777772; // 045227 SSRAM[19096] = 36'o400000000000; // 045230 SSRAM[19097] = 36'o200000000000; // 045231 SSRAM[19098] = 36'o000000000000; // 045232 SSRAM[19099] = 36'o000000000000; // 045233 SSRAM[19100] = 36'o000000000000; // 045234 SSRAM[19101] = 36'o045223040544; // 045235 SSRAM[19102] = 36'o777777777775; // 045236 SSRAM[19103] = 36'o400000000000; // 045237 SSRAM[19104] = 36'o000000000000; // 045240 SSRAM[19105] = 36'o000000000000; // 045241 SSRAM[19106] = 36'o000000000006; // 045242 SSRAM[19107] = 36'o000000000000; // 045243 SSRAM[19108] = 36'o600000000000; // 045244 SSRAM[19109] = 36'o400000000000; // 045245 SSRAM[19110] = 36'o000000000000; // 045246 SSRAM[19111] = 36'o000000000000; // 045247 SSRAM[19112] = 36'o045236040544; // 045250 SSRAM[19113] = 36'o777777777775; // 045251 SSRAM[19114] = 36'o000000000000; // 045252 SSRAM[19115] = 36'o000000000000; // 045253 SSRAM[19116] = 36'o000000000000; // 045254 SSRAM[19117] = 36'o000000000006; // 045255 SSRAM[19118] = 36'o400000000000; // 045256 SSRAM[19119] = 36'o600000000000; // 045257 SSRAM[19120] = 36'o400000000000; // 045260 SSRAM[19121] = 36'o000000000000; // 045261 SSRAM[19122] = 36'o000000000000; // 045262 SSRAM[19123] = 36'o045251040544; // 045263 SSRAM[19124] = 36'o000000000003; // 045264 SSRAM[19125] = 36'o400000000000; // 045265 SSRAM[19126] = 36'o400000000000; // 045266 SSRAM[19127] = 36'o000000000000; // 045267 SSRAM[19128] = 36'o777777777772; // 045270 SSRAM[19129] = 36'o400000000000; // 045271 SSRAM[19130] = 36'o600000000000; // 045272 SSRAM[19131] = 36'o400000000000; // 045273 SSRAM[19132] = 36'o000000000000; // 045274 SSRAM[19133] = 36'o000000000000; // 045275 SSRAM[19134] = 36'o045264040544; // 045276 SSRAM[19135] = 36'o000000000003; // 045277 SSRAM[19136] = 36'o400000000000; // 045300 SSRAM[19137] = 36'o000000000000; // 045301 SSRAM[19138] = 36'o400000000000; // 045302 SSRAM[19139] = 36'o777777777772; // 045303 SSRAM[19140] = 36'o400000000000; // 045304 SSRAM[19141] = 36'o600000000000; // 045305 SSRAM[19142] = 36'o400000000000; // 045306 SSRAM[19143] = 36'o000000000000; // 045307 SSRAM[19144] = 36'o000000000000; // 045310 SSRAM[19145] = 36'o045277040544; // 045311 SSRAM[19146] = 36'o000000000003; // 045312 SSRAM[19147] = 36'o000000000000; // 045313 SSRAM[19148] = 36'o400000000000; // 045314 SSRAM[19149] = 36'o400000000000; // 045315 SSRAM[19150] = 36'o000000000006; // 045316 SSRAM[19151] = 36'o400000000000; // 045317 SSRAM[19152] = 36'o200000000000; // 045320 SSRAM[19153] = 36'o000000000000; // 045321 SSRAM[19154] = 36'o000000000000; // 045322 SSRAM[19155] = 36'o000000000000; // 045323 SSRAM[19156] = 36'o045312040544; // 045324 SSRAM[19157] = 36'o000000000003; // 045325 SSRAM[19158] = 36'o400000000000; // 045326 SSRAM[19159] = 36'o400000000000; // 045327 SSRAM[19160] = 36'o400000000000; // 045330 SSRAM[19161] = 36'o000000000006; // 045331 SSRAM[19162] = 36'o000000000000; // 045332 SSRAM[19163] = 36'o200000000000; // 045333 SSRAM[19164] = 36'o000000000000; // 045334 SSRAM[19165] = 36'o000000000000; // 045335 SSRAM[19166] = 36'o000000000000; // 045336 SSRAM[19167] = 36'o045325040544; // 045337 SSRAM[19168] = 36'o000000000001; // 045340 SSRAM[19169] = 36'o000000000000; // 045341 SSRAM[19170] = 36'o000000000000; // 045342 SSRAM[19171] = 36'o000000000000; // 045343 SSRAM[19172] = 36'o000000000001; // 045344 SSRAM[19173] = 36'o000000000001; // 045345 SSRAM[19174] = 36'o377777777777; // 045346 SSRAM[19175] = 36'o000000000000; // 045347 SSRAM[19176] = 36'o000000000001; // 045350 SSRAM[19177] = 36'o000000000000; // 045351 SSRAM[19178] = 36'o045340040544; // 045352 SSRAM[19179] = 36'o644563640046; // 045353 SSRAM[19180] = 36'o001500616557; // 045354 SSRAM[19181] = 36'o645145566417; // 045355 SSRAM[19182] = 36'o624555415156; // 045356 SSRAM[19183] = 36'o444562005156; // 045357 SSRAM[19184] = 36'o435762624543; // 045360 SSRAM[19185] = 36'o647700000000; // 045361 SSRAM[19186] = 36'o044073041025; // 045362 SSRAM[19187] = 36'o000013000014; // 045363 SSRAM[19188] = 36'o045353040754; // 045364 SSRAM[19189] = 36'o644563640046; // 045365 SSRAM[19190] = 36'o001500604300; // 045366 SSRAM[19191] = 36'o465441476300; // 045367 SSRAM[19192] = 36'o515643576262; // 045370 SSRAM[19193] = 36'o454364001500; // 045371 SSRAM[19194] = 36'o425164630020; // 045372 SSRAM[19195] = 36'o000600212277; // 045373 SSRAM[19196] = 36'o044073041025; // 045374 SSRAM[19197] = 36'o000014040521; // 045375 SSRAM[19198] = 36'o045365040754; // 045376 SSRAM[19199] = 36'o000000000001; // 045377 SSRAM[19200] = 36'o000000000000; // 045400 SSRAM[19201] = 36'o000000000000; // 045401 SSRAM[19202] = 36'o000000000000; // 045402 SSRAM[19203] = 36'o777777777776; // 045403 SSRAM[19204] = 36'o777777777777; // 045404 SSRAM[19205] = 36'o400000000001; // 045405 SSRAM[19206] = 36'o400000000000; // 045406 SSRAM[19207] = 36'o000000000001; // 045407 SSRAM[19208] = 36'o000000000000; // 045410 SSRAM[19209] = 36'o045377040544; // 045411 SSRAM[19210] = 36'o777777777777; // 045412 SSRAM[19211] = 36'o400000000000; // 045413 SSRAM[19212] = 36'o400000000000; // 045414 SSRAM[19213] = 36'o400000000000; // 045415 SSRAM[19214] = 36'o000000000001; // 045416 SSRAM[19215] = 36'o000000000001; // 045417 SSRAM[19216] = 36'o400000000001; // 045420 SSRAM[19217] = 36'o400000000000; // 045421 SSRAM[19218] = 36'o777777777777; // 045422 SSRAM[19219] = 36'o400000000000; // 045423 SSRAM[19220] = 36'o045412040544; // 045424 SSRAM[19221] = 36'o777777777777; // 045425 SSRAM[19222] = 36'o400000000000; // 045426 SSRAM[19223] = 36'o400000000000; // 045427 SSRAM[19224] = 36'o400000000000; // 045430 SSRAM[19225] = 36'o777777777776; // 045431 SSRAM[19226] = 36'o777777777777; // 045432 SSRAM[19227] = 36'o377777777777; // 045433 SSRAM[19228] = 36'o000000000000; // 045434 SSRAM[19229] = 36'o777777777777; // 045435 SSRAM[19230] = 36'o400000000000; // 045436 SSRAM[19231] = 36'o045425040544; // 045437 SSRAM[19232] = 36'o000000000000; // 045440 SSRAM[19233] = 36'o377777777777; // 045441 SSRAM[19234] = 36'o377777777777; // 045442 SSRAM[19235] = 36'o377777777777; // 045443 SSRAM[19236] = 36'o000000000001; // 045444 SSRAM[19237] = 36'o000000000000; // 045445 SSRAM[19238] = 36'o377777777777; // 045446 SSRAM[19239] = 36'o377777777777; // 045447 SSRAM[19240] = 36'o000000000000; // 045450 SSRAM[19241] = 36'o377777777777; // 045451 SSRAM[19242] = 36'o045440040544; // 045452 SSRAM[19243] = 36'o000000000000; // 045453 SSRAM[19244] = 36'o377777777777; // 045454 SSRAM[19245] = 36'o377777777777; // 045455 SSRAM[19246] = 36'o377777777777; // 045456 SSRAM[19247] = 36'o777777777777; // 045457 SSRAM[19248] = 36'o400000000000; // 045460 SSRAM[19249] = 36'o400000000000; // 045461 SSRAM[19250] = 36'o400000000001; // 045462 SSRAM[19251] = 36'o000000000000; // 045463 SSRAM[19252] = 36'o377777777777; // 045464 SSRAM[19253] = 36'o045453040544; // 045465 SSRAM[19254] = 36'o777777777777; // 045466 SSRAM[19255] = 36'o400000000000; // 045467 SSRAM[19256] = 36'o400000000000; // 045470 SSRAM[19257] = 36'o400000000001; // 045471 SSRAM[19258] = 36'o000000000001; // 045472 SSRAM[19259] = 36'o000000000000; // 045473 SSRAM[19260] = 36'o400000000000; // 045474 SSRAM[19261] = 36'o400000000001; // 045475 SSRAM[19262] = 36'o777777777777; // 045476 SSRAM[19263] = 36'o400000000001; // 045477 SSRAM[19264] = 36'o045466040544; // 045500 SSRAM[19265] = 36'o777777777777; // 045501 SSRAM[19266] = 36'o400000000000; // 045502 SSRAM[19267] = 36'o400000000000; // 045503 SSRAM[19268] = 36'o400000000001; // 045504 SSRAM[19269] = 36'o777777777777; // 045505 SSRAM[19270] = 36'o400000000000; // 045506 SSRAM[19271] = 36'o377777777777; // 045507 SSRAM[19272] = 36'o377777777777; // 045510 SSRAM[19273] = 36'o777777777777; // 045511 SSRAM[19274] = 36'o400000000001; // 045512 SSRAM[19275] = 36'o045501040544; // 045513 SSRAM[19276] = 36'o000000000000; // 045514 SSRAM[19277] = 36'o000000000000; // 045515 SSRAM[19278] = 36'o000000000000; // 045516 SSRAM[19279] = 36'o000000000001; // 045517 SSRAM[19280] = 36'o000000000000; // 045520 SSRAM[19281] = 36'o000000000000; // 045521 SSRAM[19282] = 36'o045514040630; // 045522 SSRAM[19283] = 36'o644563640047; // 045523 SSRAM[19284] = 36'o001500445166; // 045524 SSRAM[19285] = 36'o514445564400; // 045525 SSRAM[19286] = 36'o435041564745; // 045526 SSRAM[19287] = 36'o440057560057; // 045527 SSRAM[19288] = 36'o661756574451; // 045530 SSRAM[19289] = 36'o667700000000; // 045531 SSRAM[19290] = 36'o044073041025; // 045532 SSRAM[19291] = 36'o000013000014; // 045533 SSRAM[19292] = 36'o045523040754; // 045534 SSRAM[19293] = 36'o400040000000; // 045535 SSRAM[19294] = 36'o644563640047; // 045536 SSRAM[19295] = 36'o001500604300; // 045537 SSRAM[19296] = 36'o465441476300; // 045540 SSRAM[19297] = 36'o515643576262; // 045541 SSRAM[19298] = 36'o454364001500; // 045542 SSRAM[19299] = 36'o425164630020; // 045543 SSRAM[19300] = 36'o062122770000; // 045544 SSRAM[19301] = 36'o044073041025; // 045545 SSRAM[19302] = 36'o000014040567; // 045546 SSRAM[19303] = 36'o045536040754; // 045547 SSRAM[19304] = 36'o000000000000; // 045550 SSRAM[19305] = 36'o000000000000; // 045551 SSRAM[19306] = 36'o000000000001; // 045552 SSRAM[19307] = 36'o000000000000; // 045553 SSRAM[19308] = 36'o000000000000; // 045554 SSRAM[19309] = 36'o000000000000; // 045555 SSRAM[19310] = 36'o045550040630; // 045556 SSRAM[19311] = 36'o000000000000; // 045557 SSRAM[19312] = 36'o000000000001; // 045560 SSRAM[19313] = 36'o000000000000; // 045561 SSRAM[19314] = 36'o000000000000; // 045562 SSRAM[19315] = 36'o000000000000; // 045563 SSRAM[19316] = 36'o000000000000; // 045564 SSRAM[19317] = 36'o045557040630; // 045565 SSRAM[19318] = 36'o000000000001; // 045566 SSRAM[19319] = 36'o000000000000; // 045567 SSRAM[19320] = 36'o000000000000; // 045570 SSRAM[19321] = 36'o000000000000; // 045571 SSRAM[19322] = 36'o000000000000; // 045572 SSRAM[19323] = 36'o000000000000; // 045573 SSRAM[19324] = 36'o045566040630; // 045574 SSRAM[19325] = 36'o777777777777; // 045575 SSRAM[19326] = 36'o777777777777; // 045576 SSRAM[19327] = 36'o777777777777; // 045577 SSRAM[19328] = 36'o777777777777; // 045600 SSRAM[19329] = 36'o000000000000; // 045601 SSRAM[19330] = 36'o000000000000; // 045602 SSRAM[19331] = 36'o045575040630; // 045603 SSRAM[19332] = 36'o000000000000; // 045604 SSRAM[19333] = 36'o000000000001; // 045605 SSRAM[19334] = 36'o000000000000; // 045606 SSRAM[19335] = 36'o000000000000; // 045607 SSRAM[19336] = 36'o000000000000; // 045610 SSRAM[19337] = 36'o000000000001; // 045611 SSRAM[19338] = 36'o045604040630; // 045612 SSRAM[19339] = 36'o000000000000; // 045613 SSRAM[19340] = 36'o000000000001; // 045614 SSRAM[19341] = 36'o000000000000; // 045615 SSRAM[19342] = 36'o000000000000; // 045616 SSRAM[19343] = 36'o777777777777; // 045617 SSRAM[19344] = 36'o777777777777; // 045620 SSRAM[19345] = 36'o045613040630; // 045621 SSRAM[19346] = 36'o000000000001; // 045622 SSRAM[19347] = 36'o000000000000; // 045623 SSRAM[19348] = 36'o000000000000; // 045624 SSRAM[19349] = 36'o000000000000; // 045625 SSRAM[19350] = 36'o000000000000; // 045626 SSRAM[19351] = 36'o000000000001; // 045627 SSRAM[19352] = 36'o045622040630; // 045630 SSRAM[19353] = 36'o000000000001; // 045631 SSRAM[19354] = 36'o000000000000; // 045632 SSRAM[19355] = 36'o000000000000; // 045633 SSRAM[19356] = 36'o000000000000; // 045634 SSRAM[19357] = 36'o777777777777; // 045635 SSRAM[19358] = 36'o777777777777; // 045636 SSRAM[19359] = 36'o045631040630; // 045637 SSRAM[19360] = 36'o777777777777; // 045640 SSRAM[19361] = 36'o777777777777; // 045641 SSRAM[19362] = 36'o400000000000; // 045642 SSRAM[19363] = 36'o400000000000; // 045643 SSRAM[19364] = 36'o000000000000; // 045644 SSRAM[19365] = 36'o000000000001; // 045645 SSRAM[19366] = 36'o045640040630; // 045646 SSRAM[19367] = 36'o777777777777; // 045647 SSRAM[19368] = 36'o777777777777; // 045650 SSRAM[19369] = 36'o400000000000; // 045651 SSRAM[19370] = 36'o400000000000; // 045652 SSRAM[19371] = 36'o777777777777; // 045653 SSRAM[19372] = 36'o777777777777; // 045654 SSRAM[19373] = 36'o045647040630; // 045655 SSRAM[19374] = 36'o777777777777; // 045656 SSRAM[19375] = 36'o400000000000; // 045657 SSRAM[19376] = 36'o400000000000; // 045660 SSRAM[19377] = 36'o400000000000; // 045661 SSRAM[19378] = 36'o000000000000; // 045662 SSRAM[19379] = 36'o000000000001; // 045663 SSRAM[19380] = 36'o045656040630; // 045664 SSRAM[19381] = 36'o777777777777; // 045665 SSRAM[19382] = 36'o400000000000; // 045666 SSRAM[19383] = 36'o400000000000; // 045667 SSRAM[19384] = 36'o400000000000; // 045670 SSRAM[19385] = 36'o777777777777; // 045671 SSRAM[19386] = 36'o777777777777; // 045672 SSRAM[19387] = 36'o045665040630; // 045673 SSRAM[19388] = 36'o000000000001; // 045674 SSRAM[19389] = 36'o000000000000; // 045675 SSRAM[19390] = 36'o000000000000; // 045676 SSRAM[19391] = 36'o000000000000; // 045677 SSRAM[19392] = 36'o000000000001; // 045700 SSRAM[19393] = 36'o000000000000; // 045701 SSRAM[19394] = 36'o045674040630; // 045702 SSRAM[19395] = 36'o000000000001; // 045703 SSRAM[19396] = 36'o000000000000; // 045704 SSRAM[19397] = 36'o000000000000; // 045705 SSRAM[19398] = 36'o000000000000; // 045706 SSRAM[19399] = 36'o777777777777; // 045707 SSRAM[19400] = 36'o000000000000; // 045710 SSRAM[19401] = 36'o045703040630; // 045711 SSRAM[19402] = 36'o777777777777; // 045712 SSRAM[19403] = 36'o400000000000; // 045713 SSRAM[19404] = 36'o400000000000; // 045714 SSRAM[19405] = 36'o400000000000; // 045715 SSRAM[19406] = 36'o000000000001; // 045716 SSRAM[19407] = 36'o000000000000; // 045717 SSRAM[19408] = 36'o045712040630; // 045720 SSRAM[19409] = 36'o777777777777; // 045721 SSRAM[19410] = 36'o400000000000; // 045722 SSRAM[19411] = 36'o400000000000; // 045723 SSRAM[19412] = 36'o400000000000; // 045724 SSRAM[19413] = 36'o777777777777; // 045725 SSRAM[19414] = 36'o400000000000; // 045726 SSRAM[19415] = 36'o045721040630; // 045727 SSRAM[19416] = 36'o000000000000; // 045730 SSRAM[19417] = 36'o377777777777; // 045731 SSRAM[19418] = 36'o377777777777; // 045732 SSRAM[19419] = 36'o377777777777; // 045733 SSRAM[19420] = 36'o000000000000; // 045734 SSRAM[19421] = 36'o377777777777; // 045735 SSRAM[19422] = 36'o045730040630; // 045736 SSRAM[19423] = 36'o000000000000; // 045737 SSRAM[19424] = 36'o377777777777; // 045740 SSRAM[19425] = 36'o377777777777; // 045741 SSRAM[19426] = 36'o377777777777; // 045742 SSRAM[19427] = 36'o777777777777; // 045743 SSRAM[19428] = 36'o400000000001; // 045744 SSRAM[19429] = 36'o045737040630; // 045745 SSRAM[19430] = 36'o045457040630; // 045746 SSRAM[19431] = 36'o777777777777; // 045747 SSRAM[19432] = 36'o400000000000; // 045750 SSRAM[19433] = 36'o400000000000; // 045751 SSRAM[19434] = 36'o400000000001; // 045752 SSRAM[19435] = 36'o777777777777; // 045753 SSRAM[19436] = 36'o400000000001; // 045754 SSRAM[19437] = 36'o045747040630; // 045755 SSRAM[19438] = 36'o043027040630; // 045756 SSRAM[19439] = 36'o000000000001; // 045757 SSRAM[19440] = 36'o000000000000; // 045760 SSRAM[19441] = 36'o377777777777; // 045761 SSRAM[19442] = 36'o377777777777; // 045762 SSRAM[19443] = 36'o777777777777; // 045763 SSRAM[19444] = 36'o400000000001; // 045764 SSRAM[19445] = 36'o045757040630; // 045765 SSRAM[19446] = 36'o777777777776; // 045766 SSRAM[19447] = 36'o777777777777; // 045767 SSRAM[19448] = 36'o400000000000; // 045770 SSRAM[19449] = 36'o400000000001; // 045771 SSRAM[19450] = 36'o000000000000; // 045772 SSRAM[19451] = 36'o377777777777; // 045773 SSRAM[19452] = 36'o045766040630; // 045774 SSRAM[19453] = 36'o777777777776; // 045775 SSRAM[19454] = 36'o777777777777; // 045776 SSRAM[19455] = 36'o400000000000; // 045777 SSRAM[19456] = 36'o400000000001; // 046000 SSRAM[19457] = 36'o777777777777; // 046001 SSRAM[19458] = 36'o400000000001; // 046002 SSRAM[19459] = 36'o045775040630; // 046003 SSRAM[19460] = 36'o400000000000; // 046004 SSRAM[19461] = 36'o400000000000; // 046005 SSRAM[19462] = 36'o400000000000; // 046006 SSRAM[19463] = 36'o400000000000; // 046007 SSRAM[19464] = 36'o400000000000; // 046010 SSRAM[19465] = 36'o400000000000; // 046011 SSRAM[19466] = 36'o046004040630; // 046012 SSRAM[19467] = 36'o377777777777; // 046013 SSRAM[19468] = 36'o377777777777; // 046014 SSRAM[19469] = 36'o377777777777; // 046015 SSRAM[19470] = 36'o377777777777; // 046016 SSRAM[19471] = 36'o377777777777; // 046017 SSRAM[19472] = 36'o377777777777; // 046020 SSRAM[19473] = 36'o046013040630; // 046021 SSRAM[19474] = 36'o377777777777; // 046022 SSRAM[19475] = 36'o377777777777; // 046023 SSRAM[19476] = 36'o377777777777; // 046024 SSRAM[19477] = 36'o377777777777; // 046025 SSRAM[19478] = 36'o400000000000; // 046026 SSRAM[19479] = 36'o400000000001; // 046027 SSRAM[19480] = 36'o046022040630; // 046030 SSRAM[19481] = 36'o400000000000; // 046031 SSRAM[19482] = 36'o400000000001; // 046032 SSRAM[19483] = 36'o400000000000; // 046033 SSRAM[19484] = 36'o400000000000; // 046034 SSRAM[19485] = 36'o377777777777; // 046035 SSRAM[19486] = 36'o377777777777; // 046036 SSRAM[19487] = 36'o046031040630; // 046037 SSRAM[19488] = 36'o000000000001; // 046040 SSRAM[19489] = 36'o400000000000; // 046041 SSRAM[19490] = 36'o777777777777; // 046042 SSRAM[19491] = 36'o777777777777; // 046043 SSRAM[19492] = 36'o000000000000; // 046044 SSRAM[19493] = 36'o377777777777; // 046045 SSRAM[19494] = 36'o046040040630; // 046046 SSRAM[19495] = 36'o000000000001; // 046047 SSRAM[19496] = 36'o000000000000; // 046050 SSRAM[19497] = 36'o377777777777; // 046051 SSRAM[19498] = 36'o377777777777; // 046052 SSRAM[19499] = 36'o777777777777; // 046053 SSRAM[19500] = 36'o000000000001; // 046054 SSRAM[19501] = 36'o046047040630; // 046055 SSRAM[19502] = 36'o777777777776; // 046056 SSRAM[19503] = 36'o377777777777; // 046057 SSRAM[19504] = 36'o000000000000; // 046060 SSRAM[19505] = 36'o000000000001; // 046061 SSRAM[19506] = 36'o000000000000; // 046062 SSRAM[19507] = 36'o777777777777; // 046063 SSRAM[19508] = 36'o046056040630; // 046064 SSRAM[19509] = 36'o777777777776; // 046065 SSRAM[19510] = 36'o777777777777; // 046066 SSRAM[19511] = 36'o000000000000; // 046067 SSRAM[19512] = 36'o000000000001; // 046070 SSRAM[19513] = 36'o777777777777; // 046071 SSRAM[19514] = 36'o400000000001; // 046072 SSRAM[19515] = 36'o046065040630; // 046073 SSRAM[19516] = 36'o040502040504; // 046074 SSRAM[19517] = 36'o040544040550; // 046075 SSRAM[19518] = 36'o000000040517; // 046076 SSRAM[19519] = 36'o040630040634; // 046077 SSRAM[19520] = 36'o000000040565; // 046100 SSRAM[19521] = 36'o416547455644; // 046101 SSRAM[19522] = 36'o320000770000; // 046102 SSRAM[19523] = 36'o414444455644; // 046103 SSRAM[19524] = 36'o320000770000; // 046104 SSRAM[19525] = 36'o624563655464; // 046105 SSRAM[19526] = 36'o320000770000; // 046106 SSRAM[19527] = 36'o555156654556; // 046107 SSRAM[19528] = 36'o443200000000; // 046110 SSRAM[19529] = 36'o007700000000; // 046111 SSRAM[19530] = 36'o636542646241; // 046112 SSRAM[19531] = 36'o504556443200; // 046113 SSRAM[19532] = 36'o007700000000; // 046114 SSRAM[19533] = 36'o624563655464; // 046115 SSRAM[19534] = 36'o320000000000; // 046116 SSRAM[19535] = 36'o007700000000; // 046117 SSRAM[19536] = 36'o556554645160; // 046120 SSRAM[19537] = 36'o545143415644; // 046121 SSRAM[19538] = 36'o320000770000; // 046122 SSRAM[19539] = 36'o556554645160; // 046123 SSRAM[19540] = 36'o545145623200; // 046124 SSRAM[19541] = 36'o000000770000; // 046125 SSRAM[19542] = 36'o624563655464; // 046126 SSRAM[19543] = 36'o320000000000; // 046127 SSRAM[19544] = 36'o000000770000; // 046130 SSRAM[19545] = 36'o445166514445; // 046131 SSRAM[19546] = 36'o564432000077; // 046132 SSRAM[19547] = 36'o445166516357; // 046133 SSRAM[19548] = 36'o623200000077; // 046134 SSRAM[19549] = 36'o616557645145; // 046135 SSRAM[19550] = 36'o566432000077; // 046136 SSRAM[19551] = 36'o000062455541; // 046137 SSRAM[19552] = 36'o515644456232; // 046140 SSRAM[19553] = 36'o000077000000; // 046141 SSRAM[21251] = 36'o000000000000; // 051403 SSRAM[21276] = 36'o000000000000; // 051434 Dist/rtl/testbench/t10backup.exe0000700000175100010010000015677012065222322015234 0ustar RobNoneMZ@ !L!This program cannot be run in DOS mode. $PEL $P8 0|D@@` .text.0`P`.data @ 4@`/4P@@0.bssC``.idataB@0/14@HB/29BJB/45%&PB/57ovB/71 |B/8300B/96+@B/107+P BU$#@'D$D$$'D$D$$'D$D$$'D$D$$'ÐU$@@-tgD$@@$-tPD$`@$P@СJ@t3$@@-t3D$@@$s-t$J@Ð@@t륐t&@@uÐt&U$@@&-t'D$A@$-t$P@Ðt&@@uÐUv@D$D$ A@E$&ED$ D$D$$DA@&US$} tFv@&@ \$D$C@$&EE]&P \$E D$$V&}u&@ $PE$-&US$v@&@ \$D$C@$,&E E]f&P \$ED$$%$[]U8E`@EE EEE EEEEE EEE? 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