////////////////////////////////////////////////////////////////////////////////
//
// KS-10 Processor
//
// Brief
//   Clock Divider
//
// Details
//   This divides the input clock frequency and synchronizes the reset input
//   to that clock.
//
// File
//   esm_clk.v
//
// Author
//   Rob Doyle - doyle (at) cox (dot) net
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2012-2013 Rob Doyle
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify it
// under the terms of the GNU Lesser General Public License as published by the
// Free Software Foundation; version 2.1 of the License.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
// for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, download it from
// http://www.gnu.org/licenses/lgpl.txt
//
////////////////////////////////////////////////////////////////////////////////

module ESM_CLK(clkIn, rstIn, clkOutT, clkoutR, rstOut, locked);

   input  clkIn;
   input  rstIn;
   output clkOutT;
   output clkOutR;
   output rstOut;
   output locked;

   //
   // Clock Divider
   //

   always @(posedge clkIn or posedge rstIn)
     begin
        if (rstIn)
          begin
             clkOutT <= 0;
             clkOutR <= 0;
          end
     end
   
   //
   // Synchronize rstOut to the new clock domain.
   //

   reg d0;
   reg d1;

   always @(posedge clkOut or posedge rstIn)
     begin
        if (rstIn)
          begin
             d0 <= 1;
             d1 <= 1;
          end
        else
          begin
             d0 <= 0;
             d1 <= d0;
          end
     end

   assign rstOut = d1;

endmodule
