////////////////////////////////////////////////////////////////////
//
// KS-10 Processor
//
// Brief
//   Double Buffered UART Receiver
//
// Details
//
// Note
//
// File
//   uart_bufrx.vhd
//
// Author
//   Rob Doyle - doyle (at) cox (dot) net
//
////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2009-2013 Rob Doyle
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// version 2.1 of the License.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.gnu.org/licenses/lgpl.txt
//
////////////////////////////////////////////////////////////////////

module UART_BUFRX(clk, rst, clkBR, clr, rxd, full, data);

   input        clk;            // Clock
   input        rst;            // Reset
   input        clkBR;          // Clock Enable from BRG
   input        clr;            // Clear Receiver
   input        rxd;            // Receiver Serial Data
   output       full;           // Buffer is full
   output [7:0] data;           // Receiver Data

   //
   // Full Flag
   //
   // Details
   //  This process maintains the receiver status
   //

   reg  full;                   // Full flag
   wire intr;                   // Data available from receiver

   always @(posedge clk or posedge rst)
     begin
        if (rst)
          full <= 0;
        else
          begin
             if (clr)
               full <= 0;
             else if (intr)
               full <= 1;
          end
     end

   //
   // Unbuffered Receiver
   //

   UART_RX uUART_RX
     (.clk      (clk),
      .rst      (rst),
      .clkBR    (clkBR),
      .rxd      (rxd),
      .intr     (intr),
      .data     (data)
      );

endmodule
