I, Keith Monahan, am a retro-computing and electronics enthusiast. I grew up on the Commodore Amiga 500, and many of the projects on this site surround that machine. In the 1980’s, I was really impressed by the capabilities of this awesome line of personal computers. I’ve always had an interest in electronics. Much to the chagrin of my father, I took every toy apart to see how it ticked, usually ruining it. Very little escaped my prying.
The electronics building started with the Forest M. Mims III and his little books at Radio Shack. I played with things like the 555 timer ICs, but the too discrete nature of electronics in the 80s kept me away. Too many transistors, too many passives required, too much wiring where mistakes can be made. And besides making things flash, or little counters, I did very little. I was even anti-hardware for awhile, claiming I was just a software guy.
Fast forward to 2005, and I decided to resurrect my Amiga, and my couple thousand floppy disks. Due to PC floppy controller incompatibilities with the Amiga Disk format, I started to build my own hardware controller(first a Parallax Microcontroller, then Xilinx FPGA) and custom software (Java). Enter the Amiga Floppy Project Blog. This detailed my trial and error method of developing a custom software and hardware solution to read Amiga floppy disks and created .ADFs.
Other similar projects have begun with an idea, and have served as the journey through learning about electronics. People too often confuse my goals with being about the destination instead of the journey. These projects serve as the medium through which I travel.
I attended the University of Pittsburgh Computer Science Program where I learned plenty of good stuff.
I manage and do software quality assurance testing for a living where my pedantic attention to detail prevents users from ever seeing the bugs I find, and I probably irritate a couple developers here or there, too.
I’m married to a lovely wife, and have two beautiful children whose energetic curiosity reminds me of my toy-disassembly days.
Lastly, I’m a hacker. In almost all senses and definitions of the word, at one point of my life, or another.
I’m always excited to hear from people and can be reached by simply emailing the same domain you’re on now and putting my first name before AT symbol.
Please note that users using GMAIL addresses to reach out, that Google aggressively filters inbound email, and incorrectly categorizes many messages from my domain into users’ SPAM folders. While I’m trying to remediate this the best I can, check the SPAM folder or whitelist my domain. I reply to 95% of the email I receive within 24 hours or so.
The Amiga Picture above is “© Bill Bertram 2006, CC-BY-2.5 — Attribution. You must give the original author credit.”
You can also use this form below:
Love your pages, always a source of inspiration.
Just a “nudge” regarding posting your Cirrus Logic CS4335 DAC Verilog code 🙂
Thanks for the nudge!
I’ve updated the post to include the entire project directory for Quartus II. This may/may not be relevant to what you’re working on, but be sure to read my updated comment at the bottom of the post for the details.
Good luck with your project!
Thanks a lot for sharing. I would like to know more about MAX 10 UFM accessing. I am planing to write and read UFM using UART interface with an host PC and I don’t want to use NIOS processor for doing that. If you can shed some light on that would be highly appreciated!
Thanks for your comment.
Use the IP Wizard for “Altera On-chip flash” which will launch QSYS. The overall flash storage is broken into two parts: User Flash (for your application) and Configuration Flash (for storing your bitstream to boot the FPGA). This essentially lets you carve up those areas as you see fit.
Be sure that Assignments….Device…Device and Pin options…..Configuration matches what you have configured in that wizard. Otherwise, you’ll get a fatal compilation error.
I forget if there’s an option in the wizard to generate an instantiation template or not, but you’re gonna need one. If you don’t see it in the wizard, right-click the added .qsys file, and generate HDL from there.
The generated UFM controller has an “Avalon-MM” slave bus style interface. Reading from it, you don’t have to do much besides place the address on the bus, and wait (5) clock cycles (the standard latency) for the data to appear on the bus.
I initialize the FLASH with a .MIF file that contains a ROM, so I don’t write to it with Verilog.
There’s a little added complexity with writing because it looks like you have to disable a “write protection” register, you need to hold your write for a specified time, check to ensure that the write was successful, and then re-enable that write protection register. It doesn’t sound hard, but you’ll need some circuitry to handle this. I’d use another FSM.
I’d pay special attention to how the UFM is setup/configured, and then the later diagrams that show the input/output signals, and the read/write timing diagrams. They will tell you essentially everything you need to know.
So setup a top file that instantiates the UARTs, instantiates the UFM, and then use a FSM to control the whole thing.
This should get you started. Feel free to email me keith at this domain if you have follow up questions.