A501 DRAM Card Redesign

A501 512K DRAM Card Redesign Project


So in my overall quest to understand more about the Commodore Amiga 500, I decided just recently to take on a new project. I want to build a replacement A501 512K memory expansion trapdoor card. Not a sidecar memory expansion.  Not even a 1MB version or larger version(yet). Just a straight-up simple A501 replacement.

Now, I know this has been done before, but I’d like to make my own.  It doesn’t seem like there is very much documentation on the A500 DRAM memory controller located in Agnus as far as things like Data Setup and Hold, the type of refreshes, and all the necessary details.

I’ve attached my HP Logic Analyzer to an A500, and sniffing the connection that goes to a Rev 5 A501. I’ve figured out what is happening, and I’ll tell the story and give logic analyzer traces to show exactly how this external card functions.

As with many of my projects, I’ve solicited help from online in terms of requesting documentation, advice from people much more knowledgeable than I, and just overall guidance.  No one has helped more than Mingy!  This guy is a genius, and I’m happy to have someone who really knows his stuff help me out. Thanks Mingy!!

I’ll provide an updated summary here, along with the traces I’ve captured here.   I’ll be using blog posts to detail the day by day efforts which have already begun…..


Project Goals

  • Learn how the Amiga trapdoor 512K expansion memory system works. What makes it tick? How often does it tick? green20x
  • Create glue logic that connects a DRAM controller(Agnus) to a SRAM memory chip green20x
  • Create a prototype solderless breadboard version that works. green20x
  • Use cheap, modern components that are available off-the-shelf from Digi-Key or similar. green20x
  • Create a PCB that matches the form factor (probably much smaller) than the original. green20x
  • Provide all the necessary technical details online, for free — hopefully doing a better job than I’ve done before on previous projects. wip44
  • Speed up overall development, because I think my projects take too long. green20x
  • Incorporate the real-time clock to the design. green20x

Project Summary: As of 1/11/14, the PCB is working exactly as designed! Active timeframe on the project was approximately October 2013-January 2014!

Next Steps: Continued testing of the prototype.  Get more information online.


  • The Amiga looks like it sends RAS-only refreshes.  I don’t see CAS-Before-RAS, Hidden refreshes, Pin-1 Refreshes (no such thing on the LH21256 chips anyways) and so on.
  • PIns 37 and 38 on the 56-pin male dual-row header are switched in the A500 Plus Service manual. This means that /XRAS0 (the Row Address Strobe for the internal 512K RAM) is actually on pin 37. So /XRAS1 (the Row Address Strobe for the trapdoor 512K RAM) is actually on pin 38.  There is a jumper(actually just pads) on the motherboard that control which one is which…..which probably explains the differences.  This pad is called JP3 and located directly to the right of the top most soldered-in DRAM chip on the motherboard.


This is a multiple page schematic.  The first page is an overall schematic.  The second page contains the main design, including the so-called glue logic for converting RAS/CAS’s into Chip Enable’s for the SRAM.  The last page contains the RTC design.

Full Hi-Res Schematics in a PDF. Download here.






What will you make available?  See my answer on this comment.

Why did you use SRAM instead of DRAM?

Good question.  The main issue was finding low-cost 5v-compatible 256k 16-bit width(wider chips have many more pins and more complicated to solder packages) DRAM available in single-unit quantities available from a normal supplier.  The real time clock I use is a $6+ chip, which is the most expensive component of the whole project.  At the time, no DRAM chips at Digikey, Mouser, or Newark fit the bill.  I searched a few weeks ago, and found exactly (1) chip marked as Legacy, having no current datasheet available, that cost around $13.00 each.  One of the stated project goals is using off-the-shelf modern components, and the less than $4.50 ISSI SRAM fit nicely.  Besides, the additional complexity required for the glue logic, in terms of the added logic design components (and cost), and PCB size was pretty minor — and a lot of fun figuring out the best approach.  ‘Nuff said on this.


Logic Analyzer Traces

This one below shows RAS-only refreshes happening.  Notice how the ROW address(0CF, 0D0, 0D1) keeps incrementing.  Also notice that both the internal RAS0, and external RAS1 refreshes happen at the same time.

RAS’s are negative going pulses, usually about 168ns wide, and the memory uses it to latch the incoming ROW Address.  Each row needs accessed (either by a refresh, or by a normal access) within some fixed period of time. These refreshes are separated by 557.813ns.  The CAS address shows 0x085 but is really irrelevant because it is simply not used.  The RAS and CAS addresses are 9 bits wide.

The falling edge is nicely centered on the row address. And also notice that the rising edge of the clock on Agnus Pin 38, the ~7mhz clock. — The falling edge of RAS is synchronous with it.


This next one below shows the read timing.  I’ll add some more description when I find the time.



This shows some writes happening.


The image below shows the internal operation of a write cycle on the new PCB.  The write cycle is critical because we need to ensure that the incoming latched column address is stable prior to dropping /CE, respecting the Address Setup Time requirements of the SRAM.


M5 Blue Line: /RAS falls. Notice that /XWE is already setup, so we know this is a write cycle. This causes the row address to latch, in P8 above.

M4 Red Line: Both CASs fall which indicate a full 16-bit WORD write instead of a BYTE write.

M3 Yellow Line: Glue logic reacts to the /CAS edge and causes the column address to be latched.

M2 Purple Line: Both our R and S inputs to our LS00 SR NAND latch have been satisfied to cause /CE to drop.  In order to slow this latch down to give additional time for our address bus to settle, I moved this from 74ACT logic to 74LS logic to INCREASE the propagation time.

M1 Green Line: The bus is settled.  This happens around 10ns before /CE falls.

Found Brown Line: /CE is forced low, bringing the SRAM active.

More information like parts list, and theory of operation will be coming. (wrote this 2/22/14)

RTC Traces

The trace below shows a write occurring during the AmigaDos command “setclock save.”  The address bus(XA) shows that a “1-minute register” write is occurring, because register “2” is associated with that position.  The value being written was an “8”, so the time was 21:58, or 21:48, or 21:38…you get the picture.

What confuses me is why we see a double-write?  The register is first zero’d out, but then another write-cycle occurs and writes the correct “8” into it.  This seems odd, please get in touch with me if you know the answer!  I’d love to look at the source of setclock or commented (dis)assembly.



These were shot with a Nikon D300 with the AF-S VR Micro-Nikkor 105mm f/2.8G IF-ED lens with off-camera lighting, including an SB700 mounted on a tripod.  They were mostly shot handheld!  Most were done at ISO200, f/32, 1/60s.  This lens is pretty sharp, and allowed me to get in really close, within 5 or 6 inches of the PCB from the front of lens. I’m not thrilled with my overall composition skills, but they work for me.

PCB_overall overall_right overall_closeup lowangle latch_closeup closeup_vias center




Leave a comment
    • Martin,

      We use U7A and U7B flip flops (74ACT74’s) as latches. We clock the data into the flip flop using RAS. So when RAS goes negative, it gets inverted through U2A and then latches the current value of A8 from D->Q.

      We thought about using 9-bit latches but they are more expensive, less standard, less available, and we had the need for the flip flops at one point anyways. I don’t remember specifically if the other need (for more flip flops) disappeared, but it’s been about a year since I’ve touched this.

      9-bit latches would have made the design simpler.

      That help?

      • Yes. Thanks for your reply. I was thinking about trying to do something similar to this to replace a load of 41256 Dram.I have been having trouble with the timing using Dram in a project I’m working on. I am trying to replace 36 x 41256 with 3 x (256 x 16) Dram (I only need 12 bits of the 16 for data) I have seen other Sram designs were only one set of the multiplexed addresses went through a latch (74574) and the others went straight to the sram then all data is clocked in at the same time, (by both the latches) but using your design it looks like the Sram is isolated somewhat so it may be possible to stack another board (with another sram) on top and not have any bus contention? (If I even know what I’m talking about) I will have to save up for a logic analyser. It helps to see what’s going on.Your work and descriptions regarding your A500 board has been very useful reading.
        Thanks again

        • Martin,

          Thanks for your comments on my projects. I really enjoy doing them, and if I’m helping someone else out in the process, then I get paid twice. 🙂

          The only purpose I could see about stacking my modules would be get WIDER data, so instead of 16-bits, maybe 32-bits or something. In your case, it sounds like you need DEEPER data, ala you need to support more address bits. Stacking wouldn’t get you extra address bits…..for those remember you need additional latch support.

          The same basic concept could definitely be used.

          I don’t have time now to reply, but you can email me keith (at) the same domain as you’re visiting now, and I’d be happy to get some more specifics from you on what you’re trying to do and provide some cursory help!

  • Hi. I was wondering if you are planning to sell any boards or kits in the near future? I have two bad A501s that I need to fix or replace. My guess is that either battery corrosion did more damage than is apparent to the naked eye, or capacitors need to be replaced. I would actually rather go with a modern replacement board than invest time and effort in trying to repair these old duds.

  • Hi Keith,
    I was just wondering what kind of logic analyzer do you use?
    It’s definitely not the 16700a you mentioned elsewhere on this site.
    I was also looking for KiCAD files here …

    • Hi Michal,

      I’ve got several logic analyzers. The best one is my HP 16700A. Those screenshots you see above are certainly captures from the 16700.

      Why did you think they weren’t from there?

      I also have a 34-channel 500mhz Intronix LogicPort, an 8-port Logic from Saleae, a smaller 4-port, and another 100mhz unit.

      I’ll have to dig up the KiCAD files, although I have to make sure they are current. We made a minor mistake in the first run, and while it’s fixable with a just a short jumper, I’m not sure we ever went back to updated them. I don’t have plans to make any more than the original (10), but I don’t like the “half-state” that I think the files are in.


      • Hi Keith,
        I use my 16702A/16750A through X11 (MobaXTerm) on Win 7 and have never gotten
        such a nice shadowed labels :). The user interface remains Motiff like (grey and more grey :).
        Also I see more than 2 markers, I think that I have only two (green and yellow).

        It’s nice to see finished and working KiCAD design. I’ve been OrCAD (licensed) then Altium (not so licensed 🙂 guy for some time who tried KiCAD for his simple designs and liked it. It is useful to have a design which works – it proves that the library parts are right and one can reuse them
        without much worries.

        Happy new year anyway 🙂

        • Hey Michal,

          After I posted I was thinking about it, and I figured you were seeing the UI improvements in the updated software. I’ve also used the X-interface remotely with Mobaterm.

          If you export your 16700 capture as “Fast Binary Output” (a .fbo) file, to a network share, then using Windows 8/10(!), you can import these into the modern 16900 software, “Logic and Protocol Analyzer” version 5.90 which is a free and unlicensed download.

          This software is much better, especially for annotating captures, as you’ve noticed. 🙂

          You can’t operate the equipment live, but working in a modern OS with all the bells/whistles they provide makes a heck of a difference.


          I think that’s the link.

          The help files show you how exactly to export it on the 167xx if you’re not clear, and how to load it, if it’s not obvious.

          Regarding KiCad, yeah, it turned out to be functionally fine in producing a good end result. Many of the footprints needed changed or modified because the tolerance on them were too small to allow easy soldering. For the 44-pin TSOP II package, we used a design from a surfboard (Surface mount to DIP) design, and that really made it easy. I printed the design and then manually placed each component on the printout, checking with 2x magnification to ensure proper alignment/sizing of the pads. I don’t think we kept the original footprint on any of the packages…..The design would have been different if we weren’t targeting a moderate-ability hand-solderer like myself. 🙂

          Happy New Year, and go get that other software. The workflow is a little clumsy having to capture, then export, then import, but if you’ve set triggering up correctly, and have grabbed the right sample, then playing with it in that software is a lot easier.

          • Keith, thank you for your reply.
            I’ve been pretty busy recently,
            no chance to test the 16900 SW yet,
            but it’s on my todo list 🙂

  • Hi,

    Cool project!

    I’m looking to make some of these for myself (I have several ram expansions eaten by Varta NiCds 🙁 )

    Are you still planning on making the PCB files and BOM available?

    • I can still do that. The only problem is that the PCB requires a minor work around to function due to a mistake we made. You have to solder one small wire on the PCB to fix it. It’s trivial but important. Let me see what I can do. Thanks for the comment.

        • I think the schematics are clean and updated. I’m not sure I ever updated the gerbers. The change doesn’t affect the number of parts — just consumes one less gate or flip flop. I forget which. I’ll see about getting a BOM up soon. FWIW, the mistake is easily correctable by cutting a couple pins and attaching a single wire.

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