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inital results on error correction

While I have yet to actually implement the full-scale error correction as I want to, I did some manual tests today. I basically took a track that I was erroring out on, and swapped in 1-bit away values for the bad bytes.  In some cases, it appeared...

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PCB ordered from Seeed Studio

I placed the order late last night for the PCB! The PCB design is obviously finished, fully passes the kicad DRC checks, the problems with the footprints were solved. I’ve decided to go with Seeed Studio’s...

FPGA eval board

One of these arrived today.  Very cool.  I’ve only done minor things with it so far — but I’m learning. I’ve got FPGAs by Example for Verilog coming within a couple days.  Looks like a good book...

sanding a 556 timer IC to expose the die

So tonight, just for the fun of it, I decided to sand, by hand, a 556 timer IC. I just bought an extremely inexpensive microscope and was very interested to see what pictures I could get from it. Unfortunately, for me...

interesting results

OK, I’ve applied the “double 1’s” fix that I talked about earlier today. This definitely helped things. I think my results are quite possibly the best I’ve seen them yet. Now, my SX...

new read routine implementation started

Last night, until 3am, I spent redoing my read routine to incorporate the method discussed in the comment of the last post. Basically, I use the time between the pulses as an indication of the data.  I store 2-bit...

on memory controller optimization

So I’ve been trying to optimize a freeware memory controller for my particular memory chip. I’m running into this situation where the DRAM to ALTRAM copy takes upwards of 24us per line. But I only have a...

first night wiring progress

Now I remember why I like FPGAs so much, no freakin’ wiring!@!# Here’s a start to what the monster looks like.  I think I’ll like the PCB form factor a little better. 🙂 I thought a little bit about how...