Schematics now available for A501 replacement card!
This is a category for the A501 Replacement card project.
Schematics now available for A501 replacement card!
Added some new photos of the populated PCB for the Commodore Amiga A501 memory replacement card.
Find them on the main project page here.
So the very first A500 I had been testing on since the beginning of the project had a Bug Katcher installed. It turns out that I wasn’t really using it, but I left it plugged in anyways.
I’m not sure electrically what the exact effects of having that installed are, but removing it caused all of my instability and boot issues to disappear.
I was able to boot the amiga (10) times in a row from a cold start without an associated hang.
I still want to reconnect the logic analyzer, and verify that the race condition(which was/is a separate issue) has truly been addressed.
There was an issue where /CE could get asserted low prior to the latched addresses being clocked (or stabilizing) into the SRAM. I solved this by using slower logic(LS instead of ACT) on the logic path of /CE. While not ideal, I think it’s pretty effective.
I’m going to verify that those setup times for the SRAM are being respected, and I have a sufficient design margin.
So I think the Amiga 500 I was testing with has problems. I’m not sure precisely what or why but
Today, I dropped my new A501 replacement card into a known-working Commodore Amiga 500. It fired up immediately no issues with booting, everything worked, no wonkiness, memory tests passed 100%. This amiga has an accelerator card, and I was able to run 300 tests of pretty much the entire memory space on the card in about 5 minutes. Everything worked without error.
I’d like to get more data points here before I call it DONE, but it looks GREAT to me!
I’ve got to start putting up some more information, update the schematics with a few small fixes, and do some more testing.
Good milestone tonight!
While I had my logic analyzer connected to my memory card tonight, I noticed that I no longer had the white screen hang on bootup problem that I’ve been plagued with since this card came in.
As a matter of fact, it was booting up about 100% of the time.
I disconnected my HP logic analyzer probes, and all of a sudden, the Amiga won’t boot any longer.
It seems as if the impedance loading of the probes have been POSITIVELY affecting my circuit….slowing down the rise times and fixing whatever issue was in place.
The address pins and a single ground connection must be left attached to my turned off logic analyzer in order for this card to allow the Amiga to boot normally and properly detect the memory.
I’ve also read previously that it’s possible to have too fast rise times for older legacy hardware, and perhaps the choice to “upgrade” to 74ACT last minute has shot myself in the foot. I do have some 74LS components ordered for exactly this emergency, but time will tell.
So I’ve written some assembly in the monitor software I’ve been using, and I’ve just created a large loop to see if I can get the card to fail.
I’m still having plenty of problems on bootup, but everything else is checking on. So I’m not sure what the cause is, but I’m double checking that the memory system is reliable over a large number of reads/writes.
Overnight tonight, I’m doing about 650 million individual reads and writes to the memory card. I’m interleaving those with another 650 million reads/writes with the internal memory. To make sure that there’s no trouble when both memory banks are accessed.
So far, it looks pretty clean.
Gotta get to the bottom of the startup issue though.
RTC appears to be working and keeping the date and time across cold-starts.
I picked the Epson RTC-72423 which is about a $6 chip, but is obviously directly compatible with the OKI Semiconductor MSM6242B. The design, including the battery supervisor, had never been tested — not even as a prototype… and appears to have worked the first time!
I needed to do a “setclock reset”, set the date via “Date 28-Dec-13 02:26:00” command, and then did a “setclock save” Subsequent setclock loads brings it back!
More thorough testing needs to be done, but initial indications look real nice!
After looking at datasheets for the 273 latches used and 74act74 flipflop used, the worst case propagation delay is something like 12.3ns.
But my NAND gate ACT00 logic which is triggered by the same CAS signals has a lower propagation delay of between 1-9ns.
So despite a 0ns setup time, it’s possible that I’m violating the SRAM setup times during a write by dropping /CE before the addresses have stabilized into the memory.
I haven’t come up with a solution yet, but it will likely involve adding an additional gate or two to increase the propagation delay.
Lots of progress but little time to talk about it.
Here’s the fully populated card installed. There were two issues identified so far with the PCB design. One, the battery holder silkscreen was upside down. The second fix involved an inverter that needed removed whenever we decided to migrates from a flip-flop(74LS74) design to a SR NAND latch made out of NAND(74LS00) gates.
The memory tests are passing at 100% now!@#
However, there is still a minor issue with how the card responds on bootup, and I’m investigating!