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FPGA eval board

One of these arrived today.  Very cool.  I’ve only done minor things with it so far — but I’m learning. I’ve got FPGAs by Example for Verilog coming within a couple days.  Looks like a good book...

redone transfer routine

So my transfer routine has been a little flaky lately. I’m not sure exactly why but I think it’s related to the number of processes I’m running. While it’s a P4 2.4, I think USB scheduling is...

redesign of read routine

After skimming the patent I referenced in the earlier post, I’m starting to come to the realization that in order to have an effective floppy controller, I need to implement a decent PLL which can better track the...