I’ve been struggling for quite a few nights and weekends over the last month or so. I’ve now successfully attached the J68 to the built-in User Flash Memory. This means that the 16KB (actually about ~13KB)...
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LCD Test image and pixel-level detail
So I’ve managed to get a semi-working test pattern image up on the LCD. Here are a couple shots: If we zoom in about 10 times, we can see how the LCD really works, on an individual pixel level: Pretty challenging...
J68 boots VUBUG monitor on the BEMICRO MAX 10 FPGA board
Here’s an image showing a ROM monitor VUBUG running on the J68 softcore, which is in turn running on a BEMICRO Max 10 FPGA board.
VUBUG will be used until we can get our own (unwritten, so far) custom code booting!
Launch of HOPE Badge Computer project
This is the first post of many in this category. We have a project page giving the general goals of the project, but most of the hands-on action will happen here in the blog posts. For the latest status, reading these...
My Custom HP Logic Analyzer 16700A Cart
So after looking at the high priced real HP logic analyzer cart that didn’t look that great to me, I decided to build my own incorporating a ton of features that just really makes my life easier. This is optimized...
Memory controllers in FPGAs are the bane of my existence, help needed
I want to put together a softcore 68K computer system, just something simple. I’ve purchased, but not yet received, the Terasic Cyclone V GX Starter Kit, an Altera FPGA eval board. It looks pretty sweet and...
