With this new FPGA solution, certain tracks would result in what I call a “short read.” A short read is any received track that contains less than 28,125 delta T’s, aka pulse times. Given a certain capture time, there are minimum’s and maximum’s of the number of pulses on an amiga track.
If we have a 300 rpm drive, then its 60s/300 = 200ms per revolution. If the bitcells are 2us wide, then you have at most 200ms/2us = 100,000 bit cells. The one’s density is at max 50%(raw MFM ’10’), so this means every other cell would contain a 1. So 50,000 pulses, so 50,000 delta T’s. The minimum one’s density is 25%(raw MFM ‘1000’), so 25,000 pulses. Now we read more than just one revolution of data, because we will very likely start reading in the middle of a sector. So instead of 11 sectors worth of read time, we actually need to read 12 sectors worth, to ensure we read the entire sector in which we started. This is 218.2ms of time minimum. We could potentially re-assemble data, using some type of circular buffer, but this is more trouble than it’s worth. I currently read 225ms of data.
225ms / 2us = 56,250 maximum, 28,125 minimum.
I had my FTDI chip, for the usb<->ttl converter, D2XX USB parameters setting the USB transfer size to 57000 bytes. This is definitely over and above what was needed. Or so I thought.
I bumped the transfer size from 57000 to 60032 (docs said specifically 64 byte multiples), and everything started working. I had already narrowed it down that the problem tracks were ones that had a high density, where there were lots and lots of pulses. So I knew the size of the track was related. I checked for FIFO overflow, and it wasn’t overflowing.
I’ve got to look when I have a free second, but I think my USB packet size is 4096 bytes. So 56250+4096 (some amount of padding?) = 60346. Uh-o, I better bump that to 60,352. I think the driver (or windows?) that maxes out at 64k transfer size, so I still have a little wiggle room.
Long and short is that it appears to be working much better. I was glad to find this bug with just a little brainstorming, and getting better visibility into my actual pulses count on the FPGA.