So since I first picked up this Xilinx Spartan-3E starter kit evaluation board, I’ve been trying to get some memory working on the FPGA. The DDR is as elusive as beast as I can find. I’ve not yet given up...
Archive - 2009
SX EOL
I hate when this happens. 🙂 The Parallax SX microcontroller line has reached production EOL. The owner of the SX design (www.ubicom.com) has given Parallax final notice that we are to place a lifetime buy of wafers. We...
Histogram of one track
Here’s a histogram of one track off an amiga floppy disk. Notice the peaks near 4us, 6us, and 8us. I’ve got this data from my logic analyzer, crunched through my little C proggie, and then graphed with...
bought a Saleae Logic. Another tool for my toolbox
I bought at Saleae Logic which is an inexpensive logic analyzer. See link here. It isn’t nearly as fast (only samples at 24mhz max), and it doesn’t have as advanced triggering capabilities, but it does do...
Finally had some luck with FPGA board
So I bought an FPGA eval board and a book on Verilog awhile back. I made some progress learning things, and had some simple things like UARTs, writing to the LCD, and even some small VGA software(hrrrm, maybe I should...
got build environment working again, fixed uart code
So awhile ago I bought a quad core machine which runs Vista 64. Once I had the new machine, I tried getting my build environment for the AFP working again. NetBeans, the java IDE I use, has 64-bit support but there...
my checksum algorithm
So I’m using an XOR checksum to detect errors in the transfer between the SX and the PC. I always thought it was a reasonably strong checksum, even though it’s still an 8 bit checksum. I found a neat...
sanding a 556 timer IC to expose the die
So tonight, just for the fun of it, I decided to sand, by hand, a 556 timer IC. I just bought an extremely inexpensive microscope and was very interested to see what pictures I could get from it. Unfortunately, for me...
upgraded Tivo HD serial 652
I followed the instructions at but when I tried to expand the partition after the copy, it failed with the following error: Primary volume header corrupt, trying backup. Secondary volume header corrupt, giving up...
FPGA eval board
One of these arrived today. Very cool. I’ve only done minor things with it so far — but I’m learning. I’ve got FPGAs by Example for Verilog coming within a couple days. Looks like a good book...
