I took David’s advice, and I rewrote the code last night. Some highlights:
1. ISR is entirely in assembly. Although I haven’t manually counted, it appears to be about 400ns in length.
2. ISR triggers only due to an edge now. I admit I do like the fact that there are no longer RTCC-triggered interrupts. The RTCC runs freely now and is not reset or resync’d. The difference in time(ticks) between the edges define the data.
3. I’m using a prescaler of 1:2 on the RTCC, so the RTCC rollsover every 10.24us. This means that each RTCC tick happens every (10240ns / 256=) 40ns.
4. Edge detection seems to be working perfect.
5. Main is completely empty. Just a loop to keep it alive
I don’t like the fact that the shift register gets slammed with up to 4 bits all at once. I’m using a
and once I have shifted 8 times, I transfer SRH to the PC.
A transfer can happen at inter-bit times, but thats ok — the ISR can run forever, up to 4us from the start.
I’ll post results if I can get some! 🙂