I think that’s really the problem I’ve been facing with this floppy project. Trials and tribulations indeed. Or at least trial and error, with stress on the error part. There are probably less than half-a...
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I originally thought that the SX might be sending the data too fast for the PC to handle. As my last post mentioned, one full cycle is 12us, but who knows if this is during a disk-write, going into the cache, etc. I...
Timing problems still?
I think I’m still having timing related issues. I have RTCC overflowing every 1.8us which I *know* is less than the 2us bit cell(or less than half the bit cell, if you take it to be 4us), but this seems to be what...
PC xfer working now, timing in order
Welp I pretty much solved the big problems I encountered over the past couple weeks. Ground issues — turned out I was attaching ground of one interface to Vdd on another interface. That was solved by actually...
Of timing, and general progress
I’ve determined that programming is like whack-a-mole(only took me 15 years to figure this out!) Fix one problem, and another one that already works stops working. This is what happened to me yesterday. My ISR...
Am I reading MFM wrong?
I’m beginning to think that I don’t fully understand the signalling coming out of the drive. I understand the concepts behind MFM (I think), but the actual application to this project, I’m not so sure...
