PC xfer working now, timing in order

Welp I pretty much solved the big problems I encountered over the past couple weeks.

Ground issues — turned out I was attaching ground of one interface to Vdd on another interface. That was solved by actually doing the wiring properly.

PC xfer issues —- I had made so many modifications that I forgot I changed my parallel port in the BIOS to ECP instead of BI-DIRECTIONAL. And of course, you have to remember to set the appropriate Bi-Directional bit in order to make the data port, pins 2-9, input pins. There are other problems(namely edge trigger checking) that made me think this was worse off than it was.

Timing issues —- trying to get the SX to sample at the right time has been surprisingly easy by setting up the ISR to raise and lower a pin when entering and exiting. It’s easy to see when its sampling too early or too late. I want to put up a photo of this, because its pretty cool. Overall — I’m still not getting intelligible data yet on the PC. I’m not sure why yet, why that is. I want to fix my current problem, where the edge triggers the interrupt, but then the check on WKPND_B doesn’t show that a signal edge was detected. I think this is something stupid I’m doing, and betting on what I’ve seen so far — I bet the bits in WKPND_B are *set*, enabled, ‘1’, when they are unused. This has gotta be the case. I should have thought of that sooner, but the documentation didn’t mention it anyplace.

About the author

keith

Amateur Electronics Design Engineer and Hacker