With help from Ralf on this comment I was able to Disable the memory by no-longer grounding PIN 32, and sometimes forcing CE high on the SRAM chip. Boot a workbench disk, and then break it on startup. Insert a disk...
Latest articles
Ended up destroying the v1 prototype, too many damn wires
This version is much better, much cleaner. I also ordered some new wires that I hope will clean up the latch <—–>memory connections and amiga connector (CNX) to the protoboard. Things are coming...
first night wiring progress
Now I remember why I like FPGAs so much, no freakin’ wiring!@!# Here’s a start to what the monster looks like. I think I’ll like the PCB form factor a little better. 🙂 I thought a little bit about how...
Let the fun begin!@#!@#
Everything has arrived! I think the first order of business is soldering this darn memory chip…. Not sure how hard this is going to be, but I’m going to give it a shot!@#
Converting Rigol DS1102D Logic Analyzer .csv files to OLS data file format using Linux
How to convert .csv files exported from a Rigol DS1102D MSO to OLS data file format. So I own a Rigol DS1102D 100mhz MSO which has two-channels of analog and 16 channels of logic analysis through the active logic head...
