Found potential race condition on writes

After looking at datasheets for the 273 latches used and 74act74 flipflop used, the worst case propagation delay is something like 12.3ns.

But my NAND gate ACT00 logic which is triggered by the same CAS signals has a lower propagation delay of between 1-9ns.

So despite a 0ns setup time, it’s possible that I’m violating the SRAM setup times during a write by dropping /CE before the addresses have stabilized into the memory.

I haven’t come up with a solution yet, but it will likely involve adding an additional gate or two to increase the propagation delay.



Amateur Electronics Design Engineer and Hacker


  • Measured the setup time today, and the addresses had about 6ns to settle. My logic analyzer was set to 3ns, so it could be just a tick over 3ns. It is still more than the 0ns required, however, I might replace the ACT series NAND gate with an LS to slow it down a bit and give more error margin.