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inital results on error correction

While I have yet to actually implement the full-scale error correction as I want to, I did some manual tests today. I basically took a track that I was erroring out on, and swapped in 1-bit away values for the bad bytes.  In some cases, it appeared...

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new read routine implementation started

Last night, until 3am, I spent redoing my read routine to incorporate the method discussed in the comment of the last post. Basically, I use the time between the pulses as an indication of the data.  I store 2-bit...

first night wiring progress

Now I remember why I like FPGAs so much, no freakin’ wiring!@!# Here’s a start to what the monster looks like.  I think I’ll like the PCB form factor a little better. 🙂 I thought a little bit about how...

Histogram of one track

Here’s a histogram of one track off an amiga floppy disk.  Notice the peaks near 4us, 6us, and 8us. I’ve got this data from my logic analyzer, crunched through my little C proggie, and then graphed with...

Marco Veneri

I had the great pleasure of trading emails with Marco Veneri today.  He is the original author of the Amiga Floppy Reader(AFR), of which I refer to very frequently, and have based most of my work to date on. I have...

redone transfer routine

So my transfer routine has been a little flaky lately. I’m not sure exactly why but I think it’s related to the number of processes I’m running. While it’s a P4 2.4, I think USB scheduling is...

switching design from DRAM to ALTRAMs

So as my last couple posts alluded to, I’ve been having problems with my DRAM-based design. My controller isn’t dual-port. And I’ve been trying to wrap my head around a time-slot method for arbitration...