Interesting snippet from FPGA Prototyping by Chu

This is exactly the problem that I’ve been facing for the last couple weeks. I could get the memory tests to pass at 100% if only the CPU was talking with the external SRAM. As soon as I added in my time slot system, where every other cycle is for the CPU and the video display circuit, then the test would fail miserably.

What I settled on was simply disabling access to the SRAM from the video display during the fairly short interval that the CPU was accessing. This guarantees that the CPU has relatively error free access. The suggestion above is to only allow writing video memory during the blanking interval, and I think that’s a good idea too.

I still see some small percentage of errors both on the CPU side and the video driver side, but the rate is small enough to not cause any problems currently.

I’ll revisit this noise issue later, but for now, it kinda gives a little Max Headroom kinda vibe to the project, and I like this!

For what it’s worth, knowing that the “struggle is real” and that what I’m dealing with is a conventional problem is refreshing. I’m sure the early computer designers also ran into problems…..

About the author

keith

Amateur Electronics Design Engineer and Hacker