While I have yet to actually implement the full-scale error correction as I want to, I did some manual tests today. I basically took a track that I was erroring out on, and swapped in 1-bit away values for the bad bytes. In some cases, it appeared...
Found potential race condition on writes
After looking at datasheets for the 273 latches used and 74act74 flipflop used, the worst case propagation delay is something like 12.3ns. But my NAND gate ACT00 logic which is triggered by the same CAS signals has a...
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