So far, I’ve been using a user-selectable mux, with a physical switch, to control which process is connected to the single-port memory controller.
If the switch is in one position, you can upload via USB a properly formatted image. In the other position, the display FSM is active, and it is reading from the memory and displaying it on the output video port.
But since I’m transitioning to a model where I have simultaneous input from the amiga, while outputting to the monitor — things are going to have to get more complicated.
Finding working, easy to use, free memory controllers for FPGAs is tough. A lot of the stuff on OpenCores sucks, and even when they work, there is zero documentation, and reliability is shaky. Sure there are commercial cores.
My memory controller is a freeware wishbone slave. I know I need some type of arbitration, but I’m not even convinced yet that there is enough time (bandwidth?) to allow everyone to properly interleave the access they need. It’s also weird, in that, we read from the memory much faster than we write. Which means that we in essence do unnecessary reads. Do we do some type of per-line synchronization? Can I get away with some other type of scheme?
I’ll take any hints from people who have experience with this stuff.
Arriving video information from the amiga comes at a 7.14mhz pixel clock speed, getting 12 bits (16 bits packed) every 140ns. This translates to about 14 megabytes per second. Wow!
Output video is a 25mhz pixel clock, with 12 bits (16 packed) leaving every 40ns. This translates to about 50 megabytes per second.
It’s approximately a 4:1 ratio of reads from memory (aka output to monitor) to writes (aka input from amiga)
My memory is running at 133mhz, and is 16-bit wide. The controller is setup to do a burst size of 2. I think I can access 32 bits every 30ns with a 100mhz user clock best case. So I’m getting at least an effective 1 gigbit / second throughput. This doesn’t include writing it into secondary memory (block ram, etc).