progress on amiga vsc made this weekend, VSYNC problem persists

Worked on the Amiga VSC this past weekend at Notacon with my super smart friend Brian P.  We made some progress, including eliminating all but the smallest HSYNC related bugs.

There is still a problem that is haunting us with VSYNC where the screen is shifting up and down constantly.  We have not uncovered a clue to what the problem is despite many theories and attempts.

I’ll post a picture and new video soon.



Amateur Electronics Design Engineer and Hacker


  • Hello,

    I have done the same kind of project 2 weeks ago by hooking up an Altera dev board to my A2000B’s Denise chip. Mine is finished 🙂

    Here are some hints:
    You cannot rely on RGB and CSYNC signals only, you have to tap the RGA bus too.
    Agnus chip sends strobe signals by using dummy RGA values (STREQU, STRVBL, STRHOR or STRLONG registers) to Denise at the beginning of each horizontal lines (DMA cycle #0 : 1st refresh slot).
    With those strobes, Denise re-initializes its HPOS counter (when STREQU, STRVBL or STRHOR is received), knows when a long line is used (STRLONG received on DMA cycle #2 or 2nd refresh slot), knows when there is a vertical blanking (STRVBL or STREQU) and knows when there is a VSYNC (STREQU).
    HPOS counter in Denise counts from 2 to 456, it uses clock CDAC#, when STRLONG is received, it stops counting during two CDAC# cycles.
    HBLANK occurs between HPOS = 19 and HPOS = 97.
    HSYNC occurs between HPOS = 32 and HPOS = 65.
    RGA value can be sampled at the rising edge of CDAC# when CCK = 1.

    Hope this will help.



  • Greetings Frederic! Thanks so much for your comment. This really helps me.

    Just playing devil’s advocate, but doesn’t the monitor just rely on the RGB signals and CSYNC to display the image? If the monitor can display it correctly, why can’t I use the same signals to recover the same data?

    Thanks again for the detailed information. I’ve got find some time to continue working on it, but this is definitely what I need.

    I have a reasonable collection of amiga reference books. Do you know where this process might be detailed? Which book?

    Did you document your project any place?


  • Hello,

    CSYNC is good for TVs, not for VGA monitors : it contains equalization and serration pulses.

    There are very few explanations on STROBE registers in the hardware reference manual. STROBEs are also used by Paula to generate the VBLANK interrupt (if you look at Paula’s pinout, you will see no VSYNC input from Agnus).

    In the same vein, you have the DMAL signal between Paula and Agnus : at the beginning of an horizontal line, Paula serially outputs (one bit per CCK) Disk DMA request/direction and Audio DMA request/restart.
    BTW, MFM bit duration is 1.955us for NTSC Amiga and 1.974us for PAL Amiga, not 2us. Paula takes the 3.5 MHz clock and divide it by 7.

    I gathered all this info by hooking up a FPGA dev board to Denise and by using SignalTap as a logic analyzer.
    I did not document my project on the web, this is the first time I am talking about it. I cannot find time to run a website.

    In general for the Amiga, apply the KISS rule :-). Keep in mind that the chipset was made with 3um process, each component had only 20,000 transistors and was running mostly at 3.5 MHz (the whole chipset is actually less complex than the 68000 sitting next to it !).



  • Hi admin & Frederic,

    Do either of you have a public repo for your HDL code? I wrote an Amiga demo years ago which I’d like to upload to YouTube/Vimeo, but it doesn’t run very well on UAE, so I thought a nice project would be to just record the raw 12-bit digital video stream from Denise direct to disk using FPGALink (, and then building an AVI from the individual frames offline (I did something fairly similar for

    However, like you guys I also need to be able to recover the HSYNC and VSYNC signals, in order to be able to recover the individual frames from the resulting long stream of pixel data. Looking at your code will make life a *lot* easier.

    Also, I was thinking of being lazy and just recording everything synchronous to the HiRes clock (14.2MHz?) rather than trying to detect the switch from LoRes to HiRes. Would that work OK do you think?



  • Chris, Thanks for your comment.

    I can put my Verilog up. Might not be pretty, but it mostly works.

    Let me look into it, and I’ll get back to you soon.